Ian McCulloch / nRF24L01

nRF24L01 driver

Dependents:   Nucleo_IOT1 wireless

nRF24L01P.cpp@3:39e8335cce5d, 2016-09-02 (annotated)

Committer:
ianmcc
Date:
Fri Sep 02 15:51:22 2016 +0000
Revision:
3:39e8335cce5d
Parent:
1:cd113026825f
Child:
4:8f612189af31
Fix to initialization of the RF_SETUP register to match reset state

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ianmcc 0:7313e63394c3 1 #include "nRF24L01P.h"
ianmcc 0:7313e63394c3 2
ianmcc 0:7313e63394c3 3 #define NRF24L01P_SPI_MAX_DATA_RATE 10000000
ianmcc 0:7313e63394c3 4
ianmcc 0:7313e63394c3 5 #define NRF24L01P_CMD_R_REGISTER 0x00
ianmcc 0:7313e63394c3 6 #define NRF24L01P_CMD_W_REGISTER 0x20
ianmcc 0:7313e63394c3 7 #define NRF24L01P_CMD_R_RX_PAYLOAD 0x61
ianmcc 0:7313e63394c3 8 #define NRF24L01P_CMD_W_TX_PAYLOAD 0xA0
ianmcc 0:7313e63394c3 9 #define NRF24L01P_CMD_FLUSH_TX 0xE1
ianmcc 0:7313e63394c3 10 #define NRF24L01P_CMD_FLUSH_RX 0xE2
ianmcc 0:7313e63394c3 11 #define NRF24L01P_CMD_REUSE_TX_PL 0xE3
ianmcc 0:7313e63394c3 12 #define NRF24L01P_CMD_R_RX_PL_WID 0x60
ianmcc 0:7313e63394c3 13 #define NRF24L01P_CMD_W_ACK_PAYLOAD 0xA8
ianmcc 0:7313e63394c3 14 #define NRF24L01P_CMD_W_TX_PYLD_NO_ACK 0xB0
ianmcc 0:7313e63394c3 15 #define NRF24L01P_CMD_NOP 0xFF
ianmcc 0:7313e63394c3 16
ianmcc 0:7313e63394c3 17 // registers
ianmcc 0:7313e63394c3 18 #define NRF24L01P_CONFIG 0x00
ianmcc 0:7313e63394c3 19 #define NRF24L01P_EN_AA 0x01
ianmcc 0:7313e63394c3 20 #define NRF24L01P_EN_RXADDR 0x02
ianmcc 0:7313e63394c3 21 #define NRF24L01P_SETUP_AW 0x03
ianmcc 0:7313e63394c3 22 #define NRF24L01P_SETUP_RETR 0x04
ianmcc 0:7313e63394c3 23 #define NRF24L01P_RF_CH 0x05
ianmcc 0:7313e63394c3 24 #define NRF24L01P_RF_SETUP 0x06
ianmcc 0:7313e63394c3 25 #define NRF24L01P_STATUS 0x07
ianmcc 0:7313e63394c3 26 #define NRF24L01P_OBSERVE_TX 0x08
ianmcc 0:7313e63394c3 27 #define NRF24L01P_RPD 0x09
ianmcc 0:7313e63394c3 28 #define NRF24L01P_RX_ADDR_P0 0x0A
ianmcc 0:7313e63394c3 29 #define NRF24L01P_RX_ADDR_P1 0x0B
ianmcc 0:7313e63394c3 30 #define NRF24L01P_RX_ADDR_P2 0x0C
ianmcc 0:7313e63394c3 31 #define NRF24L01P_RX_ADDR_P3 0x0D
ianmcc 0:7313e63394c3 32 #define NRF24L01P_RX_ADDR_P4 0x0E
ianmcc 0:7313e63394c3 33 #define NRF24L01P_RX_ADDR_P5 0x0F
ianmcc 0:7313e63394c3 34 #define NRF24L01P_TX_ADDR 0x10
ianmcc 0:7313e63394c3 35 #define NRF24L01P_RX_PW_P0 0x11
ianmcc 0:7313e63394c3 36 #define NRF24L01P_RX_PW_P1 0x12
ianmcc 0:7313e63394c3 37 #define NRF24L01P_RX_PW_P2 0x13
ianmcc 0:7313e63394c3 38 #define NRF24L01P_RX_PW_P3 0x14
ianmcc 0:7313e63394c3 39 #define NRF24L01P_RX_PW_P4 0x15
ianmcc 0:7313e63394c3 40 #define NRF24L01P_RX_PW_P5 0x16
ianmcc 0:7313e63394c3 41 #define NRF24L01P_FIFO_STATUS 0x17
ianmcc 0:7313e63394c3 42 #define NRF24L01P_DYNPD 0x1C
ianmcc 0:7313e63394c3 43 #define NRF24L01P_FEATURE 0x1D
ianmcc 0:7313e63394c3 44
ianmcc 0:7313e63394c3 45 #define NRF24L01P_MAX 0x1F
ianmcc 0:7313e63394c3 46
ianmcc 0:7313e63394c3 47 nRF24L01P::nRF24L01P(PinName mosi, PinName miso, PinName sck, PinName csn, long SPIFrequency)
ianmcc 0:7313e63394c3 48 : Spi(mosi, miso, sck),
ianmcc 0:7313e63394c3 49 NCS(csn)
ianmcc 0:7313e63394c3 50 {
ianmcc 0:7313e63394c3 51 Spi.format(8,0); // 8-bit, ClockPhase = 0, ClockPolarity = 0
ianmcc 0:7313e63394c3 52 Spi.frequency(SPIFrequency);
ianmcc 0:7313e63394c3 53 NCS = 1;
ianmcc 0:7313e63394c3 54 this->reset();
ianmcc 0:7313e63394c3 55 }
ianmcc 0:7313e63394c3 56
ianmcc 0:7313e63394c3 57 void
ianmcc 0:7313e63394c3 58 nRF24L01P::reset()
ianmcc 0:7313e63394c3 59 {
ianmcc 0:7313e63394c3 60 this->write_register(NRF24L01P_CONFIG, 0x08); // power down
ianmcc 0:7313e63394c3 61 this->flush_tx_fifo();
ianmcc 0:7313e63394c3 62 this->flush_rx_fifo();
ianmcc 0:7313e63394c3 63 this->write_register(NRF24L01P_EN_AA, 0x3F);
ianmcc 0:7313e63394c3 64 this->write_register(NRF24L01P_EN_RXADDR, 0x03);
ianmcc 0:7313e63394c3 65 this->write_register(NRF24L01P_SETUP_AW, 0x03);
ianmcc 0:7313e63394c3 66 this->write_register(NRF24L01P_SETUP_RETR, 0x03);
ianmcc 0:7313e63394c3 67 this->write_register(NRF24L01P_RF_CH, 0x02);
ianmcc 3:39e8335cce5d 68 this->write_register(NRF24L01P_RF_SETUP, 0x0F);
ianmcc 0:7313e63394c3 69 this->write_register(NRF24L01P_STATUS, 0x0E);
ianmcc 0:7313e63394c3 70 this->write_register_40(NRF24L01P_RX_ADDR_P0, 0xE7E7E7E7E7ULL);
ianmcc 0:7313e63394c3 71 this->write_register_40(NRF24L01P_RX_ADDR_P1, 0xC2C2C2C2C2ULL);
ianmcc 0:7313e63394c3 72 this->write_register(NRF24L01P_RX_ADDR_P2, 0xC3);
ianmcc 0:7313e63394c3 73 this->write_register(NRF24L01P_RX_ADDR_P3, 0xC4);
ianmcc 0:7313e63394c3 74 this->write_register(NRF24L01P_RX_ADDR_P4, 0xC4);
ianmcc 0:7313e63394c3 75 this->write_register(NRF24L01P_RX_ADDR_P5, 0xC5);
ianmcc 0:7313e63394c3 76 this->write_register_40(NRF24L01P_TX_ADDR, 0xE7E7E7E7E7ULL);
ianmcc 0:7313e63394c3 77 this->write_register(NRF24L01P_RX_PW_P0, 0x00);
ianmcc 0:7313e63394c3 78 this->write_register(NRF24L01P_RX_PW_P1, 0x00);
ianmcc 0:7313e63394c3 79 this->write_register(NRF24L01P_RX_PW_P2, 0x00);
ianmcc 0:7313e63394c3 80 this->write_register(NRF24L01P_RX_PW_P3, 0x00);
ianmcc 0:7313e63394c3 81 this->write_register(NRF24L01P_RX_PW_P4, 0x00);
ianmcc 0:7313e63394c3 82 this->write_register(NRF24L01P_RX_PW_P5, 0x00);
ianmcc 0:7313e63394c3 83 this->write_register(NRF24L01P_FIFO_STATUS, 0x00);
ianmcc 0:7313e63394c3 84 this->write_register(NRF24L01P_DYNPD, 0x00);
ianmcc 0:7313e63394c3 85 this->write_register(NRF24L01P_FEATURE, 0x00);
ianmcc 0:7313e63394c3 86 }
ianmcc 0:7313e63394c3 87
ianmcc 0:7313e63394c3 88 void
ianmcc 0:7313e63394c3 89 nRF24L01P::set_spi_frequency(long Freq)
ianmcc 0:7313e63394c3 90 {
ianmcc 0:7313e63394c3 91 Spi.frequency(Freq);
ianmcc 0:7313e63394c3 92 }
ianmcc 0:7313e63394c3 93
ianmcc 0:7313e63394c3 94 void
ianmcc 0:7313e63394c3 95 nRF24L01P::set_air_data_rate(int Rate)
ianmcc 0:7313e63394c3 96 {
ianmcc 0:7313e63394c3 97 char r = 0;
ianmcc 0:7313e63394c3 98 if (Rate == 250)
ianmcc 0:7313e63394c3 99 r = 0x20;
ianmcc 0:7313e63394c3 100 else if (Rate == 1000)
ianmcc 0:7313e63394c3 101 r = 0x00;
ianmcc 0:7313e63394c3 102 else if (Rate == 2000)
ianmcc 0:7313e63394c3 103 r = 0x04;
ianmcc 0:7313e63394c3 104 char c = this->read_register(NRF24L01P_RF_SETUP);
ianmcc 0:7313e63394c3 105 this->write_register(NRF24L01P_RF_SETUP, (c & 0xDB) | r);
ianmcc 0:7313e63394c3 106 }
ianmcc 0:7313e63394c3 107
ianmcc 0:7313e63394c3 108 void
ianmcc 0:7313e63394c3 109 nRF24L01P::set_channel(int Channel)
ianmcc 0:7313e63394c3 110 {
ianmcc 0:7313e63394c3 111 char c = Channel;
ianmcc 0:7313e63394c3 112 c = c & 0x7F;
ianmcc 0:7313e63394c3 113 this->write_register(NRF24L01P_RF_CH, c);
ianmcc 0:7313e63394c3 114 }
ianmcc 0:7313e63394c3 115
ianmcc 0:7313e63394c3 116 bool
ianmcc 0:7313e63394c3 117 nRF24L01P::received_power_detector()
ianmcc 0:7313e63394c3 118 {
ianmcc 0:7313e63394c3 119 return this->read_register(NRF24L01P_RPD) == 0x01;
ianmcc 0:7313e63394c3 120 }
ianmcc 0:7313e63394c3 121
ianmcc 0:7313e63394c3 122 void
ianmcc 0:7313e63394c3 123 nRF24L01P::set_tx_power(int Power)
ianmcc 0:7313e63394c3 124 {
ianmcc 0:7313e63394c3 125 char p = 0;
ianmcc 0:7313e63394c3 126 if (Power == 0)
ianmcc 0:7313e63394c3 127 p = 0x03;
ianmcc 1:cd113026825f 128 else if (Power == -6)
ianmcc 0:7313e63394c3 129 p = 0x02;
ianmcc 0:7313e63394c3 130 else if (Power == -12)
ianmcc 0:7313e63394c3 131 p = 0x01;
ianmcc 0:7313e63394c3 132 else if (Power == -18)
ianmcc 0:7313e63394c3 133 p = 0x00;
ianmcc 0:7313e63394c3 134 char c = this->read_register(NRF24L01P_RF_SETUP);
ianmcc 0:7313e63394c3 135 this->write_register(NRF24L01P_RF_SETUP, (c & 0xFC) | p);
ianmcc 0:7313e63394c3 136 }
ianmcc 0:7313e63394c3 137
ianmcc 0:7313e63394c3 138 void
ianmcc 0:7313e63394c3 139 nRF24L01P::enable_dynamic_payload(int Pipe, bool Enable)
ianmcc 0:7313e63394c3 140 {
ianmcc 0:7313e63394c3 141 char Mask = 1 << Pipe;
ianmcc 0:7313e63394c3 142 char c = this->read_register(NRF24L01P_DYNPD);
ianmcc 0:7313e63394c3 143 if (Enable)
ianmcc 0:7313e63394c3 144 c = c | Mask;
ianmcc 0:7313e63394c3 145 else
ianmcc 0:7313e63394c3 146 c = c & ~Mask;
ianmcc 0:7313e63394c3 147 this->write_register(NRF24L01P_DYNPD, c);
ianmcc 0:7313e63394c3 148 }
ianmcc 0:7313e63394c3 149
ianmcc 0:7313e63394c3 150 void
ianmcc 0:7313e63394c3 151 nRF24L01P::enable_ack_payload(bool Enable)
ianmcc 0:7313e63394c3 152 {
ianmcc 0:7313e63394c3 153 char c = this->read_register(NRF24L01P_FEATURE);
ianmcc 0:7313e63394c3 154 this->write_register(NRF24L01P_FEATURE, Enable ? (c | 0x02) : (c & 0xFD));
ianmcc 0:7313e63394c3 155 }
ianmcc 0:7313e63394c3 156
ianmcc 0:7313e63394c3 157 void
ianmcc 0:7313e63394c3 158 nRF24L01P::enable_no_ack(bool Enable)
ianmcc 0:7313e63394c3 159 {
ianmcc 0:7313e63394c3 160 char c = this->read_register(NRF24L01P_FEATURE);
ianmcc 0:7313e63394c3 161 this->write_register(NRF24L01P_FEATURE, Enable ? (c | 0x01) : (c & 0xFE));
ianmcc 0:7313e63394c3 162 }
ianmcc 0:7313e63394c3 163
ianmcc 0:7313e63394c3 164 void
ianmcc 0:7313e63394c3 165 nRF24L01P::set_address_width(int Width)
ianmcc 0:7313e63394c3 166 {
ianmcc 0:7313e63394c3 167 char c = 0;
ianmcc 0:7313e63394c3 168 if (Width == 3)
ianmcc 0:7313e63394c3 169 c = 0x01;
ianmcc 0:7313e63394c3 170 else if (Width == 4)
ianmcc 0:7313e63394c3 171 c = 0x02;
ianmcc 0:7313e63394c3 172 else if (Width == 5)
ianmcc 0:7313e63394c3 173 c = 0x03;
ianmcc 0:7313e63394c3 174 this->write_register(NRF24L01P_SETUP_AW, c);
ianmcc 0:7313e63394c3 175 }
ianmcc 0:7313e63394c3 176
ianmcc 0:7313e63394c3 177 int
ianmcc 0:7313e63394c3 178 nRF24L01P::get_address_width()
ianmcc 0:7313e63394c3 179 {
ianmcc 0:7313e63394c3 180 int r = this->read_register(NRF24L01P_SETUP_AW);
ianmcc 0:7313e63394c3 181 switch (r & 0x03)
ianmcc 0:7313e63394c3 182 {
ianmcc 0:7313e63394c3 183 case 0x01 : return 3;
ianmcc 0:7313e63394c3 184 case 0x02 : return 4;
ianmcc 0:7313e63394c3 185 case 0x03 : return 5;
ianmcc 0:7313e63394c3 186 }
ianmcc 0:7313e63394c3 187 return 0;
ianmcc 0:7313e63394c3 188 }
ianmcc 0:7313e63394c3 189
ianmcc 0:7313e63394c3 190 void
ianmcc 0:7313e63394c3 191 nRF24L01P::set_rx_address(int Pipe, uint64_t Address)
ianmcc 0:7313e63394c3 192 {
ianmcc 0:7313e63394c3 193 if (Pipe < 0 || Pipe > 1)
ianmcc 0:7313e63394c3 194 error("RF24L01P::set_rx_address: invalid pipe");
ianmcc 0:7313e63394c3 195 this->write_register_40(NRF24L01P_RX_ADDR_P0+Pipe, Address);
ianmcc 0:7313e63394c3 196 }
ianmcc 0:7313e63394c3 197
ianmcc 0:7313e63394c3 198 void
ianmcc 0:7313e63394c3 199 nRF24L01P::set_rx_address_low(int Pipe, uint8_t Address)
ianmcc 0:7313e63394c3 200 {
ianmcc 0:7313e63394c3 201 this->write_register(NRF24L01P_RX_ADDR_P0+Pipe, Address);
ianmcc 0:7313e63394c3 202 }
ianmcc 0:7313e63394c3 203
ianmcc 0:7313e63394c3 204 void
ianmcc 0:7313e63394c3 205 nRF24L01P::set_rx_payload_bytes(int Pipe, int Bytes)
ianmcc 0:7313e63394c3 206 {
ianmcc 0:7313e63394c3 207 this->write_register(NRF24L01P_RX_PW_P0+Pipe, Bytes & 0x1F);
ianmcc 0:7313e63394c3 208 }
ianmcc 0:7313e63394c3 209
ianmcc 0:7313e63394c3 210 bool
ianmcc 0:7313e63394c3 211 nRF24L01P::is_rx_full()
ianmcc 0:7313e63394c3 212 {
ianmcc 0:7313e63394c3 213 return (this->read_register(NRF24L01P_FIFO_STATUS) & 0x02) != 0x00;
ianmcc 0:7313e63394c3 214 }
ianmcc 0:7313e63394c3 215
ianmcc 0:7313e63394c3 216 bool
ianmcc 0:7313e63394c3 217 nRF24L01P::is_rx_empty()
ianmcc 0:7313e63394c3 218 {
ianmcc 0:7313e63394c3 219 return (this->read_register(NRF24L01P_FIFO_STATUS) & 0x01) != 0x00;
ianmcc 0:7313e63394c3 220 }
ianmcc 0:7313e63394c3 221
ianmcc 0:7313e63394c3 222 bool
ianmcc 0:7313e63394c3 223 nRF24L01P::is_rx_ready()
ianmcc 0:7313e63394c3 224 {
ianmcc 0:7313e63394c3 225 return (this->read_register(NRF24L01P_STATUS) & 0x40) != 0x00;
ianmcc 0:7313e63394c3 226 }
ianmcc 0:7313e63394c3 227
ianmcc 0:7313e63394c3 228 void
ianmcc 0:7313e63394c3 229 nRF24L01P::clear_rx_ready()
ianmcc 0:7313e63394c3 230 {
ianmcc 0:7313e63394c3 231 char c = this->read_register(NRF24L01P_STATUS);
ianmcc 0:7313e63394c3 232 this->write_register(NRF24L01P_STATUS, c | 0x40);
ianmcc 0:7313e63394c3 233 }
ianmcc 0:7313e63394c3 234
ianmcc 0:7313e63394c3 235 void
ianmcc 0:7313e63394c3 236 nRF24L01P::set_interrupt_rx_ready(bool Enable)
ianmcc 0:7313e63394c3 237 {
ianmcc 0:7313e63394c3 238 char c = this->read_register(NRF24L01P_CONFIG);
ianmcc 0:7313e63394c3 239 this->write_register(NRF24L01P_CONFIG, Enable ? (c & 0xBF) : (c | 0x40));
ianmcc 0:7313e63394c3 240 }
ianmcc 0:7313e63394c3 241
ianmcc 0:7313e63394c3 242 bool
ianmcc 0:7313e63394c3 243 nRF24L01P::is_tx_full()
ianmcc 0:7313e63394c3 244 {
ianmcc 0:7313e63394c3 245 return (this->read_register(NRF24L01P_FIFO_STATUS) & 0x20) != 0x00;
ianmcc 0:7313e63394c3 246 }
ianmcc 0:7313e63394c3 247
ianmcc 0:7313e63394c3 248 bool
ianmcc 0:7313e63394c3 249 nRF24L01P::is_tx_empty()
ianmcc 0:7313e63394c3 250 {
ianmcc 0:7313e63394c3 251 return (this->read_register(NRF24L01P_FIFO_STATUS) & 0x10) != 0x00;
ianmcc 0:7313e63394c3 252 }
ianmcc 0:7313e63394c3 253
ianmcc 0:7313e63394c3 254 bool
ianmcc 0:7313e63394c3 255 nRF24L01P::is_tx_sent()
ianmcc 0:7313e63394c3 256 {
ianmcc 0:7313e63394c3 257 return (this->read_register(NRF24L01P_STATUS) & 0x20) != 0x00;
ianmcc 0:7313e63394c3 258 }
ianmcc 0:7313e63394c3 259
ianmcc 0:7313e63394c3 260 void
ianmcc 0:7313e63394c3 261 nRF24L01P::clear_tx_sent()
ianmcc 0:7313e63394c3 262 {
ianmcc 0:7313e63394c3 263 char c = this->read_register(NRF24L01P_STATUS);
ianmcc 0:7313e63394c3 264 this->write_register(NRF24L01P_STATUS, c | 0x20);
ianmcc 0:7313e63394c3 265 }
ianmcc 0:7313e63394c3 266
ianmcc 0:7313e63394c3 267 void
ianmcc 0:7313e63394c3 268 nRF24L01P::set_interrupt_tx(bool Enable)
ianmcc 0:7313e63394c3 269 {
ianmcc 0:7313e63394c3 270 char c = this->read_register(NRF24L01P_CONFIG);
ianmcc 0:7313e63394c3 271 this->write_register(NRF24L01P_CONFIG, Enable ? (c & 0xDF) : (c | 0x20));
ianmcc 0:7313e63394c3 272 }
ianmcc 0:7313e63394c3 273
ianmcc 0:7313e63394c3 274 void
ianmcc 0:7313e63394c3 275 nRF24L01P::set_retransmit_delay(int Delay)
ianmcc 0:7313e63394c3 276 {
ianmcc 0:7313e63394c3 277 }
ianmcc 0:7313e63394c3 278
ianmcc 0:7313e63394c3 279 bool
ianmcc 0:7313e63394c3 280 nRF24L01P::is_max_rt()
ianmcc 0:7313e63394c3 281 {
ianmcc 0:7313e63394c3 282 return (this->read_register(NRF24L01P_STATUS) & 0x10) != 0x00;
ianmcc 0:7313e63394c3 283 }
ianmcc 0:7313e63394c3 284
ianmcc 0:7313e63394c3 285 void
ianmcc 0:7313e63394c3 286 nRF24L01P::clear_max_rt()
ianmcc 0:7313e63394c3 287 {
ianmcc 0:7313e63394c3 288 char c = this->read_register(NRF24L01P_STATUS);
ianmcc 0:7313e63394c3 289 this->write_register(NRF24L01P_STATUS, c | 0x10);
ianmcc 0:7313e63394c3 290 }
ianmcc 0:7313e63394c3 291
ianmcc 0:7313e63394c3 292 void
ianmcc 0:7313e63394c3 293 nRF24L01P::set_interrupt_max_rt(bool Enable)
ianmcc 0:7313e63394c3 294 {
ianmcc 0:7313e63394c3 295 char c = this->read_register(NRF24L01P_CONFIG);
ianmcc 0:7313e63394c3 296 this->write_register(NRF24L01P_CONFIG, Enable ? (c & 0xEF) : (c | 0x10));
ianmcc 0:7313e63394c3 297 }
ianmcc 0:7313e63394c3 298
ianmcc 0:7313e63394c3 299 void
ianmcc 0:7313e63394c3 300 nRF24L01P::set_crc_width(int Width)
ianmcc 0:7313e63394c3 301 {
ianmcc 0:7313e63394c3 302 char c = this->read_register(NRF24L01P_CONFIG);
ianmcc 0:7313e63394c3 303 this->write_register(NRF24L01P_CONFIG, Width == 1 ? (c & 0xFB) : (c | 0x04));
ianmcc 0:7313e63394c3 304 }
ianmcc 0:7313e63394c3 305
ianmcc 0:7313e63394c3 306 void
ianmcc 0:7313e63394c3 307 nRF24L01P::enable_crc(bool Enable)
ianmcc 0:7313e63394c3 308 {
ianmcc 0:7313e63394c3 309 char c = this->read_register(NRF24L01P_CONFIG);
ianmcc 0:7313e63394c3 310 this->write_register(NRF24L01P_CONFIG, Enable ? (c | 0x08) : (c & 0xF7));
ianmcc 0:7313e63394c3 311 }
ianmcc 0:7313e63394c3 312
ianmcc 0:7313e63394c3 313
ianmcc 0:7313e63394c3 314 void
ianmcc 0:7313e63394c3 315 nRF24L01P::set_power_up()
ianmcc 0:7313e63394c3 316 {
ianmcc 0:7313e63394c3 317 char c = this->read_register(NRF24L01P_CONFIG);
ianmcc 0:7313e63394c3 318 this->write_register(NRF24L01P_CONFIG, c | 0x02);
ianmcc 0:7313e63394c3 319 }
ianmcc 0:7313e63394c3 320
ianmcc 0:7313e63394c3 321 void
ianmcc 0:7313e63394c3 322 nRF24L01P::set_power_down()
ianmcc 0:7313e63394c3 323 {
ianmcc 0:7313e63394c3 324 char c = this->read_register(NRF24L01P_CONFIG);
ianmcc 0:7313e63394c3 325 this->write_register(NRF24L01P_CONFIG, c & 0xFD);
ianmcc 0:7313e63394c3 326 }
ianmcc 0:7313e63394c3 327
ianmcc 0:7313e63394c3 328 void
ianmcc 0:7313e63394c3 329 nRF24L01P::set_prx_mode()
ianmcc 0:7313e63394c3 330 {
ianmcc 0:7313e63394c3 331 char c = this->read_register(NRF24L01P_CONFIG);
ianmcc 0:7313e63394c3 332 this->write_register(NRF24L01P_CONFIG, c | 0x01);
ianmcc 0:7313e63394c3 333 }
ianmcc 0:7313e63394c3 334
ianmcc 0:7313e63394c3 335 void
ianmcc 0:7313e63394c3 336 nRF24L01P::set_ptx_mode()
ianmcc 0:7313e63394c3 337 {
ianmcc 0:7313e63394c3 338 char c = this->read_register(NRF24L01P_CONFIG);
ianmcc 0:7313e63394c3 339 this->write_register(NRF24L01P_CONFIG, c & 0xFE);
ianmcc 0:7313e63394c3 340 }
ianmcc 0:7313e63394c3 341
ianmcc 0:7313e63394c3 342
ianmcc 0:7313e63394c3 343 void
ianmcc 0:7313e63394c3 344 nRF24L01P::set_auto_acknowledge(int Pipe, bool Enable)
ianmcc 0:7313e63394c3 345 {
ianmcc 0:7313e63394c3 346 char c = this->read_register(NRF24L01P_EN_AA);
ianmcc 0:7313e63394c3 347 char Mask = 1 << Pipe;
ianmcc 0:7313e63394c3 348 this->write_register(NRF24L01P_EN_AA, Enable ? (c | Mask) : (c & ~Mask));
ianmcc 0:7313e63394c3 349 }
ianmcc 0:7313e63394c3 350
ianmcc 0:7313e63394c3 351 void
ianmcc 0:7313e63394c3 352 nRF24L01P::enable_rx_pipe(int Pipe, bool Enable)
ianmcc 0:7313e63394c3 353 {
ianmcc 0:7313e63394c3 354 char c = this->read_register(NRF24L01P_EN_RXADDR);
ianmcc 0:7313e63394c3 355 char Mask = 1 << Pipe;
ianmcc 0:7313e63394c3 356 this->write_register(NRF24L01P_EN_RXADDR, Enable ? (c | Mask) : (c & ~Mask));
ianmcc 0:7313e63394c3 357 }
ianmcc 0:7313e63394c3 358
ianmcc 0:7313e63394c3 359
ianmcc 0:7313e63394c3 360 int
ianmcc 0:7313e63394c3 361 nRF24L01P::which_rx_pipe()
ianmcc 0:7313e63394c3 362 {
ianmcc 0:7313e63394c3 363 return (this->read_register(NRF24L01P_STATUS) & 0x0E) >> 1;
ianmcc 0:7313e63394c3 364 }
ianmcc 0:7313e63394c3 365
ianmcc 0:7313e63394c3 366 bool
ianmcc 0:7313e63394c3 367 nRF24L01P::tx_full()
ianmcc 0:7313e63394c3 368 {
ianmcc 0:7313e63394c3 369 return this->read_register(NRF24L01P_STATUS) & 0x01;
ianmcc 0:7313e63394c3 370 }
ianmcc 0:7313e63394c3 371
ianmcc 0:7313e63394c3 372 int
ianmcc 0:7313e63394c3 373 nRF24L01P::num_lost_packets()
ianmcc 0:7313e63394c3 374 {
ianmcc 0:7313e63394c3 375 return (this->read_register(NRF24L01P_OBSERVE_TX) & 0xF0) >> 4;
ianmcc 0:7313e63394c3 376 }
ianmcc 0:7313e63394c3 377
ianmcc 0:7313e63394c3 378 int
ianmcc 0:7313e63394c3 379 nRF24L01P::num_retransmitted_packets()
ianmcc 0:7313e63394c3 380 {
ianmcc 0:7313e63394c3 381 return this->read_register(NRF24L01P_OBSERVE_TX) & 0x0F;
ianmcc 0:7313e63394c3 382 }
ianmcc 0:7313e63394c3 383
ianmcc 0:7313e63394c3 384 void
ianmcc 0:7313e63394c3 385 nRF24L01P::set_tx_address(uint64_t Address)
ianmcc 0:7313e63394c3 386 {
ianmcc 0:7313e63394c3 387 this->write_register_40(NRF24L01P_TX_ADDR, Address);
ianmcc 0:7313e63394c3 388 }
ianmcc 0:7313e63394c3 389
ianmcc 0:7313e63394c3 390 // commands
ianmcc 0:7313e63394c3 391
ianmcc 0:7313e63394c3 392 int
ianmcc 0:7313e63394c3 393 nRF24L01P::read_register(int Register)
ianmcc 0:7313e63394c3 394 {
ianmcc 0:7313e63394c3 395 NCS = 0;
ianmcc 0:7313e63394c3 396 Spi.write(NRF24L01P_CMD_R_REGISTER | Register);
ianmcc 0:7313e63394c3 397 int Result = Spi.write(NRF24L01P_CMD_NOP);
ianmcc 0:7313e63394c3 398 NCS = 1;
ianmcc 0:7313e63394c3 399 return Result;
ianmcc 0:7313e63394c3 400 }
ianmcc 0:7313e63394c3 401
ianmcc 0:7313e63394c3 402 int
ianmcc 0:7313e63394c3 403 nRF24L01P::read_register_n(int Register, char* Buf, int Bytes)
ianmcc 0:7313e63394c3 404 {
ianmcc 0:7313e63394c3 405 NCS = 0;
ianmcc 0:7313e63394c3 406 Spi.write(NRF24L01P_CMD_R_REGISTER | Register);
ianmcc 0:7313e63394c3 407 for (int i = 0; i < Bytes; ++i)
ianmcc 0:7313e63394c3 408 {
ianmcc 0:7313e63394c3 409 *Buf++ = Spi.write(NRF24L01P_CMD_NOP);
ianmcc 0:7313e63394c3 410 }
ianmcc 0:7313e63394c3 411 NCS = 1;
ianmcc 0:7313e63394c3 412 return 0;
ianmcc 0:7313e63394c3 413 }
ianmcc 0:7313e63394c3 414
ianmcc 0:7313e63394c3 415 int
ianmcc 0:7313e63394c3 416 nRF24L01P::write_register(int Register, char x)
ianmcc 0:7313e63394c3 417 {
ianmcc 0:7313e63394c3 418 NCS = 0;
ianmcc 0:7313e63394c3 419 Spi.write(NRF24L01P_CMD_W_REGISTER | Register);
ianmcc 0:7313e63394c3 420 Spi.write(x);
ianmcc 0:7313e63394c3 421 NCS = 1;
ianmcc 0:7313e63394c3 422 return 0;
ianmcc 0:7313e63394c3 423 }
ianmcc 0:7313e63394c3 424
ianmcc 0:7313e63394c3 425 int
ianmcc 0:7313e63394c3 426 nRF24L01P::write_register_16(int Register, uint16_t x)
ianmcc 0:7313e63394c3 427 {
ianmcc 0:7313e63394c3 428 NCS = 0;
ianmcc 0:7313e63394c3 429 Spi.write(NRF24L01P_CMD_W_REGISTER | Register);
ianmcc 0:7313e63394c3 430 Spi.write(x & 0xFF);
ianmcc 0:7313e63394c3 431 Spi.write((x >> 8) & 0xFF);
ianmcc 0:7313e63394c3 432 NCS = 1;
ianmcc 0:7313e63394c3 433 return 0;
ianmcc 0:7313e63394c3 434 }
ianmcc 0:7313e63394c3 435
ianmcc 0:7313e63394c3 436 int64_t
ianmcc 0:7313e63394c3 437 nRF24L01P::write_register_40(int Register, uint64_t x)
ianmcc 0:7313e63394c3 438 {
ianmcc 0:7313e63394c3 439 NCS = 0;
ianmcc 0:7313e63394c3 440 Spi.write(NRF24L01P_CMD_W_REGISTER | Register);
ianmcc 0:7313e63394c3 441 Spi.write(x & 0xFF);
ianmcc 0:7313e63394c3 442 x = x >> 8;
ianmcc 0:7313e63394c3 443 Spi.write(x & 0xFF);
ianmcc 0:7313e63394c3 444 x = x >> 8;
ianmcc 0:7313e63394c3 445 Spi.write(x & 0xFF);
ianmcc 0:7313e63394c3 446 x = x >> 8;
ianmcc 0:7313e63394c3 447 Spi.write(x & 0xFF);
ianmcc 0:7313e63394c3 448 x = x >> 8;
ianmcc 0:7313e63394c3 449 Spi.write(x & 0xFF);
ianmcc 0:7313e63394c3 450 NCS = 1;
ianmcc 0:7313e63394c3 451 return 0;
ianmcc 0:7313e63394c3 452 }
ianmcc 0:7313e63394c3 453
ianmcc 0:7313e63394c3 454 int
ianmcc 0:7313e63394c3 455 nRF24L01P::write_register_bytes(int Register, char const* Buf, int Bytes)
ianmcc 0:7313e63394c3 456 {
ianmcc 0:7313e63394c3 457 NCS = 0;
ianmcc 0:7313e63394c3 458 Spi.write(NRF24L01P_CMD_W_REGISTER | Register);
ianmcc 0:7313e63394c3 459 for (int i = 0; i < Bytes; ++i)
ianmcc 0:7313e63394c3 460 {
ianmcc 0:7313e63394c3 461 Spi.write(*Buf++);
ianmcc 0:7313e63394c3 462 }
ianmcc 0:7313e63394c3 463 NCS = 1;
ianmcc 0:7313e63394c3 464 return 0;
ianmcc 0:7313e63394c3 465 }
ianmcc 0:7313e63394c3 466
ianmcc 0:7313e63394c3 467 void
ianmcc 0:7313e63394c3 468 nRF24L01P::write_tx_payload(char const* Buf, int Bytes)
ianmcc 0:7313e63394c3 469 {
ianmcc 0:7313e63394c3 470 NCS = 0;
ianmcc 0:7313e63394c3 471 Spi.write(NRF24L01P_CMD_W_TX_PAYLOAD);
ianmcc 0:7313e63394c3 472 for (int i = 0; i < Bytes; ++i)
ianmcc 0:7313e63394c3 473 {
ianmcc 0:7313e63394c3 474 Spi.write(*Buf++);
ianmcc 0:7313e63394c3 475 }
ianmcc 0:7313e63394c3 476 NCS = 1;
ianmcc 0:7313e63394c3 477 }
ianmcc 0:7313e63394c3 478
ianmcc 0:7313e63394c3 479 void
ianmcc 0:7313e63394c3 480 nRF24L01P::write_tx_payload_no_ack(char const* Buf, int Bytes)
ianmcc 0:7313e63394c3 481 {
ianmcc 0:7313e63394c3 482 NCS = 0;
ianmcc 0:7313e63394c3 483 Spi.write(NRF24L01P_CMD_W_TX_PYLD_NO_ACK);
ianmcc 0:7313e63394c3 484 for (int i = 0; i < Bytes; ++i)
ianmcc 0:7313e63394c3 485 {
ianmcc 0:7313e63394c3 486 Spi.write(*Buf++);
ianmcc 0:7313e63394c3 487 }
ianmcc 0:7313e63394c3 488 NCS = 1;
ianmcc 0:7313e63394c3 489 }
ianmcc 0:7313e63394c3 490
ianmcc 0:7313e63394c3 491 void
ianmcc 0:7313e63394c3 492 nRF24L01P::flush_tx_fifo()
ianmcc 0:7313e63394c3 493 {
ianmcc 0:7313e63394c3 494 NCS = 0;
ianmcc 0:7313e63394c3 495 Spi.write(NRF24L01P_CMD_FLUSH_TX);
ianmcc 0:7313e63394c3 496 NCS = 1;
ianmcc 0:7313e63394c3 497 }
ianmcc 0:7313e63394c3 498
ianmcc 0:7313e63394c3 499 void
ianmcc 0:7313e63394c3 500 nRF24L01P::reuse_tx_payload()
ianmcc 0:7313e63394c3 501 {
ianmcc 0:7313e63394c3 502 NCS = 0;
ianmcc 0:7313e63394c3 503 Spi.write(NRF24L01P_CMD_REUSE_TX_PL);
ianmcc 0:7313e63394c3 504 NCS = 1;
ianmcc 0:7313e63394c3 505 }
ianmcc 0:7313e63394c3 506
ianmcc 0:7313e63394c3 507 int
ianmcc 0:7313e63394c3 508 nRF24L01P::rx_payload_width()
ianmcc 0:7313e63394c3 509 {
ianmcc 0:7313e63394c3 510 NCS = 0;
ianmcc 0:7313e63394c3 511 Spi.write(NRF24L01P_CMD_R_RX_PL_WID);
ianmcc 0:7313e63394c3 512 int Result = Spi.write(NRF24L01P_CMD_NOP);
ianmcc 0:7313e63394c3 513 NCS = 1;
ianmcc 0:7313e63394c3 514 return Result;
ianmcc 0:7313e63394c3 515
ianmcc 0:7313e63394c3 516 }
ianmcc 0:7313e63394c3 517
ianmcc 0:7313e63394c3 518 void
ianmcc 0:7313e63394c3 519 nRF24L01P::read_rx_payload(char* Buf, int Bytes)
ianmcc 0:7313e63394c3 520 {
ianmcc 0:7313e63394c3 521 NCS = 0;
ianmcc 0:7313e63394c3 522 Spi.write(NRF24L01P_CMD_R_RX_PAYLOAD);
ianmcc 0:7313e63394c3 523 for (int i = 0; i < Bytes; ++i)
ianmcc 0:7313e63394c3 524 {
ianmcc 0:7313e63394c3 525 *Buf++ = Spi.write(NRF24L01P_CMD_NOP);
ianmcc 0:7313e63394c3 526 }
ianmcc 0:7313e63394c3 527 NCS = 1;
ianmcc 0:7313e63394c3 528 }
ianmcc 0:7313e63394c3 529
ianmcc 0:7313e63394c3 530 int
ianmcc 0:7313e63394c3 531 nRF24L01P::read_rx_payload(char* Buf)
ianmcc 0:7313e63394c3 532 {
ianmcc 0:7313e63394c3 533 this->read_rx_payload(Buf, this->rx_payload_width());
ianmcc 0:7313e63394c3 534 return 0;
ianmcc 0:7313e63394c3 535 }
ianmcc 0:7313e63394c3 536
ianmcc 0:7313e63394c3 537 void
ianmcc 0:7313e63394c3 538 nRF24L01P::flush_rx_fifo()
ianmcc 0:7313e63394c3 539 {
ianmcc 0:7313e63394c3 540 NCS = 0;
ianmcc 0:7313e63394c3 541 Spi.write(NRF24L01P_CMD_FLUSH_RX);
ianmcc 0:7313e63394c3 542 NCS = 1;
ianmcc 0:7313e63394c3 543 }
ianmcc 0:7313e63394c3 544
ianmcc 0:7313e63394c3 545 void
ianmcc 0:7313e63394c3 546 nRF24L01P::write_ack_payload(int Pipe, char const* Buf, int Bytes)
ianmcc 0:7313e63394c3 547 {
ianmcc 0:7313e63394c3 548 NCS = 0;
ianmcc 0:7313e63394c3 549 Spi.write(NRF24L01P_CMD_W_ACK_PAYLOAD);
ianmcc 0:7313e63394c3 550 for (int i = 0; i < Bytes; ++i)
ianmcc 0:7313e63394c3 551 {
ianmcc 0:7313e63394c3 552 Spi.write(*Buf++);
ianmcc 0:7313e63394c3 553 }
ianmcc 0:7313e63394c3 554 NCS = 1;
ianmcc 0:7313e63394c3 555 }