Hugo Zijlmans / Mbed 2 deprecated BLDC

Dependencies:   mbed

UART0.c@2:f034e862af1f, 2010-12-02 (annotated)

Committer:
hugozijlmans
Date:
Thu Dec 02 20:55:45 2010 +0000
Revision:
2:f034e862af1f
Added UART0 support over USB mBed1768

Who changed what in which revision?

UserRevisionLine numberNew contents of line
hugozijlmans 2:f034e862af1f 1 #include "LPC17xx.h"
hugozijlmans 2:f034e862af1f 2 #include "core_cm3.h"
hugozijlmans 2:f034e862af1f 3 #include "cmsis_nvic.h"
hugozijlmans 2:f034e862af1f 4 #include "UART0.h"
hugozijlmans 2:f034e862af1f 5 #include "main.h"
hugozijlmans 2:f034e862af1f 6 #include "LPC1768.h"
hugozijlmans 2:f034e862af1f 7
hugozijlmans 2:f034e862af1f 8 void UART0_interrupt_enable(void) {
hugozijlmans 2:f034e862af1f 9
hugozijlmans 2:f034e862af1f 10 // Enable UART0 interrupt
hugozijlmans 2:f034e862af1f 11 NVIC_EnableIRQ(UART0_IRQn);
hugozijlmans 2:f034e862af1f 12 }
hugozijlmans 2:f034e862af1f 13
hugozijlmans 2:f034e862af1f 14 void UART0_interrupt_disable(void) {
hugozijlmans 2:f034e862af1f 15
hugozijlmans 2:f034e862af1f 16 // Disable UART0 interrupt
hugozijlmans 2:f034e862af1f 17 NVIC_DisableIRQ(UART0_IRQn);
hugozijlmans 2:f034e862af1f 18 }
hugozijlmans 2:f034e862af1f 19
hugozijlmans 2:f034e862af1f 20 void UART0_IRQHandler(void) {
hugozijlmans 2:f034e862af1f 21
hugozijlmans 2:f034e862af1f 22 // Determine the cause of the interrupt
hugozijlmans 2:f034e862af1f 23
hugozijlmans 2:f034e862af1f 24 // If THRE then buffer is empty
hugozijlmans 2:f034e862af1f 25 if ((U0IIR & 0x2) == 0x2)
hugozijlmans 2:f034e862af1f 26 i_flags.UART0_tx_idle = 1;
hugozijlmans 2:f034e862af1f 27
hugozijlmans 2:f034e862af1f 28 // If receive buffer contains a byte
hugozijlmans 2:f034e862af1f 29 if ((U0IIR & 0x8) == 0x8) {
hugozijlmans 2:f034e862af1f 30 i_flags.UART0_rx_idle = 0;
hugozijlmans 2:f034e862af1f 31 UART0_rx_interrupt_disable();
hugozijlmans 2:f034e862af1f 32 }
hugozijlmans 2:f034e862af1f 33
hugozijlmans 2:f034e862af1f 34 // Clear the UART0 interrupt
hugozijlmans 2:f034e862af1f 35 NVIC_ClearPendingIRQ(UART0_IRQn);
hugozijlmans 2:f034e862af1f 36
hugozijlmans 2:f034e862af1f 37 }
hugozijlmans 2:f034e862af1f 38
hugozijlmans 2:f034e862af1f 39 void UART0_init(void) {
hugozijlmans 2:f034e862af1f 40
hugozijlmans 2:f034e862af1f 41 // Set UART0 interrupt priority
hugozijlmans 2:f034e862af1f 42 NVIC_SetPriority(UART0_IRQn, 12);
hugozijlmans 2:f034e862af1f 43
hugozijlmans 2:f034e862af1f 44 // Set RXD0/TXD0 to function UART0
hugozijlmans 2:f034e862af1f 45 PINSEL0 &= ~(0xF0);
hugozijlmans 2:f034e862af1f 46 PINSEL0 |= 0x50;
hugozijlmans 2:f034e862af1f 47
hugozijlmans 2:f034e862af1f 48 // Select the UART0 clk
hugozijlmans 2:f034e862af1f 49 UART0_select_clk();
hugozijlmans 2:f034e862af1f 50
hugozijlmans 2:f034e862af1f 51 // Power the UART0
hugozijlmans 2:f034e862af1f 52 PCONP |= PCUART0;
hugozijlmans 2:f034e862af1f 53
hugozijlmans 2:f034e862af1f 54 // Set the UART0 Line Control Register
hugozijlmans 2:f034e862af1f 55 U0LCR &= 0;
hugozijlmans 2:f034e862af1f 56 U0LCR |= (1 << 1) | (1 << 0) // 8 bit
hugozijlmans 2:f034e862af1f 57 | (1 << 2) // 1 stop bit
hugozijlmans 2:f034e862af1f 58 | (0 << 3) // disable parity
hugozijlmans 2:f034e862af1f 59 | (1 << 5) | (0 << 4) // force 1 stick parity
hugozijlmans 2:f034e862af1f 60 | (0 << 6) // disable break control
hugozijlmans 2:f034e862af1f 61 | (1 << 7); // divisor access bit enable
hugozijlmans 2:f034e862af1f 62
hugozijlmans 2:f034e862af1f 63 // Set Baudrate 115200
hugozijlmans 2:f034e862af1f 64 // DIVADDVAL 3
hugozijlmans 2:f034e862af1f 65 // MULVAL 10
hugozijlmans 2:f034e862af1f 66 // DLL 40
hugozijlmans 2:f034e862af1f 67 // DLM 0
hugozijlmans 2:f034e862af1f 68 // Error 0.1603%
hugozijlmans 2:f034e862af1f 69
hugozijlmans 2:f034e862af1f 70 // Set Fractional Divider Register
hugozijlmans 2:f034e862af1f 71 U0FDR = 0xA3;
hugozijlmans 2:f034e862af1f 72
hugozijlmans 2:f034e862af1f 73 // Set Baudrate divisor
hugozijlmans 2:f034e862af1f 74 U0DLL = 40;
hugozijlmans 2:f034e862af1f 75 U0DLM = 0;
hugozijlmans 2:f034e862af1f 76
hugozijlmans 2:f034e862af1f 77 // Set divisor access bit 0
hugozijlmans 2:f034e862af1f 78 U0LCR &= ~(1 << 7);
hugozijlmans 2:f034e862af1f 79
hugozijlmans 2:f034e862af1f 80 // Set Fifo control register
hugozijlmans 2:f034e862af1f 81 U0FCR &= 0;
hugozijlmans 2:f034e862af1f 82 U0FCR |= (1 << 7) | (1 << 6) // RX Fifo DMA @ 14 bytes
hugozijlmans 2:f034e862af1f 83 | (1 << 3) // 1 stop bit
hugozijlmans 2:f034e862af1f 84 | (1 << 2) // disable parity
hugozijlmans 2:f034e862af1f 85 | (1 << 1) // disable break control
hugozijlmans 2:f034e862af1f 86 | (1 << 0); // divisor access bit enable
hugozijlmans 2:f034e862af1f 87
hugozijlmans 2:f034e862af1f 88 // Set interrupt enable sources THRE & RBR
hugozijlmans 2:f034e862af1f 89 U0IER |= 3;
hugozijlmans 2:f034e862af1f 90
hugozijlmans 2:f034e862af1f 91 // Set that the TX is idle
hugozijlmans 2:f034e862af1f 92 i_flags.UART0_tx_idle = 1;
hugozijlmans 2:f034e862af1f 93 // Set that the RX is idle
hugozijlmans 2:f034e862af1f 94 i_flags.UART0_rx_idle = 1;
hugozijlmans 2:f034e862af1f 95
hugozijlmans 2:f034e862af1f 96 // Connect the UART0 interrupt to the interrupt handler
hugozijlmans 2:f034e862af1f 97 NVIC_SetVector(UART0_IRQn, (uint32_t)&UART0_IRQHandler);
hugozijlmans 2:f034e862af1f 98
hugozijlmans 2:f034e862af1f 99 UART0_interrupt_enable();
hugozijlmans 2:f034e862af1f 100
hugozijlmans 2:f034e862af1f 101 }
hugozijlmans 2:f034e862af1f 102
hugozijlmans 2:f034e862af1f 103 void UART0_select_clk(void) {
hugozijlmans 2:f034e862af1f 104
hugozijlmans 2:f034e862af1f 105 // Including work-around described in errata.lpc1768.pdf R04
hugozijlmans 2:f034e862af1f 106
hugozijlmans 2:f034e862af1f 107 PLL0_disconnect();
hugozijlmans 2:f034e862af1f 108
hugozijlmans 2:f034e862af1f 109 PLL0_disable();
hugozijlmans 2:f034e862af1f 110
hugozijlmans 2:f034e862af1f 111 // Timer0 perhiperal clock select (01 = CCLK)
hugozijlmans 2:f034e862af1f 112 PCLKSEL0 &= ~(PCLK_UART0_1 | PCLK_UART0_0);
hugozijlmans 2:f034e862af1f 113 PCLKSEL0 |= PCLK_UART0_0;
hugozijlmans 2:f034e862af1f 114
hugozijlmans 2:f034e862af1f 115 PLL0_enable();
hugozijlmans 2:f034e862af1f 116
hugozijlmans 2:f034e862af1f 117 PLL0_connect();
hugozijlmans 2:f034e862af1f 118
hugozijlmans 2:f034e862af1f 119 }
hugozijlmans 2:f034e862af1f 120
hugozijlmans 2:f034e862af1f 121 void UART0_write(uint8_t byte) {
hugozijlmans 2:f034e862af1f 122
hugozijlmans 2:f034e862af1f 123 // Send byte to writebuffer
hugozijlmans 2:f034e862af1f 124 U0THR = byte;
hugozijlmans 2:f034e862af1f 125 }
hugozijlmans 2:f034e862af1f 126
hugozijlmans 2:f034e862af1f 127 uint8_t UART0_read(void) {
hugozijlmans 2:f034e862af1f 128
hugozijlmans 2:f034e862af1f 129 // Read the RX FIFO
hugozijlmans 2:f034e862af1f 130 uint8_t byte = U0RBR;
hugozijlmans 2:f034e862af1f 131
hugozijlmans 2:f034e862af1f 132 UART0_rx_interrupt_enable();
hugozijlmans 2:f034e862af1f 133
hugozijlmans 2:f034e862af1f 134 return byte;
hugozijlmans 2:f034e862af1f 135 }
hugozijlmans 2:f034e862af1f 136
hugozijlmans 2:f034e862af1f 137 void UART0_rx_interrupt_disable(void) {
hugozijlmans 2:f034e862af1f 138 U0IER &= ~(1);
hugozijlmans 2:f034e862af1f 139 }
hugozijlmans 2:f034e862af1f 140
hugozijlmans 2:f034e862af1f 141 void UART0_rx_interrupt_enable(void) {
hugozijlmans 2:f034e862af1f 142 U0IER |= 1;
hugozijlmans 2:f034e862af1f 143 }