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Dependents: UsbHostMAX3421E_Hello
cdcprolific.h@0:84353c479782, 2020-07-12 (annotated)
- Committer:
- hudakz
- Date:
- Sun Jul 12 20:39:26 2020 +0000
- Revision:
- 0:84353c479782
- Child:
- 1:2263e77400e9
MAX3421E-based USB Host Shield Library
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
hudakz | 0:84353c479782 | 1 | /* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved. |
hudakz | 0:84353c479782 | 2 | |
hudakz | 0:84353c479782 | 3 | This software may be distributed and modified under the terms of the GNU |
hudakz | 0:84353c479782 | 4 | General Public License version 2 (GPL2) as published by the Free Software |
hudakz | 0:84353c479782 | 5 | Foundation and appearing in the file GPL2.TXT included in the packaging of |
hudakz | 0:84353c479782 | 6 | this file. Please note that GPL2 Section 2[b] requires that all works based |
hudakz | 0:84353c479782 | 7 | on this software must also be made publicly available under the terms of |
hudakz | 0:84353c479782 | 8 | the GPL2 ("Copyleft"). |
hudakz | 0:84353c479782 | 9 | |
hudakz | 0:84353c479782 | 10 | Contact information |
hudakz | 0:84353c479782 | 11 | ------------------- |
hudakz | 0:84353c479782 | 12 | |
hudakz | 0:84353c479782 | 13 | Circuits At Home, LTD |
hudakz | 0:84353c479782 | 14 | Web : http://www.circuitsathome.com |
hudakz | 0:84353c479782 | 15 | e-mail : support@circuitsathome.com |
hudakz | 0:84353c479782 | 16 | */ |
hudakz | 0:84353c479782 | 17 | #if !defined(__CDCPROLIFIC_H__) |
hudakz | 0:84353c479782 | 18 | #define __CDCPROLIFIC_H__ |
hudakz | 0:84353c479782 | 19 | |
hudakz | 0:84353c479782 | 20 | #include "cdcacm.h" |
hudakz | 0:84353c479782 | 21 | |
hudakz | 0:84353c479782 | 22 | //#define PL2303_COMPAT // Uncomment it if you have compatibility problems |
hudakz | 0:84353c479782 | 23 | |
hudakz | 0:84353c479782 | 24 | #define PL_VID 0x067B |
hudakz | 0:84353c479782 | 25 | #define CHECK_PID(pid) ( pid != 0x2303 && pid != 0x0609 ) |
hudakz | 0:84353c479782 | 26 | |
hudakz | 0:84353c479782 | 27 | //#define PL_PID 0x0609 |
hudakz | 0:84353c479782 | 28 | |
hudakz | 0:84353c479782 | 29 | #define PROLIFIC_REV_H 0x0202 |
hudakz | 0:84353c479782 | 30 | #define PROLIFIC_REV_X 0x0300 |
hudakz | 0:84353c479782 | 31 | #define PROLIFIC_REV_HX_CHIP_D 0x0400 |
hudakz | 0:84353c479782 | 32 | #define PROLIFIC_REV_1 0x0001 |
hudakz | 0:84353c479782 | 33 | |
hudakz | 0:84353c479782 | 34 | #define kXOnChar '\x11' |
hudakz | 0:84353c479782 | 35 | #define kXOffChar '\x13' |
hudakz | 0:84353c479782 | 36 | |
hudakz | 0:84353c479782 | 37 | #define SPECIAL_SHIFT (5) |
hudakz | 0:84353c479782 | 38 | #define SPECIAL_MASK ((1<<SPECIAL_SHIFT) - 1) |
hudakz | 0:84353c479782 | 39 | #define STATE_ALL ( PD_RS232_S_MASK | PD_S_MASK ) |
hudakz | 0:84353c479782 | 40 | #define FLOW_RX_AUTO ( PD_RS232_A_RFR | PD_RS232_A_DTR | PD_RS232_A_RXO ) |
hudakz | 0:84353c479782 | 41 | #define FLOW_TX_AUTO ( PD_RS232_A_CTS | PD_RS232_A_DSR | PD_RS232_A_TXO | PD_RS232_A_DCD ) |
hudakz | 0:84353c479782 | 42 | #define CAN_BE_AUTO ( FLOW_RX_AUTO | FLOW_TX_AUTO ) |
hudakz | 0:84353c479782 | 43 | #define CAN_NOTIFY ( PD_RS232_N_MASK ) |
hudakz | 0:84353c479782 | 44 | #define EXTERNAL_MASK ( PD_S_MASK | (PD_RS232_S_MASK & ~PD_RS232_S_LOOP) ) |
hudakz | 0:84353c479782 | 45 | #define INTERNAL_DELAY ( PD_RS232_S_LOOP ) |
hudakz | 0:84353c479782 | 46 | #define DEFAULT_AUTO ( PD_RS232_A_DTR | PD_RS232_A_RFR | PD_RS232_A_CTS | PD_RS232_A_DSR ) |
hudakz | 0:84353c479782 | 47 | #define DEFAULT_NOTIFY 0x00 |
hudakz | 0:84353c479782 | 48 | #define DEFAULT_STATE ( PD_S_TX_ENABLE | PD_S_RX_ENABLE | PD_RS232_A_TXO | PD_RS232_A_RXO ) |
hudakz | 0:84353c479782 | 49 | |
hudakz | 0:84353c479782 | 50 | #define CONTINUE_SEND 1 |
hudakz | 0:84353c479782 | 51 | #define PAUSE_SEND 2 |
hudakz | 0:84353c479782 | 52 | |
hudakz | 0:84353c479782 | 53 | #define kRxAutoFlow ((UInt32)( PD_RS232_A_RFR | PD_RS232_A_DTR | PD_RS232_A_RXO )) |
hudakz | 0:84353c479782 | 54 | #define kTxAutoFlow ((UInt32)( PD_RS232_A_CTS | PD_RS232_A_DSR | PD_RS232_A_TXO | PD_RS232_A_DCD )) |
hudakz | 0:84353c479782 | 55 | #define kControl_StateMask ((UInt32)( PD_RS232_S_CTS | PD_RS232_S_DSR | PD_RS232_S_CAR | PD_RS232_S_RI )) |
hudakz | 0:84353c479782 | 56 | #define kRxQueueState ((UInt32)( PD_S_RXQ_EMPTY | PD_S_RXQ_LOW_WATER | PD_S_RXQ_HIGH_WATER | PD_S_RXQ_FULL )) |
hudakz | 0:84353c479782 | 57 | #define kTxQueueState ((UInt32)( PD_S_TXQ_EMPTY | PD_S_TXQ_LOW_WATER | PD_S_TXQ_HIGH_WATER | PD_S_TXQ_FULL )) |
hudakz | 0:84353c479782 | 58 | |
hudakz | 0:84353c479782 | 59 | #define kCONTROL_DTR 0x01 |
hudakz | 0:84353c479782 | 60 | #define kCONTROL_RTS 0x02 |
hudakz | 0:84353c479782 | 61 | |
hudakz | 0:84353c479782 | 62 | #define kStateTransientMask 0x74 |
hudakz | 0:84353c479782 | 63 | #define kBreakError 0x04 |
hudakz | 0:84353c479782 | 64 | #define kFrameError 0x10 |
hudakz | 0:84353c479782 | 65 | #define kParityError 0x20 |
hudakz | 0:84353c479782 | 66 | #define kOverrunError 0x40 |
hudakz | 0:84353c479782 | 67 | |
hudakz | 0:84353c479782 | 68 | #define kCTS 0x80 |
hudakz | 0:84353c479782 | 69 | #define kDSR 0x02 |
hudakz | 0:84353c479782 | 70 | #define kRI 0x08 |
hudakz | 0:84353c479782 | 71 | #define kDCD 0x01 |
hudakz | 0:84353c479782 | 72 | #define kHandshakeInMask ((UInt32)( PD_RS232_S_CTS | PD_RS232_S_DSR | PD_RS232_S_CAR | PD_RS232_S_RI )) |
hudakz | 0:84353c479782 | 73 | |
hudakz | 0:84353c479782 | 74 | #define VENDOR_WRITE_REQUEST_TYPE 0x40 |
hudakz | 0:84353c479782 | 75 | #define VENDOR_WRITE_REQUEST 0x01 |
hudakz | 0:84353c479782 | 76 | |
hudakz | 0:84353c479782 | 77 | #define VENDOR_READ_REQUEST_TYPE 0xc0 |
hudakz | 0:84353c479782 | 78 | #define VENDOR_READ_REQUEST 0x01 |
hudakz | 0:84353c479782 | 79 | |
hudakz | 0:84353c479782 | 80 | // Device Configuration Registers (DCR0, DCR1, DCR2) |
hudakz | 0:84353c479782 | 81 | #define SET_DCR0 0x00 |
hudakz | 0:84353c479782 | 82 | #define GET_DCR0 0x80 |
hudakz | 0:84353c479782 | 83 | #define DCR0_INIT 0x01 |
hudakz | 0:84353c479782 | 84 | #define DCR0_INIT_H 0x41 |
hudakz | 0:84353c479782 | 85 | #define DCR0_INIT_X 0x61 |
hudakz | 0:84353c479782 | 86 | |
hudakz | 0:84353c479782 | 87 | #define SET_DCR1 0x01 |
hudakz | 0:84353c479782 | 88 | #define GET_DCR1 0x81 |
hudakz | 0:84353c479782 | 89 | #define DCR1_INIT_H 0x80 |
hudakz | 0:84353c479782 | 90 | #define DCR1_INIT_X 0x00 |
hudakz | 0:84353c479782 | 91 | |
hudakz | 0:84353c479782 | 92 | #define SET_DCR2 0x02 |
hudakz | 0:84353c479782 | 93 | #define GET_DCR2 0x82 |
hudakz | 0:84353c479782 | 94 | #define DCR2_INIT_H 0x24 |
hudakz | 0:84353c479782 | 95 | #define DCR2_INIT_X 0x44 |
hudakz | 0:84353c479782 | 96 | |
hudakz | 0:84353c479782 | 97 | // On-chip Data Buffers: |
hudakz | 0:84353c479782 | 98 | #define RESET_DOWNSTREAM_DATA_PIPE 0x08 |
hudakz | 0:84353c479782 | 99 | #define RESET_UPSTREAM_DATA_PIPE 0x09 |
hudakz | 0:84353c479782 | 100 | |
hudakz | 0:84353c479782 | 101 | |
hudakz | 0:84353c479782 | 102 | #define PL_MAX_ENDPOINTS 4 |
hudakz | 0:84353c479782 | 103 | |
hudakz | 0:84353c479782 | 104 | enum tXO_State { |
hudakz | 0:84353c479782 | 105 | kXOnSent = -2, |
hudakz | 0:84353c479782 | 106 | kXOffSent = -1, |
hudakz | 0:84353c479782 | 107 | kXO_Idle = 0, |
hudakz | 0:84353c479782 | 108 | kXOffNeeded = 1, |
hudakz | 0:84353c479782 | 109 | kXOnNeeded = 2 |
hudakz | 0:84353c479782 | 110 | }; |
hudakz | 0:84353c479782 | 111 | |
hudakz | 0:84353c479782 | 112 | enum pl2303_type { |
hudakz | 0:84353c479782 | 113 | unknown, |
hudakz | 0:84353c479782 | 114 | type_0, /* don't know the difference between type 0 and */ |
hudakz | 0:84353c479782 | 115 | type_1, /* type 1, until someone from prolific tells us... */ |
hudakz | 0:84353c479782 | 116 | rev_X, |
hudakz | 0:84353c479782 | 117 | rev_HX, /* HX version of the pl2303 chip */ |
hudakz | 0:84353c479782 | 118 | rev_H |
hudakz | 0:84353c479782 | 119 | }; |
hudakz | 0:84353c479782 | 120 | |
hudakz | 0:84353c479782 | 121 | |
hudakz | 0:84353c479782 | 122 | class PL2303 : public ACM { |
hudakz | 0:84353c479782 | 123 | uint16_t wPLType; // Type of chip |
hudakz | 0:84353c479782 | 124 | |
hudakz | 0:84353c479782 | 125 | public: |
hudakz | 0:84353c479782 | 126 | PL2303(USB *pusb, CDCAsyncOper *pasync); |
hudakz | 0:84353c479782 | 127 | |
hudakz | 0:84353c479782 | 128 | // USBDeviceConfig implementation |
hudakz | 0:84353c479782 | 129 | uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed); |
hudakz | 0:84353c479782 | 130 | //virtual uint8_t Release(); |
hudakz | 0:84353c479782 | 131 | //virtual uint8_t Poll(); |
hudakz | 0:84353c479782 | 132 | //virtual uint8_t GetAddress() { return bAddress; }; |
hudakz | 0:84353c479782 | 133 | |
hudakz | 0:84353c479782 | 134 | //// UsbConfigXtracter implementation |
hudakz | 0:84353c479782 | 135 | //virtual void EndpointXtract(uint8_t conf, uint8_t iface, uint8_t alt, uint8_t proto, const USB_ENDPOINT_DESCRIPTOR *ep); |
hudakz | 0:84353c479782 | 136 | |
hudakz | 0:84353c479782 | 137 | #ifdef PL2303_COMPAT |
hudakz | 0:84353c479782 | 138 | private: |
hudakz | 0:84353c479782 | 139 | /* Prolific proprietary requests */ |
hudakz | 0:84353c479782 | 140 | uint8_t vendorRead( uint8_t val_lo, uint8_t val_hi, uint16_t index, uint8_t* buf ); |
hudakz | 0:84353c479782 | 141 | uint8_t vendorWrite( uint8_t val_lo, uint8_t val_hi, uint8_t index ); |
hudakz | 0:84353c479782 | 142 | #endif |
hudakz | 0:84353c479782 | 143 | }; |
hudakz | 0:84353c479782 | 144 | |
hudakz | 0:84353c479782 | 145 | #ifdef PL2303_COMPAT |
hudakz | 0:84353c479782 | 146 | /* vendor read request */ |
hudakz | 0:84353c479782 | 147 | inline uint8_t PL2303::vendorRead( uint8_t val_lo, uint8_t val_hi, uint16_t index, uint8_t* buf ) |
hudakz | 0:84353c479782 | 148 | { |
hudakz | 0:84353c479782 | 149 | return( pUsb->ctrlReq(bAddress, 0, VENDOR_READ_REQUEST_TYPE, VENDOR_READ_REQUEST, val_lo, val_hi, index, 1, 1, buf, NULL )); |
hudakz | 0:84353c479782 | 150 | } |
hudakz | 0:84353c479782 | 151 | |
hudakz | 0:84353c479782 | 152 | /* vendor write request */ |
hudakz | 0:84353c479782 | 153 | inline uint8_t PL2303::vendorWrite( uint8_t val_lo, uint8_t val_hi, uint8_t index ) |
hudakz | 0:84353c479782 | 154 | { |
hudakz | 0:84353c479782 | 155 | return( pUsb->ctrlReq(bAddress, 0, VENDOR_WRITE_REQUEST_TYPE, VENDOR_WRITE_REQUEST, val_lo, val_hi, index, 0, 0, NULL, NULL )); |
hudakz | 0:84353c479782 | 156 | } |
hudakz | 0:84353c479782 | 157 | #endif |
hudakz | 0:84353c479782 | 158 | |
hudakz | 0:84353c479782 | 159 | #endif // __CDCPROLIFIC_H__ |