Zoltan Hudak / UsbHostMAX3421E

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Dependents:   UsbHostMAX3421E_Hello

cdc_XR21B1411.h@0:84353c479782, 2020-07-12 (annotated)

Committer:
hudakz
Date:
Sun Jul 12 20:39:26 2020 +0000
Revision:
0:84353c479782
Child:
1:2263e77400e9
MAX3421E-based USB Host Shield Library

Who changed what in which revision?

UserRevisionLine numberNew contents of line
hudakz 0:84353c479782 1 /* Copyright (C) 2015 Andrew J. Kroll
hudakz 0:84353c479782 2 and
hudakz 0:84353c479782 3 Circuits At Home, LTD. All rights reserved.
hudakz 0:84353c479782 4
hudakz 0:84353c479782 5 This software may be distributed and modified under the terms of the GNU
hudakz 0:84353c479782 6 General Public License version 2 (GPL2) as published by the Free Software
hudakz 0:84353c479782 7 Foundation and appearing in the file GPL2.TXT included in the packaging of
hudakz 0:84353c479782 8 this file. Please note that GPL2 Section 2[b] requires that all works based
hudakz 0:84353c479782 9 on this software must also be made publicly available under the terms of
hudakz 0:84353c479782 10 the GPL2 ("Copyleft").
hudakz 0:84353c479782 11
hudakz 0:84353c479782 12 Contact information
hudakz 0:84353c479782 13 -------------------
hudakz 0:84353c479782 14
hudakz 0:84353c479782 15 Circuits At Home, LTD
hudakz 0:84353c479782 16 Web : http://www.circuitsathome.com
hudakz 0:84353c479782 17 e-mail : support@circuitsathome.com
hudakz 0:84353c479782 18 */
hudakz 0:84353c479782 19 #if !defined(__CDC_XR21B1411_H__)
hudakz 0:84353c479782 20 #define __CDC_XR21B1411_H__
hudakz 0:84353c479782 21
hudakz 0:84353c479782 22 #include "cdcacm.h"
hudakz 0:84353c479782 23
hudakz 0:84353c479782 24 #define XR_REG_CUSTOM_DRIVER (0x020DU) // DRIVER SELECT
hudakz 0:84353c479782 25 #define XR_REG_CUSTOM_DRIVER_ACTIVE (0x0001U) // 0: CDC 1: CUSTOM
hudakz 0:84353c479782 26
hudakz 0:84353c479782 27 #define XR_REG_ACM_FLOW_CTL (0x0216U) // FLOW CONTROL REGISTER CDCACM MODE
hudakz 0:84353c479782 28 #define XR_REG_FLOW_CTL (0x0C06U) // FLOW CONTROL REGISTER CUSTOM MODE
hudakz 0:84353c479782 29 #define XR_REG_FLOW_CTL_HALF_DPLX (0x0008U) // 0:FULL DUPLEX 1:HALF DUPLEX
hudakz 0:84353c479782 30 #define XR_REG_FLOW_CTL_MODE_MASK (0x0007U) // MODE BITMASK
hudakz 0:84353c479782 31 #define XR_REG_FLOW_CTL_NONE (0x0000U) // NO FLOW CONTROL
hudakz 0:84353c479782 32 #define XR_REG_FLOW_CTL_HW (0x0001U) // HARDWARE FLOW CONTROL
hudakz 0:84353c479782 33 #define XR_REG_FLOW_CTL_SW (0x0002U) // SOFTWARE FLOW CONTROL
hudakz 0:84353c479782 34 #define XR_REG_FLOW_CTL_MMMRX (0x0003U) // MULTIDROP RX UPON ADDRESS MATCH
hudakz 0:84353c479782 35 #define XR_REG_FLOW_CTL_MMMRXTX (0x0004U) // MULTIDROP RX/TX UPON ADDRESS MATCH
hudakz 0:84353c479782 36
hudakz 0:84353c479782 37 #define XR_REG_ACM_GPIO_MODE (0x0217U) // GPIO MODE REGISTER IN CDCACM MODE
hudakz 0:84353c479782 38 #define XR_REG_GPIO_MODE (0x0C0CU) // GPIO MODE REGISTER IN CUSTOM MODE
hudakz 0:84353c479782 39 #define XR_REG_GPIO_MODE_GPIO (0x0000U) // ALL GPIO PINS ACM PROGRAMMABLE
hudakz 0:84353c479782 40 #define XR_REG_GPIO_MODE_FC_RTSCTS (0x0001U) // AUTO RTSCTS HW FC (GPIO 4/5)
hudakz 0:84353c479782 41 #define XR_REG_GPIO_MODE_FC_DTRDSR (0x0002U) // AUTO DTRDSR HW FC (GPIO 2/3)
hudakz 0:84353c479782 42 #define XR_REG_GPIO_MODE_ATE (0x0003U) // AUTO TRANSCEIVER ENABLE DURING TX (GPIO 5)
hudakz 0:84353c479782 43 #define XR_REG_GPIO_MODE_ATE_ADDRESS (0x0004U) // AUTO TRANSCEIVER ENABLE ON ADDRESS MATCH (GPIO 5)
hudakz 0:84353c479782 44
hudakz 0:84353c479782 45 #define XR_REG_ACM_GPIO_DIR (0x0218U) // GPIO DIRECTION REGISTER CDCACM MODE, 0:IN 1:OUT
hudakz 0:84353c479782 46 #define XR_REG_GPIO_DIR (0x0C0DU) // GPIO DIRECTION REGISTER CUSTOM MODE, 0:IN 1:OUT
hudakz 0:84353c479782 47
hudakz 0:84353c479782 48 #define XR_REG_ACM_GPIO_INT (0x0219U) // GPIO PIN CHANGE INTERRUPT ENABLE CDCACM MODE, 0: ENABLED 1: DISABLED
hudakz 0:84353c479782 49 #define XR_REG_GPIO_INT (0x0C11U) // GPIO PIN CHANGE INTERRUPT ENABLE CUSTOM MODE, 0: ENABLED 1: DISABLED
hudakz 0:84353c479782 50 #define XR_REG_GPIO_MASK (0x001FU) // GPIO REGISTERS BITMASK
hudakz 0:84353c479782 51
hudakz 0:84353c479782 52 #define XR_REG_UART_ENABLE (0x0C00U) // UART I/O ENABLE REGISTER
hudakz 0:84353c479782 53 #define XR_REG_UART_ENABLE_RX (0x0002U) // 0:DISABLED 1:ENABLED
hudakz 0:84353c479782 54 #define XR_REG_UART_ENABLE_TX (0x0001U) // 0:DISABLED 1:ENABLED
hudakz 0:84353c479782 55
hudakz 0:84353c479782 56 #define XR_REG_ERROR_STATUS (0x0C09U) // ERROR STATUS REGISTER
hudakz 0:84353c479782 57 #define XR_REG_ERROR_STATUS_MASK (0x00F8U) // ERROR STATUS BITMASK
hudakz 0:84353c479782 58 #define XR_REG_ERROR_STATUS_ERROR (0x0070U) // ERROR STATUS ERROR BITMASK
hudakz 0:84353c479782 59 #define XR_REG_ERROR_STATUS_BREAK (0x0008U) // BREAK HAS BEEN DETECTED
hudakz 0:84353c479782 60 #define XR_REG_ERROR_STATUS_OVERRUN (0x0010U) // RX OVERRUN ERROR
hudakz 0:84353c479782 61 #define XR_REG_ERROR_STATUS_PARITY (0x0020U) // PARITY ERROR
hudakz 0:84353c479782 62 #define XR_REG_ERROR_STATUS_FRAME (0x0040U) // FRAMING ERROR
hudakz 0:84353c479782 63 #define XR_REG_ERROR_STATUS_BREAKING (0x0080U) // BREAK IS BEING DETECTED
hudakz 0:84353c479782 64
hudakz 0:84353c479782 65 #define XR_REG_TX_BREAK (0x0C0AU) // TRANSMIT BREAK. 0X0001-0XFFE TIME IN MS, 0X0000 STOP, 0X0FFF BREAK ON
hudakz 0:84353c479782 66
hudakz 0:84353c479782 67 #define XR_REG_XCVR_EN_DELAY (0x0C0BU) // TURN-ARROUND DELAY IN BIT-TIMES 0X0000-0X000F
hudakz 0:84353c479782 68
hudakz 0:84353c479782 69 #define XR_REG_GPIO_SET (0x0C0EU) // 1:SET GPIO PIN
hudakz 0:84353c479782 70
hudakz 0:84353c479782 71 #define XR_REG_GPIO_CLR (0x0C0FU) // 1:CLEAR GPIO PIN
hudakz 0:84353c479782 72
hudakz 0:84353c479782 73 #define XR_REG_GPIO_STATUS (0x0C10U) // READ GPIO PINS
hudakz 0:84353c479782 74
hudakz 0:84353c479782 75 #define XR_REG_CUSTOMISED_INT (0x0C12U) // 0:STANDARD 1:CUSTOM SEE DATA SHEET
hudakz 0:84353c479782 76
hudakz 0:84353c479782 77 #define XR_REG_PIN_PULLUP_ENABLE (0x0C14U) // 0:DISABLE 1:ENABLE, BITS 0-5:GPIO, 6:RX 7:TX
hudakz 0:84353c479782 78
hudakz 0:84353c479782 79 #define XR_REG_PIN_PULLDOWN_ENABLE (0x0C15U) // 0:DISABLE 1:ENABLE, BITS 0-5:GPIO, 6:RX 7:TX
hudakz 0:84353c479782 80
hudakz 0:84353c479782 81 #define XR_REG_LOOPBACK (0x0C16U) // 0:DISABLE 1:ENABLE, SEE DATA SHEET
hudakz 0:84353c479782 82
hudakz 0:84353c479782 83 #define XR_REG_RX_FIFO_LATENCY (0x0CC2U) // FIFO LATENCY REGISTER
hudakz 0:84353c479782 84 #define XR_REG_RX_FIFO_LATENCY_ENABLE (0x0001U) //
hudakz 0:84353c479782 85
hudakz 0:84353c479782 86 #define XR_REG_WIDE_MODE (0x0D02U)
hudakz 0:84353c479782 87 #define XR_REG_WIDE_MODE_ENABLE (0x0001U)
hudakz 0:84353c479782 88
hudakz 0:84353c479782 89 #define XR_REG_XON_CHAR (0x0C07U)
hudakz 0:84353c479782 90 #define XR_REG_XOFF_CHAR (0x0C08U)
hudakz 0:84353c479782 91
hudakz 0:84353c479782 92 #define XR_REG_TX_FIFO_RESET (0x0C80U) // 1: RESET, SELF-CLEARING
hudakz 0:84353c479782 93 #define XR_REG_TX_FIFO_COUNT (0x0C81U) // READ-ONLY
hudakz 0:84353c479782 94 #define XR_REG_RX_FIFO_RESET (0x0CC0U) // 1: RESET, SELF-CLEARING
hudakz 0:84353c479782 95 #define XR_REG_RX_FIFO_COUNT (0x0CC1U) // READ-ONLY
hudakz 0:84353c479782 96
hudakz 0:84353c479782 97 #define XR_WRITE_REQUEST_TYPE (0x40U)
hudakz 0:84353c479782 98
hudakz 0:84353c479782 99 #define XR_READ_REQUEST_TYPE (0xC0U)
hudakz 0:84353c479782 100
hudakz 0:84353c479782 101 #define XR_MAX_ENDPOINTS 4
hudakz 0:84353c479782 102
hudakz 0:84353c479782 103 class XR21B1411 : public ACM {
hudakz 0:84353c479782 104 protected:
hudakz 0:84353c479782 105
hudakz 0:84353c479782 106 public:
hudakz 0:84353c479782 107 XR21B1411(USB *pusb, CDCAsyncOper *pasync);
hudakz 0:84353c479782 108
hudakz 0:84353c479782 109 /**
hudakz 0:84353c479782 110 * Used by the USB core to check what this driver support.
hudakz 0:84353c479782 111 * @param vid The device's VID.
hudakz 0:84353c479782 112 * @param pid The device's PID.
hudakz 0:84353c479782 113 * @return Returns true if the device's VID and PID matches this driver.
hudakz 0:84353c479782 114 */
hudakz 0:84353c479782 115 virtual bool VIDPIDOK(uint16_t vid, uint16_t pid) {
hudakz 0:84353c479782 116 return (((vid == 0x2890U) && (pid == 0x0201U)) || ((vid == 0x04e2U) && (pid == 0x1411U)));
hudakz 0:84353c479782 117 };
hudakz 0:84353c479782 118
hudakz 0:84353c479782 119 uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed);
hudakz 0:84353c479782 120
hudakz 0:84353c479782 121 virtual tty_features enhanced_features(void) {
hudakz 0:84353c479782 122 tty_features rv;
hudakz 0:84353c479782 123 rv.enhanced = true;
hudakz 0:84353c479782 124 rv.autoflow_RTS = true;
hudakz 0:84353c479782 125 rv.autoflow_DSR = true;
hudakz 0:84353c479782 126 rv.autoflow_XON = true;
hudakz 0:84353c479782 127 rv.half_duplex = true;
hudakz 0:84353c479782 128 rv.wide = true;
hudakz 0:84353c479782 129 return rv;
hudakz 0:84353c479782 130 };
hudakz 0:84353c479782 131
hudakz 0:84353c479782 132 uint8_t read_register(uint16_t reg, uint16_t *val) {
hudakz 0:84353c479782 133 return (pUsb->ctrlReq(bAddress, 0, XR_READ_REQUEST_TYPE, 1, 0, 0, reg, 2, 2, (uint8_t *)val, NULL));
hudakz 0:84353c479782 134 }
hudakz 0:84353c479782 135
hudakz 0:84353c479782 136 uint8_t write_register(uint16_t reg, uint16_t val) {
hudakz 0:84353c479782 137 return (pUsb->ctrlReq(bAddress, 0, XR_WRITE_REQUEST_TYPE, 0, BGRAB0(val), BGRAB1(val), reg, 0, 0, NULL, NULL));
hudakz 0:84353c479782 138 }
hudakz 0:84353c479782 139
hudakz 0:84353c479782 140
hudakz 0:84353c479782 141 ////////////////////////////////////////////////////////////////////////
hudakz 0:84353c479782 142 // The following methods set the CDC-ACM defaults.
hudakz 0:84353c479782 143 ////////////////////////////////////////////////////////////////////////
hudakz 0:84353c479782 144
hudakz 0:84353c479782 145 virtual void autoflowRTS(bool s) {
hudakz 0:84353c479782 146 uint16_t val;
hudakz 0:84353c479782 147 uint8_t rval;
hudakz 0:84353c479782 148 rval = read_register(XR_REG_ACM_FLOW_CTL, &val);
hudakz 0:84353c479782 149 if(!rval) {
hudakz 0:84353c479782 150 if(s) {
hudakz 0:84353c479782 151 val &= XR_REG_FLOW_CTL_HALF_DPLX;
hudakz 0:84353c479782 152 val |= XR_REG_FLOW_CTL_HW;
hudakz 0:84353c479782 153 } else {
hudakz 0:84353c479782 154 val &= XR_REG_FLOW_CTL_HALF_DPLX;
hudakz 0:84353c479782 155 }
hudakz 0:84353c479782 156 rval = write_register(XR_REG_ACM_FLOW_CTL, val);
hudakz 0:84353c479782 157 if(!rval) {
hudakz 0:84353c479782 158 rval = write_register(XR_REG_ACM_GPIO_MODE, XR_REG_GPIO_MODE_GPIO);
hudakz 0:84353c479782 159 if(!rval) {
hudakz 0:84353c479782 160 // ACM commands apply the new settings.
hudakz 0:84353c479782 161 LINE_CODING LCT;
hudakz 0:84353c479782 162 rval = GetLineCoding(&LCT);
hudakz 0:84353c479782 163 if(!rval) {
hudakz 0:84353c479782 164 rval = SetLineCoding(&LCT);
hudakz 0:84353c479782 165 if(!rval) {
hudakz 0:84353c479782 166 _enhanced_status.autoflow_XON = false;
hudakz 0:84353c479782 167 _enhanced_status.autoflow_DSR = false;
hudakz 0:84353c479782 168 _enhanced_status.autoflow_RTS = s;
hudakz 0:84353c479782 169 }
hudakz 0:84353c479782 170 }
hudakz 0:84353c479782 171 }
hudakz 0:84353c479782 172 }
hudakz 0:84353c479782 173 }
hudakz 0:84353c479782 174 };
hudakz 0:84353c479782 175
hudakz 0:84353c479782 176 virtual void autoflowDSR(bool s) {
hudakz 0:84353c479782 177 uint16_t val;
hudakz 0:84353c479782 178 uint8_t rval;
hudakz 0:84353c479782 179 rval = read_register(XR_REG_ACM_FLOW_CTL, &val);
hudakz 0:84353c479782 180 if(!rval) {
hudakz 0:84353c479782 181 if(s) {
hudakz 0:84353c479782 182 val &= XR_REG_FLOW_CTL_HALF_DPLX;
hudakz 0:84353c479782 183 val |= XR_REG_FLOW_CTL_HW;
hudakz 0:84353c479782 184 } else {
hudakz 0:84353c479782 185 val &= XR_REG_FLOW_CTL_HALF_DPLX;
hudakz 0:84353c479782 186 }
hudakz 0:84353c479782 187 rval = write_register(XR_REG_ACM_FLOW_CTL, val);
hudakz 0:84353c479782 188 if(!rval) {
hudakz 0:84353c479782 189 if(s) {
hudakz 0:84353c479782 190 rval = write_register(XR_REG_ACM_GPIO_MODE, XR_REG_GPIO_MODE_FC_DTRDSR);
hudakz 0:84353c479782 191 } else {
hudakz 0:84353c479782 192 rval = write_register(XR_REG_ACM_GPIO_MODE, XR_REG_GPIO_MODE_GPIO);
hudakz 0:84353c479782 193 }
hudakz 0:84353c479782 194 if(!rval) {
hudakz 0:84353c479782 195 // ACM commands apply the new settings.
hudakz 0:84353c479782 196 LINE_CODING LCT;
hudakz 0:84353c479782 197 rval = GetLineCoding(&LCT);
hudakz 0:84353c479782 198 if(!rval) {
hudakz 0:84353c479782 199 rval = SetLineCoding(&LCT);
hudakz 0:84353c479782 200 if(!rval) {
hudakz 0:84353c479782 201 _enhanced_status.autoflow_XON = false;
hudakz 0:84353c479782 202 _enhanced_status.autoflow_RTS = false;
hudakz 0:84353c479782 203 _enhanced_status.autoflow_DSR = s;
hudakz 0:84353c479782 204 }
hudakz 0:84353c479782 205 }
hudakz 0:84353c479782 206 }
hudakz 0:84353c479782 207 }
hudakz 0:84353c479782 208 }
hudakz 0:84353c479782 209 };
hudakz 0:84353c479782 210
hudakz 0:84353c479782 211 virtual void autoflowXON(bool s) {
hudakz 0:84353c479782 212 // NOTE: hardware defaults to the normal XON/XOFF
hudakz 0:84353c479782 213 uint16_t val;
hudakz 0:84353c479782 214 uint8_t rval;
hudakz 0:84353c479782 215 rval = read_register(XR_REG_ACM_FLOW_CTL, &val);
hudakz 0:84353c479782 216 if(!rval) {
hudakz 0:84353c479782 217 if(s) {
hudakz 0:84353c479782 218 val &= XR_REG_FLOW_CTL_HALF_DPLX;
hudakz 0:84353c479782 219 val |= XR_REG_FLOW_CTL_SW;
hudakz 0:84353c479782 220 } else {
hudakz 0:84353c479782 221 val &= XR_REG_FLOW_CTL_HALF_DPLX;
hudakz 0:84353c479782 222 }
hudakz 0:84353c479782 223 rval = write_register(XR_REG_ACM_FLOW_CTL, val);
hudakz 0:84353c479782 224 if(!rval) {
hudakz 0:84353c479782 225 rval = write_register(XR_REG_ACM_GPIO_MODE, XR_REG_GPIO_MODE_GPIO);
hudakz 0:84353c479782 226 if(!rval) {
hudakz 0:84353c479782 227 // ACM commands apply the new settings.
hudakz 0:84353c479782 228 LINE_CODING LCT;
hudakz 0:84353c479782 229 rval = GetLineCoding(&LCT);
hudakz 0:84353c479782 230 if(!rval) {
hudakz 0:84353c479782 231 rval = SetLineCoding(&LCT);
hudakz 0:84353c479782 232 if(!rval) {
hudakz 0:84353c479782 233 _enhanced_status.autoflow_RTS = false;
hudakz 0:84353c479782 234 _enhanced_status.autoflow_DSR = false;
hudakz 0:84353c479782 235 _enhanced_status.autoflow_XON = s;
hudakz 0:84353c479782 236 }
hudakz 0:84353c479782 237 }
hudakz 0:84353c479782 238 }
hudakz 0:84353c479782 239 }
hudakz 0:84353c479782 240 }
hudakz 0:84353c479782 241 };
hudakz 0:84353c479782 242
hudakz 0:84353c479782 243 virtual void half_duplex(bool s) {
hudakz 0:84353c479782 244 uint16_t val;
hudakz 0:84353c479782 245 uint8_t rval;
hudakz 0:84353c479782 246 rval = read_register(XR_REG_ACM_FLOW_CTL, &val);
hudakz 0:84353c479782 247 if(!rval) {
hudakz 0:84353c479782 248 if(s) {
hudakz 0:84353c479782 249 val |= XR_REG_FLOW_CTL_HALF_DPLX;
hudakz 0:84353c479782 250 } else {
hudakz 0:84353c479782 251 val &= XR_REG_FLOW_CTL_MODE_MASK;
hudakz 0:84353c479782 252 }
hudakz 0:84353c479782 253 rval = write_register(XR_REG_ACM_FLOW_CTL, val);
hudakz 0:84353c479782 254 if(!rval) {
hudakz 0:84353c479782 255 // ACM commands apply the new settings.
hudakz 0:84353c479782 256 LINE_CODING LCT;
hudakz 0:84353c479782 257 rval = GetLineCoding(&LCT);
hudakz 0:84353c479782 258 if(!rval) {
hudakz 0:84353c479782 259 rval = SetLineCoding(&LCT);
hudakz 0:84353c479782 260 if(!rval) {
hudakz 0:84353c479782 261 _enhanced_status.half_duplex = s;
hudakz 0:84353c479782 262 }
hudakz 0:84353c479782 263 }
hudakz 0:84353c479782 264 }
hudakz 0:84353c479782 265 }
hudakz 0:84353c479782 266 };
hudakz 0:84353c479782 267
hudakz 0:84353c479782 268
hudakz 0:84353c479782 269
hudakz 0:84353c479782 270 };
hudakz 0:84353c479782 271
hudakz 0:84353c479782 272 #endif // __CDCPROLIFIC_H__