Zoltan Hudak / TLE5012B

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Dependents:   TLE5012B_Hello

TLE5012B_REG.h@0:4b76b1dc05cd, 2020-09-19 (annotated)

Committer:
hudakz
Date:
Sat Sep 19 18:01:49 2020 +0000
Revision:
0:4b76b1dc05cd
Library for the TLE5012B Giant Magneto Resistance (GMR) based angle sensor.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
hudakz 0:4b76b1dc05cd 1 /*!
hudakz 0:4b76b1dc05cd 2 * \name TLE5012B_REG.h - Mbed port of Arduino library for the TLE5012B angle sensor.
hudakz 0:4b76b1dc05cd 3 * \author Infineon Technologies AG (Dr.Olaf Filies)
hudakz 0:4b76b1dc05cd 4 * \copyright 2019 Infineon Technologies AG
hudakz 0:4b76b1dc05cd 5 * \version 2.0.1
hudakz 0:4b76b1dc05cd 6 * \brief GMR-based angle sensor for angular position sensing in automotive applications
hudakz 0:4b76b1dc05cd 7 * This library include the register read and bit separation function.
hudakz 0:4b76b1dc05cd 8 * \details Ported to Mbed by Zoltan Hudak 2020-08
hudakz 0:4b76b1dc05cd 9 *
hudakz 0:4b76b1dc05cd 10 * Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
hudakz 0:4b76b1dc05cd 11 * following conditions are met:
hudakz 0:4b76b1dc05cd 12 *
hudakz 0:4b76b1dc05cd 13 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
hudakz 0:4b76b1dc05cd 14 * disclaimer.
hudakz 0:4b76b1dc05cd 15 *
hudakz 0:4b76b1dc05cd 16 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
hudakz 0:4b76b1dc05cd 17 * disclaimer in the documentation and/or other materials provided with the distribution.
hudakz 0:4b76b1dc05cd 18 *
hudakz 0:4b76b1dc05cd 19 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
hudakz 0:4b76b1dc05cd 20 * products derived from this software without specific prior written permission.
hudakz 0:4b76b1dc05cd 21 *
hudakz 0:4b76b1dc05cd 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
hudakz 0:4b76b1dc05cd 23 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
hudakz 0:4b76b1dc05cd 24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
hudakz 0:4b76b1dc05cd 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
hudakz 0:4b76b1dc05cd 26 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
hudakz 0:4b76b1dc05cd 27 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
hudakz 0:4b76b1dc05cd 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
hudakz 0:4b76b1dc05cd 29 *
hudakz 0:4b76b1dc05cd 30 */
hudakz 0:4b76b1dc05cd 31
hudakz 0:4b76b1dc05cd 32 #ifndef TLE5012B_REG_H
hudakz 0:4b76b1dc05cd 33 #define TLE5012B_REG_H
hudakz 0:4b76b1dc05cd 34
hudakz 0:4b76b1dc05cd 35 #include "mbed.h"
hudakz 0:4b76b1dc05cd 36 #include "TLE5012B.h"
hudakz 0:4b76b1dc05cd 37
hudakz 0:4b76b1dc05cd 38 #define MAX_NUM_REG 0x16 //!< defines the value for temporary data to read all readable registers
hudakz 0:4b76b1dc05cd 39
hudakz 0:4b76b1dc05cd 40 using namespace TLE5012;
hudakz 0:4b76b1dc05cd 41
hudakz 0:4b76b1dc05cd 42 class TLE5012B_REG: public TLE5012B
hudakz 0:4b76b1dc05cd 43 {
hudakz 0:4b76b1dc05cd 44 public:
hudakz 0:4b76b1dc05cd 45
hudakz 0:4b76b1dc05cd 46 /*!
hudakz 0:4b76b1dc05cd 47 * Automatic calibration of offset and amplitude synchronicity for applications
hudakz 0:4b76b1dc05cd 48 * with full-turn. Only 1 LSB corrected at each update. CRC check of calibration
hudakz 0:4b76b1dc05cd 49 * registers is automatically disabled if AUTOCAL activated.
hudakz 0:4b76b1dc05cd 50 */
hudakz 0:4b76b1dc05cd 51 enum calibrationMode
hudakz 0:4b76b1dc05cd 52 {
hudakz 0:4b76b1dc05cd 53 noAutoCal = 0x0,//!< noAutoCal = no auto-calibration
hudakz 0:4b76b1dc05cd 54 mode1, //!< mode1 update every angle update cycle (FIR_MD setting)
hudakz 0:4b76b1dc05cd 55 mode2, //!< mode2 update every 1.5 revolutions
hudakz 0:4b76b1dc05cd 56 mode3 //!< mode3 update every 11.25°
hudakz 0:4b76b1dc05cd 57 };
hudakz 0:4b76b1dc05cd 58
hudakz 0:4b76b1dc05cd 59 /*!
hudakz 0:4b76b1dc05cd 60 * List of possible interface types
hudakz 0:4b76b1dc05cd 61 * witch are preset by fuses and can
hudakz 0:4b76b1dc05cd 62 * be changed into each other
hudakz 0:4b76b1dc05cd 63 */
hudakz 0:4b76b1dc05cd 64 enum interfaceType
hudakz 0:4b76b1dc05cd 65 {
hudakz 0:4b76b1dc05cd 66 IIF = 0, //!< IIF Incremental Interface (IIF)
hudakz 0:4b76b1dc05cd 67 PWM, //!< PWM Pulse-Width-Modulation (PWM)
hudakz 0:4b76b1dc05cd 68 HSM, //!< HSM Hall Switch Mode (HSM)
hudakz 0:4b76b1dc05cd 69 SPC, //!< SPC Short-PWM-Code (SPC)
hudakz 0:4b76b1dc05cd 70 SSC //!< SSC Synchronous Serial Communication (SSC)
hudakz 0:4b76b1dc05cd 71 };
hudakz 0:4b76b1dc05cd 72
hudakz 0:4b76b1dc05cd 73 /*!
hudakz 0:4b76b1dc05cd 74 * List of possible Sensor types and PCB variants
hudakz 0:4b76b1dc05cd 75 * with and without attached XMC2Go
hudakz 0:4b76b1dc05cd 76 */
hudakz 0:4b76b1dc05cd 77 enum sensorType
hudakz 0:4b76b1dc05cd 78 {
hudakz 0:4b76b1dc05cd 79 TLE5012B_E1000= 0x0,//!< TLE5012B_E1000 Sensor2Go variant
hudakz 0:4b76b1dc05cd 80 TLE5012B_E3005, //!< TLE5012B_E3005
hudakz 0:4b76b1dc05cd 81 TLE5012B_E5000, //!< TLE5012B_E5000 Sensor2Go variant
hudakz 0:4b76b1dc05cd 82 TLE5012B_E5020, //!< TLE5012B_E5020
hudakz 0:4b76b1dc05cd 83 TLE5012B_E9000, //!< TLE5012B_E9000 Sensor2Go variant
hudakz 0:4b76b1dc05cd 84 };
hudakz 0:4b76b1dc05cd 85
hudakz 0:4b76b1dc05cd 86 //using TLE5012B::TLE5012B; //!< Using the inherited constructor
hudakz 0:4b76b1dc05cd 87
hudakz 0:4b76b1dc05cd 88 struct stat_t //!< Status register 0x00
hudakz 0:4b76b1dc05cd 89 {
hudakz 0:4b76b1dc05cd 90 bool RDST; //!< bits 15:15 Read status
hudakz 0:4b76b1dc05cd 91 uint8_t SNR; //!< bits 14:13 Slave number
hudakz 0:4b76b1dc05cd 92 bool NOGMRA; //!< bits 12:12 No valid GMR angle value
hudakz 0:4b76b1dc05cd 93 bool NOGMRXY; //!< bits 11:11 No valid GMR XY values
hudakz 0:4b76b1dc05cd 94 bool SROM; //!< bits 10:10 Status ROM
hudakz 0:4b76b1dc05cd 95 bool SADCT; //!< bits 9:9 Status ADC Test
hudakz 0:4b76b1dc05cd 96 bool Reserved1; //!< bits 8:8
hudakz 0:4b76b1dc05cd 97 bool SMAGOL; //!< bits 7:7 Status magnitude out of Limit
hudakz 0:4b76b1dc05cd 98 bool SXYOL; //!< bits 6:6 Status X,Y Data out of Limit
hudakz 0:4b76b1dc05cd 99 bool SOV; //!< bits 5:5 Status overflow
hudakz 0:4b76b1dc05cd 100 bool SDSPU; //!< bits 4:4 Status digital signal processing unit
hudakz 0:4b76b1dc05cd 101 bool SFUSE; //!< bits 3:3 Status fuse CRC
hudakz 0:4b76b1dc05cd 102 bool SVR; //!< bits 2:2 Status voltage regulator
hudakz 0:4b76b1dc05cd 103 bool SWD; //!< bits 1:1 Status Watch dog
hudakz 0:4b76b1dc05cd 104 bool SRST; //!< bits 0:0 Status Reset
hudakz 0:4b76b1dc05cd 105 uint16_t reg; //!< the register value
hudakz 0:4b76b1dc05cd 106
hudakz 0:4b76b1dc05cd 107 bool fetch_SRST(uint16_t reg) {SRST = (reg & 0x1);return (SRST);} //!< status reset
hudakz 0:4b76b1dc05cd 108 bool fetch_SWD(uint16_t reg) {SWD = (reg & 0x2) >> 1;return (SWD);} //!< status watch dog
hudakz 0:4b76b1dc05cd 109 bool fetch_SVR(uint16_t reg) {SVR = (reg & 0x4) >> 2;return (SVR);} //!< status voltage regulator
hudakz 0:4b76b1dc05cd 110 bool fetch_SFUSE(uint16_t reg) {SFUSE = (reg & 0x8) >> 3;return (SFUSE);} //!< status fuses
hudakz 0:4b76b1dc05cd 111 bool fetch_SDSPU(uint16_t reg) {SDSPU = (reg & 0x10) >> 4;return (SDSPU);} //!< status digital signal processing unit
hudakz 0:4b76b1dc05cd 112 bool fetch_SXYOL(uint16_t reg) {SXYOL = (reg & 0x20) >> 5;return (SXYOL);} //!< status overflow
hudakz 0:4b76b1dc05cd 113 bool fetch_SOV(uint16_t reg) {SOV = (reg & 0x40) >> 6;return (SOV);} //!< status X/Y data out limit
hudakz 0:4b76b1dc05cd 114 bool fetch_SMAGOL(uint16_t reg) {SMAGOL = (reg & 0x80) >> 7;return (SMAGOL);} //!< status magnitude out limit
hudakz 0:4b76b1dc05cd 115 bool fetch_Reserved1(uint16_t reg) {Reserved1 = (reg & 0x100) >> 8;return (Reserved1);} //!< reserved
hudakz 0:4b76b1dc05cd 116 bool fetch_SADCT(uint16_t reg) {SADCT = (reg & 0x200) >> 9;return (SADCT);} //!< status ADC test
hudakz 0:4b76b1dc05cd 117 bool fetch_SROM(uint16_t reg) {SROM = (reg & 0x400) >> 10;return (SROM);} //!< status ROM
hudakz 0:4b76b1dc05cd 118 bool fetch_NOGMRXY(uint16_t reg) {NOGMRXY = (reg & 0x800) >> 11;return (NOGMRXY);} //!< no valid GMR XY Values
hudakz 0:4b76b1dc05cd 119 bool fetch_NOGMRA(uint16_t reg) {NOGMRA = (reg & 0x1000) >> 12;return (NOGMRA);} //!< no valid GMR Angle Value
hudakz 0:4b76b1dc05cd 120 uint8_t fetch_SNR(uint16_t reg) {SNR = (reg & 0x6000) >> 13;return (SNR);} //!< slave number
hudakz 0:4b76b1dc05cd 121 bool fetch_RDST(uint16_t reg) {RDST = (reg & 0x8000) >> 15;return (RDST);} //!< read status
hudakz 0:4b76b1dc05cd 122 };
hudakz 0:4b76b1dc05cd 123
hudakz 0:4b76b1dc05cd 124 struct acstat_t //!< Activation Status register offset 0x01
hudakz 0:4b76b1dc05cd 125 {
hudakz 0:4b76b1dc05cd 126 uint8_t Reserved1; //!< bits 15:11
hudakz 0:4b76b1dc05cd 127 bool ASFRST; //!< bits 10:10 Activation of Firmware Reset
hudakz 0:4b76b1dc05cd 128 bool ASADCT; //!< bits 9:9 Enable ADC Test vector Check
hudakz 0:4b76b1dc05cd 129 bool Reserved2; //!< bits 8:8
hudakz 0:4b76b1dc05cd 130 bool ASVEGMAG; //!< bits 7:7 Activation of Magnitude Check
hudakz 0:4b76b1dc05cd 131 bool ASVECXY; //!< bits 6:6 Activation of X,Y Out of Limit-Check
hudakz 0:4b76b1dc05cd 132 bool ASOV; //!< bits 5:5 Enable of DSPU Overflow Check
hudakz 0:4b76b1dc05cd 133 bool ASDSPU; //!< bits 4:4 Activation DSPU BIST
hudakz 0:4b76b1dc05cd 134 bool ASFUSE; //!< bits 3:3 Activation Fuse CRC
hudakz 0:4b76b1dc05cd 135 bool ASVR; //!< bits 2:2 Enable Voltage regulator Check
hudakz 0:4b76b1dc05cd 136 bool ASWD; //!< bits 1:1 Enable DSPU Watch dog
hudakz 0:4b76b1dc05cd 137 bool ASRST; //!< bits 0:0 Activation of Hardware Reset
hudakz 0:4b76b1dc05cd 138 uint16_t reg; //!< the register value
hudakz 0:4b76b1dc05cd 139
hudakz 0:4b76b1dc05cd 140 bool fetch_ASRST(uint16_t reg) {ASRST = (reg & 0x1);return (ASRST);}
hudakz 0:4b76b1dc05cd 141 bool fetch_ASWD(uint16_t reg) {ASWD = (reg & 0x2) >> 1;return (ASWD);}
hudakz 0:4b76b1dc05cd 142 bool fetch_ASVR(uint16_t reg) {ASVR = (reg & 0x4) >> 2;return (ASVR);}
hudakz 0:4b76b1dc05cd 143 bool fetch_ASFUSE(uint16_t reg) {ASFUSE = (reg & 0x8) >> 3;return (ASFUSE);}
hudakz 0:4b76b1dc05cd 144 bool fetch_ASDSPU(uint16_t reg) {ASDSPU = (reg & 0x10) >> 4;return (ASDSPU);}
hudakz 0:4b76b1dc05cd 145 bool fetch_ASOV(uint16_t reg) {ASOV = (reg & 0x20) >> 5;return (ASOV);}
hudakz 0:4b76b1dc05cd 146 bool fetch_ASVECXY(uint16_t reg) {ASVECXY = (reg & 0x40) >> 6;return (ASVECXY);};
hudakz 0:4b76b1dc05cd 147 bool fetch_ASVEGMAG(uint16_t reg) {ASVEGMAG = (reg & 0x80) >> 7;return (ASVEGMAG);}
hudakz 0:4b76b1dc05cd 148 bool fetch_Reserved2(uint16_t reg) {Reserved2 = (reg & 0x100) >> 8;return (Reserved2);}
hudakz 0:4b76b1dc05cd 149 bool fetch_ASADCT(uint16_t reg) {ASADCT = (reg & 0x200) >> 9;return (ASADCT);}
hudakz 0:4b76b1dc05cd 150 bool fetch_ASFRST(uint16_t reg) {ASFRST = (reg & 0x400) >> 10;return (ASFRST);}
hudakz 0:4b76b1dc05cd 151 uint8_t fetch_Reserved1(uint16_t reg) {Reserved1 = (reg & 0xF800) >> 11;return (Reserved1);}
hudakz 0:4b76b1dc05cd 152 };
hudakz 0:4b76b1dc05cd 153
hudakz 0:4b76b1dc05cd 154 struct aval_t //!< Angle Value register offset 0x02
hudakz 0:4b76b1dc05cd 155 {
hudakz 0:4b76b1dc05cd 156 uint16_t ANGVAL; //!< bits 14:0 Calculated Angle Value (signed 15-bit)
hudakz 0:4b76b1dc05cd 157 bool RDAV; //!< bits 15:15 Read Status, Angle Value
hudakz 0:4b76b1dc05cd 158 uint16_t reg; //!< the register value
hudakz 0:4b76b1dc05cd 159
hudakz 0:4b76b1dc05cd 160 bool fetch_ANGVAL(uint16_t reg) {ANGVAL = (reg & 0x7FFF);return (ANGVAL);}
hudakz 0:4b76b1dc05cd 161 uint16_t fetch_RDAV(uint16_t reg) {RDAV = (reg & 0x8000) >> 15;return (RDAV);}
hudakz 0:4b76b1dc05cd 162 };
hudakz 0:4b76b1dc05cd 163
hudakz 0:4b76b1dc05cd 164 struct aspd_t //!< Angle Speed register offset 0x03
hudakz 0:4b76b1dc05cd 165 {
hudakz 0:4b76b1dc05cd 166 uint16_t ANGSPD; //!< bits 14:0 Signed value, where the sign bit [14] indicates the direction of the rotation.
hudakz 0:4b76b1dc05cd 167 bool RDAS; //!< bits 15:15 Read Status, Angle Speed
hudakz 0:4b76b1dc05cd 168 uint16_t reg; //!< the register value
hudakz 0:4b76b1dc05cd 169
hudakz 0:4b76b1dc05cd 170 bool fetch_ANGSPD(uint16_t reg) {ANGSPD = (reg & 0x7FFF);return (ANGSPD);}
hudakz 0:4b76b1dc05cd 171 uint16_t fetch_RDAS(uint16_t reg) {RDAS = (reg & 0x8000) >> 15;return (RDAS);}
hudakz 0:4b76b1dc05cd 172 };
hudakz 0:4b76b1dc05cd 173
hudakz 0:4b76b1dc05cd 174 struct arev_t //!< Angle Revolution register offset 0x04
hudakz 0:4b76b1dc05cd 175 {
hudakz 0:4b76b1dc05cd 176 int16_t REVOL; //!< bits 8:0 Revolution counter. Increments for every full rotation in counter-clockwise direction
hudakz 0:4b76b1dc05cd 177 uint16_t FCNT; //!< bits 14:9 Internal frame counter. Increments every update period
hudakz 0:4b76b1dc05cd 178 bool RDREV; //!< bits 15:15 Read Status, Revolution
hudakz 0:4b76b1dc05cd 179 uint16_t reg; //!< the register value
hudakz 0:4b76b1dc05cd 180 uint16_t fetch_FCNT(uint16_t reg) {FCNT = (reg & 0x7E00) >> 9;return (FCNT);} //!< Frame Counter
hudakz 0:4b76b1dc05cd 181 bool fetch_RDREV(uint16_t reg) {RDREV = (reg & 0x8000) >> 15;return (RDREV);} //!< Read Status, Revolution
hudakz 0:4b76b1dc05cd 182 int16_t fetch_REVOL(uint16_t reg)
hudakz 0:4b76b1dc05cd 183 {
hudakz 0:4b76b1dc05cd 184 REVOL = (reg & 0xFF);
hudakz 0:4b76b1dc05cd 185 if (REVOL & 0x100)
hudakz 0:4b76b1dc05cd 186 {
hudakz 0:4b76b1dc05cd 187 REVOL = REVOL * -1;
hudakz 0:4b76b1dc05cd 188 }
hudakz 0:4b76b1dc05cd 189 return (REVOL);
hudakz 0:4b76b1dc05cd 190 }
hudakz 0:4b76b1dc05cd 191 };
hudakz 0:4b76b1dc05cd 192
hudakz 0:4b76b1dc05cd 193 struct fsync_t //!< Frame Synchronization register offset 0x05
hudakz 0:4b76b1dc05cd 194 {
hudakz 0:4b76b1dc05cd 195 uint16_t FSYNC; //!< bits 15:9 Frame Synchronization Counter Value
hudakz 0:4b76b1dc05cd 196 int16_t TEMPR; //!< bits 8:0 Signed offset compensated temperature value.
hudakz 0:4b76b1dc05cd 197 uint16_t reg; //!< the register value
hudakz 0:4b76b1dc05cd 198
hudakz 0:4b76b1dc05cd 199 int16_t fetch_TEMPR(uint16_t reg)
hudakz 0:4b76b1dc05cd 200 {
hudakz 0:4b76b1dc05cd 201 TEMPR = (reg & 0xFF);
hudakz 0:4b76b1dc05cd 202 if (TEMPR & 0x100)
hudakz 0:4b76b1dc05cd 203 {
hudakz 0:4b76b1dc05cd 204 TEMPR = TEMPR * -1;
hudakz 0:4b76b1dc05cd 205 }
hudakz 0:4b76b1dc05cd 206 return (TEMPR);
hudakz 0:4b76b1dc05cd 207 }
hudakz 0:4b76b1dc05cd 208 uint16_t fetch_FSYNC(uint16_t reg)
hudakz 0:4b76b1dc05cd 209 {
hudakz 0:4b76b1dc05cd 210 FSYNC = (reg & 0xFE00) >> 9;
hudakz 0:4b76b1dc05cd 211 return (FSYNC);
hudakz 0:4b76b1dc05cd 212 }
hudakz 0:4b76b1dc05cd 213 };
hudakz 0:4b76b1dc05cd 214
hudakz 0:4b76b1dc05cd 215 struct mod1_t //!< MOD_1 Interface Mode1 register offset 0x06
hudakz 0:4b76b1dc05cd 216 {
hudakz 0:4b76b1dc05cd 217 uint8_t FIRMD; //!< bits 15:14 Update Rate Setting
hudakz 0:4b76b1dc05cd 218 uint16_t Reserverd1; //!< bits 13:5
hudakz 0:4b76b1dc05cd 219 bool CLKSEL; //!< bits 4:4 Switch to external clock at start-up only.
hudakz 0:4b76b1dc05cd 220 bool Reserverd2; //!< bits 3:3
hudakz 0:4b76b1dc05cd 221 bool DSPUHOLD; //!< bits 2:2 If DSPU is on hold, no watch dog reset is performed by DSPU
hudakz 0:4b76b1dc05cd 222 uint8_t IIFMOD; //!< bits 1:0 Incremental Interface Mode
hudakz 0:4b76b1dc05cd 223 uint16_t reg; //!< the register value
hudakz 0:4b76b1dc05cd 224
hudakz 0:4b76b1dc05cd 225 uint8_t fetch_IIFMOD(uint16_t reg) {IIFMOD = (reg & 0x3);return (IIFMOD);}
hudakz 0:4b76b1dc05cd 226 bool fetch_DSPUHOLD(uint16_t reg) {DSPUHOLD = (reg & 0x4) >> 2;return (DSPUHOLD);}
hudakz 0:4b76b1dc05cd 227 uint16_t fetch_Reserverd1(uint16_t reg) {Reserverd1 = (reg & 0x8) >> 3;return (Reserverd1);}
hudakz 0:4b76b1dc05cd 228 bool fetch_CLKSEL(uint16_t reg) {CLKSEL = (reg & 0x10) >> 4;return (CLKSEL);}
hudakz 0:4b76b1dc05cd 229 bool fetch_Reserverd2(uint16_t reg) {Reserverd2 = (reg & 0x3FE0) >> 5;return (Reserverd2);}
hudakz 0:4b76b1dc05cd 230 uint8_t fetch_FIRMD(uint16_t reg) {FIRMD = (reg & 0x6000) >> 13;return (FIRMD);}
hudakz 0:4b76b1dc05cd 231 };
hudakz 0:4b76b1dc05cd 232
hudakz 0:4b76b1dc05cd 233 struct sil_t //!< SIL register offset 0x07
hudakz 0:4b76b1dc05cd 234 {
hudakz 0:4b76b1dc05cd 235 bool FILTPAR; //!< bits 15:15
hudakz 0:4b76b1dc05cd 236 bool FILTINV; //!< bits 14:14 The raw X-signal is routed also to the raw Y-signal input of the filter so SIN and COS signal should be identical.
hudakz 0:4b76b1dc05cd 237 uint8_t Reserverd1; //!< bits 13:11 The X- and Y-signals are inverted. The angle output is then shifted by 180°.
hudakz 0:4b76b1dc05cd 238 bool FUSEREL; //!< bits 10:10 Triggers reload of default values from laser fuses into configuration registers.
hudakz 0:4b76b1dc05cd 239 uint8_t Reserverd2; //!< bits 9:7
hudakz 0:4b76b1dc05cd 240 bool ADCTVEN; //!< bits 6:6 Sensor elements are internally disconnected and test voltages are connected to ADCs.
hudakz 0:4b76b1dc05cd 241 uint8_t ADCTVY; //!< bits 5:3 Test vector X
hudakz 0:4b76b1dc05cd 242 uint8_t ADCTVX; //!< bits 2:0 Test vector Y
hudakz 0:4b76b1dc05cd 243 uint16_t reg; //!< the register value
hudakz 0:4b76b1dc05cd 244
hudakz 0:4b76b1dc05cd 245 uint8_t fetch_ADCTVX(uint16_t reg) {ADCTVX = (reg & 0x7);return (ADCTVX);}
hudakz 0:4b76b1dc05cd 246 uint8_t fetch_ADCTVY(uint16_t reg) {ADCTVY = (reg & 0x38) >> 3;return (ADCTVY);}
hudakz 0:4b76b1dc05cd 247 bool fetch_ADCTVEN(uint16_t reg) {ADCTVEN = (reg & 0x40) >> 6;return (ADCTVEN);}
hudakz 0:4b76b1dc05cd 248 uint8_t fetch_Reserverd1(uint16_t reg) {Reserverd1 = (reg & 0x380) >> 7;return (Reserverd1);}
hudakz 0:4b76b1dc05cd 249 bool fetch_FUSEREL(uint16_t reg) {FUSEREL = (reg & 0x400) >> 10;return (FUSEREL);}
hudakz 0:4b76b1dc05cd 250 uint8_t fetch_Reserverd2(uint16_t reg) {Reserverd2 = (reg & 0x3800) >> 11;return (Reserverd2);}
hudakz 0:4b76b1dc05cd 251 bool fetch_FILTINV(uint16_t reg) {FILTINV = (reg & 0x4000) >> 14;return (FILTINV);}
hudakz 0:4b76b1dc05cd 252 bool fetch_FILTPAR(uint16_t reg) {FILTPAR = (reg & 0x8000) >> 15;return (FILTPAR);}
hudakz 0:4b76b1dc05cd 253 };
hudakz 0:4b76b1dc05cd 254
hudakz 0:4b76b1dc05cd 255 struct mod2_t //!< MOD_2 Interface Mode2 register offset 0x08
hudakz 0:4b76b1dc05cd 256 {
hudakz 0:4b76b1dc05cd 257 bool Reserverd1; //!< bits 15:15
hudakz 0:4b76b1dc05cd 258 uint16_t ANGRANGE; //!< bits 14:4 Changes the representation of the angle output by multiplying the output with a factor ANG_RANGE/128.
hudakz 0:4b76b1dc05cd 259 bool ANGDIR; //!< bits 3:3 Inverts angle and angle speed values and revolution counter behavior.
hudakz 0:4b76b1dc05cd 260 bool PREDICT; //!< bits 2:2 Prediction of angle value based on current angle speed
hudakz 0:4b76b1dc05cd 261 uint8_t AUTOCAL; //!< bits 1:0 Automatic calibration of offset and amplitude synchronicity for applications with full-turn.
hudakz 0:4b76b1dc05cd 262 uint16_t reg; //!< the register value
hudakz 0:4b76b1dc05cd 263
hudakz 0:4b76b1dc05cd 264 uint8_t fetch_AUTOCAL(uint16_t reg) {AUTOCAL = (reg & 0x3);return (AUTOCAL);}
hudakz 0:4b76b1dc05cd 265 bool fetch_PREDICT(uint16_t reg) {PREDICT = (reg & 0x4) >> 2;return (PREDICT);}
hudakz 0:4b76b1dc05cd 266 bool fetch_ANGDIR(uint16_t reg) {ANGDIR = (reg & 0x8) >> 3;return (ANGDIR);}
hudakz 0:4b76b1dc05cd 267 uint16_t fetch_ANGRANGE(uint16_t reg) {ANGRANGE = (reg & 0x7FF0) >> 4;return (ANGRANGE);}
hudakz 0:4b76b1dc05cd 268 bool fetch_Reserverd1(uint16_t reg) {Reserverd1 = (reg & 0x8000) >> 15;return (Reserverd1);}
hudakz 0:4b76b1dc05cd 269 };
hudakz 0:4b76b1dc05cd 270
hudakz 0:4b76b1dc05cd 271 struct mod3_t //!< MOD_3 Interface Mode3 register offset 0x09
hudakz 0:4b76b1dc05cd 272 {
hudakz 0:4b76b1dc05cd 273 uint16_t ANG_BASE; //!< bits 15:4 Sets the 0° angle position (12 bit value). Angle base is factory-calibrated to make the 0° direction parallel to the edge of the chip.
hudakz 0:4b76b1dc05cd 274 bool SPIKEF; //!< bits 3:3 Filters voltage spikes on input pads (IFC, SCK and CSQ).
hudakz 0:4b76b1dc05cd 275 bool SSCOD; //!< bits 2:2 SSC-Interface Data Pin Output Mode
hudakz 0:4b76b1dc05cd 276 uint8_t PADDRV; //!< bits 1;0 Configuration of Pad-Driver
hudakz 0:4b76b1dc05cd 277 uint16_t reg; //!< the register value
hudakz 0:4b76b1dc05cd 278
hudakz 0:4b76b1dc05cd 279 uint8_t fetch_PADDRV(uint16_t reg) {PADDRV = (reg & 0x3);return (PADDRV);}
hudakz 0:4b76b1dc05cd 280 bool fetch_SSCOD(uint16_t reg) {SSCOD = (reg & 0x4) >> 2;return (SSCOD);}
hudakz 0:4b76b1dc05cd 281 bool fetch_SPIKEF(uint16_t reg) {SPIKEF = (reg & 0x8) >> 3;return (SPIKEF);}
hudakz 0:4b76b1dc05cd 282 uint16_t fetch_ANG_BASE(uint16_t reg) {ANG_BASE = (reg & 0xFFF0) >> 4;return (ANG_BASE);}
hudakz 0:4b76b1dc05cd 283 };
hudakz 0:4b76b1dc05cd 284
hudakz 0:4b76b1dc05cd 285 struct offx_t //!< Offset X offset 0x0a
hudakz 0:4b76b1dc05cd 286 {
hudakz 0:4b76b1dc05cd 287 int16_t XOFFSET; //!< bits 15:4 12-bit signed integer value of raw X-signal offset correction at 25°C.
hudakz 0:4b76b1dc05cd 288 uint8_t Reserverd1; //!< bits 3:0
hudakz 0:4b76b1dc05cd 289 uint16_t reg; //!< the register value
hudakz 0:4b76b1dc05cd 290
hudakz 0:4b76b1dc05cd 291 uint8_t fetch_Reserverd1(uint16_t reg) {Reserverd1 = (reg & 0xF);return (Reserverd1);}
hudakz 0:4b76b1dc05cd 292 int16_t fetch_XOFFSET(uint16_t reg)
hudakz 0:4b76b1dc05cd 293 {
hudakz 0:4b76b1dc05cd 294 XOFFSET = ((reg & 0xFFF0) >> 4);
hudakz 0:4b76b1dc05cd 295 if (XOFFSET & 0x800)
hudakz 0:4b76b1dc05cd 296 {
hudakz 0:4b76b1dc05cd 297 XOFFSET = XOFFSET * -1;
hudakz 0:4b76b1dc05cd 298 }
hudakz 0:4b76b1dc05cd 299 return (XOFFSET);
hudakz 0:4b76b1dc05cd 300 }
hudakz 0:4b76b1dc05cd 301 };
hudakz 0:4b76b1dc05cd 302
hudakz 0:4b76b1dc05cd 303 struct offy_t //!< Offset Y offset 0x0b
hudakz 0:4b76b1dc05cd 304 {
hudakz 0:4b76b1dc05cd 305 int16_t YOFFSET; //!< bits 15:4 12-bit signed integer value of raw Y-signal offset correction at 25°C.
hudakz 0:4b76b1dc05cd 306 uint8_t Reserverd1; //!< bits 3:0
hudakz 0:4b76b1dc05cd 307 uint16_t reg; //!< the register value
hudakz 0:4b76b1dc05cd 308
hudakz 0:4b76b1dc05cd 309 uint8_t fetch_Reserverd1(uint16_t reg) {Reserverd1 = (reg & 0xF);return (Reserverd1);}
hudakz 0:4b76b1dc05cd 310 int16_t fetch_YOFFSET(uint16_t reg)
hudakz 0:4b76b1dc05cd 311 {
hudakz 0:4b76b1dc05cd 312 YOFFSET = ((reg & 0xFFF0) >> 4);
hudakz 0:4b76b1dc05cd 313 if (YOFFSET & 0x800)
hudakz 0:4b76b1dc05cd 314 {
hudakz 0:4b76b1dc05cd 315 YOFFSET = YOFFSET * -1;
hudakz 0:4b76b1dc05cd 316 }
hudakz 0:4b76b1dc05cd 317 return (YOFFSET);
hudakz 0:4b76b1dc05cd 318 }
hudakz 0:4b76b1dc05cd 319 };
hudakz 0:4b76b1dc05cd 320
hudakz 0:4b76b1dc05cd 321 struct synch_t { //!< Synchronicity offset 0x0c
hudakz 0:4b76b1dc05cd 322 int16_t SYNCH; //!< bits 15:4 12-bit signed integer value of amplitude synchronicity
hudakz 0:4b76b1dc05cd 323 uint8_t Reserverd1; //!< bits 3:0
hudakz 0:4b76b1dc05cd 324 uint16_t reg; //!< the register value
hudakz 0:4b76b1dc05cd 325
hudakz 0:4b76b1dc05cd 326 uint8_t fetch_Reserverd1(uint16_t reg) {Reserverd1 = (reg & 0xF);return (Reserverd1);}
hudakz 0:4b76b1dc05cd 327 int16_t fetch_SYNCH(uint16_t reg) {
hudakz 0:4b76b1dc05cd 328 SYNCH = ((reg & 0xFFF0) >> 4);
hudakz 0:4b76b1dc05cd 329 if (SYNCH & 0x800) {
hudakz 0:4b76b1dc05cd 330 SYNCH = SYNCH * -1;
hudakz 0:4b76b1dc05cd 331 }
hudakz 0:4b76b1dc05cd 332 return (SYNCH);
hudakz 0:4b76b1dc05cd 333 }
hudakz 0:4b76b1dc05cd 334 };
hudakz 0:4b76b1dc05cd 335
hudakz 0:4b76b1dc05cd 336 struct ifab_t { //!< IFAB register offset 0x0d
hudakz 0:4b76b1dc05cd 337 int16_t ORTHO; //!< bits 15:4 Orthogonality Correction of X and Y Components
hudakz 0:4b76b1dc05cd 338 bool FIRUDR; //!< bits 3:3 Initial filter update rate (FIR)
hudakz 0:4b76b1dc05cd 339 bool IFABOD; //!< bits 2:2 IFA,IFB,IFC Output Mode
hudakz 0:4b76b1dc05cd 340 uint8_t IFADHYST; //!< bits 1:0 Hysteresis (multi-purpose)
hudakz 0:4b76b1dc05cd 341 uint16_t reg; //!< the register value
hudakz 0:4b76b1dc05cd 342
hudakz 0:4b76b1dc05cd 343 uint8_t fetch_IFADHYST(uint16_t reg) {IFADHYST = (reg & 0x3);return (IFADHYST);}
hudakz 0:4b76b1dc05cd 344 bool fetch_IFABOD(uint16_t reg) {IFABOD = (reg & 0x4) >> 2;return (IFABOD);}
hudakz 0:4b76b1dc05cd 345 bool fetch_FIRUDR(uint16_t reg) {FIRUDR = (reg & 0x8) >> 3;return (FIRUDR);}
hudakz 0:4b76b1dc05cd 346 int16_t fetch_ORTHO(uint16_t reg) {
hudakz 0:4b76b1dc05cd 347 ORTHO = ((reg & 0xFFF0) >> 4);
hudakz 0:4b76b1dc05cd 348 if (ORTHO & 0x800) {
hudakz 0:4b76b1dc05cd 349 ORTHO = ORTHO * -1;
hudakz 0:4b76b1dc05cd 350 }
hudakz 0:4b76b1dc05cd 351 return (ORTHO);
hudakz 0:4b76b1dc05cd 352 }
hudakz 0:4b76b1dc05cd 353 };
hudakz 0:4b76b1dc05cd 354
hudakz 0:4b76b1dc05cd 355 struct mod4_t { //!< MOD_4 Interface Mode4 register offset 0x0e
hudakz 0:4b76b1dc05cd 356 int8_t TCOXT; //!< bits 15:9 7-bit signed integer value of X-offset temperature coefficient.
hudakz 0:4b76b1dc05cd 357 uint8_t HSMPLP; //!< bits 8:5 Hall Switch mode (multi-purpose)
hudakz 0:4b76b1dc05cd 358 uint8_t IFABRES; //!< bits 4:3 IIF resolution (multi-purpose)
hudakz 0:4b76b1dc05cd 359 bool Reserverd1; //!< bits 2:2
hudakz 0:4b76b1dc05cd 360 uint8_t IFMD; //!< bits 1:0 Interface Mode on IFA,IFB,IFC
hudakz 0:4b76b1dc05cd 361 uint16_t reg; //!< the register value
hudakz 0:4b76b1dc05cd 362
hudakz 0:4b76b1dc05cd 363 uint8_t fetch_IFMD(uint16_t reg) {IFMD = (reg & 0x3);return (IFMD);}
hudakz 0:4b76b1dc05cd 364 bool fetch_Reserverd1(uint16_t reg) {Reserverd1 = (reg & 0x4) >> 2;return (Reserverd1);}
hudakz 0:4b76b1dc05cd 365 uint8_t fetch_IFABRES(uint16_t reg) {IFABRES = (reg & 0x18) >> 3;return (IFABRES);}
hudakz 0:4b76b1dc05cd 366 uint8_t fetch_HSMPLP(uint16_t reg) {HSMPLP = (reg & 0x1E0) >> 5;return (HSMPLP);}
hudakz 0:4b76b1dc05cd 367 int8_t fetch_TCOXT(uint16_t reg) {
hudakz 0:4b76b1dc05cd 368 TCOXT = ((reg & 0x7E00) >> 9);
hudakz 0:4b76b1dc05cd 369 if (TCOXT & 0x8000) {
hudakz 0:4b76b1dc05cd 370 TCOXT = TCOXT * -1;
hudakz 0:4b76b1dc05cd 371 }
hudakz 0:4b76b1dc05cd 372 return (TCOXT);
hudakz 0:4b76b1dc05cd 373 }
hudakz 0:4b76b1dc05cd 374 };
hudakz 0:4b76b1dc05cd 375
hudakz 0:4b76b1dc05cd 376 struct tcoy_t { //!< TCO_Y Temperature Coefficient register offset 0x0f
hudakz 0:4b76b1dc05cd 377 int8_t TCOYT; //!< bits 15:9 7-bit signed integer value of Y-offset temperature coefficient.
hudakz 0:4b76b1dc05cd 378 bool SBIST; //!< bits 8:8 Startup-BIST
hudakz 0:4b76b1dc05cd 379 uint16_t CRCPAR; //!< bits 7:0 CRC of Parameters
hudakz 0:4b76b1dc05cd 380 uint16_t reg; //!< the register value
hudakz 0:4b76b1dc05cd 381
hudakz 0:4b76b1dc05cd 382 uint16_t fetch_CRCPAR(uint16_t reg) {TCOYT = (reg & 0x7F);return (TCOYT);}
hudakz 0:4b76b1dc05cd 383 bool fetch_SBIST(uint16_t reg) {SBIST = (reg & 0x80) >> 8;return (SBIST);}
hudakz 0:4b76b1dc05cd 384 int8_t fetch_TCOYT(uint16_t reg) {
hudakz 0:4b76b1dc05cd 385 TCOYT = ((reg & 0x7E00) >> 9);
hudakz 0:4b76b1dc05cd 386 if (TCOYT & 0x8000) {
hudakz 0:4b76b1dc05cd 387 TCOYT = TCOYT * -1;
hudakz 0:4b76b1dc05cd 388 }
hudakz 0:4b76b1dc05cd 389 return (TCOYT);
hudakz 0:4b76b1dc05cd 390 }
hudakz 0:4b76b1dc05cd 391 };
hudakz 0:4b76b1dc05cd 392
hudakz 0:4b76b1dc05cd 393 struct adc_t { //!< ADC_X offset 0x10, ADC_Y offset 0x11
hudakz 0:4b76b1dc05cd 394 int16_t ADCX; //!< bits 15:0 ADC value of X-GMR
hudakz 0:4b76b1dc05cd 395 int16_t ADCY; //!< bits 15:0 ADC value of Y-GMR
hudakz 0:4b76b1dc05cd 396 };
hudakz 0:4b76b1dc05cd 397
hudakz 0:4b76b1dc05cd 398 struct dmag_t { //!< D_Mag vector magnitude offset 0x14
hudakz 0:4b76b1dc05cd 399 uint8_t Reserverd1; //!< bits 15:10
hudakz 0:4b76b1dc05cd 400 uint16_t MAG; //!< bits 9:0 Unsigned Angle Vector Magnitude after X, Y error compensation (due to temperature).
hudakz 0:4b76b1dc05cd 401 uint16_t reg; //!< the register value
hudakz 0:4b76b1dc05cd 402
hudakz 0:4b76b1dc05cd 403 uint16_t fetch_MAG(uint16_t reg) {MAG = (reg & 0x3FF);return (MAG);}
hudakz 0:4b76b1dc05cd 404 uint8_t fetch_Reserverd1(uint16_t reg) {Reserverd1 = (reg & 0xFC00) >> 10;return (Reserverd1);}
hudakz 0:4b76b1dc05cd 405 };
hudakz 0:4b76b1dc05cd 406
hudakz 0:4b76b1dc05cd 407 struct traw_t { //!< T_RAW temperature raw data offset 0x15
hudakz 0:4b76b1dc05cd 408 bool TTGL; //!< bits 15:15 Temperature Sensor Raw-Value Toggle toggles after every new temperature value
hudakz 0:4b76b1dc05cd 409 uint8_t Reserverd1; //!< bits 14:10
hudakz 0:4b76b1dc05cd 410 uint16_t TRAW; //!< bits 9:0 Temperature Sensor Raw-Value at ADC without offset
hudakz 0:4b76b1dc05cd 411 uint16_t reg; //!< the register value
hudakz 0:4b76b1dc05cd 412
hudakz 0:4b76b1dc05cd 413 bool fetch_TRAW(uint16_t reg) {TRAW = (reg & 0x3FF);return (TRAW);}
hudakz 0:4b76b1dc05cd 414 uint8_t fetch_Reserverd1(uint16_t reg) {Reserverd1 = (reg & 0xFC00) >> 10;return (Reserverd1);}
hudakz 0:4b76b1dc05cd 415 uint16_t fetch_TTGL(uint16_t reg) {TTGL = (reg & 0x8000) >> 15;return (TTGL);}
hudakz 0:4b76b1dc05cd 416 };
hudakz 0:4b76b1dc05cd 417
hudakz 0:4b76b1dc05cd 418 struct iifcnt_t { //!< IIF counter value offset 0x20
hudakz 0:4b76b1dc05cd 419 bool Reserverd1; //!< bits 15:14
hudakz 0:4b76b1dc05cd 420 uint16_t IIFCNT; //!< bits 14:0 14 bit counter value of IIF increments
hudakz 0:4b76b1dc05cd 421 uint16_t reg; //!< the register value
hudakz 0:4b76b1dc05cd 422
hudakz 0:4b76b1dc05cd 423 uint16_t fetch_IIFCNT(uint16_t reg) {IIFCNT = (reg & 0x7FFF);return (IIFCNT);}
hudakz 0:4b76b1dc05cd 424 bool fetch_Reserverd1(uint16_t reg) {Reserverd1 = (reg & 0x8000) >> 15;return (Reserverd1);}
hudakz 0:4b76b1dc05cd 425 };
hudakz 0:4b76b1dc05cd 426
hudakz 0:4b76b1dc05cd 427 struct t250_t { //!< register T250 offset 0x30
hudakz 0:4b76b1dc05cd 428 int16_t T250; //!< bits 15:9 Signed offset value at 25°C temperature; 1dig=0.36°C.
hudakz 0:4b76b1dc05cd 429 uint16_t Reserverd1; //!< bit 8:0
hudakz 0:4b76b1dc05cd 430 uint16_t reg; //!< the register value
hudakz 0:4b76b1dc05cd 431
hudakz 0:4b76b1dc05cd 432 int16_t fetch_T250(uint16_t reg) {T250 = (reg & 0x1FFF);return (T250);}
hudakz 0:4b76b1dc05cd 433 uint16_t fetch_Reserverd1(uint16_t reg) {Reserverd1 = (reg & 0xFE00) >> 9;return (Reserverd1);}
hudakz 0:4b76b1dc05cd 434 };
hudakz 0:4b76b1dc05cd 435
hudakz 0:4b76b1dc05cd 436 typedef struct {
hudakz 0:4b76b1dc05cd 437 uint16_t registers[MAX_NUM_REG]; //!< raw register memory
hudakz 0:4b76b1dc05cd 438 interfaceType interface; //!< enum identify the Interface type
hudakz 0:4b76b1dc05cd 439 sensorType sensorBoard; //!< enum identify the PCM board type
hudakz 0:4b76b1dc05cd 440 char interfaceName[4];
hudakz 0:4b76b1dc05cd 441 char sensorName[16];
hudakz 0:4b76b1dc05cd 442 const char* nameOfRegister[MAX_NUM_REG] = {
hudakz 0:4b76b1dc05cd 443 "STAT ","ACSTAT","AVAL ","ASPD ","AREV ",
hudakz 0:4b76b1dc05cd 444 "FSYNC ","MOD1 ","SIL ","MOD2 ","MOD3 ",
hudakz 0:4b76b1dc05cd 445 "OFFX ","OFFY ","SYNCH ","IFAB ","MOD4 ",
hudakz 0:4b76b1dc05cd 446 "TCOY ","ADCX ","ADCY ","DMAG ","TRAW ",
hudakz 0:4b76b1dc05cd 447 "IIFCNT","T250 "
hudakz 0:4b76b1dc05cd 448 };
hudakz 0:4b76b1dc05cd 449 struct stat_t stat;
hudakz 0:4b76b1dc05cd 450 struct acstat_t acstat;
hudakz 0:4b76b1dc05cd 451 struct aval_t aval;
hudakz 0:4b76b1dc05cd 452 struct aspd_t aspd;
hudakz 0:4b76b1dc05cd 453 struct arev_t arev;
hudakz 0:4b76b1dc05cd 454 struct fsync_t fsync;
hudakz 0:4b76b1dc05cd 455 struct mod1_t mod1;
hudakz 0:4b76b1dc05cd 456 struct sil_t sil;
hudakz 0:4b76b1dc05cd 457 struct mod2_t mod2;
hudakz 0:4b76b1dc05cd 458 struct mod3_t mod3;
hudakz 0:4b76b1dc05cd 459 struct offx_t offx;
hudakz 0:4b76b1dc05cd 460 struct offy_t offy;
hudakz 0:4b76b1dc05cd 461 struct synch_t synch;
hudakz 0:4b76b1dc05cd 462 struct ifab_t ifab;
hudakz 0:4b76b1dc05cd 463 struct mod4_t mod4;
hudakz 0:4b76b1dc05cd 464 struct tcoy_t tcoy;
hudakz 0:4b76b1dc05cd 465 struct adc_t adc;
hudakz 0:4b76b1dc05cd 466 struct dmag_t dmag;
hudakz 0:4b76b1dc05cd 467 struct traw_t traw;
hudakz 0:4b76b1dc05cd 468 struct iifcnt_t iifcnt;
hudakz 0:4b76b1dc05cd 469 struct t250_t t250;
hudakz 0:4b76b1dc05cd 470 } regSensor_t;
hudakz 0:4b76b1dc05cd 471
hudakz 0:4b76b1dc05cd 472 regSensor_t sensorRegister; //!< sensor register read and separation
hudakz 0:4b76b1dc05cd 473
hudakz 0:4b76b1dc05cd 474 /*!
hudakz 0:4b76b1dc05cd 475 * Function reads all readable sensor registers
hudakz 0:4b76b1dc05cd 476 * and separates the information fields. This function
hudakz 0:4b76b1dc05cd 477 * is needed for finding the selected interface type.
hudakz 0:4b76b1dc05cd 478 * @param [in,out] sensorRegister point to the sensor register structure
hudakz 0:4b76b1dc05cd 479 * @return CRC error type
hudakz 0:4b76b1dc05cd 480 */
hudakz 0:4b76b1dc05cd 481 errorTypes readSensorType();
hudakz 0:4b76b1dc05cd 482
hudakz 0:4b76b1dc05cd 483 /*!
hudakz 0:4b76b1dc05cd 484 * Function identifies the current set interface type
hudakz 0:4b76b1dc05cd 485 * according some characteristic register settings
hudakz 0:4b76b1dc05cd 486 * @return CRC error type
hudakz 0:4b76b1dc05cd 487 */
hudakz 0:4b76b1dc05cd 488 errorTypes identifyInterfaceType();
hudakz 0:4b76b1dc05cd 489
hudakz 0:4b76b1dc05cd 490 /*!
hudakz 0:4b76b1dc05cd 491 * Functions switches between all possible interface types.
hudakz 0:4b76b1dc05cd 492 * ATTENTION: The different interfaces support not always all
hudakz 0:4b76b1dc05cd 493 * values, see documentation for the ability of each interface.
hudakz 0:4b76b1dc05cd 494 * If you want to be save, than choose the default SSC interface
hudakz 0:4b76b1dc05cd 495 * which always supports all possible parameter.
hudakz 0:4b76b1dc05cd 496 * @param iface type of interface to switch to
hudakz 0:4b76b1dc05cd 497 * @return CRC error type
hudakz 0:4b76b1dc05cd 498 */
hudakz 0:4b76b1dc05cd 499 errorTypes writeInterfaceType(interfaceType iface);
hudakz 0:4b76b1dc05cd 500
hudakz 0:4b76b1dc05cd 501 /*!
hudakz 0:4b76b1dc05cd 502 * Function reset the Sensor to fuse defaults
hudakz 0:4b76b1dc05cd 503 * @return CRC error type
hudakz 0:4b76b1dc05cd 504 */
hudakz 0:4b76b1dc05cd 505 errorTypes resetFirmware();
hudakz 0:4b76b1dc05cd 506
hudakz 0:4b76b1dc05cd 507 /*!
hudakz 0:4b76b1dc05cd 508 * Function set the sensors calibration mode. Keep in mind,
hudakz 0:4b76b1dc05cd 509 * not all Sensor interface setups have the autocalibration
hudakz 0:4b76b1dc05cd 510 * switched on, so maybe you have to set it explicitly.
hudakz 0:4b76b1dc05cd 511 * @param [in] calibrationMode the auto calibration mode to set
hudakz 0:4b76b1dc05cd 512 * @return CRC error type
hudakz 0:4b76b1dc05cd 513 */
hudakz 0:4b76b1dc05cd 514 errorTypes setCalibration(calibrationMode calMode);
hudakz 0:4b76b1dc05cd 515
hudakz 0:4b76b1dc05cd 516
hudakz 0:4b76b1dc05cd 517 private:
hudakz 0:4b76b1dc05cd 518
hudakz 0:4b76b1dc05cd 519 /*!
hudakz 0:4b76b1dc05cd 520 * Identify the sensor interface and PCB board
hudakz 0:4b76b1dc05cd 521 */
hudakz 0:4b76b1dc05cd 522 void _identify();
hudakz 0:4b76b1dc05cd 523
hudakz 0:4b76b1dc05cd 524 };
hudakz 0:4b76b1dc05cd 525
hudakz 0:4b76b1dc05cd 526 #endif