EMAC driver for the ENC28J60 Ethernet controller. This is a simplified fork of https://github.com/tobiasjaster/ENC28J60-EMAC-Driver published by Tobias Jaster.
Dependents: MQTT_Hello MQTT_HelloENC28J60
EMAC driver for the ENC28J60 Ethernet controller
This is a fork (the INT and RST pins are not used) of the ENC28J60-EMAC driver published by Tobias Jaster at
https://github.com/tobiasjaster/ENC28J60-EMAC-Driver
Usage:
- Connect the ENC28J60 module to the Mbed board as follows:
- Import (add) this ENC28J60-EMAC library to your program.
- Add a "mbed_app.json" file with the following content to the root directory of your program:
{ "target_overrides": { "*": { "platform.callback-nontrivial": true, "enc28j60-emac.mosi": "D11", "enc28j60-emac.miso": "D12", "enc28j60-emac.sck" : "D13", "enc28j60-emac.cs" : "D10" } } }
- Replace "D11", ..., "D10" with the actual pin names you selected on the Mbed board to be used for the SPI communication.
- To set the MAC address define an array with the desired address bytes and call the "set_hwaddr(mac)" function before calling the network interface "connect" function.
For example:
const uint8_t MAC[6] = { 0, 1, 2, 3, 4, 5 }; EthernetInterface net; int main() { net.get_emac().set_hwaddr(MAC); // set MAC address if (net.connect() != 0) { printf("Error: Unable to connect to the network.\n"); return -1; } ...
enc28j60_reg.h@0:b599e748252c, 2021-03-26 (annotated)
- Committer:
- hudakz
- Date:
- Fri Mar 26 15:58:28 2021 +0000
- Revision:
- 0:b599e748252c
Mbed OS Ethernet MAC (EMAC) driver for the ENC28J60 Ethernet controller.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
hudakz | 0:b599e748252c | 1 | /***************************************************************************** |
hudakz | 0:b599e748252c | 2 | * |
hudakz | 0:b599e748252c | 3 | * Title : Microchip ENC28J60 Ethernet Controller Registers |
hudakz | 0:b599e748252c | 4 | * Author : Pascal Stang (c)2005 |
hudakz | 0:b599e748252c | 5 | * Modified by : Tobias Jaster |
hudakz | 0:b599e748252c | 6 | * Modified by : Zoltan Hudak |
hudakz | 0:b599e748252c | 7 | * Copyright : GPL V2 |
hudakz | 0:b599e748252c | 8 | * |
hudakz | 0:b599e748252c | 9 | *This driver provides initialization and transmit/receive |
hudakz | 0:b599e748252c | 10 | *functions for the Microchip ENC28J60 10Mb Ethernet Controller and PHY. |
hudakz | 0:b599e748252c | 11 | *This chip is novel in that it is a full MAC+PHY interface all in a 28-pin |
hudakz | 0:b599e748252c | 12 | *chip, using an SPI interface to the host processor. |
hudakz | 0:b599e748252c | 13 | * |
hudakz | 0:b599e748252c | 14 | * |
hudakz | 0:b599e748252c | 15 | *****************************************************************************/ |
hudakz | 0:b599e748252c | 16 | #ifndef ENC28J60_REG_H |
hudakz | 0:b599e748252c | 17 | #define ENC28J60_REG_H |
hudakz | 0:b599e748252c | 18 | #include <inttypes.h> |
hudakz | 0:b599e748252c | 19 | #include "enc28j60_emac_config.h" |
hudakz | 0:b599e748252c | 20 | |
hudakz | 0:b599e748252c | 21 | // ENC28J60 Control Registers |
hudakz | 0:b599e748252c | 22 | |
hudakz | 0:b599e748252c | 23 | // Control register definitions are a combination of address, |
hudakz | 0:b599e748252c | 24 | // bank number, and Ethernet/MAC/PHY indicator bits. |
hudakz | 0:b599e748252c | 25 | // - Register address (bits 0-4) |
hudakz | 0:b599e748252c | 26 | // - Bank number (bits 5-6) |
hudakz | 0:b599e748252c | 27 | // - MAC/PHY indicator (bit 7) |
hudakz | 0:b599e748252c | 28 | #define ADDR_MASK 0x1F |
hudakz | 0:b599e748252c | 29 | #define BANK_MASK 0x60 |
hudakz | 0:b599e748252c | 30 | #define SPRD_MASK 0x80 |
hudakz | 0:b599e748252c | 31 | // All-bank registers |
hudakz | 0:b599e748252c | 32 | #define EIE 0x1B // ETHERNET INTERRUPT ENABLE REGISTER |
hudakz | 0:b599e748252c | 33 | #define EIR 0x1C // ETHERNET INTERRUPT REQUEST (FLAG) REGISTER |
hudakz | 0:b599e748252c | 34 | #define ESTAT 0x1D // ETHERNET STATUS REGISTER |
hudakz | 0:b599e748252c | 35 | #define ECON2 0x1E // ETHERNET CONTROL REGISTER 2 |
hudakz | 0:b599e748252c | 36 | #define ECON1 0x1F // ETHERNET CONTROL REGISTER 1 |
hudakz | 0:b599e748252c | 37 | |
hudakz | 0:b599e748252c | 38 | /* |
hudakz | 0:b599e748252c | 39 | * Bank 0 registers |
hudakz | 0:b599e748252c | 40 | */ |
hudakz | 0:b599e748252c | 41 | |
hudakz | 0:b599e748252c | 42 | // Points to a location in receive/transmit buffer to read from |
hudakz | 0:b599e748252c | 43 | #define ERDPTL (0x00 | 0x00) // Ethernet buffer Read Pointer Low Byte (ERDPT<7:0>) |
hudakz | 0:b599e748252c | 44 | #define ERDPTH (0x01 | 0x00) // Ethernet buffer Read Pointer High Byte (ERDPT<12:8>) |
hudakz | 0:b599e748252c | 45 | |
hudakz | 0:b599e748252c | 46 | // Points to a location in receive/transmit buffer to write to |
hudakz | 0:b599e748252c | 47 | #define EWRPTL (0x02 | 0x00) // Ethernet buffer Write Pointer Low Byte (EWRPT<7:0>) |
hudakz | 0:b599e748252c | 48 | #define EWRPTH (0x03 | 0x00) // Ethernet buffer Write Pointer High Byte (EWRPT<12:8>) |
hudakz | 0:b599e748252c | 49 | |
hudakz | 0:b599e748252c | 50 | // Pointers to transmit buffer boundaries |
hudakz | 0:b599e748252c | 51 | #define ETXSTL (0x04 | 0x00) // Ethernet Transmit buffer Start Low Byte (ETXST<7:0>) |
hudakz | 0:b599e748252c | 52 | #define ETXSTH (0x05 | 0x00) // Ethernet Transmit buffer Start High Byte (ETXST<12:8>) |
hudakz | 0:b599e748252c | 53 | #define ETXNDL (0x06 | 0x00) // Ethernet Transmit buffer End Low Byte (ETXND<7:0>) |
hudakz | 0:b599e748252c | 54 | #define ETXNDH (0x07 | 0x00) // Ethernet Transmit buffer End High Byte (ETXND<12:8>) |
hudakz | 0:b599e748252c | 55 | |
hudakz | 0:b599e748252c | 56 | // Pointers to receive buffer boundaries |
hudakz | 0:b599e748252c | 57 | #define ERXSTL (0x08 | 0x00) // Ethernet Receive buffer Start Low Byte (ERXST<7:0>) |
hudakz | 0:b599e748252c | 58 | #define ERXSTH (0x09 | 0x00) // Ethernet Receive buffer Start High Byte (ERXST<12:8>) |
hudakz | 0:b599e748252c | 59 | #define ERXNDL (0x0A | 0x00) // Ethernet Receive buffer End Low Byte (ERXND<7:0>) |
hudakz | 0:b599e748252c | 60 | #define ERXNDH (0x0B | 0x00) // Ethernet Receive buffer End High Byte (ERXND<12:8>) |
hudakz | 0:b599e748252c | 61 | |
hudakz | 0:b599e748252c | 62 | // Receive pointer. Receive hardware will write data up to, but not including the memory pointed to by ERXRDPT |
hudakz | 0:b599e748252c | 63 | #define ERXRDPTL (0x0C | 0x00) // Ethernet Receive buffer RD Pointer Low Byte (ERXRDPT<7:0>) |
hudakz | 0:b599e748252c | 64 | #define ERXRDPTH (0x0D | 0x00) // Ethernet Receive buffer RD Pointer High Byte (ERXRDPT<12:8>) |
hudakz | 0:b599e748252c | 65 | |
hudakz | 0:b599e748252c | 66 | // Location within the receive buffer where the hardware will write bytes that it receives. |
hudakz | 0:b599e748252c | 67 | // The pointer is read-only and is automatically updated by the hardware whenever |
hudakz | 0:b599e748252c | 68 | // a new packet is successfully received. |
hudakz | 0:b599e748252c | 69 | #define ERXWRPTL (0x0E | 0x00) // Ethernet Receive buffer WR Pointer Low Byte (ERXWRPT<7:0>) Read-only |
hudakz | 0:b599e748252c | 70 | #define ERXWRPTH (0x0F | 0x00) // Ethernet Receive buffer WR Pointer High Byte (ERXWRPT<12:8>) Read-only |
hudakz | 0:b599e748252c | 71 | |
hudakz | 0:b599e748252c | 72 | // Pointers to DMA boundaries |
hudakz | 0:b599e748252c | 73 | #define EDMASTL (0x10 | 0x00) // Ethernet buffer DMA Start Low Byte (EDMAST<7:0>) |
hudakz | 0:b599e748252c | 74 | #define EDMASTH (0x11 | 0x00) // Ethernet buffer DMA Start High Byte (EDMAST<12:8>) |
hudakz | 0:b599e748252c | 75 | #define EDMANDL (0x12 | 0x00) // Ethernet buffer DMA End Low Byte (EDMAND<7:0>) |
hudakz | 0:b599e748252c | 76 | #define EDMANDH (0x13 | 0x00) // Ethernet buffer DMA End High Byte (EDMAND<12:8>) |
hudakz | 0:b599e748252c | 77 | |
hudakz | 0:b599e748252c | 78 | // Points to the DMA memory copying destination in receive/transmit buffer |
hudakz | 0:b599e748252c | 79 | #define EDMADSTL (0x14 | 0x00) // Ethernet buffer DMA Destination Low Byte (EDMADST<7:0>) |
hudakz | 0:b599e748252c | 80 | #define EDMADSTH (0x15 | 0x00) // Ethernet buffer DMA Destination High Byte (EDMADST<12:8>) |
hudakz | 0:b599e748252c | 81 | |
hudakz | 0:b599e748252c | 82 | // Points to the DMA check sum calcularion location in receive/transmit buffer |
hudakz | 0:b599e748252c | 83 | #define EDMACSL (0x16 | 0x00) // Ethernet buffer DMA Checksum Low Byte (EDMACS<7:0>) |
hudakz | 0:b599e748252c | 84 | #define EDMACSH (0x17 | 0x00) // Ethernet buffer DMA Checksum High Byte (EDMACS<15:8>) |
hudakz | 0:b599e748252c | 85 | |
hudakz | 0:b599e748252c | 86 | /* |
hudakz | 0:b599e748252c | 87 | * Bank 1 registers |
hudakz | 0:b599e748252c | 88 | */ |
hudakz | 0:b599e748252c | 89 | #define EHT0 (0x00 | 0x20) //Hash Table Byte 0 (EHT<7:0>) |
hudakz | 0:b599e748252c | 90 | #define EHT1 (0x01 | 0x20) //Hash Table Byte 0 (EHT<7:0>) |
hudakz | 0:b599e748252c | 91 | #define EHT2 (0x02 | 0x20) //Hash Table Byte 0 (EHT<7:0>) |
hudakz | 0:b599e748252c | 92 | #define EHT3 (0x03 | 0x20) //Hash Table Byte 3 (EHT<31:24>) |
hudakz | 0:b599e748252c | 93 | #define EHT4 (0x04 | 0x20) //Hash Table Byte 3 (EHT<31:24>) |
hudakz | 0:b599e748252c | 94 | #define EHT5 (0x05 | 0x20) //Hash Table Byte 3 (EHT<31:24>) |
hudakz | 0:b599e748252c | 95 | #define EHT6 (0x06 | 0x20) //Hash Table Byte 3 (EHT<31:24>) |
hudakz | 0:b599e748252c | 96 | #define EHT7 (0x07 | 0x20) //Hash Table Byte 3 (EHT<31:24>) |
hudakz | 0:b599e748252c | 97 | #define EPMM0 (0x08 | 0x20) //Pattern Match Mask Byte 0 (EPMM<7:0>) |
hudakz | 0:b599e748252c | 98 | #define EPMM1 (0x09 | 0x20) //Pattern Match Mask Byte 1 (EPMM<15:8>) |
hudakz | 0:b599e748252c | 99 | #define EPMM2 (0x0A | 0x20) //Pattern Match Mask Byte 2 (EPMM<23:16>) |
hudakz | 0:b599e748252c | 100 | #define EPMM3 (0x0B | 0x20) //Pattern Match Mask Byte 3 (EPMM<31:24>) |
hudakz | 0:b599e748252c | 101 | #define EPMM4 (0x0C | 0x20) //Pattern Match Mask Byte 4 (EPMM<39:32>) |
hudakz | 0:b599e748252c | 102 | #define EPMM5 (0x0D | 0x20) //Pattern Match Mask Byte 5 (EPMM<47:40>) |
hudakz | 0:b599e748252c | 103 | #define EPMM6 (0x0E | 0x20) //Pattern Match Mask Byte 6 (EPMM<55:48>) |
hudakz | 0:b599e748252c | 104 | #define EPMM7 (0x0F | 0x20) //Pattern Match Mask Byte 7 (EPMM<63:56>) |
hudakz | 0:b599e748252c | 105 | #define EPMCSL (0x10 | 0x20) //Pattern Match Checksum Low Byte (EPMCS<7:0>) |
hudakz | 0:b599e748252c | 106 | #define EPMCSH (0x11 | 0x20) //Pattern Match Checksum High Byte (EPMCS<15:0>) |
hudakz | 0:b599e748252c | 107 | #define EPMOL (0x14 | 0x20) //Pattern Match Offset Low Byte (EPMO<7:0>) |
hudakz | 0:b599e748252c | 108 | #define EPMOH (0x15 | 0x20) //Pattern Match Offset High Byte (EPMO<12:8>) |
hudakz | 0:b599e748252c | 109 | #define EWOLIE (0x16 | 0x20) //Reserved |
hudakz | 0:b599e748252c | 110 | #define EWOLIR (0x17 | 0x20) //Reserved |
hudakz | 0:b599e748252c | 111 | #define ERXFCON (0x18 | 0x20) //ETHERNET RECEIVE FILTER CONTROL REGISTER |
hudakz | 0:b599e748252c | 112 | #define EPKTCNT (0x19 | 0x20) //Ethernet Packet Count |
hudakz | 0:b599e748252c | 113 | |
hudakz | 0:b599e748252c | 114 | /* |
hudakz | 0:b599e748252c | 115 | * Bank 2 registers |
hudakz | 0:b599e748252c | 116 | */ |
hudakz | 0:b599e748252c | 117 | #define MACON1 (0x00 | 0x40 | 0x80) //MAC CONTROL REGISTER 1 |
hudakz | 0:b599e748252c | 118 | #define MACON2 (0x01 | 0x40 | 0x80) //MAC CONTROL REGISTER 2 |
hudakz | 0:b599e748252c | 119 | #define MACON3 (0x02 | 0x40 | 0x80) //MAC CONTROL REGISTER 3 |
hudakz | 0:b599e748252c | 120 | #define MACON4 (0x03 | 0x40 | 0x80) //MAC CONTROL REGISTER 4 |
hudakz | 0:b599e748252c | 121 | #define MABBIPG (0x04 | 0x40 | 0x80) //Back-to-Back Inter-Packet Gap (BBIPG<6:0>) |
hudakz | 0:b599e748252c | 122 | #define MAIPGL (0x06 | 0x40 | 0x80) //Non-Back-to-Back Inter-Packet Gap Low Byte (MAIPGL<6:0>) |
hudakz | 0:b599e748252c | 123 | #define MAIPGH (0x07 | 0x40 | 0x80) //Non-Back-to-Back Inter-Packet Gap High Byte (MAIPGH<6:0>) |
hudakz | 0:b599e748252c | 124 | #define MACLCON1 (0x08 | 0x40 | 0x80) //Retransmission Maximum (RETMAX<3:0>) |
hudakz | 0:b599e748252c | 125 | #define MACLCON2 (0x09 | 0x40 | 0x80) //Collision Window (COLWIN<5:0> |
hudakz | 0:b599e748252c | 126 | #define MAMXFLL (0x0A | 0x40 | 0x80) //Maximum Frame Length Low Byte (MAMXFL<7:0>) |
hudakz | 0:b599e748252c | 127 | #define MAMXFLH (0x0B | 0x40 | 0x80) //Maximum Frame Length High Byte (MAMXFL<15:8>) |
hudakz | 0:b599e748252c | 128 | #define MAPHSUP (0x0D | 0x40 | 0x80) //Reserved |
hudakz | 0:b599e748252c | 129 | #define MICON (0x11 | 0x40 | 0x80) //Reserved |
hudakz | 0:b599e748252c | 130 | #define MICMD (0x12 | 0x40 | 0x80) //MII COMMAND REGISTER |
hudakz | 0:b599e748252c | 131 | #define MIREGADR (0x14 | 0x40 | 0x80) //MII Register Address (MIREGADR<4:0>) |
hudakz | 0:b599e748252c | 132 | #define MIWRL (0x16 | 0x40 | 0x80) //MII Write Data Low Byte (MIWR<7:0>) |
hudakz | 0:b599e748252c | 133 | #define MIWRH (0x17 | 0x40 | 0x80) //MII Write Data High Byte (MIWR<15:8>) |
hudakz | 0:b599e748252c | 134 | #define MIRDL (0x18 | 0x40 | 0x80) //MII Read Data Low Byte (MIRD<7:0>) |
hudakz | 0:b599e748252c | 135 | #define MIRDH (0x19 | 0x40 | 0x80) //MII Read Data High Byte(MIRD<15:8>) |
hudakz | 0:b599e748252c | 136 | |
hudakz | 0:b599e748252c | 137 | /* |
hudakz | 0:b599e748252c | 138 | * Bank 3 registers |
hudakz | 0:b599e748252c | 139 | */ |
hudakz | 0:b599e748252c | 140 | #define MAADR1 (0x00 | 0x60 | 0x80) //MAC Address Byte 1 (MAADR<47:40>), OUI Byte 1 |
hudakz | 0:b599e748252c | 141 | #define MAADR0 (0x01 | 0x60 | 0x80) //MAC Address Byte 2 (MAADR<39:32>), OUI Byte 2 |
hudakz | 0:b599e748252c | 142 | #define MAADR3 (0x02 | 0x60 | 0x80) //MAC Address Byte 3 (MAADR<31:24>), OUI Byte 3 |
hudakz | 0:b599e748252c | 143 | #define MAADR2 (0x03 | 0x60 | 0x80) //MAC Address Byte 4 (MAADR<23:16>) |
hudakz | 0:b599e748252c | 144 | #define MAADR5 (0x04 | 0x60 | 0x80) //MAC Address Byte 5 (MAADR<15:8>) |
hudakz | 0:b599e748252c | 145 | #define MAADR4 (0x05 | 0x60 | 0x80) //MAC Address Byte 4 (MAADR<23:16>) |
hudakz | 0:b599e748252c | 146 | #define EBSTSD (0x06 | 0x60) //Built-in Self-Test Fill Seed (EBSTSD<7:0>) |
hudakz | 0:b599e748252c | 147 | #define EBSTCON (0x07 | 0x60) // |
hudakz | 0:b599e748252c | 148 | #define EBSTCSL (0x08 | 0x60) //Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>) |
hudakz | 0:b599e748252c | 149 | #define EBSTCSH (0x09 | 0x60) //Built-in Self-Test Checksum High Byte (EBSTCS<15:8>) |
hudakz | 0:b599e748252c | 150 | #define MISTAT (0x0A | 0x60 | 0x80) //MII STATUS REGISTER |
hudakz | 0:b599e748252c | 151 | #define EREVID (0x12 | 0x60) //Ethernet Revision ID (EREVID<4:0>) |
hudakz | 0:b599e748252c | 152 | #define ECOCON (0x15 | 0x60) //CLOCK OUTPUT CONTROL REGISTER |
hudakz | 0:b599e748252c | 153 | #define EFLOCON (0x17 | 0x60) //ETHERNET FLOW CONTROL REGISTER |
hudakz | 0:b599e748252c | 154 | #define EPAUSL (0x18 | 0x60) //Pause Timer Value Low Byte (EPAUS<7:0>) |
hudakz | 0:b599e748252c | 155 | #define EPAUSH (0x19 | 0x60) //Pause Timer Value High Byte (EPAUS<15:8>) |
hudakz | 0:b599e748252c | 156 | |
hudakz | 0:b599e748252c | 157 | /* |
hudakz | 0:b599e748252c | 158 | * PHY registers |
hudakz | 0:b599e748252c | 159 | */ |
hudakz | 0:b599e748252c | 160 | #define PHCON1 0x00 //PHY CONTROL REGISTER 1 |
hudakz | 0:b599e748252c | 161 | #define PHSTAT1 0x01 //PHYSICAL LAYER STATUS REGISTER 1 |
hudakz | 0:b599e748252c | 162 | #define PHHID1 0x02 // |
hudakz | 0:b599e748252c | 163 | #define PHHID2 0x03 // |
hudakz | 0:b599e748252c | 164 | #define PHCON2 0x10 //PHY CONTROL REGISTER 2 |
hudakz | 0:b599e748252c | 165 | #define PHSTAT2 0x11 //PHYSICAL LAYER STATUS REGISTER 2 |
hudakz | 0:b599e748252c | 166 | #define PHIE 0x12 //PHY INTERRUPT ENABLE REGISTER |
hudakz | 0:b599e748252c | 167 | #define PHIR 0x13 //PHY INTERRUPT REQUEST (FLAG) REGISTER |
hudakz | 0:b599e748252c | 168 | #define PHLCON 0x14 //PHY MODULE LED CONTROL REGISTER |
hudakz | 0:b599e748252c | 169 | |
hudakz | 0:b599e748252c | 170 | /* |
hudakz | 0:b599e748252c | 171 | * ENC28J60 ERXFCON Register Bit Definitions |
hudakz | 0:b599e748252c | 172 | */ |
hudakz | 0:b599e748252c | 173 | #define ERXFCON_UCEN 0x80 |
hudakz | 0:b599e748252c | 174 | #define ERXFCON_ANDOR 0x40 |
hudakz | 0:b599e748252c | 175 | #define ERXFCON_CRCEN 0x20 |
hudakz | 0:b599e748252c | 176 | #define ERXFCON_PMEN 0x10 |
hudakz | 0:b599e748252c | 177 | #define ERXFCON_MPEN 0x08 |
hudakz | 0:b599e748252c | 178 | #define ERXFCON_HTEN 0x04 |
hudakz | 0:b599e748252c | 179 | #define ERXFCON_MCEN 0x02 |
hudakz | 0:b599e748252c | 180 | #define ERXFCON_BCEN 0x01 |
hudakz | 0:b599e748252c | 181 | /* |
hudakz | 0:b599e748252c | 182 | * ENC28J60 EIE Register Bit Definitions |
hudakz | 0:b599e748252c | 183 | */ |
hudakz | 0:b599e748252c | 184 | #define EIE_INTIE 0x80 |
hudakz | 0:b599e748252c | 185 | #define EIE_PKTIE 0x40 |
hudakz | 0:b599e748252c | 186 | #define EIE_DMAIE 0x20 |
hudakz | 0:b599e748252c | 187 | #define EIE_LINKIE 0x10 |
hudakz | 0:b599e748252c | 188 | #define EIE_TXIE 0x08 |
hudakz | 0:b599e748252c | 189 | #define EIE_WOLIE 0x04 |
hudakz | 0:b599e748252c | 190 | #define EIE_TXERIE 0x02 |
hudakz | 0:b599e748252c | 191 | #define EIE_RXERIE 0x01 |
hudakz | 0:b599e748252c | 192 | /* |
hudakz | 0:b599e748252c | 193 | * ENC28J60 EIR Register Bit Definitions |
hudakz | 0:b599e748252c | 194 | */ |
hudakz | 0:b599e748252c | 195 | #define EIR_PKTIF 0x40 // Receive Packet Pending Interrupt Flag bit |
hudakz | 0:b599e748252c | 196 | #define EIR_DMAIF 0x20 // DMA Interrupt Flag bit |
hudakz | 0:b599e748252c | 197 | #define EIR_LINKIF 0x10 // Link Change Interrupt Flag bit |
hudakz | 0:b599e748252c | 198 | #define EIR_TXIF 0x08 // Transmit Interrupt Flag bit |
hudakz | 0:b599e748252c | 199 | #define EIR_WOLIF 0x04 |
hudakz | 0:b599e748252c | 200 | #define EIR_TXERIF 0x02 // Transmit Error Interrupt Flag bit |
hudakz | 0:b599e748252c | 201 | #define EIR_RXERIF 0x01 // Receive Error Interrupt Flag bit |
hudakz | 0:b599e748252c | 202 | |
hudakz | 0:b599e748252c | 203 | /* |
hudakz | 0:b599e748252c | 204 | * ENC28J60 ESTAT Register Bit Definitions |
hudakz | 0:b599e748252c | 205 | */ |
hudakz | 0:b599e748252c | 206 | #define ESTAT_INT 0x80 // INT Interrupt Flag bit (INT interrupt is pending) |
hudakz | 0:b599e748252c | 207 | #define ESTAT_BUFER 0x40 // Ethernet Buffer Error Status bit |
hudakz | 0:b599e748252c | 208 | #define ESTAT_LATECOL 0x10 // Late Collision Error bit |
hudakz | 0:b599e748252c | 209 | #define ESTAT_RXBUSY 0x04 // Receive Busy bit |
hudakz | 0:b599e748252c | 210 | #define ESTAT_TXABRT 0x02 // Transmit Abort Error bit |
hudakz | 0:b599e748252c | 211 | #define ESTAT_CLKRDY 0x01 // Clock Ready bit |
hudakz | 0:b599e748252c | 212 | |
hudakz | 0:b599e748252c | 213 | /* |
hudakz | 0:b599e748252c | 214 | * ENC28J60 ECON2 Register Bit Definitions |
hudakz | 0:b599e748252c | 215 | */ |
hudakz | 0:b599e748252c | 216 | #define ECON2_AUTOINC 0x80 |
hudakz | 0:b599e748252c | 217 | #define ECON2_PKTDEC 0x40 |
hudakz | 0:b599e748252c | 218 | #define ECON2_PWRSV 0x20 |
hudakz | 0:b599e748252c | 219 | #define ECON2_VRPS 0x08 |
hudakz | 0:b599e748252c | 220 | /* |
hudakz | 0:b599e748252c | 221 | * ENC28J60 ECON1 Register Bit Definitions |
hudakz | 0:b599e748252c | 222 | */ |
hudakz | 0:b599e748252c | 223 | #define ECON1_TXRST 0x80 |
hudakz | 0:b599e748252c | 224 | #define ECON1_RXRST 0x40 |
hudakz | 0:b599e748252c | 225 | #define ECON1_DMAST 0x20 |
hudakz | 0:b599e748252c | 226 | #define ECON1_CSUMEN 0x10 |
hudakz | 0:b599e748252c | 227 | #define ECON1_TXRTS 0x08 |
hudakz | 0:b599e748252c | 228 | #define ECON1_RXEN 0x04 |
hudakz | 0:b599e748252c | 229 | #define ECON1_BSEL1 0x02 |
hudakz | 0:b599e748252c | 230 | #define ECON1_BSEL0 0x01 |
hudakz | 0:b599e748252c | 231 | /* |
hudakz | 0:b599e748252c | 232 | * ENC28J60 MACON1 Register Bit Definitions |
hudakz | 0:b599e748252c | 233 | */ |
hudakz | 0:b599e748252c | 234 | #define MACON1_LOOPBK 0x10 |
hudakz | 0:b599e748252c | 235 | #define MACON1_TXPAUS 0x08 |
hudakz | 0:b599e748252c | 236 | #define MACON1_RXPAUS 0x04 |
hudakz | 0:b599e748252c | 237 | #define MACON1_PASSALL 0x02 |
hudakz | 0:b599e748252c | 238 | #define MACON1_MARXEN 0x01 |
hudakz | 0:b599e748252c | 239 | /* |
hudakz | 0:b599e748252c | 240 | * ENC28J60 MACON2 Register Bit Definitions |
hudakz | 0:b599e748252c | 241 | */ |
hudakz | 0:b599e748252c | 242 | #define MACON2_MARST 0x80 |
hudakz | 0:b599e748252c | 243 | #define MACON2_RNDRST 0x40 |
hudakz | 0:b599e748252c | 244 | #define MACON2_MARXRST 0x08 |
hudakz | 0:b599e748252c | 245 | #define MACON2_RFUNRST 0x04 |
hudakz | 0:b599e748252c | 246 | #define MACON2_MATXRST 0x02 |
hudakz | 0:b599e748252c | 247 | #define MACON2_TFUNRST 0x01 |
hudakz | 0:b599e748252c | 248 | /* |
hudakz | 0:b599e748252c | 249 | * ENC28J60 MACON3 Register Bit Definitions |
hudakz | 0:b599e748252c | 250 | */ |
hudakz | 0:b599e748252c | 251 | #define MACON3_PADCFG2 0x80 |
hudakz | 0:b599e748252c | 252 | #define MACON3_PADCFG1 0x40 |
hudakz | 0:b599e748252c | 253 | #define MACON3_PADCFG0 0x20 |
hudakz | 0:b599e748252c | 254 | #define MACON3_TXCRCEN 0x10 |
hudakz | 0:b599e748252c | 255 | #define MACON3_PHDRLEN 0x08 |
hudakz | 0:b599e748252c | 256 | #define MACON3_HFRMLEN 0x04 |
hudakz | 0:b599e748252c | 257 | #define MACON3_FRMLNEN 0x02 |
hudakz | 0:b599e748252c | 258 | #define MACON3_FULDPX 0x01 |
hudakz | 0:b599e748252c | 259 | /* |
hudakz | 0:b599e748252c | 260 | * ENC28J60 MACON4 Register Bit Definitions |
hudakz | 0:b599e748252c | 261 | */ |
hudakz | 0:b599e748252c | 262 | #define MACON4_DEFER 0x40 |
hudakz | 0:b599e748252c | 263 | #define MACON4_BPEN 0x20 |
hudakz | 0:b599e748252c | 264 | #define MACON4_NOBKOFF 0x10 |
hudakz | 0:b599e748252c | 265 | /* |
hudakz | 0:b599e748252c | 266 | * ENC28J60 MICMD Register Bit Definitions |
hudakz | 0:b599e748252c | 267 | */ |
hudakz | 0:b599e748252c | 268 | #define MICMD_MIISCAN 0x02 |
hudakz | 0:b599e748252c | 269 | #define MICMD_MIIRD 0x01 |
hudakz | 0:b599e748252c | 270 | /* |
hudakz | 0:b599e748252c | 271 | * ENC28J60 MISTAT Register Bit Definitions |
hudakz | 0:b599e748252c | 272 | */ |
hudakz | 0:b599e748252c | 273 | #define MISTAT_NVALID 0x04 |
hudakz | 0:b599e748252c | 274 | #define MISTAT_SCAN 0x02 |
hudakz | 0:b599e748252c | 275 | #define MISTAT_BUSY 0x01 |
hudakz | 0:b599e748252c | 276 | /* |
hudakz | 0:b599e748252c | 277 | * ENC28J60 PHY PHCON1 Register Bit Definitions |
hudakz | 0:b599e748252c | 278 | */ |
hudakz | 0:b599e748252c | 279 | #define PHCON1_PRST 0x8000 |
hudakz | 0:b599e748252c | 280 | #define PHCON1_PLOOPBK 0x4000 |
hudakz | 0:b599e748252c | 281 | #define PHCON1_PPWRSV 0x0800 |
hudakz | 0:b599e748252c | 282 | #define PHCON1_PDPXMD 0x0100 |
hudakz | 0:b599e748252c | 283 | /* |
hudakz | 0:b599e748252c | 284 | * ENC28J60 PHY PHSTAT1 Register Bit Definitions |
hudakz | 0:b599e748252c | 285 | */ |
hudakz | 0:b599e748252c | 286 | #define PHSTAT1_PFDPX 0x1000 |
hudakz | 0:b599e748252c | 287 | #define PHSTAT1_PHDPX 0x0800 |
hudakz | 0:b599e748252c | 288 | #define PHSTAT1_LLSTAT 0x0004 |
hudakz | 0:b599e748252c | 289 | #define PHSTAT1_JBSTAT 0x0002 |
hudakz | 0:b599e748252c | 290 | /* |
hudakz | 0:b599e748252c | 291 | * ENC28J60 PHY PHSTAT2 Register Bit Definitions |
hudakz | 0:b599e748252c | 292 | */ |
hudakz | 0:b599e748252c | 293 | #define PHSTAT2_TXSTAT 0x2000 |
hudakz | 0:b599e748252c | 294 | #define PHSTAT2_RXSTAT 0x1000 |
hudakz | 0:b599e748252c | 295 | #define PHSTAT2_COLSTAT 0x0800 |
hudakz | 0:b599e748252c | 296 | #define PHSTAT2_LSTAT 0x0400 |
hudakz | 0:b599e748252c | 297 | #define PHSTAT2_DPXSTAT 0x0200 |
hudakz | 0:b599e748252c | 298 | #define PHSTAT2_PLRITY 0x0020 |
hudakz | 0:b599e748252c | 299 | /* |
hudakz | 0:b599e748252c | 300 | * ENC28J60 PHY PHCON2 Register Bit Definitions |
hudakz | 0:b599e748252c | 301 | */ |
hudakz | 0:b599e748252c | 302 | #define PHCON2_FRCLINK 0x4000 |
hudakz | 0:b599e748252c | 303 | #define PHCON2_TXDIS 0x2000 |
hudakz | 0:b599e748252c | 304 | #define PHCON2_JABBER 0x0400 |
hudakz | 0:b599e748252c | 305 | #define PHCON2_HDLDIS 0x0100 |
hudakz | 0:b599e748252c | 306 | /* |
hudakz | 0:b599e748252c | 307 | * ENC28J60 PHY PHIE Register Bit Definitions |
hudakz | 0:b599e748252c | 308 | */ |
hudakz | 0:b599e748252c | 309 | #define PHIE_PLNKIE 0x0010 |
hudakz | 0:b599e748252c | 310 | #define PHIE_PGEIE 0x0002 |
hudakz | 0:b599e748252c | 311 | /* |
hudakz | 0:b599e748252c | 312 | * ENC28J60 Packet Control Byte Bit Definitions |
hudakz | 0:b599e748252c | 313 | */ |
hudakz | 0:b599e748252c | 314 | #define PKTCTRL_PHUGEEN 0x08 |
hudakz | 0:b599e748252c | 315 | #define PKTCTRL_PPADEN 0x04 |
hudakz | 0:b599e748252c | 316 | #define PKTCTRL_PCRCEN 0x02 |
hudakz | 0:b599e748252c | 317 | #define PKTCTRL_POVERRIDE 0x01 |
hudakz | 0:b599e748252c | 318 | /* |
hudakz | 0:b599e748252c | 319 | * SPI operation codes |
hudakz | 0:b599e748252c | 320 | */ |
hudakz | 0:b599e748252c | 321 | #define ENC28J60_READ_CTRL_REG 0x00 |
hudakz | 0:b599e748252c | 322 | #define ENC28J60_READ_BUF_MEM 0x3A |
hudakz | 0:b599e748252c | 323 | #define ENC28J60_WRITE_CTRL_REG 0x40 |
hudakz | 0:b599e748252c | 324 | #define ENC28J60_WRITE_BUF_MEM 0x7A |
hudakz | 0:b599e748252c | 325 | #define ENC28J60_BIT_FIELD_SET 0x80 |
hudakz | 0:b599e748252c | 326 | #define ENC28J60_BIT_FIELD_CLR 0xA0 |
hudakz | 0:b599e748252c | 327 | #define ENC28J60_SOFT_RESET 0xFF |
hudakz | 0:b599e748252c | 328 | |
hudakz | 0:b599e748252c | 329 | // The ERXST_INI should be zero. See Silicon Errata: |
hudakz | 0:b599e748252c | 330 | |
hudakz | 0:b599e748252c | 331 | // Sometimes, when ERXST or ERXND is written to, the exact value, 0000h, is stored in the Internal |
hudakz | 0:b599e748252c | 332 | // Receive Write Pointer instead of the ERXST address. |
hudakz | 0:b599e748252c | 333 | // Workaround: |
hudakz | 0:b599e748252c | 334 | // Use the lower segment of the buffer memory for the receive buffer, starting at address 0000h. |
hudakz | 0:b599e748252c | 335 | // Use the range (0000h to n) for the receive buffer, and ((n + 1) to 8191) for the transmit buffer. |
hudakz | 0:b599e748252c | 336 | #define ERXST_INI 0x0000U |
hudakz | 0:b599e748252c | 337 | |
hudakz | 0:b599e748252c | 338 | // RX buffer end. Make sure this is an odd value ( See Rev. B1,B4,B5,B7 Silicon Errata 'Memory (Ethernet Buffer)') |
hudakz | 0:b599e748252c | 339 | #define ERXND_INI (ENC28J60_ETH_RXBUF_SIZE_KB * 1024 - 1) |
hudakz | 0:b599e748252c | 340 | |
hudakz | 0:b599e748252c | 341 | // TX buffer start. |
hudakz | 0:b599e748252c | 342 | #define ETXST_INI (ERXND_INI + 1) |
hudakz | 0:b599e748252c | 343 | |
hudakz | 0:b599e748252c | 344 | // TX buffer end at end of ethernet buffer memory. |
hudakz | 0:b599e748252c | 345 | #define ETXND_INI 0x1FFF |
hudakz | 0:b599e748252c | 346 | |
hudakz | 0:b599e748252c | 347 | // max frame length which the conroller will accept: |
hudakz | 0:b599e748252c | 348 | #define MAX_FRAMELEN ENC28J60_ETH_MTU_SIZE // (note: maximum ethernet frame length would be 1518) |
hudakz | 0:b599e748252c | 349 | |
hudakz | 0:b599e748252c | 350 | #define RX_NEXT_LEN 2U // next packet pointer bytes |
hudakz | 0:b599e748252c | 351 | #define RX_STAT_LEN 4U // receive status vector bytes |
hudakz | 0:b599e748252c | 352 | #define RX_CRC_LEN 4U // CRC bytes |
hudakz | 0:b599e748252c | 353 | #define TX_CTRL_LEN 1U // control byte |
hudakz | 0:b599e748252c | 354 | #define TX_STAT_LEN 7U // transmit status vector bytes |
hudakz | 0:b599e748252c | 355 | |
hudakz | 0:b599e748252c | 356 | #endif //ENC28J60_REG_H |