Bare-metal configuration for a Bluepill board.
Warning
It does not work with the Mbed Online Compiler.
Follow these steps to import and compile them with Mbed CLI:
mbed import https://os.mbed.com/users/hudakz/code/Baremetal_Blinky_Bluepill mbed compile -t GCC_ARM -m bluepill
TARGET_BLUEPILL/device/system_clock.c@3:90a9ecd02b47, 2020-06-04 (annotated)
- Committer:
- hudakz
- Date:
- Thu Jun 04 21:46:13 2020 +0000
- Revision:
- 3:90a9ecd02b47
- Parent:
- 0:a04710facbb6
Bare-metal blinky on Bluepill.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
hudakz | 0:a04710facbb6 | 1 | /* mbed Microcontroller Library |
hudakz | 0:a04710facbb6 | 2 | * Copyright (c) 2006-2017 ARM Limited |
hudakz | 0:a04710facbb6 | 3 | * |
hudakz | 0:a04710facbb6 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
hudakz | 0:a04710facbb6 | 5 | * you may not use this file except in compliance with the License. |
hudakz | 0:a04710facbb6 | 6 | * You may obtain a copy of the License at |
hudakz | 0:a04710facbb6 | 7 | * |
hudakz | 0:a04710facbb6 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
hudakz | 0:a04710facbb6 | 9 | * |
hudakz | 0:a04710facbb6 | 10 | * Unless required by applicable law or agreed to in writing, software |
hudakz | 0:a04710facbb6 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
hudakz | 0:a04710facbb6 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
hudakz | 0:a04710facbb6 | 13 | * See the License for the specific language governing permissions and |
hudakz | 0:a04710facbb6 | 14 | * limitations under the License. |
hudakz | 0:a04710facbb6 | 15 | */ |
hudakz | 0:a04710facbb6 | 16 | |
hudakz | 0:a04710facbb6 | 17 | /** |
hudakz | 0:a04710facbb6 | 18 | * This file configures the system clock as follows: |
hudakz | 0:a04710facbb6 | 19 | *----------------------------------------------------------------------------- |
hudakz | 0:a04710facbb6 | 20 | * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI |
hudakz | 0:a04710facbb6 | 21 | * | (external 8 MHz clock) | (internal 8 MHz) |
hudakz | 0:a04710facbb6 | 22 | * | 2- PLL_HSE_XTAL | |
hudakz | 0:a04710facbb6 | 23 | * | (external 8 MHz xtal) | |
hudakz | 0:a04710facbb6 | 24 | *----------------------------------------------------------------------------- |
hudakz | 0:a04710facbb6 | 25 | * SYSCLK(MHz) | 72 | 64 |
hudakz | 0:a04710facbb6 | 26 | *----------------------------------------------------------------------------- |
hudakz | 0:a04710facbb6 | 27 | * AHBCLK (MHz) | 72 | 64 |
hudakz | 0:a04710facbb6 | 28 | *----------------------------------------------------------------------------- |
hudakz | 0:a04710facbb6 | 29 | * APB1CLK (MHz) | 36 | 32 |
hudakz | 0:a04710facbb6 | 30 | *----------------------------------------------------------------------------- |
hudakz | 0:a04710facbb6 | 31 | * APB2CLK (MHz) | 72 | 64 |
hudakz | 0:a04710facbb6 | 32 | *----------------------------------------------------------------------------- |
hudakz | 0:a04710facbb6 | 33 | * USB capable (48 MHz precise clock) | NO | NO |
hudakz | 0:a04710facbb6 | 34 | *----------------------------------------------------------------------------- |
hudakz | 0:a04710facbb6 | 35 | ****************************************************************************** |
hudakz | 0:a04710facbb6 | 36 | */ |
hudakz | 0:a04710facbb6 | 37 | |
hudakz | 0:a04710facbb6 | 38 | #include "stm32f1xx.h" |
hudakz | 0:a04710facbb6 | 39 | |
hudakz | 0:a04710facbb6 | 40 | /*!< Uncomment the following line if you need to relocate your vector Table in |
hudakz | 0:a04710facbb6 | 41 | Internal SRAM. */ |
hudakz | 0:a04710facbb6 | 42 | /* #define VECT_TAB_SRAM */ |
hudakz | 0:a04710facbb6 | 43 | #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. |
hudakz | 0:a04710facbb6 | 44 | This value must be a multiple of 0x200. */ |
hudakz | 0:a04710facbb6 | 45 | |
hudakz | 0:a04710facbb6 | 46 | |
hudakz | 0:a04710facbb6 | 47 | /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ |
hudakz | 0:a04710facbb6 | 48 | #define USE_PLL_HSE_EXTC (0) /* Use external clock */ |
hudakz | 0:a04710facbb6 | 49 | #define USE_PLL_HSE_XTAL (1) /* Use external xtal */ |
hudakz | 0:a04710facbb6 | 50 | |
hudakz | 0:a04710facbb6 | 51 | |
hudakz | 0:a04710facbb6 | 52 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
hudakz | 0:a04710facbb6 | 53 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
hudakz | 0:a04710facbb6 | 54 | #endif |
hudakz | 0:a04710facbb6 | 55 | |
hudakz | 0:a04710facbb6 | 56 | uint8_t SetSysClock_PLL_HSI(void); |
hudakz | 0:a04710facbb6 | 57 | |
hudakz | 0:a04710facbb6 | 58 | |
hudakz | 0:a04710facbb6 | 59 | /** |
hudakz | 0:a04710facbb6 | 60 | * @brief Setup the microcontroller system |
hudakz | 0:a04710facbb6 | 61 | * Initialize the Embedded Flash Interface, the PLL and update the |
hudakz | 0:a04710facbb6 | 62 | * SystemCoreClock variable. |
hudakz | 0:a04710facbb6 | 63 | * @note This function should be used only after reset. |
hudakz | 0:a04710facbb6 | 64 | * @param None |
hudakz | 0:a04710facbb6 | 65 | * @retval None |
hudakz | 0:a04710facbb6 | 66 | */ |
hudakz | 0:a04710facbb6 | 67 | void SystemInit (void) |
hudakz | 0:a04710facbb6 | 68 | { |
hudakz | 0:a04710facbb6 | 69 | /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ |
hudakz | 0:a04710facbb6 | 70 | /* Set HSION bit */ |
hudakz | 0:a04710facbb6 | 71 | RCC->CR |= 0x00000001U; |
hudakz | 0:a04710facbb6 | 72 | |
hudakz | 0:a04710facbb6 | 73 | /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ |
hudakz | 0:a04710facbb6 | 74 | #if !defined(STM32F105xC) && !defined(STM32F107xC) |
hudakz | 0:a04710facbb6 | 75 | RCC->CFGR &= 0xF8FF0000U; |
hudakz | 0:a04710facbb6 | 76 | #else |
hudakz | 0:a04710facbb6 | 77 | RCC->CFGR &= 0xF0FF0000U; |
hudakz | 0:a04710facbb6 | 78 | #endif /* STM32F105xC */ |
hudakz | 0:a04710facbb6 | 79 | |
hudakz | 0:a04710facbb6 | 80 | /* Reset HSEON, CSSON and PLLON bits */ |
hudakz | 0:a04710facbb6 | 81 | RCC->CR &= 0xFEF6FFFFU; |
hudakz | 0:a04710facbb6 | 82 | |
hudakz | 0:a04710facbb6 | 83 | /* Reset HSEBYP bit */ |
hudakz | 0:a04710facbb6 | 84 | RCC->CR &= 0xFFFBFFFFU; |
hudakz | 0:a04710facbb6 | 85 | |
hudakz | 0:a04710facbb6 | 86 | /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ |
hudakz | 0:a04710facbb6 | 87 | RCC->CFGR &= 0xFF80FFFFU; |
hudakz | 0:a04710facbb6 | 88 | |
hudakz | 0:a04710facbb6 | 89 | #if defined(STM32F105xC) || defined(STM32F107xC) |
hudakz | 0:a04710facbb6 | 90 | /* Reset PLL2ON and PLL3ON bits */ |
hudakz | 0:a04710facbb6 | 91 | RCC->CR &= 0xEBFFFFFFU; |
hudakz | 0:a04710facbb6 | 92 | |
hudakz | 0:a04710facbb6 | 93 | /* Disable all interrupts and clear pending bits */ |
hudakz | 0:a04710facbb6 | 94 | RCC->CIR = 0x00FF0000U; |
hudakz | 0:a04710facbb6 | 95 | |
hudakz | 0:a04710facbb6 | 96 | /* Reset CFGR2 register */ |
hudakz | 0:a04710facbb6 | 97 | RCC->CFGR2 = 0x00000000U; |
hudakz | 0:a04710facbb6 | 98 | #elif defined(STM32F100xB) || defined(STM32F100xE) |
hudakz | 0:a04710facbb6 | 99 | /* Disable all interrupts and clear pending bits */ |
hudakz | 0:a04710facbb6 | 100 | RCC->CIR = 0x009F0000U; |
hudakz | 0:a04710facbb6 | 101 | |
hudakz | 0:a04710facbb6 | 102 | /* Reset CFGR2 register */ |
hudakz | 0:a04710facbb6 | 103 | RCC->CFGR2 = 0x00000000U; |
hudakz | 0:a04710facbb6 | 104 | #else |
hudakz | 0:a04710facbb6 | 105 | /* Disable all interrupts and clear pending bits */ |
hudakz | 0:a04710facbb6 | 106 | RCC->CIR = 0x009F0000U; |
hudakz | 0:a04710facbb6 | 107 | #endif /* STM32F105xC */ |
hudakz | 0:a04710facbb6 | 108 | |
hudakz | 0:a04710facbb6 | 109 | #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) |
hudakz | 0:a04710facbb6 | 110 | #ifdef DATA_IN_ExtSRAM |
hudakz | 0:a04710facbb6 | 111 | SystemInit_ExtMemCtl(); |
hudakz | 0:a04710facbb6 | 112 | #endif /* DATA_IN_ExtSRAM */ |
hudakz | 0:a04710facbb6 | 113 | #endif |
hudakz | 0:a04710facbb6 | 114 | |
hudakz | 0:a04710facbb6 | 115 | #ifdef VECT_TAB_SRAM |
hudakz | 0:a04710facbb6 | 116 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ |
hudakz | 0:a04710facbb6 | 117 | #else |
hudakz | 0:a04710facbb6 | 118 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ |
hudakz | 0:a04710facbb6 | 119 | #endif |
hudakz | 0:a04710facbb6 | 120 | |
hudakz | 0:a04710facbb6 | 121 | } |
hudakz | 0:a04710facbb6 | 122 | |
hudakz | 0:a04710facbb6 | 123 | /** |
hudakz | 0:a04710facbb6 | 124 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
hudakz | 0:a04710facbb6 | 125 | * AHB/APBx prescalers and Flash settings |
hudakz | 0:a04710facbb6 | 126 | * @note This function should be called only once the RCC clock configuration |
hudakz | 0:a04710facbb6 | 127 | * is reset to the default reset state (done in SystemInit() function). |
hudakz | 0:a04710facbb6 | 128 | * @param None |
hudakz | 0:a04710facbb6 | 129 | * @retval None |
hudakz | 0:a04710facbb6 | 130 | */ |
hudakz | 0:a04710facbb6 | 131 | void SetSysClock(void) |
hudakz | 0:a04710facbb6 | 132 | { |
hudakz | 0:a04710facbb6 | 133 | /* 1- Try to start with HSE and external clock */ |
hudakz | 0:a04710facbb6 | 134 | #if USE_PLL_HSE_EXTC != 0 |
hudakz | 0:a04710facbb6 | 135 | if (SetSysClock_PLL_HSE(1) == 0) |
hudakz | 0:a04710facbb6 | 136 | #endif |
hudakz | 0:a04710facbb6 | 137 | { |
hudakz | 0:a04710facbb6 | 138 | /* 2- If fail try to start with HSE and external xtal */ |
hudakz | 0:a04710facbb6 | 139 | #if USE_PLL_HSE_XTAL != 0 |
hudakz | 0:a04710facbb6 | 140 | if (SetSysClock_PLL_HSE(0) == 0) |
hudakz | 0:a04710facbb6 | 141 | #endif |
hudakz | 0:a04710facbb6 | 142 | { |
hudakz | 0:a04710facbb6 | 143 | /* 3- If fail start with HSI clock */ |
hudakz | 0:a04710facbb6 | 144 | if (SetSysClock_PLL_HSI() == 0) { |
hudakz | 0:a04710facbb6 | 145 | while(1) { |
hudakz | 0:a04710facbb6 | 146 | // [TODO] Put something here to tell the user that a problem occured... |
hudakz | 0:a04710facbb6 | 147 | } |
hudakz | 0:a04710facbb6 | 148 | } |
hudakz | 0:a04710facbb6 | 149 | } |
hudakz | 0:a04710facbb6 | 150 | } |
hudakz | 0:a04710facbb6 | 151 | |
hudakz | 0:a04710facbb6 | 152 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
hudakz | 0:a04710facbb6 | 153 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 72 MHz or 64 MHz |
hudakz | 0:a04710facbb6 | 154 | } |
hudakz | 0:a04710facbb6 | 155 | |
hudakz | 0:a04710facbb6 | 156 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
hudakz | 0:a04710facbb6 | 157 | /******************************************************************************/ |
hudakz | 0:a04710facbb6 | 158 | /* PLL (clocked by HSE) used as System clock source */ |
hudakz | 0:a04710facbb6 | 159 | /******************************************************************************/ |
hudakz | 0:a04710facbb6 | 160 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
hudakz | 0:a04710facbb6 | 161 | { |
hudakz | 0:a04710facbb6 | 162 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
hudakz | 0:a04710facbb6 | 163 | RCC_OscInitTypeDef RCC_OscInitStruct; |
hudakz | 0:a04710facbb6 | 164 | |
hudakz | 0:a04710facbb6 | 165 | /* Enable HSE oscillator and activate PLL with HSE as source */ |
hudakz | 0:a04710facbb6 | 166 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; |
hudakz | 0:a04710facbb6 | 167 | if (bypass == 0) { |
hudakz | 0:a04710facbb6 | 168 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ |
hudakz | 0:a04710facbb6 | 169 | } else { |
hudakz | 0:a04710facbb6 | 170 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ |
hudakz | 0:a04710facbb6 | 171 | } |
hudakz | 0:a04710facbb6 | 172 | RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; |
hudakz | 0:a04710facbb6 | 173 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
hudakz | 0:a04710facbb6 | 174 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
hudakz | 0:a04710facbb6 | 175 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9) |
hudakz | 0:a04710facbb6 | 176 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
hudakz | 0:a04710facbb6 | 177 | return 0; // FAIL |
hudakz | 0:a04710facbb6 | 178 | } |
hudakz | 0:a04710facbb6 | 179 | |
hudakz | 0:a04710facbb6 | 180 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
hudakz | 0:a04710facbb6 | 181 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
hudakz | 0:a04710facbb6 | 182 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz |
hudakz | 0:a04710facbb6 | 183 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz |
hudakz | 0:a04710facbb6 | 184 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz |
hudakz | 0:a04710facbb6 | 185 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz |
hudakz | 0:a04710facbb6 | 186 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { |
hudakz | 0:a04710facbb6 | 187 | return 0; // FAIL |
hudakz | 0:a04710facbb6 | 188 | } |
hudakz | 0:a04710facbb6 | 189 | |
hudakz | 0:a04710facbb6 | 190 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
hudakz | 0:a04710facbb6 | 191 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz |
hudakz | 0:a04710facbb6 | 192 | |
hudakz | 0:a04710facbb6 | 193 | return 1; // OK |
hudakz | 0:a04710facbb6 | 194 | } |
hudakz | 0:a04710facbb6 | 195 | #endif |
hudakz | 0:a04710facbb6 | 196 | |
hudakz | 0:a04710facbb6 | 197 | /******************************************************************************/ |
hudakz | 0:a04710facbb6 | 198 | /* PLL (clocked by HSI) used as System clock source */ |
hudakz | 0:a04710facbb6 | 199 | /******************************************************************************/ |
hudakz | 0:a04710facbb6 | 200 | uint8_t SetSysClock_PLL_HSI(void) |
hudakz | 0:a04710facbb6 | 201 | { |
hudakz | 0:a04710facbb6 | 202 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
hudakz | 0:a04710facbb6 | 203 | RCC_OscInitTypeDef RCC_OscInitStruct; |
hudakz | 0:a04710facbb6 | 204 | |
hudakz | 0:a04710facbb6 | 205 | /* Enable HSI oscillator and activate PLL with HSI as source */ |
hudakz | 0:a04710facbb6 | 206 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; |
hudakz | 0:a04710facbb6 | 207 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
hudakz | 0:a04710facbb6 | 208 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
hudakz | 0:a04710facbb6 | 209 | RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; |
hudakz | 0:a04710facbb6 | 210 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
hudakz | 0:a04710facbb6 | 211 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; |
hudakz | 0:a04710facbb6 | 212 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16) |
hudakz | 0:a04710facbb6 | 213 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
hudakz | 0:a04710facbb6 | 214 | return 0; // FAIL |
hudakz | 0:a04710facbb6 | 215 | } |
hudakz | 0:a04710facbb6 | 216 | |
hudakz | 0:a04710facbb6 | 217 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
hudakz | 0:a04710facbb6 | 218 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
hudakz | 0:a04710facbb6 | 219 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz |
hudakz | 0:a04710facbb6 | 220 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz |
hudakz | 0:a04710facbb6 | 221 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 32 MHz |
hudakz | 0:a04710facbb6 | 222 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz |
hudakz | 0:a04710facbb6 | 223 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { |
hudakz | 0:a04710facbb6 | 224 | return 0; // FAIL |
hudakz | 0:a04710facbb6 | 225 | } |
hudakz | 0:a04710facbb6 | 226 | |
hudakz | 0:a04710facbb6 | 227 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
hudakz | 0:a04710facbb6 | 228 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 8 MHz |
hudakz | 0:a04710facbb6 | 229 | |
hudakz | 0:a04710facbb6 | 230 | return 1; // OK |
hudakz | 0:a04710facbb6 | 231 | } |
hudakz | 0:a04710facbb6 | 232 |