Baremetal_Blinky_Bluepill - Bare-metal configuration for a Bluepill board.

Users » hudakz » Code » Baremetal_Blinky_Bluepill

Zoltan Hudak / Mbed OS Baremetal_Blinky_Bluepill

Bare-metal configuration for a Bluepill board.

Warning

It does not work with the Mbed Online Compiler.

Follow these steps to import and compile them with Mbed CLI:

mbed import https://os.mbed.com/users/hudakz/code/Baremetal_Blinky_Bluepill
mbed compile -t GCC_ARM -m bluepill

TARGET_BLUEPILL/device/stm32f103xb.h@3:90a9ecd02b47, 2020-06-04 (annotated)

Committer:: hudakz
Date:: Thu Jun 04 21:46:13 2020 +0000
Revision:: 3:90a9ecd02b47
Parent:: 0:a04710facbb6

Bare-metal blinky on Bluepill.

Who changed what in which revision?

User	Revision	Line number	New contents of line
hudakz	0:a04710facbb6	1	/**
hudakz	0:a04710facbb6	2	******************************************************************************
hudakz	0:a04710facbb6	3	* @file stm32f103xb.h
hudakz	0:a04710facbb6	4	* @author MCD Application Team
hudakz	0:a04710facbb6	5	* @version V4.2.0
hudakz	0:a04710facbb6	6	* @date 31-March-2017
hudakz	0:a04710facbb6	7	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
hudakz	0:a04710facbb6	8	* This file contains all the peripheral register's definitions, bits
hudakz	0:a04710facbb6	9	* definitions and memory mapping for STM32F1xx devices.
hudakz	0:a04710facbb6	10	*
hudakz	0:a04710facbb6	11	* This file contains:
hudakz	0:a04710facbb6	12	* - Data structures and the address mapping for all peripherals
hudakz	0:a04710facbb6	13	* - Peripheral's registers declarations and bits definition
hudakz	0:a04710facbb6	14	* - Macros to access peripherals registers hardware
hudakz	0:a04710facbb6	15	*
hudakz	0:a04710facbb6	16	******************************************************************************
hudakz	0:a04710facbb6	17	* @attention
hudakz	0:a04710facbb6	18	*
hudakz	0:a04710facbb6	19	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
hudakz	0:a04710facbb6	20	*
hudakz	0:a04710facbb6	21	* Redistribution and use in source and binary forms, with or without modification,
hudakz	0:a04710facbb6	22	* are permitted provided that the following conditions are met:
hudakz	0:a04710facbb6	23	* 1. Redistributions of source code must retain the above copyright notice,
hudakz	0:a04710facbb6	24	* this list of conditions and the following disclaimer.
hudakz	0:a04710facbb6	25	* 2. Redistributions in binary form must reproduce the above copyright notice,
hudakz	0:a04710facbb6	26	* this list of conditions and the following disclaimer in the documentation
hudakz	0:a04710facbb6	27	* and/or other materials provided with the distribution.
hudakz	0:a04710facbb6	28	* 3. Neither the name of STMicroelectronics nor the names of its contributors
hudakz	0:a04710facbb6	29	* may be used to endorse or promote products derived from this software
hudakz	0:a04710facbb6	30	* without specific prior written permission.
hudakz	0:a04710facbb6	31	*
hudakz	0:a04710facbb6	32	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
hudakz	0:a04710facbb6	33	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
hudakz	0:a04710facbb6	34	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
hudakz	0:a04710facbb6	35	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
hudakz	0:a04710facbb6	36	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
hudakz	0:a04710facbb6	37	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
hudakz	0:a04710facbb6	38	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
hudakz	0:a04710facbb6	39	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
hudakz	0:a04710facbb6	40	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
hudakz	0:a04710facbb6	41	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
hudakz	0:a04710facbb6	42	*
hudakz	0:a04710facbb6	43	******************************************************************************
hudakz	0:a04710facbb6	44	*/
hudakz	0:a04710facbb6	45
hudakz	0:a04710facbb6	46
hudakz	0:a04710facbb6	47	/** @addtogroup CMSIS
hudakz	0:a04710facbb6	48	* @{
hudakz	0:a04710facbb6	49	*/
hudakz	0:a04710facbb6	50
hudakz	0:a04710facbb6	51	/** @addtogroup stm32f103xb
hudakz	0:a04710facbb6	52	* @{
hudakz	0:a04710facbb6	53	*/
hudakz	0:a04710facbb6	54
hudakz	0:a04710facbb6	55	#ifndef __STM32F103xB_H
hudakz	0:a04710facbb6	56	#define __STM32F103xB_H
hudakz	0:a04710facbb6	57
hudakz	0:a04710facbb6	58	#ifdef __cplusplus
hudakz	0:a04710facbb6	59	extern "C" {
hudakz	0:a04710facbb6	60	#endif
hudakz	0:a04710facbb6	61
hudakz	0:a04710facbb6	62	/** @addtogroup Configuration_section_for_CMSIS
hudakz	0:a04710facbb6	63	* @{
hudakz	0:a04710facbb6	64	*/
hudakz	0:a04710facbb6	65	/**
hudakz	0:a04710facbb6	66	* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
hudakz	0:a04710facbb6	67	*/
hudakz	0:a04710facbb6	68	#define __CM3_REV 0x0200U /!< Core Revision r2p0 /
hudakz	0:a04710facbb6	69	#define __MPU_PRESENT 0U /!< Other STM32 devices does not provide an MPU /
hudakz	0:a04710facbb6	70	#define __NVIC_PRIO_BITS 4U /!< STM32 uses 4 Bits for the Priority Levels /
hudakz	0:a04710facbb6	71	#define __Vendor_SysTickConfig 0U /!< Set to 1 if different SysTick Config is used /
hudakz	0:a04710facbb6	72
hudakz	0:a04710facbb6	73	/**
hudakz	0:a04710facbb6	74	* @}
hudakz	0:a04710facbb6	75	*/
hudakz	0:a04710facbb6	76
hudakz	0:a04710facbb6	77	/** @addtogroup Peripheral_interrupt_number_definition
hudakz	0:a04710facbb6	78	* @{
hudakz	0:a04710facbb6	79	*/
hudakz	0:a04710facbb6	80
hudakz	0:a04710facbb6	81	/**
hudakz	0:a04710facbb6	82	* @brief STM32F10x Interrupt Number Definition, according to the selected device
hudakz	0:a04710facbb6	83	* in @ref Library_configuration_section
hudakz	0:a04710facbb6	84	*/
hudakz	0:a04710facbb6	85
hudakz	0:a04710facbb6	86	/!< Interrupt Number Definition /
hudakz	0:a04710facbb6	87	typedef enum
hudakz	0:a04710facbb6	88	{
hudakz	0:a04710facbb6	89	/**** Cortex-M3 Processor Exceptions Numbers *************************************************/
hudakz	0:a04710facbb6	90	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
hudakz	0:a04710facbb6	91	HardFault_IRQn = -13, /!< 3 Cortex-M3 Hard Fault Interrupt /
hudakz	0:a04710facbb6	92	MemoryManagement_IRQn = -12, /!< 4 Cortex-M3 Memory Management Interrupt /
hudakz	0:a04710facbb6	93	BusFault_IRQn = -11, /!< 5 Cortex-M3 Bus Fault Interrupt /
hudakz	0:a04710facbb6	94	UsageFault_IRQn = -10, /!< 6 Cortex-M3 Usage Fault Interrupt /
hudakz	0:a04710facbb6	95	SVCall_IRQn = -5, /!< 11 Cortex-M3 SV Call Interrupt /
hudakz	0:a04710facbb6	96	DebugMonitor_IRQn = -4, /!< 12 Cortex-M3 Debug Monitor Interrupt /
hudakz	0:a04710facbb6	97	PendSV_IRQn = -2, /!< 14 Cortex-M3 Pend SV Interrupt /
hudakz	0:a04710facbb6	98	SysTick_IRQn = -1, /!< 15 Cortex-M3 System Tick Interrupt /
hudakz	0:a04710facbb6	99
hudakz	0:a04710facbb6	100	/**** STM32 specific Interrupt Numbers *******************************************************/
hudakz	0:a04710facbb6	101	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
hudakz	0:a04710facbb6	102	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
hudakz	0:a04710facbb6	103	TAMPER_IRQn = 2, /!< Tamper Interrupt /
hudakz	0:a04710facbb6	104	RTC_IRQn = 3, /!< RTC global Interrupt /
hudakz	0:a04710facbb6	105	FLASH_IRQn = 4, /!< FLASH global Interrupt /
hudakz	0:a04710facbb6	106	RCC_IRQn = 5, /!< RCC global Interrupt /
hudakz	0:a04710facbb6	107	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
hudakz	0:a04710facbb6	108	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
hudakz	0:a04710facbb6	109	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
hudakz	0:a04710facbb6	110	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
hudakz	0:a04710facbb6	111	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
hudakz	0:a04710facbb6	112	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 global Interrupt /
hudakz	0:a04710facbb6	113	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 global Interrupt /
hudakz	0:a04710facbb6	114	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 global Interrupt /
hudakz	0:a04710facbb6	115	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 global Interrupt /
hudakz	0:a04710facbb6	116	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 global Interrupt /
hudakz	0:a04710facbb6	117	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 global Interrupt /
hudakz	0:a04710facbb6	118	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 global Interrupt /
hudakz	0:a04710facbb6	119	ADC1_2_IRQn = 18, /!< ADC1 and ADC2 global Interrupt /
hudakz	0:a04710facbb6	120	USB_HP_CAN1_TX_IRQn = 19, /!< USB Device High Priority or CAN1 TX Interrupts /
hudakz	0:a04710facbb6	121	USB_LP_CAN1_RX0_IRQn = 20, /!< USB Device Low Priority or CAN1 RX0 Interrupts /
hudakz	0:a04710facbb6	122	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
hudakz	0:a04710facbb6	123	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
hudakz	0:a04710facbb6	124	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
hudakz	0:a04710facbb6	125	TIM1_BRK_IRQn = 24, /!< TIM1 Break Interrupt /
hudakz	0:a04710facbb6	126	TIM1_UP_IRQn = 25, /!< TIM1 Update Interrupt /
hudakz	0:a04710facbb6	127	TIM1_TRG_COM_IRQn = 26, /!< TIM1 Trigger and Commutation Interrupt /
hudakz	0:a04710facbb6	128	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
hudakz	0:a04710facbb6	129	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
hudakz	0:a04710facbb6	130	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
hudakz	0:a04710facbb6	131	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
hudakz	0:a04710facbb6	132	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
hudakz	0:a04710facbb6	133	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
hudakz	0:a04710facbb6	134	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
hudakz	0:a04710facbb6	135	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
hudakz	0:a04710facbb6	136	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
hudakz	0:a04710facbb6	137	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
hudakz	0:a04710facbb6	138	USART1_IRQn = 37, /!< USART1 global Interrupt /
hudakz	0:a04710facbb6	139	USART2_IRQn = 38, /!< USART2 global Interrupt /
hudakz	0:a04710facbb6	140	USART3_IRQn = 39, /!< USART3 global Interrupt /
hudakz	0:a04710facbb6	141	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
hudakz	0:a04710facbb6	142	RTC_Alarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
hudakz	0:a04710facbb6	143	USBWakeUp_IRQn = 42, /!< USB Device WakeUp from suspend through EXTI Line Interrupt /
hudakz	0:a04710facbb6	144	} IRQn_Type;
hudakz	0:a04710facbb6	145
hudakz	0:a04710facbb6	146	/**
hudakz	0:a04710facbb6	147	* @}
hudakz	0:a04710facbb6	148	*/
hudakz	0:a04710facbb6	149
hudakz	0:a04710facbb6	150	#include "core_cm3.h"
hudakz	0:a04710facbb6	151	#include "system_stm32f1xx.h"
hudakz	0:a04710facbb6	152	#include <stdint.h>
hudakz	0:a04710facbb6	153
hudakz	0:a04710facbb6	154	/** @addtogroup Peripheral_registers_structures
hudakz	0:a04710facbb6	155	* @{
hudakz	0:a04710facbb6	156	*/
hudakz	0:a04710facbb6	157
hudakz	0:a04710facbb6	158	/**
hudakz	0:a04710facbb6	159	* @brief Analog to Digital Converter
hudakz	0:a04710facbb6	160	*/
hudakz	0:a04710facbb6	161
hudakz	0:a04710facbb6	162	typedef struct
hudakz	0:a04710facbb6	163	{
hudakz	0:a04710facbb6	164	__IO uint32_t SR;
hudakz	0:a04710facbb6	165	__IO uint32_t CR1;
hudakz	0:a04710facbb6	166	__IO uint32_t CR2;
hudakz	0:a04710facbb6	167	__IO uint32_t SMPR1;
hudakz	0:a04710facbb6	168	__IO uint32_t SMPR2;
hudakz	0:a04710facbb6	169	__IO uint32_t JOFR1;
hudakz	0:a04710facbb6	170	__IO uint32_t JOFR2;
hudakz	0:a04710facbb6	171	__IO uint32_t JOFR3;
hudakz	0:a04710facbb6	172	__IO uint32_t JOFR4;
hudakz	0:a04710facbb6	173	__IO uint32_t HTR;
hudakz	0:a04710facbb6	174	__IO uint32_t LTR;
hudakz	0:a04710facbb6	175	__IO uint32_t SQR1;
hudakz	0:a04710facbb6	176	__IO uint32_t SQR2;
hudakz	0:a04710facbb6	177	__IO uint32_t SQR3;
hudakz	0:a04710facbb6	178	__IO uint32_t JSQR;
hudakz	0:a04710facbb6	179	__IO uint32_t JDR1;
hudakz	0:a04710facbb6	180	__IO uint32_t JDR2;
hudakz	0:a04710facbb6	181	__IO uint32_t JDR3;
hudakz	0:a04710facbb6	182	__IO uint32_t JDR4;
hudakz	0:a04710facbb6	183	__IO uint32_t DR;
hudakz	0:a04710facbb6	184	} ADC_TypeDef;
hudakz	0:a04710facbb6	185
hudakz	0:a04710facbb6	186	typedef struct
hudakz	0:a04710facbb6	187	{
hudakz	0:a04710facbb6	188	__IO uint32_t SR; /!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address /
hudakz	0:a04710facbb6	189	__IO uint32_t CR1; /!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 /
hudakz	0:a04710facbb6	190	__IO uint32_t CR2; /!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 /
hudakz	0:a04710facbb6	191	uint32_t RESERVED[16];
hudakz	0:a04710facbb6	192	__IO uint32_t DR; /!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C /
hudakz	0:a04710facbb6	193	} ADC_Common_TypeDef;
hudakz	0:a04710facbb6	194
hudakz	0:a04710facbb6	195	/**
hudakz	0:a04710facbb6	196	* @brief Backup Registers
hudakz	0:a04710facbb6	197	*/
hudakz	0:a04710facbb6	198
hudakz	0:a04710facbb6	199	typedef struct
hudakz	0:a04710facbb6	200	{
hudakz	0:a04710facbb6	201	uint32_t RESERVED0;
hudakz	0:a04710facbb6	202	__IO uint32_t DR1;
hudakz	0:a04710facbb6	203	__IO uint32_t DR2;
hudakz	0:a04710facbb6	204	__IO uint32_t DR3;
hudakz	0:a04710facbb6	205	__IO uint32_t DR4;
hudakz	0:a04710facbb6	206	__IO uint32_t DR5;
hudakz	0:a04710facbb6	207	__IO uint32_t DR6;
hudakz	0:a04710facbb6	208	__IO uint32_t DR7;
hudakz	0:a04710facbb6	209	__IO uint32_t DR8;
hudakz	0:a04710facbb6	210	__IO uint32_t DR9;
hudakz	0:a04710facbb6	211	__IO uint32_t DR10;
hudakz	0:a04710facbb6	212	__IO uint32_t RTCCR;
hudakz	0:a04710facbb6	213	__IO uint32_t CR;
hudakz	0:a04710facbb6	214	__IO uint32_t CSR;
hudakz	0:a04710facbb6	215	} BKP_TypeDef;
hudakz	0:a04710facbb6	216
hudakz	0:a04710facbb6	217	/**
hudakz	0:a04710facbb6	218	* @brief Controller Area Network TxMailBox
hudakz	0:a04710facbb6	219	*/
hudakz	0:a04710facbb6	220
hudakz	0:a04710facbb6	221	typedef struct
hudakz	0:a04710facbb6	222	{
hudakz	0:a04710facbb6	223	__IO uint32_t TIR;
hudakz	0:a04710facbb6	224	__IO uint32_t TDTR;
hudakz	0:a04710facbb6	225	__IO uint32_t TDLR;
hudakz	0:a04710facbb6	226	__IO uint32_t TDHR;
hudakz	0:a04710facbb6	227	} CAN_TxMailBox_TypeDef;
hudakz	0:a04710facbb6	228
hudakz	0:a04710facbb6	229	/**
hudakz	0:a04710facbb6	230	* @brief Controller Area Network FIFOMailBox
hudakz	0:a04710facbb6	231	*/
hudakz	0:a04710facbb6	232
hudakz	0:a04710facbb6	233	typedef struct
hudakz	0:a04710facbb6	234	{
hudakz	0:a04710facbb6	235	__IO uint32_t RIR;
hudakz	0:a04710facbb6	236	__IO uint32_t RDTR;
hudakz	0:a04710facbb6	237	__IO uint32_t RDLR;
hudakz	0:a04710facbb6	238	__IO uint32_t RDHR;
hudakz	0:a04710facbb6	239	} CAN_FIFOMailBox_TypeDef;
hudakz	0:a04710facbb6	240
hudakz	0:a04710facbb6	241	/**
hudakz	0:a04710facbb6	242	* @brief Controller Area Network FilterRegister
hudakz	0:a04710facbb6	243	*/
hudakz	0:a04710facbb6	244
hudakz	0:a04710facbb6	245	typedef struct
hudakz	0:a04710facbb6	246	{
hudakz	0:a04710facbb6	247	__IO uint32_t FR1;
hudakz	0:a04710facbb6	248	__IO uint32_t FR2;
hudakz	0:a04710facbb6	249	} CAN_FilterRegister_TypeDef;
hudakz	0:a04710facbb6	250
hudakz	0:a04710facbb6	251	/**
hudakz	0:a04710facbb6	252	* @brief Controller Area Network
hudakz	0:a04710facbb6	253	*/
hudakz	0:a04710facbb6	254
hudakz	0:a04710facbb6	255	typedef struct
hudakz	0:a04710facbb6	256	{
hudakz	0:a04710facbb6	257	__IO uint32_t MCR;
hudakz	0:a04710facbb6	258	__IO uint32_t MSR;
hudakz	0:a04710facbb6	259	__IO uint32_t TSR;
hudakz	0:a04710facbb6	260	__IO uint32_t RF0R;
hudakz	0:a04710facbb6	261	__IO uint32_t RF1R;
hudakz	0:a04710facbb6	262	__IO uint32_t IER;
hudakz	0:a04710facbb6	263	__IO uint32_t ESR;
hudakz	0:a04710facbb6	264	__IO uint32_t BTR;
hudakz	0:a04710facbb6	265	uint32_t RESERVED0[88];
hudakz	0:a04710facbb6	266	CAN_TxMailBox_TypeDef sTxMailBox[3];
hudakz	0:a04710facbb6	267	CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
hudakz	0:a04710facbb6	268	uint32_t RESERVED1[12];
hudakz	0:a04710facbb6	269	__IO uint32_t FMR;
hudakz	0:a04710facbb6	270	__IO uint32_t FM1R;
hudakz	0:a04710facbb6	271	uint32_t RESERVED2;
hudakz	0:a04710facbb6	272	__IO uint32_t FS1R;
hudakz	0:a04710facbb6	273	uint32_t RESERVED3;
hudakz	0:a04710facbb6	274	__IO uint32_t FFA1R;
hudakz	0:a04710facbb6	275	uint32_t RESERVED4;
hudakz	0:a04710facbb6	276	__IO uint32_t FA1R;
hudakz	0:a04710facbb6	277	uint32_t RESERVED5[8];
hudakz	0:a04710facbb6	278	CAN_FilterRegister_TypeDef sFilterRegister[14];
hudakz	0:a04710facbb6	279	} CAN_TypeDef;
hudakz	0:a04710facbb6	280
hudakz	0:a04710facbb6	281	/**
hudakz	0:a04710facbb6	282	* @brief CRC calculation unit
hudakz	0:a04710facbb6	283	*/
hudakz	0:a04710facbb6	284
hudakz	0:a04710facbb6	285	typedef struct
hudakz	0:a04710facbb6	286	{
hudakz	0:a04710facbb6	287	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
hudakz	0:a04710facbb6	288	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
hudakz	0:a04710facbb6	289	uint8_t RESERVED0; /!< Reserved, Address offset: 0x05 /
hudakz	0:a04710facbb6	290	uint16_t RESERVED1; /!< Reserved, Address offset: 0x06 /
hudakz	0:a04710facbb6	291	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
hudakz	0:a04710facbb6	292	} CRC_TypeDef;
hudakz	0:a04710facbb6	293
hudakz	0:a04710facbb6	294
hudakz	0:a04710facbb6	295	/**
hudakz	0:a04710facbb6	296	* @brief Debug MCU
hudakz	0:a04710facbb6	297	*/
hudakz	0:a04710facbb6	298
hudakz	0:a04710facbb6	299	typedef struct
hudakz	0:a04710facbb6	300	{
hudakz	0:a04710facbb6	301	__IO uint32_t IDCODE;
hudakz	0:a04710facbb6	302	__IO uint32_t CR;
hudakz	0:a04710facbb6	303	}DBGMCU_TypeDef;
hudakz	0:a04710facbb6	304
hudakz	0:a04710facbb6	305	/**
hudakz	0:a04710facbb6	306	* @brief DMA Controller
hudakz	0:a04710facbb6	307	*/
hudakz	0:a04710facbb6	308
hudakz	0:a04710facbb6	309	typedef struct
hudakz	0:a04710facbb6	310	{
hudakz	0:a04710facbb6	311	__IO uint32_t CCR;
hudakz	0:a04710facbb6	312	__IO uint32_t CNDTR;
hudakz	0:a04710facbb6	313	__IO uint32_t CPAR;
hudakz	0:a04710facbb6	314	__IO uint32_t CMAR;
hudakz	0:a04710facbb6	315	} DMA_Channel_TypeDef;
hudakz	0:a04710facbb6	316
hudakz	0:a04710facbb6	317	typedef struct
hudakz	0:a04710facbb6	318	{
hudakz	0:a04710facbb6	319	__IO uint32_t ISR;
hudakz	0:a04710facbb6	320	__IO uint32_t IFCR;
hudakz	0:a04710facbb6	321	} DMA_TypeDef;
hudakz	0:a04710facbb6	322
hudakz	0:a04710facbb6	323
hudakz	0:a04710facbb6	324
hudakz	0:a04710facbb6	325	/**
hudakz	0:a04710facbb6	326	* @brief External Interrupt/Event Controller
hudakz	0:a04710facbb6	327	*/
hudakz	0:a04710facbb6	328
hudakz	0:a04710facbb6	329	typedef struct
hudakz	0:a04710facbb6	330	{
hudakz	0:a04710facbb6	331	__IO uint32_t IMR;
hudakz	0:a04710facbb6	332	__IO uint32_t EMR;
hudakz	0:a04710facbb6	333	__IO uint32_t RTSR;
hudakz	0:a04710facbb6	334	__IO uint32_t FTSR;
hudakz	0:a04710facbb6	335	__IO uint32_t SWIER;
hudakz	0:a04710facbb6	336	__IO uint32_t PR;
hudakz	0:a04710facbb6	337	} EXTI_TypeDef;
hudakz	0:a04710facbb6	338
hudakz	0:a04710facbb6	339	/**
hudakz	0:a04710facbb6	340	* @brief FLASH Registers
hudakz	0:a04710facbb6	341	*/
hudakz	0:a04710facbb6	342
hudakz	0:a04710facbb6	343	typedef struct
hudakz	0:a04710facbb6	344	{
hudakz	0:a04710facbb6	345	__IO uint32_t ACR;
hudakz	0:a04710facbb6	346	__IO uint32_t KEYR;
hudakz	0:a04710facbb6	347	__IO uint32_t OPTKEYR;
hudakz	0:a04710facbb6	348	__IO uint32_t SR;
hudakz	0:a04710facbb6	349	__IO uint32_t CR;
hudakz	0:a04710facbb6	350	__IO uint32_t AR;
hudakz	0:a04710facbb6	351	__IO uint32_t RESERVED;
hudakz	0:a04710facbb6	352	__IO uint32_t OBR;
hudakz	0:a04710facbb6	353	__IO uint32_t WRPR;
hudakz	0:a04710facbb6	354	} FLASH_TypeDef;
hudakz	0:a04710facbb6	355
hudakz	0:a04710facbb6	356	/**
hudakz	0:a04710facbb6	357	* @brief Option Bytes Registers
hudakz	0:a04710facbb6	358	*/
hudakz	0:a04710facbb6	359
hudakz	0:a04710facbb6	360	typedef struct
hudakz	0:a04710facbb6	361	{
hudakz	0:a04710facbb6	362	__IO uint16_t RDP;
hudakz	0:a04710facbb6	363	__IO uint16_t USER;
hudakz	0:a04710facbb6	364	__IO uint16_t Data0;
hudakz	0:a04710facbb6	365	__IO uint16_t Data1;
hudakz	0:a04710facbb6	366	__IO uint16_t WRP0;
hudakz	0:a04710facbb6	367	__IO uint16_t WRP1;
hudakz	0:a04710facbb6	368	__IO uint16_t WRP2;
hudakz	0:a04710facbb6	369	__IO uint16_t WRP3;
hudakz	0:a04710facbb6	370	} OB_TypeDef;
hudakz	0:a04710facbb6	371
hudakz	0:a04710facbb6	372	/**
hudakz	0:a04710facbb6	373	* @brief General Purpose I/O
hudakz	0:a04710facbb6	374	*/
hudakz	0:a04710facbb6	375
hudakz	0:a04710facbb6	376	typedef struct
hudakz	0:a04710facbb6	377	{
hudakz	0:a04710facbb6	378	__IO uint32_t CRL;
hudakz	0:a04710facbb6	379	__IO uint32_t CRH;
hudakz	0:a04710facbb6	380	__IO uint32_t IDR;
hudakz	0:a04710facbb6	381	__IO uint32_t ODR;
hudakz	0:a04710facbb6	382	__IO uint32_t BSRR;
hudakz	0:a04710facbb6	383	__IO uint32_t BRR;
hudakz	0:a04710facbb6	384	__IO uint32_t LCKR;
hudakz	0:a04710facbb6	385	} GPIO_TypeDef;
hudakz	0:a04710facbb6	386
hudakz	0:a04710facbb6	387	/**
hudakz	0:a04710facbb6	388	* @brief Alternate Function I/O
hudakz	0:a04710facbb6	389	*/
hudakz	0:a04710facbb6	390
hudakz	0:a04710facbb6	391	typedef struct
hudakz	0:a04710facbb6	392	{
hudakz	0:a04710facbb6	393	__IO uint32_t EVCR;
hudakz	0:a04710facbb6	394	__IO uint32_t MAPR;
hudakz	0:a04710facbb6	395	__IO uint32_t EXTICR[4];
hudakz	0:a04710facbb6	396	uint32_t RESERVED0;
hudakz	0:a04710facbb6	397	__IO uint32_t MAPR2;
hudakz	0:a04710facbb6	398	} AFIO_TypeDef;
hudakz	0:a04710facbb6	399	/**
hudakz	0:a04710facbb6	400	* @brief Inter Integrated Circuit Interface
hudakz	0:a04710facbb6	401	*/
hudakz	0:a04710facbb6	402
hudakz	0:a04710facbb6	403	typedef struct
hudakz	0:a04710facbb6	404	{
hudakz	0:a04710facbb6	405	__IO uint32_t CR1;
hudakz	0:a04710facbb6	406	__IO uint32_t CR2;
hudakz	0:a04710facbb6	407	__IO uint32_t OAR1;
hudakz	0:a04710facbb6	408	__IO uint32_t OAR2;
hudakz	0:a04710facbb6	409	__IO uint32_t DR;
hudakz	0:a04710facbb6	410	__IO uint32_t SR1;
hudakz	0:a04710facbb6	411	__IO uint32_t SR2;
hudakz	0:a04710facbb6	412	__IO uint32_t CCR;
hudakz	0:a04710facbb6	413	__IO uint32_t TRISE;
hudakz	0:a04710facbb6	414	} I2C_TypeDef;
hudakz	0:a04710facbb6	415
hudakz	0:a04710facbb6	416	/**
hudakz	0:a04710facbb6	417	* @brief Independent WATCHDOG
hudakz	0:a04710facbb6	418	*/
hudakz	0:a04710facbb6	419
hudakz	0:a04710facbb6	420	typedef struct
hudakz	0:a04710facbb6	421	{
hudakz	0:a04710facbb6	422	__IO uint32_t KR; /!< Key register, Address offset: 0x00 /
hudakz	0:a04710facbb6	423	__IO uint32_t PR; /!< Prescaler register, Address offset: 0x04 /
hudakz	0:a04710facbb6	424	__IO uint32_t RLR; /!< Reload register, Address offset: 0x08 /
hudakz	0:a04710facbb6	425	__IO uint32_t SR; /!< Status register, Address offset: 0x0C /
hudakz	0:a04710facbb6	426	} IWDG_TypeDef;
hudakz	0:a04710facbb6	427
hudakz	0:a04710facbb6	428	/**
hudakz	0:a04710facbb6	429	* @brief Power Control
hudakz	0:a04710facbb6	430	*/
hudakz	0:a04710facbb6	431
hudakz	0:a04710facbb6	432	typedef struct
hudakz	0:a04710facbb6	433	{
hudakz	0:a04710facbb6	434	__IO uint32_t CR;
hudakz	0:a04710facbb6	435	__IO uint32_t CSR;
hudakz	0:a04710facbb6	436	} PWR_TypeDef;
hudakz	0:a04710facbb6	437
hudakz	0:a04710facbb6	438	/**
hudakz	0:a04710facbb6	439	* @brief Reset and Clock Control
hudakz	0:a04710facbb6	440	*/
hudakz	0:a04710facbb6	441
hudakz	0:a04710facbb6	442	typedef struct
hudakz	0:a04710facbb6	443	{
hudakz	0:a04710facbb6	444	__IO uint32_t CR;
hudakz	0:a04710facbb6	445	__IO uint32_t CFGR;
hudakz	0:a04710facbb6	446	__IO uint32_t CIR;
hudakz	0:a04710facbb6	447	__IO uint32_t APB2RSTR;
hudakz	0:a04710facbb6	448	__IO uint32_t APB1RSTR;
hudakz	0:a04710facbb6	449	__IO uint32_t AHBENR;
hudakz	0:a04710facbb6	450	__IO uint32_t APB2ENR;
hudakz	0:a04710facbb6	451	__IO uint32_t APB1ENR;
hudakz	0:a04710facbb6	452	__IO uint32_t BDCR;
hudakz	0:a04710facbb6	453	__IO uint32_t CSR;
hudakz	0:a04710facbb6	454
hudakz	0:a04710facbb6	455
hudakz	0:a04710facbb6	456	} RCC_TypeDef;
hudakz	0:a04710facbb6	457
hudakz	0:a04710facbb6	458	/**
hudakz	0:a04710facbb6	459	* @brief Real-Time Clock
hudakz	0:a04710facbb6	460	*/
hudakz	0:a04710facbb6	461
hudakz	0:a04710facbb6	462	typedef struct
hudakz	0:a04710facbb6	463	{
hudakz	0:a04710facbb6	464	__IO uint32_t CRH;
hudakz	0:a04710facbb6	465	__IO uint32_t CRL;
hudakz	0:a04710facbb6	466	__IO uint32_t PRLH;
hudakz	0:a04710facbb6	467	__IO uint32_t PRLL;
hudakz	0:a04710facbb6	468	__IO uint32_t DIVH;
hudakz	0:a04710facbb6	469	__IO uint32_t DIVL;
hudakz	0:a04710facbb6	470	__IO uint32_t CNTH;
hudakz	0:a04710facbb6	471	__IO uint32_t CNTL;
hudakz	0:a04710facbb6	472	__IO uint32_t ALRH;
hudakz	0:a04710facbb6	473	__IO uint32_t ALRL;
hudakz	0:a04710facbb6	474	} RTC_TypeDef;
hudakz	0:a04710facbb6	475
hudakz	0:a04710facbb6	476	/**
hudakz	0:a04710facbb6	477	* @brief SD host Interface
hudakz	0:a04710facbb6	478	*/
hudakz	0:a04710facbb6	479
hudakz	0:a04710facbb6	480	typedef struct
hudakz	0:a04710facbb6	481	{
hudakz	0:a04710facbb6	482	__IO uint32_t POWER;
hudakz	0:a04710facbb6	483	__IO uint32_t CLKCR;
hudakz	0:a04710facbb6	484	__IO uint32_t ARG;
hudakz	0:a04710facbb6	485	__IO uint32_t CMD;
hudakz	0:a04710facbb6	486	__I uint32_t RESPCMD;
hudakz	0:a04710facbb6	487	__I uint32_t RESP1;
hudakz	0:a04710facbb6	488	__I uint32_t RESP2;
hudakz	0:a04710facbb6	489	__I uint32_t RESP3;
hudakz	0:a04710facbb6	490	__I uint32_t RESP4;
hudakz	0:a04710facbb6	491	__IO uint32_t DTIMER;
hudakz	0:a04710facbb6	492	__IO uint32_t DLEN;
hudakz	0:a04710facbb6	493	__IO uint32_t DCTRL;
hudakz	0:a04710facbb6	494	__I uint32_t DCOUNT;
hudakz	0:a04710facbb6	495	__I uint32_t STA;
hudakz	0:a04710facbb6	496	__IO uint32_t ICR;
hudakz	0:a04710facbb6	497	__IO uint32_t MASK;
hudakz	0:a04710facbb6	498	uint32_t RESERVED0[2];
hudakz	0:a04710facbb6	499	__I uint32_t FIFOCNT;
hudakz	0:a04710facbb6	500	uint32_t RESERVED1[13];
hudakz	0:a04710facbb6	501	__IO uint32_t FIFO;
hudakz	0:a04710facbb6	502	} SDIO_TypeDef;
hudakz	0:a04710facbb6	503
hudakz	0:a04710facbb6	504	/**
hudakz	0:a04710facbb6	505	* @brief Serial Peripheral Interface
hudakz	0:a04710facbb6	506	*/
hudakz	0:a04710facbb6	507
hudakz	0:a04710facbb6	508	typedef struct
hudakz	0:a04710facbb6	509	{
hudakz	0:a04710facbb6	510	__IO uint32_t CR1;
hudakz	0:a04710facbb6	511	__IO uint32_t CR2;
hudakz	0:a04710facbb6	512	__IO uint32_t SR;
hudakz	0:a04710facbb6	513	__IO uint32_t DR;
hudakz	0:a04710facbb6	514	__IO uint32_t CRCPR;
hudakz	0:a04710facbb6	515	__IO uint32_t RXCRCR;
hudakz	0:a04710facbb6	516	__IO uint32_t TXCRCR;
hudakz	0:a04710facbb6	517	__IO uint32_t I2SCFGR;
hudakz	0:a04710facbb6	518	} SPI_TypeDef;
hudakz	0:a04710facbb6	519
hudakz	0:a04710facbb6	520	/**
hudakz	0:a04710facbb6	521	* @brief TIM Timers
hudakz	0:a04710facbb6	522	*/
hudakz	0:a04710facbb6	523	typedef struct
hudakz	0:a04710facbb6	524	{
hudakz	0:a04710facbb6	525	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
hudakz	0:a04710facbb6	526	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
hudakz	0:a04710facbb6	527	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
hudakz	0:a04710facbb6	528	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
hudakz	0:a04710facbb6	529	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
hudakz	0:a04710facbb6	530	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
hudakz	0:a04710facbb6	531	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
hudakz	0:a04710facbb6	532	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
hudakz	0:a04710facbb6	533	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
hudakz	0:a04710facbb6	534	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
hudakz	0:a04710facbb6	535	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
hudakz	0:a04710facbb6	536	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
hudakz	0:a04710facbb6	537	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
hudakz	0:a04710facbb6	538	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
hudakz	0:a04710facbb6	539	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
hudakz	0:a04710facbb6	540	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
hudakz	0:a04710facbb6	541	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
hudakz	0:a04710facbb6	542	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
hudakz	0:a04710facbb6	543	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
hudakz	0:a04710facbb6	544	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
hudakz	0:a04710facbb6	545	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
hudakz	0:a04710facbb6	546	}TIM_TypeDef;
hudakz	0:a04710facbb6	547
hudakz	0:a04710facbb6	548
hudakz	0:a04710facbb6	549	/**
hudakz	0:a04710facbb6	550	* @brief Universal Synchronous Asynchronous Receiver Transmitter
hudakz	0:a04710facbb6	551	*/
hudakz	0:a04710facbb6	552
hudakz	0:a04710facbb6	553	typedef struct
hudakz	0:a04710facbb6	554	{
hudakz	0:a04710facbb6	555	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
hudakz	0:a04710facbb6	556	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
hudakz	0:a04710facbb6	557	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
hudakz	0:a04710facbb6	558	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
hudakz	0:a04710facbb6	559	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
hudakz	0:a04710facbb6	560	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
hudakz	0:a04710facbb6	561	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
hudakz	0:a04710facbb6	562	} USART_TypeDef;
hudakz	0:a04710facbb6	563
hudakz	0:a04710facbb6	564	/**
hudakz	0:a04710facbb6	565	* @brief Universal Serial Bus Full Speed Device
hudakz	0:a04710facbb6	566	*/
hudakz	0:a04710facbb6	567
hudakz	0:a04710facbb6	568	typedef struct
hudakz	0:a04710facbb6	569	{
hudakz	0:a04710facbb6	570	__IO uint16_t EP0R; /!< USB Endpoint 0 register, Address offset: 0x00 /
hudakz	0:a04710facbb6	571	__IO uint16_t RESERVED0; /!< Reserved /
hudakz	0:a04710facbb6	572	__IO uint16_t EP1R; /!< USB Endpoint 1 register, Address offset: 0x04 /
hudakz	0:a04710facbb6	573	__IO uint16_t RESERVED1; /!< Reserved /
hudakz	0:a04710facbb6	574	__IO uint16_t EP2R; /!< USB Endpoint 2 register, Address offset: 0x08 /
hudakz	0:a04710facbb6	575	__IO uint16_t RESERVED2; /!< Reserved /
hudakz	0:a04710facbb6	576	__IO uint16_t EP3R; /!< USB Endpoint 3 register, Address offset: 0x0C /
hudakz	0:a04710facbb6	577	__IO uint16_t RESERVED3; /!< Reserved /
hudakz	0:a04710facbb6	578	__IO uint16_t EP4R; /!< USB Endpoint 4 register, Address offset: 0x10 /
hudakz	0:a04710facbb6	579	__IO uint16_t RESERVED4; /!< Reserved /
hudakz	0:a04710facbb6	580	__IO uint16_t EP5R; /!< USB Endpoint 5 register, Address offset: 0x14 /
hudakz	0:a04710facbb6	581	__IO uint16_t RESERVED5; /!< Reserved /
hudakz	0:a04710facbb6	582	__IO uint16_t EP6R; /!< USB Endpoint 6 register, Address offset: 0x18 /
hudakz	0:a04710facbb6	583	__IO uint16_t RESERVED6; /!< Reserved /
hudakz	0:a04710facbb6	584	__IO uint16_t EP7R; /!< USB Endpoint 7 register, Address offset: 0x1C /
hudakz	0:a04710facbb6	585	__IO uint16_t RESERVED7[17]; /!< Reserved /
hudakz	0:a04710facbb6	586	__IO uint16_t CNTR; /!< Control register, Address offset: 0x40 /
hudakz	0:a04710facbb6	587	__IO uint16_t RESERVED8; /!< Reserved /
hudakz	0:a04710facbb6	588	__IO uint16_t ISTR; /!< Interrupt status register, Address offset: 0x44 /
hudakz	0:a04710facbb6	589	__IO uint16_t RESERVED9; /!< Reserved /
hudakz	0:a04710facbb6	590	__IO uint16_t FNR; /!< Frame number register, Address offset: 0x48 /
hudakz	0:a04710facbb6	591	__IO uint16_t RESERVEDA; /!< Reserved /
hudakz	0:a04710facbb6	592	__IO uint16_t DADDR; /!< Device address register, Address offset: 0x4C /
hudakz	0:a04710facbb6	593	__IO uint16_t RESERVEDB; /!< Reserved /
hudakz	0:a04710facbb6	594	__IO uint16_t BTABLE; /!< Buffer Table address register, Address offset: 0x50 /
hudakz	0:a04710facbb6	595	__IO uint16_t RESERVEDC; /!< Reserved /
hudakz	0:a04710facbb6	596	} USB_TypeDef;
hudakz	0:a04710facbb6	597
hudakz	0:a04710facbb6	598
hudakz	0:a04710facbb6	599	/**
hudakz	0:a04710facbb6	600	* @brief Window WATCHDOG
hudakz	0:a04710facbb6	601	*/
hudakz	0:a04710facbb6	602
hudakz	0:a04710facbb6	603	typedef struct
hudakz	0:a04710facbb6	604	{
hudakz	0:a04710facbb6	605	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
hudakz	0:a04710facbb6	606	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
hudakz	0:a04710facbb6	607	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
hudakz	0:a04710facbb6	608	} WWDG_TypeDef;
hudakz	0:a04710facbb6	609
hudakz	0:a04710facbb6	610	/**
hudakz	0:a04710facbb6	611	* @}
hudakz	0:a04710facbb6	612	*/
hudakz	0:a04710facbb6	613
hudakz	0:a04710facbb6	614	/** @addtogroup Peripheral_memory_map
hudakz	0:a04710facbb6	615	* @{
hudakz	0:a04710facbb6	616	*/
hudakz	0:a04710facbb6	617
hudakz	0:a04710facbb6	618
hudakz	0:a04710facbb6	619	#define FLASH_BASE 0x08000000U /!< FLASH base address in the alias region /
hudakz	0:a04710facbb6	620	#define FLASH_BANK1_END 0x0801FFFFU /!< FLASH END address of bank1 /
hudakz	0:a04710facbb6	621	#define SRAM_BASE 0x20000000U /!< SRAM base address in the alias region /
hudakz	0:a04710facbb6	622	#define PERIPH_BASE 0x40000000U /!< Peripheral base address in the alias region /
hudakz	0:a04710facbb6	623
hudakz	0:a04710facbb6	624	#define SRAM_BB_BASE 0x22000000U /!< SRAM base address in the bit-band region /
hudakz	0:a04710facbb6	625	#define PERIPH_BB_BASE 0x42000000U /!< Peripheral base address in the bit-band region /
hudakz	0:a04710facbb6	626
hudakz	0:a04710facbb6	627
hudakz	0:a04710facbb6	628	/!< Peripheral memory map /
hudakz	0:a04710facbb6	629	#define APB1PERIPH_BASE PERIPH_BASE
hudakz	0:a04710facbb6	630	#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
hudakz	0:a04710facbb6	631	#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
hudakz	0:a04710facbb6	632
hudakz	0:a04710facbb6	633	#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
hudakz	0:a04710facbb6	634	#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
hudakz	0:a04710facbb6	635	#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
hudakz	0:a04710facbb6	636	#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
hudakz	0:a04710facbb6	637	#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
hudakz	0:a04710facbb6	638	#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
hudakz	0:a04710facbb6	639	#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
hudakz	0:a04710facbb6	640	#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
hudakz	0:a04710facbb6	641	#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
hudakz	0:a04710facbb6	642	#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
hudakz	0:a04710facbb6	643	#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
hudakz	0:a04710facbb6	644	#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U)
hudakz	0:a04710facbb6	645	#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
hudakz	0:a04710facbb6	646	#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
hudakz	0:a04710facbb6	647	#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
hudakz	0:a04710facbb6	648	#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
hudakz	0:a04710facbb6	649	#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)
hudakz	0:a04710facbb6	650	#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)
hudakz	0:a04710facbb6	651	#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
hudakz	0:a04710facbb6	652	#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
hudakz	0:a04710facbb6	653	#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U)
hudakz	0:a04710facbb6	654	#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
hudakz	0:a04710facbb6	655	#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U)
hudakz	0:a04710facbb6	656	#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U)
hudakz	0:a04710facbb6	657	#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
hudakz	0:a04710facbb6	658	#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
hudakz	0:a04710facbb6	659
hudakz	0:a04710facbb6	660	#define SDIO_BASE (PERIPH_BASE + 0x00018000U)
hudakz	0:a04710facbb6	661
hudakz	0:a04710facbb6	662	#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
hudakz	0:a04710facbb6	663	#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
hudakz	0:a04710facbb6	664	#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
hudakz	0:a04710facbb6	665	#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
hudakz	0:a04710facbb6	666	#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
hudakz	0:a04710facbb6	667	#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
hudakz	0:a04710facbb6	668	#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
hudakz	0:a04710facbb6	669	#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
hudakz	0:a04710facbb6	670	#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
hudakz	0:a04710facbb6	671	#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
hudakz	0:a04710facbb6	672
hudakz	0:a04710facbb6	673	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /!< Flash registers base address /
hudakz	0:a04710facbb6	674	#define FLASHSIZE_BASE 0x1FFFF7E0U /!< FLASH Size register base address /
hudakz	0:a04710facbb6	675	#define UID_BASE 0x1FFFF7E8U /!< Unique device ID register base address /
hudakz	0:a04710facbb6	676	#define OB_BASE 0x1FFFF800U /!< Flash Option Bytes base address /
hudakz	0:a04710facbb6	677
hudakz	0:a04710facbb6	678
hudakz	0:a04710facbb6	679
hudakz	0:a04710facbb6	680	#define DBGMCU_BASE 0xE0042000U /!< Debug MCU registers base address /
hudakz	0:a04710facbb6	681
hudakz	0:a04710facbb6	682	/* USB device FS */
hudakz	0:a04710facbb6	683	#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /!< USB_IP Peripheral Registers base address /
hudakz	0:a04710facbb6	684	#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /!< USB_IP Packet Memory Area base address /
hudakz	0:a04710facbb6	685
hudakz	0:a04710facbb6	686
hudakz	0:a04710facbb6	687	/**
hudakz	0:a04710facbb6	688	* @}
hudakz	0:a04710facbb6	689	*/
hudakz	0:a04710facbb6	690
hudakz	0:a04710facbb6	691	/** @addtogroup Peripheral_declaration
hudakz	0:a04710facbb6	692	* @{
hudakz	0:a04710facbb6	693	*/
hudakz	0:a04710facbb6	694
hudakz	0:a04710facbb6	695	#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
hudakz	0:a04710facbb6	696	#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
hudakz	0:a04710facbb6	697	#define TIM4 ((TIM_TypeDef *)TIM4_BASE)
hudakz	0:a04710facbb6	698	#define RTC ((RTC_TypeDef *)RTC_BASE)
hudakz	0:a04710facbb6	699	#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
hudakz	0:a04710facbb6	700	#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
hudakz	0:a04710facbb6	701	#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
hudakz	0:a04710facbb6	702	#define USART2 ((USART_TypeDef *)USART2_BASE)
hudakz	0:a04710facbb6	703	#define USART3 ((USART_TypeDef *)USART3_BASE)
hudakz	0:a04710facbb6	704	#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
hudakz	0:a04710facbb6	705	#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
hudakz	0:a04710facbb6	706	#define USB ((USB_TypeDef *)USB_BASE)
hudakz	0:a04710facbb6	707	#define CAN1 ((CAN_TypeDef *)CAN1_BASE)
hudakz	0:a04710facbb6	708	#define BKP ((BKP_TypeDef *)BKP_BASE)
hudakz	0:a04710facbb6	709	#define PWR ((PWR_TypeDef *)PWR_BASE)
hudakz	0:a04710facbb6	710	#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
hudakz	0:a04710facbb6	711	#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
hudakz	0:a04710facbb6	712	#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
hudakz	0:a04710facbb6	713	#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
hudakz	0:a04710facbb6	714	#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
hudakz	0:a04710facbb6	715	#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
hudakz	0:a04710facbb6	716	#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
hudakz	0:a04710facbb6	717	#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
hudakz	0:a04710facbb6	718	#define ADC2 ((ADC_TypeDef *)ADC2_BASE)
hudakz	0:a04710facbb6	719	#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
hudakz	0:a04710facbb6	720	#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
hudakz	0:a04710facbb6	721	#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
hudakz	0:a04710facbb6	722	#define USART1 ((USART_TypeDef *)USART1_BASE)
hudakz	0:a04710facbb6	723	#define SDIO ((SDIO_TypeDef *)SDIO_BASE)
hudakz	0:a04710facbb6	724	#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
hudakz	0:a04710facbb6	725	#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
hudakz	0:a04710facbb6	726	#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
hudakz	0:a04710facbb6	727	#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
hudakz	0:a04710facbb6	728	#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
hudakz	0:a04710facbb6	729	#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
hudakz	0:a04710facbb6	730	#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
hudakz	0:a04710facbb6	731	#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
hudakz	0:a04710facbb6	732	#define RCC ((RCC_TypeDef *)RCC_BASE)
hudakz	0:a04710facbb6	733	#define CRC ((CRC_TypeDef *)CRC_BASE)
hudakz	0:a04710facbb6	734	#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
hudakz	0:a04710facbb6	735	#define OB ((OB_TypeDef *)OB_BASE)
hudakz	0:a04710facbb6	736	#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
hudakz	0:a04710facbb6	737
hudakz	0:a04710facbb6	738
hudakz	0:a04710facbb6	739	/**
hudakz	0:a04710facbb6	740	* @}
hudakz	0:a04710facbb6	741	*/
hudakz	0:a04710facbb6	742
hudakz	0:a04710facbb6	743	/** @addtogroup Exported_constants
hudakz	0:a04710facbb6	744	* @{
hudakz	0:a04710facbb6	745	*/
hudakz	0:a04710facbb6	746
hudakz	0:a04710facbb6	747	/** @addtogroup Peripheral_Registers_Bits_Definition
hudakz	0:a04710facbb6	748	* @{
hudakz	0:a04710facbb6	749	*/
hudakz	0:a04710facbb6	750
hudakz	0:a04710facbb6	751	/******************************************************************************/
hudakz	0:a04710facbb6	752	/* Peripheral Registers_Bits_Definition */
hudakz	0:a04710facbb6	753	/******************************************************************************/
hudakz	0:a04710facbb6	754
hudakz	0:a04710facbb6	755	/******************************************************************************/
hudakz	0:a04710facbb6	756	/* */
hudakz	0:a04710facbb6	757	/* CRC calculation unit (CRC) */
hudakz	0:a04710facbb6	758	/* */
hudakz	0:a04710facbb6	759	/******************************************************************************/
hudakz	0:a04710facbb6	760
hudakz	0:a04710facbb6	761	/***************** Bit definition for CRC_DR register *******************/
hudakz	0:a04710facbb6	762	#define CRC_DR_DR_Pos (0U)
hudakz	0:a04710facbb6	763	#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /!< 0xFFFFFFFF /
hudakz	0:a04710facbb6	764	#define CRC_DR_DR CRC_DR_DR_Msk /!< Data register bits /
hudakz	0:a04710facbb6	765
hudakz	0:a04710facbb6	766	/***************** Bit definition for CRC_IDR register ******************/
hudakz	0:a04710facbb6	767	#define CRC_IDR_IDR_Pos (0U)
hudakz	0:a04710facbb6	768	#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /!< 0x000000FF /
hudakz	0:a04710facbb6	769	#define CRC_IDR_IDR CRC_IDR_IDR_Msk /!< General-purpose 8-bit data register bits /
hudakz	0:a04710facbb6	770
hudakz	0:a04710facbb6	771	/****************** Bit definition for CRC_CR register ******************/
hudakz	0:a04710facbb6	772	#define CRC_CR_RESET_Pos (0U)
hudakz	0:a04710facbb6	773	#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	774	#define CRC_CR_RESET CRC_CR_RESET_Msk /!< RESET bit /
hudakz	0:a04710facbb6	775
hudakz	0:a04710facbb6	776	/******************************************************************************/
hudakz	0:a04710facbb6	777	/* */
hudakz	0:a04710facbb6	778	/* Power Control */
hudakz	0:a04710facbb6	779	/* */
hudakz	0:a04710facbb6	780	/******************************************************************************/
hudakz	0:a04710facbb6	781
hudakz	0:a04710facbb6	782	/****************** Bit definition for PWR_CR register ******************/
hudakz	0:a04710facbb6	783	#define PWR_CR_LPDS_Pos (0U)
hudakz	0:a04710facbb6	784	#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	785	#define PWR_CR_LPDS PWR_CR_LPDS_Msk /!< Low-Power Deepsleep /
hudakz	0:a04710facbb6	786	#define PWR_CR_PDDS_Pos (1U)
hudakz	0:a04710facbb6	787	#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	788	#define PWR_CR_PDDS PWR_CR_PDDS_Msk /!< Power Down Deepsleep /
hudakz	0:a04710facbb6	789	#define PWR_CR_CWUF_Pos (2U)
hudakz	0:a04710facbb6	790	#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	791	#define PWR_CR_CWUF PWR_CR_CWUF_Msk /!< Clear Wakeup Flag /
hudakz	0:a04710facbb6	792	#define PWR_CR_CSBF_Pos (3U)
hudakz	0:a04710facbb6	793	#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	794	#define PWR_CR_CSBF PWR_CR_CSBF_Msk /!< Clear Standby Flag /
hudakz	0:a04710facbb6	795	#define PWR_CR_PVDE_Pos (4U)
hudakz	0:a04710facbb6	796	#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	797	#define PWR_CR_PVDE PWR_CR_PVDE_Msk /!< Power Voltage Detector Enable /
hudakz	0:a04710facbb6	798
hudakz	0:a04710facbb6	799	#define PWR_CR_PLS_Pos (5U)
hudakz	0:a04710facbb6	800	#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /!< 0x000000E0 /
hudakz	0:a04710facbb6	801	#define PWR_CR_PLS PWR_CR_PLS_Msk /!< PLS[2:0] bits (PVD Level Selection) /
hudakz	0:a04710facbb6	802	#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	803	#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	804	#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	805
hudakz	0:a04710facbb6	806	/!< PVD level configuration /
hudakz	0:a04710facbb6	807	#define PWR_CR_PLS_LEV0 0x00000000U /!< PVD level 2.2V /
hudakz	0:a04710facbb6	808	#define PWR_CR_PLS_LEV1 0x00000020U /!< PVD level 2.3V /
hudakz	0:a04710facbb6	809	#define PWR_CR_PLS_LEV2 0x00000040U /!< PVD level 2.4V /
hudakz	0:a04710facbb6	810	#define PWR_CR_PLS_LEV3 0x00000060U /!< PVD level 2.5V /
hudakz	0:a04710facbb6	811	#define PWR_CR_PLS_LEV4 0x00000080U /!< PVD level 2.6V /
hudakz	0:a04710facbb6	812	#define PWR_CR_PLS_LEV5 0x000000A0U /!< PVD level 2.7V /
hudakz	0:a04710facbb6	813	#define PWR_CR_PLS_LEV6 0x000000C0U /!< PVD level 2.8V /
hudakz	0:a04710facbb6	814	#define PWR_CR_PLS_LEV7 0x000000E0U /!< PVD level 2.9V /
hudakz	0:a04710facbb6	815
hudakz	0:a04710facbb6	816	/* Legacy defines */
hudakz	0:a04710facbb6	817	#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
hudakz	0:a04710facbb6	818	#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
hudakz	0:a04710facbb6	819	#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
hudakz	0:a04710facbb6	820	#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
hudakz	0:a04710facbb6	821	#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
hudakz	0:a04710facbb6	822	#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
hudakz	0:a04710facbb6	823	#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
hudakz	0:a04710facbb6	824	#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
hudakz	0:a04710facbb6	825
hudakz	0:a04710facbb6	826	#define PWR_CR_DBP_Pos (8U)
hudakz	0:a04710facbb6	827	#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	828	#define PWR_CR_DBP PWR_CR_DBP_Msk /!< Disable Backup Domain write protection /
hudakz	0:a04710facbb6	829
hudakz	0:a04710facbb6	830
hudakz	0:a04710facbb6	831	/***************** Bit definition for PWR_CSR register ******************/
hudakz	0:a04710facbb6	832	#define PWR_CSR_WUF_Pos (0U)
hudakz	0:a04710facbb6	833	#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	834	#define PWR_CSR_WUF PWR_CSR_WUF_Msk /!< Wakeup Flag /
hudakz	0:a04710facbb6	835	#define PWR_CSR_SBF_Pos (1U)
hudakz	0:a04710facbb6	836	#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	837	#define PWR_CSR_SBF PWR_CSR_SBF_Msk /!< Standby Flag /
hudakz	0:a04710facbb6	838	#define PWR_CSR_PVDO_Pos (2U)
hudakz	0:a04710facbb6	839	#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	840	#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /!< PVD Output /
hudakz	0:a04710facbb6	841	#define PWR_CSR_EWUP_Pos (8U)
hudakz	0:a04710facbb6	842	#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	843	#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /!< Enable WKUP pin /
hudakz	0:a04710facbb6	844
hudakz	0:a04710facbb6	845	/******************************************************************************/
hudakz	0:a04710facbb6	846	/* */
hudakz	0:a04710facbb6	847	/* Backup registers */
hudakz	0:a04710facbb6	848	/* */
hudakz	0:a04710facbb6	849	/******************************************************************************/
hudakz	0:a04710facbb6	850
hudakz	0:a04710facbb6	851	/***************** Bit definition for BKP_DR1 register ******************/
hudakz	0:a04710facbb6	852	#define BKP_DR1_D_Pos (0U)
hudakz	0:a04710facbb6	853	#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	854	#define BKP_DR1_D BKP_DR1_D_Msk /!< Backup data /
hudakz	0:a04710facbb6	855
hudakz	0:a04710facbb6	856	/***************** Bit definition for BKP_DR2 register ******************/
hudakz	0:a04710facbb6	857	#define BKP_DR2_D_Pos (0U)
hudakz	0:a04710facbb6	858	#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	859	#define BKP_DR2_D BKP_DR2_D_Msk /!< Backup data /
hudakz	0:a04710facbb6	860
hudakz	0:a04710facbb6	861	/***************** Bit definition for BKP_DR3 register ******************/
hudakz	0:a04710facbb6	862	#define BKP_DR3_D_Pos (0U)
hudakz	0:a04710facbb6	863	#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	864	#define BKP_DR3_D BKP_DR3_D_Msk /!< Backup data /
hudakz	0:a04710facbb6	865
hudakz	0:a04710facbb6	866	/***************** Bit definition for BKP_DR4 register ******************/
hudakz	0:a04710facbb6	867	#define BKP_DR4_D_Pos (0U)
hudakz	0:a04710facbb6	868	#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	869	#define BKP_DR4_D BKP_DR4_D_Msk /!< Backup data /
hudakz	0:a04710facbb6	870
hudakz	0:a04710facbb6	871	/***************** Bit definition for BKP_DR5 register ******************/
hudakz	0:a04710facbb6	872	#define BKP_DR5_D_Pos (0U)
hudakz	0:a04710facbb6	873	#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	874	#define BKP_DR5_D BKP_DR5_D_Msk /!< Backup data /
hudakz	0:a04710facbb6	875
hudakz	0:a04710facbb6	876	/***************** Bit definition for BKP_DR6 register ******************/
hudakz	0:a04710facbb6	877	#define BKP_DR6_D_Pos (0U)
hudakz	0:a04710facbb6	878	#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	879	#define BKP_DR6_D BKP_DR6_D_Msk /!< Backup data /
hudakz	0:a04710facbb6	880
hudakz	0:a04710facbb6	881	/***************** Bit definition for BKP_DR7 register ******************/
hudakz	0:a04710facbb6	882	#define BKP_DR7_D_Pos (0U)
hudakz	0:a04710facbb6	883	#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	884	#define BKP_DR7_D BKP_DR7_D_Msk /!< Backup data /
hudakz	0:a04710facbb6	885
hudakz	0:a04710facbb6	886	/***************** Bit definition for BKP_DR8 register ******************/
hudakz	0:a04710facbb6	887	#define BKP_DR8_D_Pos (0U)
hudakz	0:a04710facbb6	888	#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	889	#define BKP_DR8_D BKP_DR8_D_Msk /!< Backup data /
hudakz	0:a04710facbb6	890
hudakz	0:a04710facbb6	891	/***************** Bit definition for BKP_DR9 register ******************/
hudakz	0:a04710facbb6	892	#define BKP_DR9_D_Pos (0U)
hudakz	0:a04710facbb6	893	#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	894	#define BKP_DR9_D BKP_DR9_D_Msk /!< Backup data /
hudakz	0:a04710facbb6	895
hudakz	0:a04710facbb6	896	/***************** Bit definition for BKP_DR10 register *****************/
hudakz	0:a04710facbb6	897	#define BKP_DR10_D_Pos (0U)
hudakz	0:a04710facbb6	898	#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	899	#define BKP_DR10_D BKP_DR10_D_Msk /!< Backup data /
hudakz	0:a04710facbb6	900
hudakz	0:a04710facbb6	901	#define RTC_BKP_NUMBER 10
hudakz	0:a04710facbb6	902
hudakz	0:a04710facbb6	903	/**************** Bit definition for BKP_RTCCR register *****************/
hudakz	0:a04710facbb6	904	#define BKP_RTCCR_CAL_Pos (0U)
hudakz	0:a04710facbb6	905	#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /!< 0x0000007F /
hudakz	0:a04710facbb6	906	#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /!< Calibration value /
hudakz	0:a04710facbb6	907	#define BKP_RTCCR_CCO_Pos (7U)
hudakz	0:a04710facbb6	908	#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	909	#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /!< Calibration Clock Output /
hudakz	0:a04710facbb6	910	#define BKP_RTCCR_ASOE_Pos (8U)
hudakz	0:a04710facbb6	911	#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	912	#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /!< Alarm or Second Output Enable /
hudakz	0:a04710facbb6	913	#define BKP_RTCCR_ASOS_Pos (9U)
hudakz	0:a04710facbb6	914	#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	915	#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /!< Alarm or Second Output Selection /
hudakz	0:a04710facbb6	916
hudakz	0:a04710facbb6	917	/****************** Bit definition for BKP_CR register ******************/
hudakz	0:a04710facbb6	918	#define BKP_CR_TPE_Pos (0U)
hudakz	0:a04710facbb6	919	#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	920	#define BKP_CR_TPE BKP_CR_TPE_Msk /!< TAMPER pin enable /
hudakz	0:a04710facbb6	921	#define BKP_CR_TPAL_Pos (1U)
hudakz	0:a04710facbb6	922	#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	923	#define BKP_CR_TPAL BKP_CR_TPAL_Msk /!< TAMPER pin active level /
hudakz	0:a04710facbb6	924
hudakz	0:a04710facbb6	925	/***************** Bit definition for BKP_CSR register ******************/
hudakz	0:a04710facbb6	926	#define BKP_CSR_CTE_Pos (0U)
hudakz	0:a04710facbb6	927	#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	928	#define BKP_CSR_CTE BKP_CSR_CTE_Msk /!< Clear Tamper event /
hudakz	0:a04710facbb6	929	#define BKP_CSR_CTI_Pos (1U)
hudakz	0:a04710facbb6	930	#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	931	#define BKP_CSR_CTI BKP_CSR_CTI_Msk /!< Clear Tamper Interrupt /
hudakz	0:a04710facbb6	932	#define BKP_CSR_TPIE_Pos (2U)
hudakz	0:a04710facbb6	933	#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	934	#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /!< TAMPER Pin interrupt enable /
hudakz	0:a04710facbb6	935	#define BKP_CSR_TEF_Pos (8U)
hudakz	0:a04710facbb6	936	#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	937	#define BKP_CSR_TEF BKP_CSR_TEF_Msk /!< Tamper Event Flag /
hudakz	0:a04710facbb6	938	#define BKP_CSR_TIF_Pos (9U)
hudakz	0:a04710facbb6	939	#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	940	#define BKP_CSR_TIF BKP_CSR_TIF_Msk /!< Tamper Interrupt Flag /
hudakz	0:a04710facbb6	941
hudakz	0:a04710facbb6	942	/******************************************************************************/
hudakz	0:a04710facbb6	943	/* */
hudakz	0:a04710facbb6	944	/* Reset and Clock Control */
hudakz	0:a04710facbb6	945	/* */
hudakz	0:a04710facbb6	946	/******************************************************************************/
hudakz	0:a04710facbb6	947
hudakz	0:a04710facbb6	948	/****************** Bit definition for RCC_CR register ******************/
hudakz	0:a04710facbb6	949	#define RCC_CR_HSION_Pos (0U)
hudakz	0:a04710facbb6	950	#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	951	#define RCC_CR_HSION RCC_CR_HSION_Msk /!< Internal High Speed clock enable /
hudakz	0:a04710facbb6	952	#define RCC_CR_HSIRDY_Pos (1U)
hudakz	0:a04710facbb6	953	#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	954	#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /!< Internal High Speed clock ready flag /
hudakz	0:a04710facbb6	955	#define RCC_CR_HSITRIM_Pos (3U)
hudakz	0:a04710facbb6	956	#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /!< 0x000000F8 /
hudakz	0:a04710facbb6	957	#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /!< Internal High Speed clock trimming /
hudakz	0:a04710facbb6	958	#define RCC_CR_HSICAL_Pos (8U)
hudakz	0:a04710facbb6	959	#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /!< 0x0000FF00 /
hudakz	0:a04710facbb6	960	#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /!< Internal High Speed clock Calibration /
hudakz	0:a04710facbb6	961	#define RCC_CR_HSEON_Pos (16U)
hudakz	0:a04710facbb6	962	#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	963	#define RCC_CR_HSEON RCC_CR_HSEON_Msk /!< External High Speed clock enable /
hudakz	0:a04710facbb6	964	#define RCC_CR_HSERDY_Pos (17U)
hudakz	0:a04710facbb6	965	#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	966	#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /!< External High Speed clock ready flag /
hudakz	0:a04710facbb6	967	#define RCC_CR_HSEBYP_Pos (18U)
hudakz	0:a04710facbb6	968	#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	969	#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /!< External High Speed clock Bypass /
hudakz	0:a04710facbb6	970	#define RCC_CR_CSSON_Pos (19U)
hudakz	0:a04710facbb6	971	#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	972	#define RCC_CR_CSSON RCC_CR_CSSON_Msk /!< Clock Security System enable /
hudakz	0:a04710facbb6	973	#define RCC_CR_PLLON_Pos (24U)
hudakz	0:a04710facbb6	974	#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	975	#define RCC_CR_PLLON RCC_CR_PLLON_Msk /!< PLL enable /
hudakz	0:a04710facbb6	976	#define RCC_CR_PLLRDY_Pos (25U)
hudakz	0:a04710facbb6	977	#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	978	#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /!< PLL clock ready flag /
hudakz	0:a04710facbb6	979
hudakz	0:a04710facbb6	980
hudakz	0:a04710facbb6	981	/***************** Bit definition for RCC_CFGR register *****************/
hudakz	0:a04710facbb6	982	/!< SW configuration /
hudakz	0:a04710facbb6	983	#define RCC_CFGR_SW_Pos (0U)
hudakz	0:a04710facbb6	984	#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /!< 0x00000003 /
hudakz	0:a04710facbb6	985	#define RCC_CFGR_SW RCC_CFGR_SW_Msk /!< SW[1:0] bits (System clock Switch) /
hudakz	0:a04710facbb6	986	#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	987	#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	988
hudakz	0:a04710facbb6	989	#define RCC_CFGR_SW_HSI 0x00000000U /!< HSI selected as system clock /
hudakz	0:a04710facbb6	990	#define RCC_CFGR_SW_HSE 0x00000001U /!< HSE selected as system clock /
hudakz	0:a04710facbb6	991	#define RCC_CFGR_SW_PLL 0x00000002U /!< PLL selected as system clock /
hudakz	0:a04710facbb6	992
hudakz	0:a04710facbb6	993	/!< SWS configuration /
hudakz	0:a04710facbb6	994	#define RCC_CFGR_SWS_Pos (2U)
hudakz	0:a04710facbb6	995	#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /!< 0x0000000C /
hudakz	0:a04710facbb6	996	#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /!< SWS[1:0] bits (System Clock Switch Status) /
hudakz	0:a04710facbb6	997	#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	998	#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	999
hudakz	0:a04710facbb6	1000	#define RCC_CFGR_SWS_HSI 0x00000000U /!< HSI oscillator used as system clock /
hudakz	0:a04710facbb6	1001	#define RCC_CFGR_SWS_HSE 0x00000004U /!< HSE oscillator used as system clock /
hudakz	0:a04710facbb6	1002	#define RCC_CFGR_SWS_PLL 0x00000008U /!< PLL used as system clock /
hudakz	0:a04710facbb6	1003
hudakz	0:a04710facbb6	1004	/!< HPRE configuration /
hudakz	0:a04710facbb6	1005	#define RCC_CFGR_HPRE_Pos (4U)
hudakz	0:a04710facbb6	1006	#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /!< 0x000000F0 /
hudakz	0:a04710facbb6	1007	#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /!< HPRE[3:0] bits (AHB prescaler) /
hudakz	0:a04710facbb6	1008	#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	1009	#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	1010	#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	1011	#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	1012
hudakz	0:a04710facbb6	1013	#define RCC_CFGR_HPRE_DIV1 0x00000000U /!< SYSCLK not divided /
hudakz	0:a04710facbb6	1014	#define RCC_CFGR_HPRE_DIV2 0x00000080U /!< SYSCLK divided by 2 /
hudakz	0:a04710facbb6	1015	#define RCC_CFGR_HPRE_DIV4 0x00000090U /!< SYSCLK divided by 4 /
hudakz	0:a04710facbb6	1016	#define RCC_CFGR_HPRE_DIV8 0x000000A0U /!< SYSCLK divided by 8 /
hudakz	0:a04710facbb6	1017	#define RCC_CFGR_HPRE_DIV16 0x000000B0U /!< SYSCLK divided by 16 /
hudakz	0:a04710facbb6	1018	#define RCC_CFGR_HPRE_DIV64 0x000000C0U /!< SYSCLK divided by 64 /
hudakz	0:a04710facbb6	1019	#define RCC_CFGR_HPRE_DIV128 0x000000D0U /!< SYSCLK divided by 128 /
hudakz	0:a04710facbb6	1020	#define RCC_CFGR_HPRE_DIV256 0x000000E0U /!< SYSCLK divided by 256 /
hudakz	0:a04710facbb6	1021	#define RCC_CFGR_HPRE_DIV512 0x000000F0U /!< SYSCLK divided by 512 /
hudakz	0:a04710facbb6	1022
hudakz	0:a04710facbb6	1023	/!< PPRE1 configuration /
hudakz	0:a04710facbb6	1024	#define RCC_CFGR_PPRE1_Pos (8U)
hudakz	0:a04710facbb6	1025	#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /!< 0x00000700 /
hudakz	0:a04710facbb6	1026	#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /!< PRE1[2:0] bits (APB1 prescaler) /
hudakz	0:a04710facbb6	1027	#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	1028	#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	1029	#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	1030
hudakz	0:a04710facbb6	1031	#define RCC_CFGR_PPRE1_DIV1 0x00000000U /!< HCLK not divided /
hudakz	0:a04710facbb6	1032	#define RCC_CFGR_PPRE1_DIV2 0x00000400U /!< HCLK divided by 2 /
hudakz	0:a04710facbb6	1033	#define RCC_CFGR_PPRE1_DIV4 0x00000500U /!< HCLK divided by 4 /
hudakz	0:a04710facbb6	1034	#define RCC_CFGR_PPRE1_DIV8 0x00000600U /!< HCLK divided by 8 /
hudakz	0:a04710facbb6	1035	#define RCC_CFGR_PPRE1_DIV16 0x00000700U /!< HCLK divided by 16 /
hudakz	0:a04710facbb6	1036
hudakz	0:a04710facbb6	1037	/!< PPRE2 configuration /
hudakz	0:a04710facbb6	1038	#define RCC_CFGR_PPRE2_Pos (11U)
hudakz	0:a04710facbb6	1039	#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /!< 0x00003800 /
hudakz	0:a04710facbb6	1040	#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /!< PRE2[2:0] bits (APB2 prescaler) /
hudakz	0:a04710facbb6	1041	#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	1042	#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	1043	#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	1044
hudakz	0:a04710facbb6	1045	#define RCC_CFGR_PPRE2_DIV1 0x00000000U /!< HCLK not divided /
hudakz	0:a04710facbb6	1046	#define RCC_CFGR_PPRE2_DIV2 0x00002000U /!< HCLK divided by 2 /
hudakz	0:a04710facbb6	1047	#define RCC_CFGR_PPRE2_DIV4 0x00002800U /!< HCLK divided by 4 /
hudakz	0:a04710facbb6	1048	#define RCC_CFGR_PPRE2_DIV8 0x00003000U /!< HCLK divided by 8 /
hudakz	0:a04710facbb6	1049	#define RCC_CFGR_PPRE2_DIV16 0x00003800U /!< HCLK divided by 16 /
hudakz	0:a04710facbb6	1050
hudakz	0:a04710facbb6	1051	/!< ADCPPRE configuration /
hudakz	0:a04710facbb6	1052	#define RCC_CFGR_ADCPRE_Pos (14U)
hudakz	0:a04710facbb6	1053	#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /!< 0x0000C000 /
hudakz	0:a04710facbb6	1054	#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /!< ADCPRE[1:0] bits (ADC prescaler) /
hudakz	0:a04710facbb6	1055	#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	1056	#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	1057
hudakz	0:a04710facbb6	1058	#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /!< PCLK2 divided by 2 /
hudakz	0:a04710facbb6	1059	#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /!< PCLK2 divided by 4 /
hudakz	0:a04710facbb6	1060	#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /!< PCLK2 divided by 6 /
hudakz	0:a04710facbb6	1061	#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /!< PCLK2 divided by 8 /
hudakz	0:a04710facbb6	1062
hudakz	0:a04710facbb6	1063	#define RCC_CFGR_PLLSRC_Pos (16U)
hudakz	0:a04710facbb6	1064	#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	1065	#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /!< PLL entry clock source /
hudakz	0:a04710facbb6	1066
hudakz	0:a04710facbb6	1067	#define RCC_CFGR_PLLXTPRE_Pos (17U)
hudakz	0:a04710facbb6	1068	#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	1069	#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /!< HSE divider for PLL entry /
hudakz	0:a04710facbb6	1070
hudakz	0:a04710facbb6	1071	/!< PLLMUL configuration /
hudakz	0:a04710facbb6	1072	#define RCC_CFGR_PLLMULL_Pos (18U)
hudakz	0:a04710facbb6	1073	#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /!< 0x003C0000 /
hudakz	0:a04710facbb6	1074	#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /!< PLLMUL[3:0] bits (PLL multiplication factor) /
hudakz	0:a04710facbb6	1075	#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	1076	#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	1077	#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	1078	#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	1079
hudakz	0:a04710facbb6	1080	#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /!< HSE clock not divided for PLL entry /
hudakz	0:a04710facbb6	1081	#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /!< HSE clock divided by 2 for PLL entry /
hudakz	0:a04710facbb6	1082
hudakz	0:a04710facbb6	1083	#define RCC_CFGR_PLLMULL2 0x00000000U /!< PLL input clock2 */
hudakz	0:a04710facbb6	1084	#define RCC_CFGR_PLLMULL3_Pos (18U)
hudakz	0:a04710facbb6	1085	#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	1086	#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /!< PLL input clock3 */
hudakz	0:a04710facbb6	1087	#define RCC_CFGR_PLLMULL4_Pos (19U)
hudakz	0:a04710facbb6	1088	#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	1089	#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /!< PLL input clock4 */
hudakz	0:a04710facbb6	1090	#define RCC_CFGR_PLLMULL5_Pos (18U)
hudakz	0:a04710facbb6	1091	#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /!< 0x000C0000 /
hudakz	0:a04710facbb6	1092	#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /!< PLL input clock5 */
hudakz	0:a04710facbb6	1093	#define RCC_CFGR_PLLMULL6_Pos (20U)
hudakz	0:a04710facbb6	1094	#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	1095	#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /!< PLL input clock6 */
hudakz	0:a04710facbb6	1096	#define RCC_CFGR_PLLMULL7_Pos (18U)
hudakz	0:a04710facbb6	1097	#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /!< 0x00140000 /
hudakz	0:a04710facbb6	1098	#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /!< PLL input clock7 */
hudakz	0:a04710facbb6	1099	#define RCC_CFGR_PLLMULL8_Pos (19U)
hudakz	0:a04710facbb6	1100	#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /!< 0x00180000 /
hudakz	0:a04710facbb6	1101	#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /!< PLL input clock8 */
hudakz	0:a04710facbb6	1102	#define RCC_CFGR_PLLMULL9_Pos (18U)
hudakz	0:a04710facbb6	1103	#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /!< 0x001C0000 /
hudakz	0:a04710facbb6	1104	#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /!< PLL input clock9 */
hudakz	0:a04710facbb6	1105	#define RCC_CFGR_PLLMULL10_Pos (21U)
hudakz	0:a04710facbb6	1106	#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	1107	#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /!< PLL input clock10 /
hudakz	0:a04710facbb6	1108	#define RCC_CFGR_PLLMULL11_Pos (18U)
hudakz	0:a04710facbb6	1109	#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /!< 0x00240000 /
hudakz	0:a04710facbb6	1110	#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /!< PLL input clock11 */
hudakz	0:a04710facbb6	1111	#define RCC_CFGR_PLLMULL12_Pos (19U)
hudakz	0:a04710facbb6	1112	#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /!< 0x00280000 /
hudakz	0:a04710facbb6	1113	#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /!< PLL input clock12 */
hudakz	0:a04710facbb6	1114	#define RCC_CFGR_PLLMULL13_Pos (18U)
hudakz	0:a04710facbb6	1115	#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /!< 0x002C0000 /
hudakz	0:a04710facbb6	1116	#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /!< PLL input clock13 */
hudakz	0:a04710facbb6	1117	#define RCC_CFGR_PLLMULL14_Pos (20U)
hudakz	0:a04710facbb6	1118	#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /!< 0x00300000 /
hudakz	0:a04710facbb6	1119	#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /!< PLL input clock14 */
hudakz	0:a04710facbb6	1120	#define RCC_CFGR_PLLMULL15_Pos (18U)
hudakz	0:a04710facbb6	1121	#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /!< 0x00340000 /
hudakz	0:a04710facbb6	1122	#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /!< PLL input clock15 */
hudakz	0:a04710facbb6	1123	#define RCC_CFGR_PLLMULL16_Pos (19U)
hudakz	0:a04710facbb6	1124	#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /!< 0x00380000 /
hudakz	0:a04710facbb6	1125	#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /!< PLL input clock16 */
hudakz	0:a04710facbb6	1126	#define RCC_CFGR_USBPRE_Pos (22U)
hudakz	0:a04710facbb6	1127	#define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	1128	#define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /!< USB Device prescaler /
hudakz	0:a04710facbb6	1129
hudakz	0:a04710facbb6	1130	/!< MCO configuration /
hudakz	0:a04710facbb6	1131	#define RCC_CFGR_MCO_Pos (24U)
hudakz	0:a04710facbb6	1132	#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /!< 0x07000000 /
hudakz	0:a04710facbb6	1133	#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /!< MCO[2:0] bits (Microcontroller Clock Output) /
hudakz	0:a04710facbb6	1134	#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	1135	#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	1136	#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	1137
hudakz	0:a04710facbb6	1138	#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /!< No clock /
hudakz	0:a04710facbb6	1139	#define RCC_CFGR_MCO_SYSCLK 0x04000000U /!< System clock selected as MCO source /
hudakz	0:a04710facbb6	1140	#define RCC_CFGR_MCO_HSI 0x05000000U /!< HSI clock selected as MCO source /
hudakz	0:a04710facbb6	1141	#define RCC_CFGR_MCO_HSE 0x06000000U /!< HSE clock selected as MCO source /
hudakz	0:a04710facbb6	1142	#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /!< PLL clock divided by 2 selected as MCO source /
hudakz	0:a04710facbb6	1143
hudakz	0:a04710facbb6	1144	/* Reference defines */
hudakz	0:a04710facbb6	1145	#define RCC_CFGR_MCOSEL RCC_CFGR_MCO
hudakz	0:a04710facbb6	1146	#define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
hudakz	0:a04710facbb6	1147	#define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
hudakz	0:a04710facbb6	1148	#define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
hudakz	0:a04710facbb6	1149	#define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
hudakz	0:a04710facbb6	1150	#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
hudakz	0:a04710facbb6	1151	#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
hudakz	0:a04710facbb6	1152	#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
hudakz	0:a04710facbb6	1153	#define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
hudakz	0:a04710facbb6	1154
hudakz	0:a04710facbb6	1155	/!<*************** Bit definition for RCC_CIR register ******************/
hudakz	0:a04710facbb6	1156	#define RCC_CIR_LSIRDYF_Pos (0U)
hudakz	0:a04710facbb6	1157	#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	1158	#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /!< LSI Ready Interrupt flag /
hudakz	0:a04710facbb6	1159	#define RCC_CIR_LSERDYF_Pos (1U)
hudakz	0:a04710facbb6	1160	#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	1161	#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /!< LSE Ready Interrupt flag /
hudakz	0:a04710facbb6	1162	#define RCC_CIR_HSIRDYF_Pos (2U)
hudakz	0:a04710facbb6	1163	#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	1164	#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /!< HSI Ready Interrupt flag /
hudakz	0:a04710facbb6	1165	#define RCC_CIR_HSERDYF_Pos (3U)
hudakz	0:a04710facbb6	1166	#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	1167	#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /!< HSE Ready Interrupt flag /
hudakz	0:a04710facbb6	1168	#define RCC_CIR_PLLRDYF_Pos (4U)
hudakz	0:a04710facbb6	1169	#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	1170	#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /!< PLL Ready Interrupt flag /
hudakz	0:a04710facbb6	1171	#define RCC_CIR_CSSF_Pos (7U)
hudakz	0:a04710facbb6	1172	#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	1173	#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /!< Clock Security System Interrupt flag /
hudakz	0:a04710facbb6	1174	#define RCC_CIR_LSIRDYIE_Pos (8U)
hudakz	0:a04710facbb6	1175	#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	1176	#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /!< LSI Ready Interrupt Enable /
hudakz	0:a04710facbb6	1177	#define RCC_CIR_LSERDYIE_Pos (9U)
hudakz	0:a04710facbb6	1178	#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	1179	#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /!< LSE Ready Interrupt Enable /
hudakz	0:a04710facbb6	1180	#define RCC_CIR_HSIRDYIE_Pos (10U)
hudakz	0:a04710facbb6	1181	#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	1182	#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /!< HSI Ready Interrupt Enable /
hudakz	0:a04710facbb6	1183	#define RCC_CIR_HSERDYIE_Pos (11U)
hudakz	0:a04710facbb6	1184	#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	1185	#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /!< HSE Ready Interrupt Enable /
hudakz	0:a04710facbb6	1186	#define RCC_CIR_PLLRDYIE_Pos (12U)
hudakz	0:a04710facbb6	1187	#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	1188	#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /!< PLL Ready Interrupt Enable /
hudakz	0:a04710facbb6	1189	#define RCC_CIR_LSIRDYC_Pos (16U)
hudakz	0:a04710facbb6	1190	#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	1191	#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /!< LSI Ready Interrupt Clear /
hudakz	0:a04710facbb6	1192	#define RCC_CIR_LSERDYC_Pos (17U)
hudakz	0:a04710facbb6	1193	#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	1194	#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /!< LSE Ready Interrupt Clear /
hudakz	0:a04710facbb6	1195	#define RCC_CIR_HSIRDYC_Pos (18U)
hudakz	0:a04710facbb6	1196	#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	1197	#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /!< HSI Ready Interrupt Clear /
hudakz	0:a04710facbb6	1198	#define RCC_CIR_HSERDYC_Pos (19U)
hudakz	0:a04710facbb6	1199	#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	1200	#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /!< HSE Ready Interrupt Clear /
hudakz	0:a04710facbb6	1201	#define RCC_CIR_PLLRDYC_Pos (20U)
hudakz	0:a04710facbb6	1202	#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	1203	#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /!< PLL Ready Interrupt Clear /
hudakz	0:a04710facbb6	1204	#define RCC_CIR_CSSC_Pos (23U)
hudakz	0:a04710facbb6	1205	#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	1206	#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /!< Clock Security System Interrupt Clear /
hudakz	0:a04710facbb6	1207
hudakz	0:a04710facbb6	1208
hudakz	0:a04710facbb6	1209	/*************** Bit definition for RCC_APB2RSTR register ***************/
hudakz	0:a04710facbb6	1210	#define RCC_APB2RSTR_AFIORST_Pos (0U)
hudakz	0:a04710facbb6	1211	#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	1212	#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /!< Alternate Function I/O reset /
hudakz	0:a04710facbb6	1213	#define RCC_APB2RSTR_IOPARST_Pos (2U)
hudakz	0:a04710facbb6	1214	#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	1215	#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /!< I/O port A reset /
hudakz	0:a04710facbb6	1216	#define RCC_APB2RSTR_IOPBRST_Pos (3U)
hudakz	0:a04710facbb6	1217	#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	1218	#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /!< I/O port B reset /
hudakz	0:a04710facbb6	1219	#define RCC_APB2RSTR_IOPCRST_Pos (4U)
hudakz	0:a04710facbb6	1220	#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	1221	#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /!< I/O port C reset /
hudakz	0:a04710facbb6	1222	#define RCC_APB2RSTR_IOPDRST_Pos (5U)
hudakz	0:a04710facbb6	1223	#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	1224	#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /!< I/O port D reset /
hudakz	0:a04710facbb6	1225	#define RCC_APB2RSTR_ADC1RST_Pos (9U)
hudakz	0:a04710facbb6	1226	#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	1227	#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /!< ADC 1 interface reset /
hudakz	0:a04710facbb6	1228
hudakz	0:a04710facbb6	1229	#define RCC_APB2RSTR_ADC2RST_Pos (10U)
hudakz	0:a04710facbb6	1230	#define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	1231	#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /!< ADC 2 interface reset /
hudakz	0:a04710facbb6	1232
hudakz	0:a04710facbb6	1233	#define RCC_APB2RSTR_TIM1RST_Pos (11U)
hudakz	0:a04710facbb6	1234	#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	1235	#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /!< TIM1 Timer reset /
hudakz	0:a04710facbb6	1236	#define RCC_APB2RSTR_SPI1RST_Pos (12U)
hudakz	0:a04710facbb6	1237	#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	1238	#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /!< SPI 1 reset /
hudakz	0:a04710facbb6	1239	#define RCC_APB2RSTR_USART1RST_Pos (14U)
hudakz	0:a04710facbb6	1240	#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	1241	#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /!< USART1 reset /
hudakz	0:a04710facbb6	1242
hudakz	0:a04710facbb6	1243
hudakz	0:a04710facbb6	1244	#define RCC_APB2RSTR_IOPERST_Pos (6U)
hudakz	0:a04710facbb6	1245	#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	1246	#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /!< I/O port E reset /
hudakz	0:a04710facbb6	1247
hudakz	0:a04710facbb6	1248
hudakz	0:a04710facbb6	1249
hudakz	0:a04710facbb6	1250
hudakz	0:a04710facbb6	1251	/*************** Bit definition for RCC_APB1RSTR register ***************/
hudakz	0:a04710facbb6	1252	#define RCC_APB1RSTR_TIM2RST_Pos (0U)
hudakz	0:a04710facbb6	1253	#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	1254	#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /!< Timer 2 reset /
hudakz	0:a04710facbb6	1255	#define RCC_APB1RSTR_TIM3RST_Pos (1U)
hudakz	0:a04710facbb6	1256	#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	1257	#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /!< Timer 3 reset /
hudakz	0:a04710facbb6	1258	#define RCC_APB1RSTR_WWDGRST_Pos (11U)
hudakz	0:a04710facbb6	1259	#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	1260	#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /!< Window Watchdog reset /
hudakz	0:a04710facbb6	1261	#define RCC_APB1RSTR_USART2RST_Pos (17U)
hudakz	0:a04710facbb6	1262	#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	1263	#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /!< USART 2 reset /
hudakz	0:a04710facbb6	1264	#define RCC_APB1RSTR_I2C1RST_Pos (21U)
hudakz	0:a04710facbb6	1265	#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	1266	#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /!< I2C 1 reset /
hudakz	0:a04710facbb6	1267
hudakz	0:a04710facbb6	1268	#define RCC_APB1RSTR_CAN1RST_Pos (25U)
hudakz	0:a04710facbb6	1269	#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	1270	#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /!< CAN1 reset /
hudakz	0:a04710facbb6	1271
hudakz	0:a04710facbb6	1272	#define RCC_APB1RSTR_BKPRST_Pos (27U)
hudakz	0:a04710facbb6	1273	#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	1274	#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /!< Backup interface reset /
hudakz	0:a04710facbb6	1275	#define RCC_APB1RSTR_PWRRST_Pos (28U)
hudakz	0:a04710facbb6	1276	#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	1277	#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /!< Power interface reset /
hudakz	0:a04710facbb6	1278
hudakz	0:a04710facbb6	1279	#define RCC_APB1RSTR_TIM4RST_Pos (2U)
hudakz	0:a04710facbb6	1280	#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	1281	#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /!< Timer 4 reset /
hudakz	0:a04710facbb6	1282	#define RCC_APB1RSTR_SPI2RST_Pos (14U)
hudakz	0:a04710facbb6	1283	#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	1284	#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /!< SPI 2 reset /
hudakz	0:a04710facbb6	1285	#define RCC_APB1RSTR_USART3RST_Pos (18U)
hudakz	0:a04710facbb6	1286	#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	1287	#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /!< USART 3 reset /
hudakz	0:a04710facbb6	1288	#define RCC_APB1RSTR_I2C2RST_Pos (22U)
hudakz	0:a04710facbb6	1289	#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	1290	#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /!< I2C 2 reset /
hudakz	0:a04710facbb6	1291
hudakz	0:a04710facbb6	1292	#define RCC_APB1RSTR_USBRST_Pos (23U)
hudakz	0:a04710facbb6	1293	#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	1294	#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /!< USB Device reset /
hudakz	0:a04710facbb6	1295
hudakz	0:a04710facbb6	1296
hudakz	0:a04710facbb6	1297
hudakz	0:a04710facbb6	1298
hudakz	0:a04710facbb6	1299
hudakz	0:a04710facbb6	1300
hudakz	0:a04710facbb6	1301	/**************** Bit definition for RCC_AHBENR register ****************/
hudakz	0:a04710facbb6	1302	#define RCC_AHBENR_DMA1EN_Pos (0U)
hudakz	0:a04710facbb6	1303	#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	1304	#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /!< DMA1 clock enable /
hudakz	0:a04710facbb6	1305	#define RCC_AHBENR_SRAMEN_Pos (2U)
hudakz	0:a04710facbb6	1306	#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	1307	#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /!< SRAM interface clock enable /
hudakz	0:a04710facbb6	1308	#define RCC_AHBENR_FLITFEN_Pos (4U)
hudakz	0:a04710facbb6	1309	#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	1310	#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /!< FLITF clock enable /
hudakz	0:a04710facbb6	1311	#define RCC_AHBENR_CRCEN_Pos (6U)
hudakz	0:a04710facbb6	1312	#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	1313	#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /!< CRC clock enable /
hudakz	0:a04710facbb6	1314
hudakz	0:a04710facbb6	1315
hudakz	0:a04710facbb6	1316
hudakz	0:a04710facbb6	1317
hudakz	0:a04710facbb6	1318	/**************** Bit definition for RCC_APB2ENR register ***************/
hudakz	0:a04710facbb6	1319	#define RCC_APB2ENR_AFIOEN_Pos (0U)
hudakz	0:a04710facbb6	1320	#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	1321	#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /!< Alternate Function I/O clock enable /
hudakz	0:a04710facbb6	1322	#define RCC_APB2ENR_IOPAEN_Pos (2U)
hudakz	0:a04710facbb6	1323	#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	1324	#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /!< I/O port A clock enable /
hudakz	0:a04710facbb6	1325	#define RCC_APB2ENR_IOPBEN_Pos (3U)
hudakz	0:a04710facbb6	1326	#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	1327	#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /!< I/O port B clock enable /
hudakz	0:a04710facbb6	1328	#define RCC_APB2ENR_IOPCEN_Pos (4U)
hudakz	0:a04710facbb6	1329	#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	1330	#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /!< I/O port C clock enable /
hudakz	0:a04710facbb6	1331	#define RCC_APB2ENR_IOPDEN_Pos (5U)
hudakz	0:a04710facbb6	1332	#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	1333	#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /!< I/O port D clock enable /
hudakz	0:a04710facbb6	1334	#define RCC_APB2ENR_ADC1EN_Pos (9U)
hudakz	0:a04710facbb6	1335	#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	1336	#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /!< ADC 1 interface clock enable /
hudakz	0:a04710facbb6	1337
hudakz	0:a04710facbb6	1338	#define RCC_APB2ENR_ADC2EN_Pos (10U)
hudakz	0:a04710facbb6	1339	#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	1340	#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /!< ADC 2 interface clock enable /
hudakz	0:a04710facbb6	1341
hudakz	0:a04710facbb6	1342	#define RCC_APB2ENR_TIM1EN_Pos (11U)
hudakz	0:a04710facbb6	1343	#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	1344	#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /!< TIM1 Timer clock enable /
hudakz	0:a04710facbb6	1345	#define RCC_APB2ENR_SPI1EN_Pos (12U)
hudakz	0:a04710facbb6	1346	#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	1347	#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /!< SPI 1 clock enable /
hudakz	0:a04710facbb6	1348	#define RCC_APB2ENR_USART1EN_Pos (14U)
hudakz	0:a04710facbb6	1349	#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	1350	#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /!< USART1 clock enable /
hudakz	0:a04710facbb6	1351
hudakz	0:a04710facbb6	1352
hudakz	0:a04710facbb6	1353	#define RCC_APB2ENR_IOPEEN_Pos (6U)
hudakz	0:a04710facbb6	1354	#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	1355	#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /!< I/O port E clock enable /
hudakz	0:a04710facbb6	1356
hudakz	0:a04710facbb6	1357
hudakz	0:a04710facbb6	1358
hudakz	0:a04710facbb6	1359
hudakz	0:a04710facbb6	1360	/*************** Bit definition for RCC_APB1ENR register ****************/
hudakz	0:a04710facbb6	1361	#define RCC_APB1ENR_TIM2EN_Pos (0U)
hudakz	0:a04710facbb6	1362	#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	1363	#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /!< Timer 2 clock enabled/
hudakz	0:a04710facbb6	1364	#define RCC_APB1ENR_TIM3EN_Pos (1U)
hudakz	0:a04710facbb6	1365	#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	1366	#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /!< Timer 3 clock enable /
hudakz	0:a04710facbb6	1367	#define RCC_APB1ENR_WWDGEN_Pos (11U)
hudakz	0:a04710facbb6	1368	#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	1369	#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /!< Window Watchdog clock enable /
hudakz	0:a04710facbb6	1370	#define RCC_APB1ENR_USART2EN_Pos (17U)
hudakz	0:a04710facbb6	1371	#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	1372	#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /!< USART 2 clock enable /
hudakz	0:a04710facbb6	1373	#define RCC_APB1ENR_I2C1EN_Pos (21U)
hudakz	0:a04710facbb6	1374	#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	1375	#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /!< I2C 1 clock enable /
hudakz	0:a04710facbb6	1376
hudakz	0:a04710facbb6	1377	#define RCC_APB1ENR_CAN1EN_Pos (25U)
hudakz	0:a04710facbb6	1378	#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	1379	#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /!< CAN1 clock enable /
hudakz	0:a04710facbb6	1380
hudakz	0:a04710facbb6	1381	#define RCC_APB1ENR_BKPEN_Pos (27U)
hudakz	0:a04710facbb6	1382	#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	1383	#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /!< Backup interface clock enable /
hudakz	0:a04710facbb6	1384	#define RCC_APB1ENR_PWREN_Pos (28U)
hudakz	0:a04710facbb6	1385	#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	1386	#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /!< Power interface clock enable /
hudakz	0:a04710facbb6	1387
hudakz	0:a04710facbb6	1388	#define RCC_APB1ENR_TIM4EN_Pos (2U)
hudakz	0:a04710facbb6	1389	#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	1390	#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /!< Timer 4 clock enable /
hudakz	0:a04710facbb6	1391	#define RCC_APB1ENR_SPI2EN_Pos (14U)
hudakz	0:a04710facbb6	1392	#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	1393	#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /!< SPI 2 clock enable /
hudakz	0:a04710facbb6	1394	#define RCC_APB1ENR_USART3EN_Pos (18U)
hudakz	0:a04710facbb6	1395	#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	1396	#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /!< USART 3 clock enable /
hudakz	0:a04710facbb6	1397	#define RCC_APB1ENR_I2C2EN_Pos (22U)
hudakz	0:a04710facbb6	1398	#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	1399	#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /!< I2C 2 clock enable /
hudakz	0:a04710facbb6	1400
hudakz	0:a04710facbb6	1401	#define RCC_APB1ENR_USBEN_Pos (23U)
hudakz	0:a04710facbb6	1402	#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	1403	#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /!< USB Device clock enable /
hudakz	0:a04710facbb6	1404
hudakz	0:a04710facbb6	1405
hudakz	0:a04710facbb6	1406
hudakz	0:a04710facbb6	1407
hudakz	0:a04710facbb6	1408
hudakz	0:a04710facbb6	1409
hudakz	0:a04710facbb6	1410	/***************** Bit definition for RCC_BDCR register *****************/
hudakz	0:a04710facbb6	1411	#define RCC_BDCR_LSEON_Pos (0U)
hudakz	0:a04710facbb6	1412	#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	1413	#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /!< External Low Speed oscillator enable /
hudakz	0:a04710facbb6	1414	#define RCC_BDCR_LSERDY_Pos (1U)
hudakz	0:a04710facbb6	1415	#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	1416	#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /!< External Low Speed oscillator Ready /
hudakz	0:a04710facbb6	1417	#define RCC_BDCR_LSEBYP_Pos (2U)
hudakz	0:a04710facbb6	1418	#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	1419	#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /!< External Low Speed oscillator Bypass /
hudakz	0:a04710facbb6	1420
hudakz	0:a04710facbb6	1421	#define RCC_BDCR_RTCSEL_Pos (8U)
hudakz	0:a04710facbb6	1422	#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /!< 0x00000300 /
hudakz	0:a04710facbb6	1423	#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /!< RTCSEL[1:0] bits (RTC clock source selection) /
hudakz	0:a04710facbb6	1424	#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	1425	#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	1426
hudakz	0:a04710facbb6	1427	/!< RTC congiguration /
hudakz	0:a04710facbb6	1428	#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /!< No clock /
hudakz	0:a04710facbb6	1429	#define RCC_BDCR_RTCSEL_LSE 0x00000100U /!< LSE oscillator clock used as RTC clock /
hudakz	0:a04710facbb6	1430	#define RCC_BDCR_RTCSEL_LSI 0x00000200U /!< LSI oscillator clock used as RTC clock /
hudakz	0:a04710facbb6	1431	#define RCC_BDCR_RTCSEL_HSE 0x00000300U /!< HSE oscillator clock divided by 128 used as RTC clock /
hudakz	0:a04710facbb6	1432
hudakz	0:a04710facbb6	1433	#define RCC_BDCR_RTCEN_Pos (15U)
hudakz	0:a04710facbb6	1434	#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	1435	#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /!< RTC clock enable /
hudakz	0:a04710facbb6	1436	#define RCC_BDCR_BDRST_Pos (16U)
hudakz	0:a04710facbb6	1437	#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	1438	#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /!< Backup domain software reset /
hudakz	0:a04710facbb6	1439
hudakz	0:a04710facbb6	1440	/***************** Bit definition for RCC_CSR register ******************/
hudakz	0:a04710facbb6	1441	#define RCC_CSR_LSION_Pos (0U)
hudakz	0:a04710facbb6	1442	#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	1443	#define RCC_CSR_LSION RCC_CSR_LSION_Msk /!< Internal Low Speed oscillator enable /
hudakz	0:a04710facbb6	1444	#define RCC_CSR_LSIRDY_Pos (1U)
hudakz	0:a04710facbb6	1445	#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	1446	#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /!< Internal Low Speed oscillator Ready /
hudakz	0:a04710facbb6	1447	#define RCC_CSR_RMVF_Pos (24U)
hudakz	0:a04710facbb6	1448	#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	1449	#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /!< Remove reset flag /
hudakz	0:a04710facbb6	1450	#define RCC_CSR_PINRSTF_Pos (26U)
hudakz	0:a04710facbb6	1451	#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	1452	#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /!< PIN reset flag /
hudakz	0:a04710facbb6	1453	#define RCC_CSR_PORRSTF_Pos (27U)
hudakz	0:a04710facbb6	1454	#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	1455	#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /!< POR/PDR reset flag /
hudakz	0:a04710facbb6	1456	#define RCC_CSR_SFTRSTF_Pos (28U)
hudakz	0:a04710facbb6	1457	#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	1458	#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /!< Software Reset flag /
hudakz	0:a04710facbb6	1459	#define RCC_CSR_IWDGRSTF_Pos (29U)
hudakz	0:a04710facbb6	1460	#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	1461	#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /!< Independent Watchdog reset flag /
hudakz	0:a04710facbb6	1462	#define RCC_CSR_WWDGRSTF_Pos (30U)
hudakz	0:a04710facbb6	1463	#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	1464	#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /!< Window watchdog reset flag /
hudakz	0:a04710facbb6	1465	#define RCC_CSR_LPWRRSTF_Pos (31U)
hudakz	0:a04710facbb6	1466	#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	1467	#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /!< Low-Power reset flag /
hudakz	0:a04710facbb6	1468
hudakz	0:a04710facbb6	1469
hudakz	0:a04710facbb6	1470
hudakz	0:a04710facbb6	1471	/******************************************************************************/
hudakz	0:a04710facbb6	1472	/* */
hudakz	0:a04710facbb6	1473	/* General Purpose and Alternate Function I/O */
hudakz	0:a04710facbb6	1474	/* */
hudakz	0:a04710facbb6	1475	/******************************************************************************/
hudakz	0:a04710facbb6	1476
hudakz	0:a04710facbb6	1477	/***************** Bit definition for GPIO_CRL register *****************/
hudakz	0:a04710facbb6	1478	#define GPIO_CRL_MODE_Pos (0U)
hudakz	0:a04710facbb6	1479	#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /!< 0x33333333 /
hudakz	0:a04710facbb6	1480	#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /!< Port x mode bits /
hudakz	0:a04710facbb6	1481
hudakz	0:a04710facbb6	1482	#define GPIO_CRL_MODE0_Pos (0U)
hudakz	0:a04710facbb6	1483	#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /!< 0x00000003 /
hudakz	0:a04710facbb6	1484	#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /!< MODE0[1:0] bits (Port x mode bits, pin 0) /
hudakz	0:a04710facbb6	1485	#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	1486	#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	1487
hudakz	0:a04710facbb6	1488	#define GPIO_CRL_MODE1_Pos (4U)
hudakz	0:a04710facbb6	1489	#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /!< 0x00000030 /
hudakz	0:a04710facbb6	1490	#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /!< MODE1[1:0] bits (Port x mode bits, pin 1) /
hudakz	0:a04710facbb6	1491	#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	1492	#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	1493
hudakz	0:a04710facbb6	1494	#define GPIO_CRL_MODE2_Pos (8U)
hudakz	0:a04710facbb6	1495	#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /!< 0x00000300 /
hudakz	0:a04710facbb6	1496	#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /!< MODE2[1:0] bits (Port x mode bits, pin 2) /
hudakz	0:a04710facbb6	1497	#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	1498	#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	1499
hudakz	0:a04710facbb6	1500	#define GPIO_CRL_MODE3_Pos (12U)
hudakz	0:a04710facbb6	1501	#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /!< 0x00003000 /
hudakz	0:a04710facbb6	1502	#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /!< MODE3[1:0] bits (Port x mode bits, pin 3) /
hudakz	0:a04710facbb6	1503	#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	1504	#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	1505
hudakz	0:a04710facbb6	1506	#define GPIO_CRL_MODE4_Pos (16U)
hudakz	0:a04710facbb6	1507	#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /!< 0x00030000 /
hudakz	0:a04710facbb6	1508	#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /!< MODE4[1:0] bits (Port x mode bits, pin 4) /
hudakz	0:a04710facbb6	1509	#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	1510	#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	1511
hudakz	0:a04710facbb6	1512	#define GPIO_CRL_MODE5_Pos (20U)
hudakz	0:a04710facbb6	1513	#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /!< 0x00300000 /
hudakz	0:a04710facbb6	1514	#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /!< MODE5[1:0] bits (Port x mode bits, pin 5) /
hudakz	0:a04710facbb6	1515	#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	1516	#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	1517
hudakz	0:a04710facbb6	1518	#define GPIO_CRL_MODE6_Pos (24U)
hudakz	0:a04710facbb6	1519	#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /!< 0x03000000 /
hudakz	0:a04710facbb6	1520	#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /!< MODE6[1:0] bits (Port x mode bits, pin 6) /
hudakz	0:a04710facbb6	1521	#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	1522	#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	1523
hudakz	0:a04710facbb6	1524	#define GPIO_CRL_MODE7_Pos (28U)
hudakz	0:a04710facbb6	1525	#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /!< 0x30000000 /
hudakz	0:a04710facbb6	1526	#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /!< MODE7[1:0] bits (Port x mode bits, pin 7) /
hudakz	0:a04710facbb6	1527	#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	1528	#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	1529
hudakz	0:a04710facbb6	1530	#define GPIO_CRL_CNF_Pos (2U)
hudakz	0:a04710facbb6	1531	#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /!< 0xCCCCCCCC /
hudakz	0:a04710facbb6	1532	#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /!< Port x configuration bits /
hudakz	0:a04710facbb6	1533
hudakz	0:a04710facbb6	1534	#define GPIO_CRL_CNF0_Pos (2U)
hudakz	0:a04710facbb6	1535	#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /!< 0x0000000C /
hudakz	0:a04710facbb6	1536	#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /!< CNF0[1:0] bits (Port x configuration bits, pin 0) /
hudakz	0:a04710facbb6	1537	#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	1538	#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	1539
hudakz	0:a04710facbb6	1540	#define GPIO_CRL_CNF1_Pos (6U)
hudakz	0:a04710facbb6	1541	#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /!< 0x000000C0 /
hudakz	0:a04710facbb6	1542	#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /!< CNF1[1:0] bits (Port x configuration bits, pin 1) /
hudakz	0:a04710facbb6	1543	#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	1544	#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	1545
hudakz	0:a04710facbb6	1546	#define GPIO_CRL_CNF2_Pos (10U)
hudakz	0:a04710facbb6	1547	#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /!< 0x00000C00 /
hudakz	0:a04710facbb6	1548	#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /!< CNF2[1:0] bits (Port x configuration bits, pin 2) /
hudakz	0:a04710facbb6	1549	#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	1550	#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	1551
hudakz	0:a04710facbb6	1552	#define GPIO_CRL_CNF3_Pos (14U)
hudakz	0:a04710facbb6	1553	#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /!< 0x0000C000 /
hudakz	0:a04710facbb6	1554	#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /!< CNF3[1:0] bits (Port x configuration bits, pin 3) /
hudakz	0:a04710facbb6	1555	#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	1556	#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	1557
hudakz	0:a04710facbb6	1558	#define GPIO_CRL_CNF4_Pos (18U)
hudakz	0:a04710facbb6	1559	#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /!< 0x000C0000 /
hudakz	0:a04710facbb6	1560	#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /!< CNF4[1:0] bits (Port x configuration bits, pin 4) /
hudakz	0:a04710facbb6	1561	#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	1562	#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	1563
hudakz	0:a04710facbb6	1564	#define GPIO_CRL_CNF5_Pos (22U)
hudakz	0:a04710facbb6	1565	#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /!< 0x00C00000 /
hudakz	0:a04710facbb6	1566	#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /!< CNF5[1:0] bits (Port x configuration bits, pin 5) /
hudakz	0:a04710facbb6	1567	#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	1568	#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	1569
hudakz	0:a04710facbb6	1570	#define GPIO_CRL_CNF6_Pos (26U)
hudakz	0:a04710facbb6	1571	#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /!< 0x0C000000 /
hudakz	0:a04710facbb6	1572	#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /!< CNF6[1:0] bits (Port x configuration bits, pin 6) /
hudakz	0:a04710facbb6	1573	#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	1574	#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	1575
hudakz	0:a04710facbb6	1576	#define GPIO_CRL_CNF7_Pos (30U)
hudakz	0:a04710facbb6	1577	#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /!< 0xC0000000 /
hudakz	0:a04710facbb6	1578	#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /!< CNF7[1:0] bits (Port x configuration bits, pin 7) /
hudakz	0:a04710facbb6	1579	#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	1580	#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	1581
hudakz	0:a04710facbb6	1582	/***************** Bit definition for GPIO_CRH register *****************/
hudakz	0:a04710facbb6	1583	#define GPIO_CRH_MODE_Pos (0U)
hudakz	0:a04710facbb6	1584	#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /!< 0x33333333 /
hudakz	0:a04710facbb6	1585	#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /!< Port x mode bits /
hudakz	0:a04710facbb6	1586
hudakz	0:a04710facbb6	1587	#define GPIO_CRH_MODE8_Pos (0U)
hudakz	0:a04710facbb6	1588	#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /!< 0x00000003 /
hudakz	0:a04710facbb6	1589	#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /!< MODE8[1:0] bits (Port x mode bits, pin 8) /
hudakz	0:a04710facbb6	1590	#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	1591	#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	1592
hudakz	0:a04710facbb6	1593	#define GPIO_CRH_MODE9_Pos (4U)
hudakz	0:a04710facbb6	1594	#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /!< 0x00000030 /
hudakz	0:a04710facbb6	1595	#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /!< MODE9[1:0] bits (Port x mode bits, pin 9) /
hudakz	0:a04710facbb6	1596	#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	1597	#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	1598
hudakz	0:a04710facbb6	1599	#define GPIO_CRH_MODE10_Pos (8U)
hudakz	0:a04710facbb6	1600	#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /!< 0x00000300 /
hudakz	0:a04710facbb6	1601	#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /!< MODE10[1:0] bits (Port x mode bits, pin 10) /
hudakz	0:a04710facbb6	1602	#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	1603	#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	1604
hudakz	0:a04710facbb6	1605	#define GPIO_CRH_MODE11_Pos (12U)
hudakz	0:a04710facbb6	1606	#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /!< 0x00003000 /
hudakz	0:a04710facbb6	1607	#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /!< MODE11[1:0] bits (Port x mode bits, pin 11) /
hudakz	0:a04710facbb6	1608	#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	1609	#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	1610
hudakz	0:a04710facbb6	1611	#define GPIO_CRH_MODE12_Pos (16U)
hudakz	0:a04710facbb6	1612	#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /!< 0x00030000 /
hudakz	0:a04710facbb6	1613	#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /!< MODE12[1:0] bits (Port x mode bits, pin 12) /
hudakz	0:a04710facbb6	1614	#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	1615	#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	1616
hudakz	0:a04710facbb6	1617	#define GPIO_CRH_MODE13_Pos (20U)
hudakz	0:a04710facbb6	1618	#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /!< 0x00300000 /
hudakz	0:a04710facbb6	1619	#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /!< MODE13[1:0] bits (Port x mode bits, pin 13) /
hudakz	0:a04710facbb6	1620	#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	1621	#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	1622
hudakz	0:a04710facbb6	1623	#define GPIO_CRH_MODE14_Pos (24U)
hudakz	0:a04710facbb6	1624	#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /!< 0x03000000 /
hudakz	0:a04710facbb6	1625	#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /!< MODE14[1:0] bits (Port x mode bits, pin 14) /
hudakz	0:a04710facbb6	1626	#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	1627	#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	1628
hudakz	0:a04710facbb6	1629	#define GPIO_CRH_MODE15_Pos (28U)
hudakz	0:a04710facbb6	1630	#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /!< 0x30000000 /
hudakz	0:a04710facbb6	1631	#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /!< MODE15[1:0] bits (Port x mode bits, pin 15) /
hudakz	0:a04710facbb6	1632	#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	1633	#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	1634
hudakz	0:a04710facbb6	1635	#define GPIO_CRH_CNF_Pos (2U)
hudakz	0:a04710facbb6	1636	#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /!< 0xCCCCCCCC /
hudakz	0:a04710facbb6	1637	#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /!< Port x configuration bits /
hudakz	0:a04710facbb6	1638
hudakz	0:a04710facbb6	1639	#define GPIO_CRH_CNF8_Pos (2U)
hudakz	0:a04710facbb6	1640	#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /!< 0x0000000C /
hudakz	0:a04710facbb6	1641	#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /!< CNF8[1:0] bits (Port x configuration bits, pin 8) /
hudakz	0:a04710facbb6	1642	#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	1643	#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	1644
hudakz	0:a04710facbb6	1645	#define GPIO_CRH_CNF9_Pos (6U)
hudakz	0:a04710facbb6	1646	#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /!< 0x000000C0 /
hudakz	0:a04710facbb6	1647	#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /!< CNF9[1:0] bits (Port x configuration bits, pin 9) /
hudakz	0:a04710facbb6	1648	#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	1649	#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	1650
hudakz	0:a04710facbb6	1651	#define GPIO_CRH_CNF10_Pos (10U)
hudakz	0:a04710facbb6	1652	#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /!< 0x00000C00 /
hudakz	0:a04710facbb6	1653	#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /!< CNF10[1:0] bits (Port x configuration bits, pin 10) /
hudakz	0:a04710facbb6	1654	#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	1655	#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	1656
hudakz	0:a04710facbb6	1657	#define GPIO_CRH_CNF11_Pos (14U)
hudakz	0:a04710facbb6	1658	#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /!< 0x0000C000 /
hudakz	0:a04710facbb6	1659	#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /!< CNF11[1:0] bits (Port x configuration bits, pin 11) /
hudakz	0:a04710facbb6	1660	#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	1661	#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	1662
hudakz	0:a04710facbb6	1663	#define GPIO_CRH_CNF12_Pos (18U)
hudakz	0:a04710facbb6	1664	#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /!< 0x000C0000 /
hudakz	0:a04710facbb6	1665	#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /!< CNF12[1:0] bits (Port x configuration bits, pin 12) /
hudakz	0:a04710facbb6	1666	#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	1667	#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	1668
hudakz	0:a04710facbb6	1669	#define GPIO_CRH_CNF13_Pos (22U)
hudakz	0:a04710facbb6	1670	#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /!< 0x00C00000 /
hudakz	0:a04710facbb6	1671	#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /!< CNF13[1:0] bits (Port x configuration bits, pin 13) /
hudakz	0:a04710facbb6	1672	#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	1673	#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	1674
hudakz	0:a04710facbb6	1675	#define GPIO_CRH_CNF14_Pos (26U)
hudakz	0:a04710facbb6	1676	#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /!< 0x0C000000 /
hudakz	0:a04710facbb6	1677	#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /!< CNF14[1:0] bits (Port x configuration bits, pin 14) /
hudakz	0:a04710facbb6	1678	#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	1679	#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	1680
hudakz	0:a04710facbb6	1681	#define GPIO_CRH_CNF15_Pos (30U)
hudakz	0:a04710facbb6	1682	#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /!< 0xC0000000 /
hudakz	0:a04710facbb6	1683	#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /!< CNF15[1:0] bits (Port x configuration bits, pin 15) /
hudakz	0:a04710facbb6	1684	#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	1685	#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	1686
hudakz	0:a04710facbb6	1687	/!<*************** Bit definition for GPIO_IDR register *****************/
hudakz	0:a04710facbb6	1688	#define GPIO_IDR_IDR0_Pos (0U)
hudakz	0:a04710facbb6	1689	#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	1690	#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /!< Port input data, bit 0 /
hudakz	0:a04710facbb6	1691	#define GPIO_IDR_IDR1_Pos (1U)
hudakz	0:a04710facbb6	1692	#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	1693	#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /!< Port input data, bit 1 /
hudakz	0:a04710facbb6	1694	#define GPIO_IDR_IDR2_Pos (2U)
hudakz	0:a04710facbb6	1695	#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	1696	#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /!< Port input data, bit 2 /
hudakz	0:a04710facbb6	1697	#define GPIO_IDR_IDR3_Pos (3U)
hudakz	0:a04710facbb6	1698	#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	1699	#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /!< Port input data, bit 3 /
hudakz	0:a04710facbb6	1700	#define GPIO_IDR_IDR4_Pos (4U)
hudakz	0:a04710facbb6	1701	#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	1702	#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /!< Port input data, bit 4 /
hudakz	0:a04710facbb6	1703	#define GPIO_IDR_IDR5_Pos (5U)
hudakz	0:a04710facbb6	1704	#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	1705	#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /!< Port input data, bit 5 /
hudakz	0:a04710facbb6	1706	#define GPIO_IDR_IDR6_Pos (6U)
hudakz	0:a04710facbb6	1707	#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	1708	#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /!< Port input data, bit 6 /
hudakz	0:a04710facbb6	1709	#define GPIO_IDR_IDR7_Pos (7U)
hudakz	0:a04710facbb6	1710	#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	1711	#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /!< Port input data, bit 7 /
hudakz	0:a04710facbb6	1712	#define GPIO_IDR_IDR8_Pos (8U)
hudakz	0:a04710facbb6	1713	#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	1714	#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /!< Port input data, bit 8 /
hudakz	0:a04710facbb6	1715	#define GPIO_IDR_IDR9_Pos (9U)
hudakz	0:a04710facbb6	1716	#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	1717	#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /!< Port input data, bit 9 /
hudakz	0:a04710facbb6	1718	#define GPIO_IDR_IDR10_Pos (10U)
hudakz	0:a04710facbb6	1719	#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	1720	#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /!< Port input data, bit 10 /
hudakz	0:a04710facbb6	1721	#define GPIO_IDR_IDR11_Pos (11U)
hudakz	0:a04710facbb6	1722	#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	1723	#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /!< Port input data, bit 11 /
hudakz	0:a04710facbb6	1724	#define GPIO_IDR_IDR12_Pos (12U)
hudakz	0:a04710facbb6	1725	#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	1726	#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /!< Port input data, bit 12 /
hudakz	0:a04710facbb6	1727	#define GPIO_IDR_IDR13_Pos (13U)
hudakz	0:a04710facbb6	1728	#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	1729	#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /!< Port input data, bit 13 /
hudakz	0:a04710facbb6	1730	#define GPIO_IDR_IDR14_Pos (14U)
hudakz	0:a04710facbb6	1731	#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	1732	#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /!< Port input data, bit 14 /
hudakz	0:a04710facbb6	1733	#define GPIO_IDR_IDR15_Pos (15U)
hudakz	0:a04710facbb6	1734	#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	1735	#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /!< Port input data, bit 15 /
hudakz	0:a04710facbb6	1736
hudakz	0:a04710facbb6	1737	/***************** Bit definition for GPIO_ODR register *****************/
hudakz	0:a04710facbb6	1738	#define GPIO_ODR_ODR0_Pos (0U)
hudakz	0:a04710facbb6	1739	#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	1740	#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /!< Port output data, bit 0 /
hudakz	0:a04710facbb6	1741	#define GPIO_ODR_ODR1_Pos (1U)
hudakz	0:a04710facbb6	1742	#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	1743	#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /!< Port output data, bit 1 /
hudakz	0:a04710facbb6	1744	#define GPIO_ODR_ODR2_Pos (2U)
hudakz	0:a04710facbb6	1745	#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	1746	#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /!< Port output data, bit 2 /
hudakz	0:a04710facbb6	1747	#define GPIO_ODR_ODR3_Pos (3U)
hudakz	0:a04710facbb6	1748	#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	1749	#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /!< Port output data, bit 3 /
hudakz	0:a04710facbb6	1750	#define GPIO_ODR_ODR4_Pos (4U)
hudakz	0:a04710facbb6	1751	#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	1752	#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /!< Port output data, bit 4 /
hudakz	0:a04710facbb6	1753	#define GPIO_ODR_ODR5_Pos (5U)
hudakz	0:a04710facbb6	1754	#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	1755	#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /!< Port output data, bit 5 /
hudakz	0:a04710facbb6	1756	#define GPIO_ODR_ODR6_Pos (6U)
hudakz	0:a04710facbb6	1757	#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	1758	#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /!< Port output data, bit 6 /
hudakz	0:a04710facbb6	1759	#define GPIO_ODR_ODR7_Pos (7U)
hudakz	0:a04710facbb6	1760	#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	1761	#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /!< Port output data, bit 7 /
hudakz	0:a04710facbb6	1762	#define GPIO_ODR_ODR8_Pos (8U)
hudakz	0:a04710facbb6	1763	#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	1764	#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /!< Port output data, bit 8 /
hudakz	0:a04710facbb6	1765	#define GPIO_ODR_ODR9_Pos (9U)
hudakz	0:a04710facbb6	1766	#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	1767	#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /!< Port output data, bit 9 /
hudakz	0:a04710facbb6	1768	#define GPIO_ODR_ODR10_Pos (10U)
hudakz	0:a04710facbb6	1769	#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	1770	#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /!< Port output data, bit 10 /
hudakz	0:a04710facbb6	1771	#define GPIO_ODR_ODR11_Pos (11U)
hudakz	0:a04710facbb6	1772	#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	1773	#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /!< Port output data, bit 11 /
hudakz	0:a04710facbb6	1774	#define GPIO_ODR_ODR12_Pos (12U)
hudakz	0:a04710facbb6	1775	#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	1776	#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /!< Port output data, bit 12 /
hudakz	0:a04710facbb6	1777	#define GPIO_ODR_ODR13_Pos (13U)
hudakz	0:a04710facbb6	1778	#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	1779	#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /!< Port output data, bit 13 /
hudakz	0:a04710facbb6	1780	#define GPIO_ODR_ODR14_Pos (14U)
hudakz	0:a04710facbb6	1781	#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	1782	#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /!< Port output data, bit 14 /
hudakz	0:a04710facbb6	1783	#define GPIO_ODR_ODR15_Pos (15U)
hudakz	0:a04710facbb6	1784	#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	1785	#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /!< Port output data, bit 15 /
hudakz	0:a04710facbb6	1786
hudakz	0:a04710facbb6	1787	/**************** Bit definition for GPIO_BSRR register *****************/
hudakz	0:a04710facbb6	1788	#define GPIO_BSRR_BS0_Pos (0U)
hudakz	0:a04710facbb6	1789	#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	1790	#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /!< Port x Set bit 0 /
hudakz	0:a04710facbb6	1791	#define GPIO_BSRR_BS1_Pos (1U)
hudakz	0:a04710facbb6	1792	#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	1793	#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /!< Port x Set bit 1 /
hudakz	0:a04710facbb6	1794	#define GPIO_BSRR_BS2_Pos (2U)
hudakz	0:a04710facbb6	1795	#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	1796	#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /!< Port x Set bit 2 /
hudakz	0:a04710facbb6	1797	#define GPIO_BSRR_BS3_Pos (3U)
hudakz	0:a04710facbb6	1798	#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	1799	#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /!< Port x Set bit 3 /
hudakz	0:a04710facbb6	1800	#define GPIO_BSRR_BS4_Pos (4U)
hudakz	0:a04710facbb6	1801	#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	1802	#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /!< Port x Set bit 4 /
hudakz	0:a04710facbb6	1803	#define GPIO_BSRR_BS5_Pos (5U)
hudakz	0:a04710facbb6	1804	#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	1805	#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /!< Port x Set bit 5 /
hudakz	0:a04710facbb6	1806	#define GPIO_BSRR_BS6_Pos (6U)
hudakz	0:a04710facbb6	1807	#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	1808	#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /!< Port x Set bit 6 /
hudakz	0:a04710facbb6	1809	#define GPIO_BSRR_BS7_Pos (7U)
hudakz	0:a04710facbb6	1810	#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	1811	#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /!< Port x Set bit 7 /
hudakz	0:a04710facbb6	1812	#define GPIO_BSRR_BS8_Pos (8U)
hudakz	0:a04710facbb6	1813	#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	1814	#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /!< Port x Set bit 8 /
hudakz	0:a04710facbb6	1815	#define GPIO_BSRR_BS9_Pos (9U)
hudakz	0:a04710facbb6	1816	#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	1817	#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /!< Port x Set bit 9 /
hudakz	0:a04710facbb6	1818	#define GPIO_BSRR_BS10_Pos (10U)
hudakz	0:a04710facbb6	1819	#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	1820	#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /!< Port x Set bit 10 /
hudakz	0:a04710facbb6	1821	#define GPIO_BSRR_BS11_Pos (11U)
hudakz	0:a04710facbb6	1822	#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	1823	#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /!< Port x Set bit 11 /
hudakz	0:a04710facbb6	1824	#define GPIO_BSRR_BS12_Pos (12U)
hudakz	0:a04710facbb6	1825	#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	1826	#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /!< Port x Set bit 12 /
hudakz	0:a04710facbb6	1827	#define GPIO_BSRR_BS13_Pos (13U)
hudakz	0:a04710facbb6	1828	#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	1829	#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /!< Port x Set bit 13 /
hudakz	0:a04710facbb6	1830	#define GPIO_BSRR_BS14_Pos (14U)
hudakz	0:a04710facbb6	1831	#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	1832	#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /!< Port x Set bit 14 /
hudakz	0:a04710facbb6	1833	#define GPIO_BSRR_BS15_Pos (15U)
hudakz	0:a04710facbb6	1834	#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	1835	#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /!< Port x Set bit 15 /
hudakz	0:a04710facbb6	1836
hudakz	0:a04710facbb6	1837	#define GPIO_BSRR_BR0_Pos (16U)
hudakz	0:a04710facbb6	1838	#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	1839	#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /!< Port x Reset bit 0 /
hudakz	0:a04710facbb6	1840	#define GPIO_BSRR_BR1_Pos (17U)
hudakz	0:a04710facbb6	1841	#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	1842	#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /!< Port x Reset bit 1 /
hudakz	0:a04710facbb6	1843	#define GPIO_BSRR_BR2_Pos (18U)
hudakz	0:a04710facbb6	1844	#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	1845	#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /!< Port x Reset bit 2 /
hudakz	0:a04710facbb6	1846	#define GPIO_BSRR_BR3_Pos (19U)
hudakz	0:a04710facbb6	1847	#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	1848	#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /!< Port x Reset bit 3 /
hudakz	0:a04710facbb6	1849	#define GPIO_BSRR_BR4_Pos (20U)
hudakz	0:a04710facbb6	1850	#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	1851	#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /!< Port x Reset bit 4 /
hudakz	0:a04710facbb6	1852	#define GPIO_BSRR_BR5_Pos (21U)
hudakz	0:a04710facbb6	1853	#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	1854	#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /!< Port x Reset bit 5 /
hudakz	0:a04710facbb6	1855	#define GPIO_BSRR_BR6_Pos (22U)
hudakz	0:a04710facbb6	1856	#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	1857	#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /!< Port x Reset bit 6 /
hudakz	0:a04710facbb6	1858	#define GPIO_BSRR_BR7_Pos (23U)
hudakz	0:a04710facbb6	1859	#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	1860	#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /!< Port x Reset bit 7 /
hudakz	0:a04710facbb6	1861	#define GPIO_BSRR_BR8_Pos (24U)
hudakz	0:a04710facbb6	1862	#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	1863	#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /!< Port x Reset bit 8 /
hudakz	0:a04710facbb6	1864	#define GPIO_BSRR_BR9_Pos (25U)
hudakz	0:a04710facbb6	1865	#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	1866	#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /!< Port x Reset bit 9 /
hudakz	0:a04710facbb6	1867	#define GPIO_BSRR_BR10_Pos (26U)
hudakz	0:a04710facbb6	1868	#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	1869	#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /!< Port x Reset bit 10 /
hudakz	0:a04710facbb6	1870	#define GPIO_BSRR_BR11_Pos (27U)
hudakz	0:a04710facbb6	1871	#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	1872	#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /!< Port x Reset bit 11 /
hudakz	0:a04710facbb6	1873	#define GPIO_BSRR_BR12_Pos (28U)
hudakz	0:a04710facbb6	1874	#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	1875	#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /!< Port x Reset bit 12 /
hudakz	0:a04710facbb6	1876	#define GPIO_BSRR_BR13_Pos (29U)
hudakz	0:a04710facbb6	1877	#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	1878	#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /!< Port x Reset bit 13 /
hudakz	0:a04710facbb6	1879	#define GPIO_BSRR_BR14_Pos (30U)
hudakz	0:a04710facbb6	1880	#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	1881	#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /!< Port x Reset bit 14 /
hudakz	0:a04710facbb6	1882	#define GPIO_BSRR_BR15_Pos (31U)
hudakz	0:a04710facbb6	1883	#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	1884	#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /!< Port x Reset bit 15 /
hudakz	0:a04710facbb6	1885
hudakz	0:a04710facbb6	1886	/***************** Bit definition for GPIO_BRR register *****************/
hudakz	0:a04710facbb6	1887	#define GPIO_BRR_BR0_Pos (0U)
hudakz	0:a04710facbb6	1888	#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	1889	#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /!< Port x Reset bit 0 /
hudakz	0:a04710facbb6	1890	#define GPIO_BRR_BR1_Pos (1U)
hudakz	0:a04710facbb6	1891	#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	1892	#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /!< Port x Reset bit 1 /
hudakz	0:a04710facbb6	1893	#define GPIO_BRR_BR2_Pos (2U)
hudakz	0:a04710facbb6	1894	#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	1895	#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /!< Port x Reset bit 2 /
hudakz	0:a04710facbb6	1896	#define GPIO_BRR_BR3_Pos (3U)
hudakz	0:a04710facbb6	1897	#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	1898	#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /!< Port x Reset bit 3 /
hudakz	0:a04710facbb6	1899	#define GPIO_BRR_BR4_Pos (4U)
hudakz	0:a04710facbb6	1900	#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	1901	#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /!< Port x Reset bit 4 /
hudakz	0:a04710facbb6	1902	#define GPIO_BRR_BR5_Pos (5U)
hudakz	0:a04710facbb6	1903	#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	1904	#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /!< Port x Reset bit 5 /
hudakz	0:a04710facbb6	1905	#define GPIO_BRR_BR6_Pos (6U)
hudakz	0:a04710facbb6	1906	#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	1907	#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /!< Port x Reset bit 6 /
hudakz	0:a04710facbb6	1908	#define GPIO_BRR_BR7_Pos (7U)
hudakz	0:a04710facbb6	1909	#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	1910	#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /!< Port x Reset bit 7 /
hudakz	0:a04710facbb6	1911	#define GPIO_BRR_BR8_Pos (8U)
hudakz	0:a04710facbb6	1912	#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	1913	#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /!< Port x Reset bit 8 /
hudakz	0:a04710facbb6	1914	#define GPIO_BRR_BR9_Pos (9U)
hudakz	0:a04710facbb6	1915	#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	1916	#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /!< Port x Reset bit 9 /
hudakz	0:a04710facbb6	1917	#define GPIO_BRR_BR10_Pos (10U)
hudakz	0:a04710facbb6	1918	#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	1919	#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /!< Port x Reset bit 10 /
hudakz	0:a04710facbb6	1920	#define GPIO_BRR_BR11_Pos (11U)
hudakz	0:a04710facbb6	1921	#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	1922	#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /!< Port x Reset bit 11 /
hudakz	0:a04710facbb6	1923	#define GPIO_BRR_BR12_Pos (12U)
hudakz	0:a04710facbb6	1924	#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	1925	#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /!< Port x Reset bit 12 /
hudakz	0:a04710facbb6	1926	#define GPIO_BRR_BR13_Pos (13U)
hudakz	0:a04710facbb6	1927	#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	1928	#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /!< Port x Reset bit 13 /
hudakz	0:a04710facbb6	1929	#define GPIO_BRR_BR14_Pos (14U)
hudakz	0:a04710facbb6	1930	#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	1931	#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /!< Port x Reset bit 14 /
hudakz	0:a04710facbb6	1932	#define GPIO_BRR_BR15_Pos (15U)
hudakz	0:a04710facbb6	1933	#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	1934	#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /!< Port x Reset bit 15 /
hudakz	0:a04710facbb6	1935
hudakz	0:a04710facbb6	1936	/**************** Bit definition for GPIO_LCKR register *****************/
hudakz	0:a04710facbb6	1937	#define GPIO_LCKR_LCK0_Pos (0U)
hudakz	0:a04710facbb6	1938	#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	1939	#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /!< Port x Lock bit 0 /
hudakz	0:a04710facbb6	1940	#define GPIO_LCKR_LCK1_Pos (1U)
hudakz	0:a04710facbb6	1941	#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	1942	#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /!< Port x Lock bit 1 /
hudakz	0:a04710facbb6	1943	#define GPIO_LCKR_LCK2_Pos (2U)
hudakz	0:a04710facbb6	1944	#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	1945	#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /!< Port x Lock bit 2 /
hudakz	0:a04710facbb6	1946	#define GPIO_LCKR_LCK3_Pos (3U)
hudakz	0:a04710facbb6	1947	#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	1948	#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /!< Port x Lock bit 3 /
hudakz	0:a04710facbb6	1949	#define GPIO_LCKR_LCK4_Pos (4U)
hudakz	0:a04710facbb6	1950	#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	1951	#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /!< Port x Lock bit 4 /
hudakz	0:a04710facbb6	1952	#define GPIO_LCKR_LCK5_Pos (5U)
hudakz	0:a04710facbb6	1953	#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	1954	#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /!< Port x Lock bit 5 /
hudakz	0:a04710facbb6	1955	#define GPIO_LCKR_LCK6_Pos (6U)
hudakz	0:a04710facbb6	1956	#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	1957	#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /!< Port x Lock bit 6 /
hudakz	0:a04710facbb6	1958	#define GPIO_LCKR_LCK7_Pos (7U)
hudakz	0:a04710facbb6	1959	#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	1960	#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /!< Port x Lock bit 7 /
hudakz	0:a04710facbb6	1961	#define GPIO_LCKR_LCK8_Pos (8U)
hudakz	0:a04710facbb6	1962	#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	1963	#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /!< Port x Lock bit 8 /
hudakz	0:a04710facbb6	1964	#define GPIO_LCKR_LCK9_Pos (9U)
hudakz	0:a04710facbb6	1965	#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	1966	#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /!< Port x Lock bit 9 /
hudakz	0:a04710facbb6	1967	#define GPIO_LCKR_LCK10_Pos (10U)
hudakz	0:a04710facbb6	1968	#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	1969	#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /!< Port x Lock bit 10 /
hudakz	0:a04710facbb6	1970	#define GPIO_LCKR_LCK11_Pos (11U)
hudakz	0:a04710facbb6	1971	#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	1972	#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /!< Port x Lock bit 11 /
hudakz	0:a04710facbb6	1973	#define GPIO_LCKR_LCK12_Pos (12U)
hudakz	0:a04710facbb6	1974	#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	1975	#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /!< Port x Lock bit 12 /
hudakz	0:a04710facbb6	1976	#define GPIO_LCKR_LCK13_Pos (13U)
hudakz	0:a04710facbb6	1977	#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	1978	#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /!< Port x Lock bit 13 /
hudakz	0:a04710facbb6	1979	#define GPIO_LCKR_LCK14_Pos (14U)
hudakz	0:a04710facbb6	1980	#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	1981	#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /!< Port x Lock bit 14 /
hudakz	0:a04710facbb6	1982	#define GPIO_LCKR_LCK15_Pos (15U)
hudakz	0:a04710facbb6	1983	#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	1984	#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /!< Port x Lock bit 15 /
hudakz	0:a04710facbb6	1985	#define GPIO_LCKR_LCKK_Pos (16U)
hudakz	0:a04710facbb6	1986	#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	1987	#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /!< Lock key /
hudakz	0:a04710facbb6	1988
hudakz	0:a04710facbb6	1989	/----------------------------------------------------------------------------/
hudakz	0:a04710facbb6	1990
hudakz	0:a04710facbb6	1991	/**************** Bit definition for AFIO_EVCR register *****************/
hudakz	0:a04710facbb6	1992	#define AFIO_EVCR_PIN_Pos (0U)
hudakz	0:a04710facbb6	1993	#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	1994	#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /!< PIN[3:0] bits (Pin selection) /
hudakz	0:a04710facbb6	1995	#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	1996	#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	1997	#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	1998	#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	1999
hudakz	0:a04710facbb6	2000	/!< PIN configuration /
hudakz	0:a04710facbb6	2001	#define AFIO_EVCR_PIN_PX0 0x00000000U /!< Pin 0 selected /
hudakz	0:a04710facbb6	2002	#define AFIO_EVCR_PIN_PX1_Pos (0U)
hudakz	0:a04710facbb6	2003	#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	2004	#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /!< Pin 1 selected /
hudakz	0:a04710facbb6	2005	#define AFIO_EVCR_PIN_PX2_Pos (1U)
hudakz	0:a04710facbb6	2006	#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	2007	#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /!< Pin 2 selected /
hudakz	0:a04710facbb6	2008	#define AFIO_EVCR_PIN_PX3_Pos (0U)
hudakz	0:a04710facbb6	2009	#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /!< 0x00000003 /
hudakz	0:a04710facbb6	2010	#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /!< Pin 3 selected /
hudakz	0:a04710facbb6	2011	#define AFIO_EVCR_PIN_PX4_Pos (2U)
hudakz	0:a04710facbb6	2012	#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	2013	#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /!< Pin 4 selected /
hudakz	0:a04710facbb6	2014	#define AFIO_EVCR_PIN_PX5_Pos (0U)
hudakz	0:a04710facbb6	2015	#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /!< 0x00000005 /
hudakz	0:a04710facbb6	2016	#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /!< Pin 5 selected /
hudakz	0:a04710facbb6	2017	#define AFIO_EVCR_PIN_PX6_Pos (1U)
hudakz	0:a04710facbb6	2018	#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /!< 0x00000006 /
hudakz	0:a04710facbb6	2019	#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /!< Pin 6 selected /
hudakz	0:a04710facbb6	2020	#define AFIO_EVCR_PIN_PX7_Pos (0U)
hudakz	0:a04710facbb6	2021	#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /!< 0x00000007 /
hudakz	0:a04710facbb6	2022	#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /!< Pin 7 selected /
hudakz	0:a04710facbb6	2023	#define AFIO_EVCR_PIN_PX8_Pos (3U)
hudakz	0:a04710facbb6	2024	#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	2025	#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /!< Pin 8 selected /
hudakz	0:a04710facbb6	2026	#define AFIO_EVCR_PIN_PX9_Pos (0U)
hudakz	0:a04710facbb6	2027	#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /!< 0x00000009 /
hudakz	0:a04710facbb6	2028	#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /!< Pin 9 selected /
hudakz	0:a04710facbb6	2029	#define AFIO_EVCR_PIN_PX10_Pos (1U)
hudakz	0:a04710facbb6	2030	#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /!< 0x0000000A /
hudakz	0:a04710facbb6	2031	#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /!< Pin 10 selected /
hudakz	0:a04710facbb6	2032	#define AFIO_EVCR_PIN_PX11_Pos (0U)
hudakz	0:a04710facbb6	2033	#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /!< 0x0000000B /
hudakz	0:a04710facbb6	2034	#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /!< Pin 11 selected /
hudakz	0:a04710facbb6	2035	#define AFIO_EVCR_PIN_PX12_Pos (2U)
hudakz	0:a04710facbb6	2036	#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /!< 0x0000000C /
hudakz	0:a04710facbb6	2037	#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /!< Pin 12 selected /
hudakz	0:a04710facbb6	2038	#define AFIO_EVCR_PIN_PX13_Pos (0U)
hudakz	0:a04710facbb6	2039	#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /!< 0x0000000D /
hudakz	0:a04710facbb6	2040	#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /!< Pin 13 selected /
hudakz	0:a04710facbb6	2041	#define AFIO_EVCR_PIN_PX14_Pos (1U)
hudakz	0:a04710facbb6	2042	#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /!< 0x0000000E /
hudakz	0:a04710facbb6	2043	#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /!< Pin 14 selected /
hudakz	0:a04710facbb6	2044	#define AFIO_EVCR_PIN_PX15_Pos (0U)
hudakz	0:a04710facbb6	2045	#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	2046	#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /!< Pin 15 selected /
hudakz	0:a04710facbb6	2047
hudakz	0:a04710facbb6	2048	#define AFIO_EVCR_PORT_Pos (4U)
hudakz	0:a04710facbb6	2049	#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /!< 0x00000070 /
hudakz	0:a04710facbb6	2050	#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /!< PORT[2:0] bits (Port selection) /
hudakz	0:a04710facbb6	2051	#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	2052	#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	2053	#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	2054
hudakz	0:a04710facbb6	2055	/!< PORT configuration /
hudakz	0:a04710facbb6	2056	#define AFIO_EVCR_PORT_PA 0x00000000 /!< Port A selected /
hudakz	0:a04710facbb6	2057	#define AFIO_EVCR_PORT_PB_Pos (4U)
hudakz	0:a04710facbb6	2058	#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	2059	#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /!< Port B selected /
hudakz	0:a04710facbb6	2060	#define AFIO_EVCR_PORT_PC_Pos (5U)
hudakz	0:a04710facbb6	2061	#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	2062	#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /!< Port C selected /
hudakz	0:a04710facbb6	2063	#define AFIO_EVCR_PORT_PD_Pos (4U)
hudakz	0:a04710facbb6	2064	#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /!< 0x00000030 /
hudakz	0:a04710facbb6	2065	#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /!< Port D selected /
hudakz	0:a04710facbb6	2066	#define AFIO_EVCR_PORT_PE_Pos (6U)
hudakz	0:a04710facbb6	2067	#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	2068	#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /!< Port E selected /
hudakz	0:a04710facbb6	2069
hudakz	0:a04710facbb6	2070	#define AFIO_EVCR_EVOE_Pos (7U)
hudakz	0:a04710facbb6	2071	#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	2072	#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /!< Event Output Enable /
hudakz	0:a04710facbb6	2073
hudakz	0:a04710facbb6	2074	/**************** Bit definition for AFIO_MAPR register *****************/
hudakz	0:a04710facbb6	2075	#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
hudakz	0:a04710facbb6	2076	#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	2077	#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /!< SPI1 remapping /
hudakz	0:a04710facbb6	2078	#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
hudakz	0:a04710facbb6	2079	#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	2080	#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /!< I2C1 remapping /
hudakz	0:a04710facbb6	2081	#define AFIO_MAPR_USART1_REMAP_Pos (2U)
hudakz	0:a04710facbb6	2082	#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	2083	#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /!< USART1 remapping /
hudakz	0:a04710facbb6	2084	#define AFIO_MAPR_USART2_REMAP_Pos (3U)
hudakz	0:a04710facbb6	2085	#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	2086	#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /!< USART2 remapping /
hudakz	0:a04710facbb6	2087
hudakz	0:a04710facbb6	2088	#define AFIO_MAPR_USART3_REMAP_Pos (4U)
hudakz	0:a04710facbb6	2089	#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /!< 0x00000030 /
hudakz	0:a04710facbb6	2090	#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /!< USART3_REMAP[1:0] bits (USART3 remapping) /
hudakz	0:a04710facbb6	2091	#define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	2092	#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	2093
hudakz	0:a04710facbb6	2094	/* USART3_REMAP configuration */
hudakz	0:a04710facbb6	2095	#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) /
hudakz	0:a04710facbb6	2096	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
hudakz	0:a04710facbb6	2097	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	2098	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) /
hudakz	0:a04710facbb6	2099	#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
hudakz	0:a04710facbb6	2100	#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /!< 0x00000030 /
hudakz	0:a04710facbb6	2101	#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) /
hudakz	0:a04710facbb6	2102
hudakz	0:a04710facbb6	2103	#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
hudakz	0:a04710facbb6	2104	#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /!< 0x000000C0 /
hudakz	0:a04710facbb6	2105	#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /!< TIM1_REMAP[1:0] bits (TIM1 remapping) /
hudakz	0:a04710facbb6	2106	#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	2107	#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	2108
hudakz	0:a04710facbb6	2109	/!< TIM1_REMAP configuration /
hudakz	0:a04710facbb6	2110	#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) /
hudakz	0:a04710facbb6	2111	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
hudakz	0:a04710facbb6	2112	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	2113	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) /
hudakz	0:a04710facbb6	2114	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
hudakz	0:a04710facbb6	2115	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /!< 0x000000C0 /
hudakz	0:a04710facbb6	2116	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) /
hudakz	0:a04710facbb6	2117
hudakz	0:a04710facbb6	2118	#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
hudakz	0:a04710facbb6	2119	#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /!< 0x00000300 /
hudakz	0:a04710facbb6	2120	#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /!< TIM2_REMAP[1:0] bits (TIM2 remapping) /
hudakz	0:a04710facbb6	2121	#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	2122	#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	2123
hudakz	0:a04710facbb6	2124	/!< TIM2_REMAP configuration /
hudakz	0:a04710facbb6	2125	#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) /
hudakz	0:a04710facbb6	2126	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
hudakz	0:a04710facbb6	2127	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	2128	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) /
hudakz	0:a04710facbb6	2129	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
hudakz	0:a04710facbb6	2130	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	2131	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) /
hudakz	0:a04710facbb6	2132	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
hudakz	0:a04710facbb6	2133	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /!< 0x00000300 /
hudakz	0:a04710facbb6	2134	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) /
hudakz	0:a04710facbb6	2135
hudakz	0:a04710facbb6	2136	#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
hudakz	0:a04710facbb6	2137	#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /!< 0x00000C00 /
hudakz	0:a04710facbb6	2138	#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /!< TIM3_REMAP[1:0] bits (TIM3 remapping) /
hudakz	0:a04710facbb6	2139	#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	2140	#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	2141
hudakz	0:a04710facbb6	2142	/!< TIM3_REMAP configuration /
hudakz	0:a04710facbb6	2143	#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) /
hudakz	0:a04710facbb6	2144	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
hudakz	0:a04710facbb6	2145	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	2146	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) /
hudakz	0:a04710facbb6	2147	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
hudakz	0:a04710facbb6	2148	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /!< 0x00000C00 /
hudakz	0:a04710facbb6	2149	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) /
hudakz	0:a04710facbb6	2150
hudakz	0:a04710facbb6	2151	#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
hudakz	0:a04710facbb6	2152	#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	2153	#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /!< TIM4_REMAP bit (TIM4 remapping) /
hudakz	0:a04710facbb6	2154
hudakz	0:a04710facbb6	2155	#define AFIO_MAPR_CAN_REMAP_Pos (13U)
hudakz	0:a04710facbb6	2156	#define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /!< 0x00006000 /
hudakz	0:a04710facbb6	2157	#define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) /
hudakz	0:a04710facbb6	2158	#define AFIO_MAPR_CAN_REMAP_0 (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	2159	#define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	2160
hudakz	0:a04710facbb6	2161	/!< CAN_REMAP configuration /
hudakz	0:a04710facbb6	2162	#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /!< CANRX mapped to PA11, CANTX mapped to PA12 /
hudakz	0:a04710facbb6	2163	#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
hudakz	0:a04710facbb6	2164	#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	2165	#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /!< CANRX mapped to PB8, CANTX mapped to PB9 /
hudakz	0:a04710facbb6	2166	#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U)
hudakz	0:a04710facbb6	2167	#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /!< 0x00006000 /
hudakz	0:a04710facbb6	2168	#define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /!< CANRX mapped to PD0, CANTX mapped to PD1 /
hudakz	0:a04710facbb6	2169
hudakz	0:a04710facbb6	2170	#define AFIO_MAPR_PD01_REMAP_Pos (15U)
hudakz	0:a04710facbb6	2171	#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	2172	#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT /
hudakz	0:a04710facbb6	2173
hudakz	0:a04710facbb6	2174	/!< SWJ_CFG configuration /
hudakz	0:a04710facbb6	2175	#define AFIO_MAPR_SWJ_CFG_Pos (24U)
hudakz	0:a04710facbb6	2176	#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /!< 0x07000000 /
hudakz	0:a04710facbb6	2177	#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) /
hudakz	0:a04710facbb6	2178	#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	2179	#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	2180	#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	2181
hudakz	0:a04710facbb6	2182	#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /!< Full SWJ (JTAG-DP + SW-DP) : Reset State /
hudakz	0:a04710facbb6	2183	#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
hudakz	0:a04710facbb6	2184	#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	2185	#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST /
hudakz	0:a04710facbb6	2186	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
hudakz	0:a04710facbb6	2187	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	2188	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /!< JTAG-DP Disabled and SW-DP Enabled /
hudakz	0:a04710facbb6	2189	#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
hudakz	0:a04710facbb6	2190	#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	2191	#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /!< JTAG-DP Disabled and SW-DP Disabled /
hudakz	0:a04710facbb6	2192
hudakz	0:a04710facbb6	2193
hudakz	0:a04710facbb6	2194	/*************** Bit definition for AFIO_EXTICR1 register ***************/
hudakz	0:a04710facbb6	2195	#define AFIO_EXTICR1_EXTI0_Pos (0U)
hudakz	0:a04710facbb6	2196	#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	2197	#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /!< EXTI 0 configuration /
hudakz	0:a04710facbb6	2198	#define AFIO_EXTICR1_EXTI1_Pos (4U)
hudakz	0:a04710facbb6	2199	#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /!< 0x000000F0 /
hudakz	0:a04710facbb6	2200	#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /!< EXTI 1 configuration /
hudakz	0:a04710facbb6	2201	#define AFIO_EXTICR1_EXTI2_Pos (8U)
hudakz	0:a04710facbb6	2202	#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /!< 0x00000F00 /
hudakz	0:a04710facbb6	2203	#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /!< EXTI 2 configuration /
hudakz	0:a04710facbb6	2204	#define AFIO_EXTICR1_EXTI3_Pos (12U)
hudakz	0:a04710facbb6	2205	#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /!< 0x0000F000 /
hudakz	0:a04710facbb6	2206	#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /!< EXTI 3 configuration /
hudakz	0:a04710facbb6	2207
hudakz	0:a04710facbb6	2208	/!< EXTI0 configuration /
hudakz	0:a04710facbb6	2209	#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /!< PA[0] pin /
hudakz	0:a04710facbb6	2210	#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
hudakz	0:a04710facbb6	2211	#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	2212	#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /!< PB[0] pin /
hudakz	0:a04710facbb6	2213	#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
hudakz	0:a04710facbb6	2214	#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	2215	#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /!< PC[0] pin /
hudakz	0:a04710facbb6	2216	#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
hudakz	0:a04710facbb6	2217	#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /!< 0x00000003 /
hudakz	0:a04710facbb6	2218	#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /!< PD[0] pin /
hudakz	0:a04710facbb6	2219	#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
hudakz	0:a04710facbb6	2220	#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	2221	#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /!< PE[0] pin /
hudakz	0:a04710facbb6	2222	#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
hudakz	0:a04710facbb6	2223	#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /!< 0x00000005 /
hudakz	0:a04710facbb6	2224	#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /!< PF[0] pin /
hudakz	0:a04710facbb6	2225	#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
hudakz	0:a04710facbb6	2226	#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /!< 0x00000006 /
hudakz	0:a04710facbb6	2227	#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /!< PG[0] pin /
hudakz	0:a04710facbb6	2228
hudakz	0:a04710facbb6	2229	/!< EXTI1 configuration /
hudakz	0:a04710facbb6	2230	#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /!< PA[1] pin /
hudakz	0:a04710facbb6	2231	#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
hudakz	0:a04710facbb6	2232	#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	2233	#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /!< PB[1] pin /
hudakz	0:a04710facbb6	2234	#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
hudakz	0:a04710facbb6	2235	#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	2236	#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /!< PC[1] pin /
hudakz	0:a04710facbb6	2237	#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
hudakz	0:a04710facbb6	2238	#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /!< 0x00000030 /
hudakz	0:a04710facbb6	2239	#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /!< PD[1] pin /
hudakz	0:a04710facbb6	2240	#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
hudakz	0:a04710facbb6	2241	#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	2242	#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /!< PE[1] pin /
hudakz	0:a04710facbb6	2243	#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
hudakz	0:a04710facbb6	2244	#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /!< 0x00000050 /
hudakz	0:a04710facbb6	2245	#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /!< PF[1] pin /
hudakz	0:a04710facbb6	2246	#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
hudakz	0:a04710facbb6	2247	#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /!< 0x00000060 /
hudakz	0:a04710facbb6	2248	#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /!< PG[1] pin /
hudakz	0:a04710facbb6	2249
hudakz	0:a04710facbb6	2250	/!< EXTI2 configuration /
hudakz	0:a04710facbb6	2251	#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /!< PA[2] pin /
hudakz	0:a04710facbb6	2252	#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
hudakz	0:a04710facbb6	2253	#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	2254	#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /!< PB[2] pin /
hudakz	0:a04710facbb6	2255	#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
hudakz	0:a04710facbb6	2256	#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	2257	#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /!< PC[2] pin /
hudakz	0:a04710facbb6	2258	#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
hudakz	0:a04710facbb6	2259	#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /!< 0x00000300 /
hudakz	0:a04710facbb6	2260	#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /!< PD[2] pin /
hudakz	0:a04710facbb6	2261	#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
hudakz	0:a04710facbb6	2262	#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	2263	#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /!< PE[2] pin /
hudakz	0:a04710facbb6	2264	#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
hudakz	0:a04710facbb6	2265	#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /!< 0x00000500 /
hudakz	0:a04710facbb6	2266	#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /!< PF[2] pin /
hudakz	0:a04710facbb6	2267	#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
hudakz	0:a04710facbb6	2268	#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /!< 0x00000600 /
hudakz	0:a04710facbb6	2269	#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /!< PG[2] pin /
hudakz	0:a04710facbb6	2270
hudakz	0:a04710facbb6	2271	/!< EXTI3 configuration /
hudakz	0:a04710facbb6	2272	#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /!< PA[3] pin /
hudakz	0:a04710facbb6	2273	#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
hudakz	0:a04710facbb6	2274	#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	2275	#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /!< PB[3] pin /
hudakz	0:a04710facbb6	2276	#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
hudakz	0:a04710facbb6	2277	#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	2278	#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /!< PC[3] pin /
hudakz	0:a04710facbb6	2279	#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
hudakz	0:a04710facbb6	2280	#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /!< 0x00003000 /
hudakz	0:a04710facbb6	2281	#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /!< PD[3] pin /
hudakz	0:a04710facbb6	2282	#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
hudakz	0:a04710facbb6	2283	#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	2284	#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /!< PE[3] pin /
hudakz	0:a04710facbb6	2285	#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
hudakz	0:a04710facbb6	2286	#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /!< 0x00005000 /
hudakz	0:a04710facbb6	2287	#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /!< PF[3] pin /
hudakz	0:a04710facbb6	2288	#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
hudakz	0:a04710facbb6	2289	#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /!< 0x00006000 /
hudakz	0:a04710facbb6	2290	#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /!< PG[3] pin /
hudakz	0:a04710facbb6	2291
hudakz	0:a04710facbb6	2292	/*************** Bit definition for AFIO_EXTICR2 register ***************/
hudakz	0:a04710facbb6	2293	#define AFIO_EXTICR2_EXTI4_Pos (0U)
hudakz	0:a04710facbb6	2294	#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	2295	#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /!< EXTI 4 configuration /
hudakz	0:a04710facbb6	2296	#define AFIO_EXTICR2_EXTI5_Pos (4U)
hudakz	0:a04710facbb6	2297	#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /!< 0x000000F0 /
hudakz	0:a04710facbb6	2298	#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /!< EXTI 5 configuration /
hudakz	0:a04710facbb6	2299	#define AFIO_EXTICR2_EXTI6_Pos (8U)
hudakz	0:a04710facbb6	2300	#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /!< 0x00000F00 /
hudakz	0:a04710facbb6	2301	#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /!< EXTI 6 configuration /
hudakz	0:a04710facbb6	2302	#define AFIO_EXTICR2_EXTI7_Pos (12U)
hudakz	0:a04710facbb6	2303	#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /!< 0x0000F000 /
hudakz	0:a04710facbb6	2304	#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /!< EXTI 7 configuration /
hudakz	0:a04710facbb6	2305
hudakz	0:a04710facbb6	2306	/!< EXTI4 configuration /
hudakz	0:a04710facbb6	2307	#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /!< PA[4] pin /
hudakz	0:a04710facbb6	2308	#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
hudakz	0:a04710facbb6	2309	#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	2310	#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /!< PB[4] pin /
hudakz	0:a04710facbb6	2311	#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
hudakz	0:a04710facbb6	2312	#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	2313	#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /!< PC[4] pin /
hudakz	0:a04710facbb6	2314	#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
hudakz	0:a04710facbb6	2315	#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /!< 0x00000003 /
hudakz	0:a04710facbb6	2316	#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /!< PD[4] pin /
hudakz	0:a04710facbb6	2317	#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
hudakz	0:a04710facbb6	2318	#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	2319	#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /!< PE[4] pin /
hudakz	0:a04710facbb6	2320	#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
hudakz	0:a04710facbb6	2321	#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /!< 0x00000005 /
hudakz	0:a04710facbb6	2322	#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /!< PF[4] pin /
hudakz	0:a04710facbb6	2323	#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
hudakz	0:a04710facbb6	2324	#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /!< 0x00000006 /
hudakz	0:a04710facbb6	2325	#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /!< PG[4] pin /
hudakz	0:a04710facbb6	2326
hudakz	0:a04710facbb6	2327	/* EXTI5 configuration */
hudakz	0:a04710facbb6	2328	#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /!< PA[5] pin /
hudakz	0:a04710facbb6	2329	#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
hudakz	0:a04710facbb6	2330	#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	2331	#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /!< PB[5] pin /
hudakz	0:a04710facbb6	2332	#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
hudakz	0:a04710facbb6	2333	#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	2334	#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /!< PC[5] pin /
hudakz	0:a04710facbb6	2335	#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
hudakz	0:a04710facbb6	2336	#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /!< 0x00000030 /
hudakz	0:a04710facbb6	2337	#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /!< PD[5] pin /
hudakz	0:a04710facbb6	2338	#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
hudakz	0:a04710facbb6	2339	#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	2340	#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /!< PE[5] pin /
hudakz	0:a04710facbb6	2341	#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
hudakz	0:a04710facbb6	2342	#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /!< 0x00000050 /
hudakz	0:a04710facbb6	2343	#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /!< PF[5] pin /
hudakz	0:a04710facbb6	2344	#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
hudakz	0:a04710facbb6	2345	#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /!< 0x00000060 /
hudakz	0:a04710facbb6	2346	#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /!< PG[5] pin /
hudakz	0:a04710facbb6	2347
hudakz	0:a04710facbb6	2348	/!< EXTI6 configuration /
hudakz	0:a04710facbb6	2349	#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /!< PA[6] pin /
hudakz	0:a04710facbb6	2350	#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
hudakz	0:a04710facbb6	2351	#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	2352	#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /!< PB[6] pin /
hudakz	0:a04710facbb6	2353	#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
hudakz	0:a04710facbb6	2354	#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	2355	#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /!< PC[6] pin /
hudakz	0:a04710facbb6	2356	#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
hudakz	0:a04710facbb6	2357	#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /!< 0x00000300 /
hudakz	0:a04710facbb6	2358	#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /!< PD[6] pin /
hudakz	0:a04710facbb6	2359	#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
hudakz	0:a04710facbb6	2360	#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	2361	#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /!< PE[6] pin /
hudakz	0:a04710facbb6	2362	#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
hudakz	0:a04710facbb6	2363	#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /!< 0x00000500 /
hudakz	0:a04710facbb6	2364	#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /!< PF[6] pin /
hudakz	0:a04710facbb6	2365	#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
hudakz	0:a04710facbb6	2366	#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /!< 0x00000600 /
hudakz	0:a04710facbb6	2367	#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /!< PG[6] pin /
hudakz	0:a04710facbb6	2368
hudakz	0:a04710facbb6	2369	/!< EXTI7 configuration /
hudakz	0:a04710facbb6	2370	#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /!< PA[7] pin /
hudakz	0:a04710facbb6	2371	#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
hudakz	0:a04710facbb6	2372	#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	2373	#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /!< PB[7] pin /
hudakz	0:a04710facbb6	2374	#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
hudakz	0:a04710facbb6	2375	#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	2376	#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /!< PC[7] pin /
hudakz	0:a04710facbb6	2377	#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
hudakz	0:a04710facbb6	2378	#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /!< 0x00003000 /
hudakz	0:a04710facbb6	2379	#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /!< PD[7] pin /
hudakz	0:a04710facbb6	2380	#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
hudakz	0:a04710facbb6	2381	#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	2382	#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /!< PE[7] pin /
hudakz	0:a04710facbb6	2383	#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
hudakz	0:a04710facbb6	2384	#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /!< 0x00005000 /
hudakz	0:a04710facbb6	2385	#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /!< PF[7] pin /
hudakz	0:a04710facbb6	2386	#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
hudakz	0:a04710facbb6	2387	#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /!< 0x00006000 /
hudakz	0:a04710facbb6	2388	#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /!< PG[7] pin /
hudakz	0:a04710facbb6	2389
hudakz	0:a04710facbb6	2390	/*************** Bit definition for AFIO_EXTICR3 register ***************/
hudakz	0:a04710facbb6	2391	#define AFIO_EXTICR3_EXTI8_Pos (0U)
hudakz	0:a04710facbb6	2392	#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	2393	#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /!< EXTI 8 configuration /
hudakz	0:a04710facbb6	2394	#define AFIO_EXTICR3_EXTI9_Pos (4U)
hudakz	0:a04710facbb6	2395	#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /!< 0x000000F0 /
hudakz	0:a04710facbb6	2396	#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /!< EXTI 9 configuration /
hudakz	0:a04710facbb6	2397	#define AFIO_EXTICR3_EXTI10_Pos (8U)
hudakz	0:a04710facbb6	2398	#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /!< 0x00000F00 /
hudakz	0:a04710facbb6	2399	#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /!< EXTI 10 configuration /
hudakz	0:a04710facbb6	2400	#define AFIO_EXTICR3_EXTI11_Pos (12U)
hudakz	0:a04710facbb6	2401	#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /!< 0x0000F000 /
hudakz	0:a04710facbb6	2402	#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /!< EXTI 11 configuration /
hudakz	0:a04710facbb6	2403
hudakz	0:a04710facbb6	2404	/!< EXTI8 configuration /
hudakz	0:a04710facbb6	2405	#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /!< PA[8] pin /
hudakz	0:a04710facbb6	2406	#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
hudakz	0:a04710facbb6	2407	#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	2408	#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /!< PB[8] pin /
hudakz	0:a04710facbb6	2409	#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
hudakz	0:a04710facbb6	2410	#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	2411	#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /!< PC[8] pin /
hudakz	0:a04710facbb6	2412	#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
hudakz	0:a04710facbb6	2413	#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /!< 0x00000003 /
hudakz	0:a04710facbb6	2414	#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /!< PD[8] pin /
hudakz	0:a04710facbb6	2415	#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
hudakz	0:a04710facbb6	2416	#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	2417	#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /!< PE[8] pin /
hudakz	0:a04710facbb6	2418	#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
hudakz	0:a04710facbb6	2419	#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /!< 0x00000005 /
hudakz	0:a04710facbb6	2420	#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /!< PF[8] pin /
hudakz	0:a04710facbb6	2421	#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
hudakz	0:a04710facbb6	2422	#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /!< 0x00000006 /
hudakz	0:a04710facbb6	2423	#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /!< PG[8] pin /
hudakz	0:a04710facbb6	2424
hudakz	0:a04710facbb6	2425	/!< EXTI9 configuration /
hudakz	0:a04710facbb6	2426	#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /!< PA[9] pin /
hudakz	0:a04710facbb6	2427	#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
hudakz	0:a04710facbb6	2428	#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	2429	#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /!< PB[9] pin /
hudakz	0:a04710facbb6	2430	#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
hudakz	0:a04710facbb6	2431	#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	2432	#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /!< PC[9] pin /
hudakz	0:a04710facbb6	2433	#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
hudakz	0:a04710facbb6	2434	#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /!< 0x00000030 /
hudakz	0:a04710facbb6	2435	#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /!< PD[9] pin /
hudakz	0:a04710facbb6	2436	#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
hudakz	0:a04710facbb6	2437	#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	2438	#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /!< PE[9] pin /
hudakz	0:a04710facbb6	2439	#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
hudakz	0:a04710facbb6	2440	#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /!< 0x00000050 /
hudakz	0:a04710facbb6	2441	#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /!< PF[9] pin /
hudakz	0:a04710facbb6	2442	#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
hudakz	0:a04710facbb6	2443	#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /!< 0x00000060 /
hudakz	0:a04710facbb6	2444	#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /!< PG[9] pin /
hudakz	0:a04710facbb6	2445
hudakz	0:a04710facbb6	2446	/!< EXTI10 configuration /
hudakz	0:a04710facbb6	2447	#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /!< PA[10] pin /
hudakz	0:a04710facbb6	2448	#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
hudakz	0:a04710facbb6	2449	#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	2450	#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /!< PB[10] pin /
hudakz	0:a04710facbb6	2451	#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
hudakz	0:a04710facbb6	2452	#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	2453	#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /!< PC[10] pin /
hudakz	0:a04710facbb6	2454	#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
hudakz	0:a04710facbb6	2455	#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /!< 0x00000300 /
hudakz	0:a04710facbb6	2456	#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /!< PD[10] pin /
hudakz	0:a04710facbb6	2457	#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
hudakz	0:a04710facbb6	2458	#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	2459	#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /!< PE[10] pin /
hudakz	0:a04710facbb6	2460	#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
hudakz	0:a04710facbb6	2461	#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /!< 0x00000500 /
hudakz	0:a04710facbb6	2462	#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /!< PF[10] pin /
hudakz	0:a04710facbb6	2463	#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
hudakz	0:a04710facbb6	2464	#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /!< 0x00000600 /
hudakz	0:a04710facbb6	2465	#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /!< PG[10] pin /
hudakz	0:a04710facbb6	2466
hudakz	0:a04710facbb6	2467	/!< EXTI11 configuration /
hudakz	0:a04710facbb6	2468	#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /!< PA[11] pin /
hudakz	0:a04710facbb6	2469	#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
hudakz	0:a04710facbb6	2470	#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	2471	#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /!< PB[11] pin /
hudakz	0:a04710facbb6	2472	#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
hudakz	0:a04710facbb6	2473	#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	2474	#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /!< PC[11] pin /
hudakz	0:a04710facbb6	2475	#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
hudakz	0:a04710facbb6	2476	#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /!< 0x00003000 /
hudakz	0:a04710facbb6	2477	#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /!< PD[11] pin /
hudakz	0:a04710facbb6	2478	#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
hudakz	0:a04710facbb6	2479	#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	2480	#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /!< PE[11] pin /
hudakz	0:a04710facbb6	2481	#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
hudakz	0:a04710facbb6	2482	#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /!< 0x00005000 /
hudakz	0:a04710facbb6	2483	#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /!< PF[11] pin /
hudakz	0:a04710facbb6	2484	#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
hudakz	0:a04710facbb6	2485	#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /!< 0x00006000 /
hudakz	0:a04710facbb6	2486	#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /!< PG[11] pin /
hudakz	0:a04710facbb6	2487
hudakz	0:a04710facbb6	2488	/*************** Bit definition for AFIO_EXTICR4 register ***************/
hudakz	0:a04710facbb6	2489	#define AFIO_EXTICR4_EXTI12_Pos (0U)
hudakz	0:a04710facbb6	2490	#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	2491	#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /!< EXTI 12 configuration /
hudakz	0:a04710facbb6	2492	#define AFIO_EXTICR4_EXTI13_Pos (4U)
hudakz	0:a04710facbb6	2493	#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /!< 0x000000F0 /
hudakz	0:a04710facbb6	2494	#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /!< EXTI 13 configuration /
hudakz	0:a04710facbb6	2495	#define AFIO_EXTICR4_EXTI14_Pos (8U)
hudakz	0:a04710facbb6	2496	#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /!< 0x00000F00 /
hudakz	0:a04710facbb6	2497	#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /!< EXTI 14 configuration /
hudakz	0:a04710facbb6	2498	#define AFIO_EXTICR4_EXTI15_Pos (12U)
hudakz	0:a04710facbb6	2499	#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /!< 0x0000F000 /
hudakz	0:a04710facbb6	2500	#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /!< EXTI 15 configuration /
hudakz	0:a04710facbb6	2501
hudakz	0:a04710facbb6	2502	/* EXTI12 configuration */
hudakz	0:a04710facbb6	2503	#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /!< PA[12] pin /
hudakz	0:a04710facbb6	2504	#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
hudakz	0:a04710facbb6	2505	#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	2506	#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /!< PB[12] pin /
hudakz	0:a04710facbb6	2507	#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
hudakz	0:a04710facbb6	2508	#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	2509	#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /!< PC[12] pin /
hudakz	0:a04710facbb6	2510	#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
hudakz	0:a04710facbb6	2511	#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /!< 0x00000003 /
hudakz	0:a04710facbb6	2512	#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /!< PD[12] pin /
hudakz	0:a04710facbb6	2513	#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
hudakz	0:a04710facbb6	2514	#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	2515	#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /!< PE[12] pin /
hudakz	0:a04710facbb6	2516	#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
hudakz	0:a04710facbb6	2517	#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /!< 0x00000005 /
hudakz	0:a04710facbb6	2518	#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /!< PF[12] pin /
hudakz	0:a04710facbb6	2519	#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
hudakz	0:a04710facbb6	2520	#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /!< 0x00000006 /
hudakz	0:a04710facbb6	2521	#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /!< PG[12] pin /
hudakz	0:a04710facbb6	2522
hudakz	0:a04710facbb6	2523	/* EXTI13 configuration */
hudakz	0:a04710facbb6	2524	#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /!< PA[13] pin /
hudakz	0:a04710facbb6	2525	#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
hudakz	0:a04710facbb6	2526	#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	2527	#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /!< PB[13] pin /
hudakz	0:a04710facbb6	2528	#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
hudakz	0:a04710facbb6	2529	#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	2530	#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /!< PC[13] pin /
hudakz	0:a04710facbb6	2531	#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
hudakz	0:a04710facbb6	2532	#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /!< 0x00000030 /
hudakz	0:a04710facbb6	2533	#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /!< PD[13] pin /
hudakz	0:a04710facbb6	2534	#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
hudakz	0:a04710facbb6	2535	#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	2536	#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /!< PE[13] pin /
hudakz	0:a04710facbb6	2537	#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
hudakz	0:a04710facbb6	2538	#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /!< 0x00000050 /
hudakz	0:a04710facbb6	2539	#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /!< PF[13] pin /
hudakz	0:a04710facbb6	2540	#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
hudakz	0:a04710facbb6	2541	#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /!< 0x00000060 /
hudakz	0:a04710facbb6	2542	#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /!< PG[13] pin /
hudakz	0:a04710facbb6	2543
hudakz	0:a04710facbb6	2544	/!< EXTI14 configuration /
hudakz	0:a04710facbb6	2545	#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /!< PA[14] pin /
hudakz	0:a04710facbb6	2546	#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
hudakz	0:a04710facbb6	2547	#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	2548	#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /!< PB[14] pin /
hudakz	0:a04710facbb6	2549	#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
hudakz	0:a04710facbb6	2550	#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	2551	#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /!< PC[14] pin /
hudakz	0:a04710facbb6	2552	#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
hudakz	0:a04710facbb6	2553	#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /!< 0x00000300 /
hudakz	0:a04710facbb6	2554	#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /!< PD[14] pin /
hudakz	0:a04710facbb6	2555	#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
hudakz	0:a04710facbb6	2556	#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	2557	#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /!< PE[14] pin /
hudakz	0:a04710facbb6	2558	#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
hudakz	0:a04710facbb6	2559	#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /!< 0x00000500 /
hudakz	0:a04710facbb6	2560	#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /!< PF[14] pin /
hudakz	0:a04710facbb6	2561	#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
hudakz	0:a04710facbb6	2562	#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /!< 0x00000600 /
hudakz	0:a04710facbb6	2563	#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /!< PG[14] pin /
hudakz	0:a04710facbb6	2564
hudakz	0:a04710facbb6	2565	/!< EXTI15 configuration /
hudakz	0:a04710facbb6	2566	#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /!< PA[15] pin /
hudakz	0:a04710facbb6	2567	#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
hudakz	0:a04710facbb6	2568	#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	2569	#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /!< PB[15] pin /
hudakz	0:a04710facbb6	2570	#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
hudakz	0:a04710facbb6	2571	#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	2572	#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /!< PC[15] pin /
hudakz	0:a04710facbb6	2573	#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
hudakz	0:a04710facbb6	2574	#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /!< 0x00003000 /
hudakz	0:a04710facbb6	2575	#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /!< PD[15] pin /
hudakz	0:a04710facbb6	2576	#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
hudakz	0:a04710facbb6	2577	#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	2578	#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /!< PE[15] pin /
hudakz	0:a04710facbb6	2579	#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
hudakz	0:a04710facbb6	2580	#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /!< 0x00005000 /
hudakz	0:a04710facbb6	2581	#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /!< PF[15] pin /
hudakz	0:a04710facbb6	2582	#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
hudakz	0:a04710facbb6	2583	#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /!< 0x00006000 /
hudakz	0:a04710facbb6	2584	#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /!< PG[15] pin /
hudakz	0:a04710facbb6	2585
hudakz	0:a04710facbb6	2586	/**************** Bit definition for AFIO_MAPR2 register ****************/
hudakz	0:a04710facbb6	2587
hudakz	0:a04710facbb6	2588
hudakz	0:a04710facbb6	2589
hudakz	0:a04710facbb6	2590	/******************************************************************************/
hudakz	0:a04710facbb6	2591	/* */
hudakz	0:a04710facbb6	2592	/* External Interrupt/Event Controller */
hudakz	0:a04710facbb6	2593	/* */
hudakz	0:a04710facbb6	2594	/******************************************************************************/
hudakz	0:a04710facbb6	2595
hudakz	0:a04710facbb6	2596	/***************** Bit definition for EXTI_IMR register *****************/
hudakz	0:a04710facbb6	2597	#define EXTI_IMR_MR0_Pos (0U)
hudakz	0:a04710facbb6	2598	#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	2599	#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /!< Interrupt Mask on line 0 /
hudakz	0:a04710facbb6	2600	#define EXTI_IMR_MR1_Pos (1U)
hudakz	0:a04710facbb6	2601	#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	2602	#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /!< Interrupt Mask on line 1 /
hudakz	0:a04710facbb6	2603	#define EXTI_IMR_MR2_Pos (2U)
hudakz	0:a04710facbb6	2604	#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	2605	#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /!< Interrupt Mask on line 2 /
hudakz	0:a04710facbb6	2606	#define EXTI_IMR_MR3_Pos (3U)
hudakz	0:a04710facbb6	2607	#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	2608	#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /!< Interrupt Mask on line 3 /
hudakz	0:a04710facbb6	2609	#define EXTI_IMR_MR4_Pos (4U)
hudakz	0:a04710facbb6	2610	#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	2611	#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /!< Interrupt Mask on line 4 /
hudakz	0:a04710facbb6	2612	#define EXTI_IMR_MR5_Pos (5U)
hudakz	0:a04710facbb6	2613	#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	2614	#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /!< Interrupt Mask on line 5 /
hudakz	0:a04710facbb6	2615	#define EXTI_IMR_MR6_Pos (6U)
hudakz	0:a04710facbb6	2616	#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	2617	#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /!< Interrupt Mask on line 6 /
hudakz	0:a04710facbb6	2618	#define EXTI_IMR_MR7_Pos (7U)
hudakz	0:a04710facbb6	2619	#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	2620	#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /!< Interrupt Mask on line 7 /
hudakz	0:a04710facbb6	2621	#define EXTI_IMR_MR8_Pos (8U)
hudakz	0:a04710facbb6	2622	#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	2623	#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /!< Interrupt Mask on line 8 /
hudakz	0:a04710facbb6	2624	#define EXTI_IMR_MR9_Pos (9U)
hudakz	0:a04710facbb6	2625	#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	2626	#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /!< Interrupt Mask on line 9 /
hudakz	0:a04710facbb6	2627	#define EXTI_IMR_MR10_Pos (10U)
hudakz	0:a04710facbb6	2628	#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	2629	#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /!< Interrupt Mask on line 10 /
hudakz	0:a04710facbb6	2630	#define EXTI_IMR_MR11_Pos (11U)
hudakz	0:a04710facbb6	2631	#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	2632	#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /!< Interrupt Mask on line 11 /
hudakz	0:a04710facbb6	2633	#define EXTI_IMR_MR12_Pos (12U)
hudakz	0:a04710facbb6	2634	#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	2635	#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /!< Interrupt Mask on line 12 /
hudakz	0:a04710facbb6	2636	#define EXTI_IMR_MR13_Pos (13U)
hudakz	0:a04710facbb6	2637	#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	2638	#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /!< Interrupt Mask on line 13 /
hudakz	0:a04710facbb6	2639	#define EXTI_IMR_MR14_Pos (14U)
hudakz	0:a04710facbb6	2640	#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	2641	#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /!< Interrupt Mask on line 14 /
hudakz	0:a04710facbb6	2642	#define EXTI_IMR_MR15_Pos (15U)
hudakz	0:a04710facbb6	2643	#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	2644	#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /!< Interrupt Mask on line 15 /
hudakz	0:a04710facbb6	2645	#define EXTI_IMR_MR16_Pos (16U)
hudakz	0:a04710facbb6	2646	#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	2647	#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /!< Interrupt Mask on line 16 /
hudakz	0:a04710facbb6	2648	#define EXTI_IMR_MR17_Pos (17U)
hudakz	0:a04710facbb6	2649	#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	2650	#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /!< Interrupt Mask on line 17 /
hudakz	0:a04710facbb6	2651	#define EXTI_IMR_MR18_Pos (18U)
hudakz	0:a04710facbb6	2652	#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	2653	#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /!< Interrupt Mask on line 18 /
hudakz	0:a04710facbb6	2654
hudakz	0:a04710facbb6	2655	/* References Defines */
hudakz	0:a04710facbb6	2656	#define EXTI_IMR_IM0 EXTI_IMR_MR0
hudakz	0:a04710facbb6	2657	#define EXTI_IMR_IM1 EXTI_IMR_MR1
hudakz	0:a04710facbb6	2658	#define EXTI_IMR_IM2 EXTI_IMR_MR2
hudakz	0:a04710facbb6	2659	#define EXTI_IMR_IM3 EXTI_IMR_MR3
hudakz	0:a04710facbb6	2660	#define EXTI_IMR_IM4 EXTI_IMR_MR4
hudakz	0:a04710facbb6	2661	#define EXTI_IMR_IM5 EXTI_IMR_MR5
hudakz	0:a04710facbb6	2662	#define EXTI_IMR_IM6 EXTI_IMR_MR6
hudakz	0:a04710facbb6	2663	#define EXTI_IMR_IM7 EXTI_IMR_MR7
hudakz	0:a04710facbb6	2664	#define EXTI_IMR_IM8 EXTI_IMR_MR8
hudakz	0:a04710facbb6	2665	#define EXTI_IMR_IM9 EXTI_IMR_MR9
hudakz	0:a04710facbb6	2666	#define EXTI_IMR_IM10 EXTI_IMR_MR10
hudakz	0:a04710facbb6	2667	#define EXTI_IMR_IM11 EXTI_IMR_MR11
hudakz	0:a04710facbb6	2668	#define EXTI_IMR_IM12 EXTI_IMR_MR12
hudakz	0:a04710facbb6	2669	#define EXTI_IMR_IM13 EXTI_IMR_MR13
hudakz	0:a04710facbb6	2670	#define EXTI_IMR_IM14 EXTI_IMR_MR14
hudakz	0:a04710facbb6	2671	#define EXTI_IMR_IM15 EXTI_IMR_MR15
hudakz	0:a04710facbb6	2672	#define EXTI_IMR_IM16 EXTI_IMR_MR16
hudakz	0:a04710facbb6	2673	#define EXTI_IMR_IM17 EXTI_IMR_MR17
hudakz	0:a04710facbb6	2674	#define EXTI_IMR_IM18 EXTI_IMR_MR18
hudakz	0:a04710facbb6	2675	#define EXTI_IMR_IM 0x0007FFFFU /!< Interrupt Mask All /
hudakz	0:a04710facbb6	2676
hudakz	0:a04710facbb6	2677	/***************** Bit definition for EXTI_EMR register *****************/
hudakz	0:a04710facbb6	2678	#define EXTI_EMR_MR0_Pos (0U)
hudakz	0:a04710facbb6	2679	#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	2680	#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /!< Event Mask on line 0 /
hudakz	0:a04710facbb6	2681	#define EXTI_EMR_MR1_Pos (1U)
hudakz	0:a04710facbb6	2682	#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	2683	#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /!< Event Mask on line 1 /
hudakz	0:a04710facbb6	2684	#define EXTI_EMR_MR2_Pos (2U)
hudakz	0:a04710facbb6	2685	#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	2686	#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /!< Event Mask on line 2 /
hudakz	0:a04710facbb6	2687	#define EXTI_EMR_MR3_Pos (3U)
hudakz	0:a04710facbb6	2688	#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	2689	#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /!< Event Mask on line 3 /
hudakz	0:a04710facbb6	2690	#define EXTI_EMR_MR4_Pos (4U)
hudakz	0:a04710facbb6	2691	#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	2692	#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /!< Event Mask on line 4 /
hudakz	0:a04710facbb6	2693	#define EXTI_EMR_MR5_Pos (5U)
hudakz	0:a04710facbb6	2694	#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	2695	#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /!< Event Mask on line 5 /
hudakz	0:a04710facbb6	2696	#define EXTI_EMR_MR6_Pos (6U)
hudakz	0:a04710facbb6	2697	#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	2698	#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /!< Event Mask on line 6 /
hudakz	0:a04710facbb6	2699	#define EXTI_EMR_MR7_Pos (7U)
hudakz	0:a04710facbb6	2700	#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	2701	#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /!< Event Mask on line 7 /
hudakz	0:a04710facbb6	2702	#define EXTI_EMR_MR8_Pos (8U)
hudakz	0:a04710facbb6	2703	#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	2704	#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /!< Event Mask on line 8 /
hudakz	0:a04710facbb6	2705	#define EXTI_EMR_MR9_Pos (9U)
hudakz	0:a04710facbb6	2706	#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	2707	#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /!< Event Mask on line 9 /
hudakz	0:a04710facbb6	2708	#define EXTI_EMR_MR10_Pos (10U)
hudakz	0:a04710facbb6	2709	#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	2710	#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /!< Event Mask on line 10 /
hudakz	0:a04710facbb6	2711	#define EXTI_EMR_MR11_Pos (11U)
hudakz	0:a04710facbb6	2712	#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	2713	#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /!< Event Mask on line 11 /
hudakz	0:a04710facbb6	2714	#define EXTI_EMR_MR12_Pos (12U)
hudakz	0:a04710facbb6	2715	#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	2716	#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /!< Event Mask on line 12 /
hudakz	0:a04710facbb6	2717	#define EXTI_EMR_MR13_Pos (13U)
hudakz	0:a04710facbb6	2718	#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	2719	#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /!< Event Mask on line 13 /
hudakz	0:a04710facbb6	2720	#define EXTI_EMR_MR14_Pos (14U)
hudakz	0:a04710facbb6	2721	#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	2722	#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /!< Event Mask on line 14 /
hudakz	0:a04710facbb6	2723	#define EXTI_EMR_MR15_Pos (15U)
hudakz	0:a04710facbb6	2724	#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	2725	#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /!< Event Mask on line 15 /
hudakz	0:a04710facbb6	2726	#define EXTI_EMR_MR16_Pos (16U)
hudakz	0:a04710facbb6	2727	#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	2728	#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /!< Event Mask on line 16 /
hudakz	0:a04710facbb6	2729	#define EXTI_EMR_MR17_Pos (17U)
hudakz	0:a04710facbb6	2730	#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	2731	#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /!< Event Mask on line 17 /
hudakz	0:a04710facbb6	2732	#define EXTI_EMR_MR18_Pos (18U)
hudakz	0:a04710facbb6	2733	#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	2734	#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /!< Event Mask on line 18 /
hudakz	0:a04710facbb6	2735
hudakz	0:a04710facbb6	2736	/* References Defines */
hudakz	0:a04710facbb6	2737	#define EXTI_EMR_EM0 EXTI_EMR_MR0
hudakz	0:a04710facbb6	2738	#define EXTI_EMR_EM1 EXTI_EMR_MR1
hudakz	0:a04710facbb6	2739	#define EXTI_EMR_EM2 EXTI_EMR_MR2
hudakz	0:a04710facbb6	2740	#define EXTI_EMR_EM3 EXTI_EMR_MR3
hudakz	0:a04710facbb6	2741	#define EXTI_EMR_EM4 EXTI_EMR_MR4
hudakz	0:a04710facbb6	2742	#define EXTI_EMR_EM5 EXTI_EMR_MR5
hudakz	0:a04710facbb6	2743	#define EXTI_EMR_EM6 EXTI_EMR_MR6
hudakz	0:a04710facbb6	2744	#define EXTI_EMR_EM7 EXTI_EMR_MR7
hudakz	0:a04710facbb6	2745	#define EXTI_EMR_EM8 EXTI_EMR_MR8
hudakz	0:a04710facbb6	2746	#define EXTI_EMR_EM9 EXTI_EMR_MR9
hudakz	0:a04710facbb6	2747	#define EXTI_EMR_EM10 EXTI_EMR_MR10
hudakz	0:a04710facbb6	2748	#define EXTI_EMR_EM11 EXTI_EMR_MR11
hudakz	0:a04710facbb6	2749	#define EXTI_EMR_EM12 EXTI_EMR_MR12
hudakz	0:a04710facbb6	2750	#define EXTI_EMR_EM13 EXTI_EMR_MR13
hudakz	0:a04710facbb6	2751	#define EXTI_EMR_EM14 EXTI_EMR_MR14
hudakz	0:a04710facbb6	2752	#define EXTI_EMR_EM15 EXTI_EMR_MR15
hudakz	0:a04710facbb6	2753	#define EXTI_EMR_EM16 EXTI_EMR_MR16
hudakz	0:a04710facbb6	2754	#define EXTI_EMR_EM17 EXTI_EMR_MR17
hudakz	0:a04710facbb6	2755	#define EXTI_EMR_EM18 EXTI_EMR_MR18
hudakz	0:a04710facbb6	2756
hudakz	0:a04710facbb6	2757	/**************** Bit definition for EXTI_RTSR register *****************/
hudakz	0:a04710facbb6	2758	#define EXTI_RTSR_TR0_Pos (0U)
hudakz	0:a04710facbb6	2759	#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	2760	#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /!< Rising trigger event configuration bit of line 0 /
hudakz	0:a04710facbb6	2761	#define EXTI_RTSR_TR1_Pos (1U)
hudakz	0:a04710facbb6	2762	#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	2763	#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /!< Rising trigger event configuration bit of line 1 /
hudakz	0:a04710facbb6	2764	#define EXTI_RTSR_TR2_Pos (2U)
hudakz	0:a04710facbb6	2765	#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	2766	#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /!< Rising trigger event configuration bit of line 2 /
hudakz	0:a04710facbb6	2767	#define EXTI_RTSR_TR3_Pos (3U)
hudakz	0:a04710facbb6	2768	#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	2769	#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /!< Rising trigger event configuration bit of line 3 /
hudakz	0:a04710facbb6	2770	#define EXTI_RTSR_TR4_Pos (4U)
hudakz	0:a04710facbb6	2771	#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	2772	#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /!< Rising trigger event configuration bit of line 4 /
hudakz	0:a04710facbb6	2773	#define EXTI_RTSR_TR5_Pos (5U)
hudakz	0:a04710facbb6	2774	#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	2775	#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /!< Rising trigger event configuration bit of line 5 /
hudakz	0:a04710facbb6	2776	#define EXTI_RTSR_TR6_Pos (6U)
hudakz	0:a04710facbb6	2777	#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	2778	#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /!< Rising trigger event configuration bit of line 6 /
hudakz	0:a04710facbb6	2779	#define EXTI_RTSR_TR7_Pos (7U)
hudakz	0:a04710facbb6	2780	#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	2781	#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /!< Rising trigger event configuration bit of line 7 /
hudakz	0:a04710facbb6	2782	#define EXTI_RTSR_TR8_Pos (8U)
hudakz	0:a04710facbb6	2783	#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	2784	#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /!< Rising trigger event configuration bit of line 8 /
hudakz	0:a04710facbb6	2785	#define EXTI_RTSR_TR9_Pos (9U)
hudakz	0:a04710facbb6	2786	#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	2787	#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /!< Rising trigger event configuration bit of line 9 /
hudakz	0:a04710facbb6	2788	#define EXTI_RTSR_TR10_Pos (10U)
hudakz	0:a04710facbb6	2789	#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	2790	#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /!< Rising trigger event configuration bit of line 10 /
hudakz	0:a04710facbb6	2791	#define EXTI_RTSR_TR11_Pos (11U)
hudakz	0:a04710facbb6	2792	#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	2793	#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /!< Rising trigger event configuration bit of line 11 /
hudakz	0:a04710facbb6	2794	#define EXTI_RTSR_TR12_Pos (12U)
hudakz	0:a04710facbb6	2795	#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	2796	#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /!< Rising trigger event configuration bit of line 12 /
hudakz	0:a04710facbb6	2797	#define EXTI_RTSR_TR13_Pos (13U)
hudakz	0:a04710facbb6	2798	#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	2799	#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /!< Rising trigger event configuration bit of line 13 /
hudakz	0:a04710facbb6	2800	#define EXTI_RTSR_TR14_Pos (14U)
hudakz	0:a04710facbb6	2801	#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	2802	#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /!< Rising trigger event configuration bit of line 14 /
hudakz	0:a04710facbb6	2803	#define EXTI_RTSR_TR15_Pos (15U)
hudakz	0:a04710facbb6	2804	#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	2805	#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /!< Rising trigger event configuration bit of line 15 /
hudakz	0:a04710facbb6	2806	#define EXTI_RTSR_TR16_Pos (16U)
hudakz	0:a04710facbb6	2807	#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	2808	#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /!< Rising trigger event configuration bit of line 16 /
hudakz	0:a04710facbb6	2809	#define EXTI_RTSR_TR17_Pos (17U)
hudakz	0:a04710facbb6	2810	#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	2811	#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /!< Rising trigger event configuration bit of line 17 /
hudakz	0:a04710facbb6	2812	#define EXTI_RTSR_TR18_Pos (18U)
hudakz	0:a04710facbb6	2813	#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	2814	#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /!< Rising trigger event configuration bit of line 18 /
hudakz	0:a04710facbb6	2815
hudakz	0:a04710facbb6	2816	/* References Defines */
hudakz	0:a04710facbb6	2817	#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
hudakz	0:a04710facbb6	2818	#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
hudakz	0:a04710facbb6	2819	#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
hudakz	0:a04710facbb6	2820	#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
hudakz	0:a04710facbb6	2821	#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
hudakz	0:a04710facbb6	2822	#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
hudakz	0:a04710facbb6	2823	#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
hudakz	0:a04710facbb6	2824	#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
hudakz	0:a04710facbb6	2825	#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
hudakz	0:a04710facbb6	2826	#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
hudakz	0:a04710facbb6	2827	#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
hudakz	0:a04710facbb6	2828	#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
hudakz	0:a04710facbb6	2829	#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
hudakz	0:a04710facbb6	2830	#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
hudakz	0:a04710facbb6	2831	#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
hudakz	0:a04710facbb6	2832	#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
hudakz	0:a04710facbb6	2833	#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
hudakz	0:a04710facbb6	2834	#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
hudakz	0:a04710facbb6	2835	#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
hudakz	0:a04710facbb6	2836
hudakz	0:a04710facbb6	2837	/**************** Bit definition for EXTI_FTSR register *****************/
hudakz	0:a04710facbb6	2838	#define EXTI_FTSR_TR0_Pos (0U)
hudakz	0:a04710facbb6	2839	#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	2840	#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /!< Falling trigger event configuration bit of line 0 /
hudakz	0:a04710facbb6	2841	#define EXTI_FTSR_TR1_Pos (1U)
hudakz	0:a04710facbb6	2842	#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	2843	#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /!< Falling trigger event configuration bit of line 1 /
hudakz	0:a04710facbb6	2844	#define EXTI_FTSR_TR2_Pos (2U)
hudakz	0:a04710facbb6	2845	#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	2846	#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /!< Falling trigger event configuration bit of line 2 /
hudakz	0:a04710facbb6	2847	#define EXTI_FTSR_TR3_Pos (3U)
hudakz	0:a04710facbb6	2848	#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	2849	#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /!< Falling trigger event configuration bit of line 3 /
hudakz	0:a04710facbb6	2850	#define EXTI_FTSR_TR4_Pos (4U)
hudakz	0:a04710facbb6	2851	#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	2852	#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /!< Falling trigger event configuration bit of line 4 /
hudakz	0:a04710facbb6	2853	#define EXTI_FTSR_TR5_Pos (5U)
hudakz	0:a04710facbb6	2854	#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	2855	#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /!< Falling trigger event configuration bit of line 5 /
hudakz	0:a04710facbb6	2856	#define EXTI_FTSR_TR6_Pos (6U)
hudakz	0:a04710facbb6	2857	#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	2858	#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /!< Falling trigger event configuration bit of line 6 /
hudakz	0:a04710facbb6	2859	#define EXTI_FTSR_TR7_Pos (7U)
hudakz	0:a04710facbb6	2860	#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	2861	#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /!< Falling trigger event configuration bit of line 7 /
hudakz	0:a04710facbb6	2862	#define EXTI_FTSR_TR8_Pos (8U)
hudakz	0:a04710facbb6	2863	#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	2864	#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /!< Falling trigger event configuration bit of line 8 /
hudakz	0:a04710facbb6	2865	#define EXTI_FTSR_TR9_Pos (9U)
hudakz	0:a04710facbb6	2866	#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	2867	#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /!< Falling trigger event configuration bit of line 9 /
hudakz	0:a04710facbb6	2868	#define EXTI_FTSR_TR10_Pos (10U)
hudakz	0:a04710facbb6	2869	#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	2870	#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /!< Falling trigger event configuration bit of line 10 /
hudakz	0:a04710facbb6	2871	#define EXTI_FTSR_TR11_Pos (11U)
hudakz	0:a04710facbb6	2872	#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	2873	#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /!< Falling trigger event configuration bit of line 11 /
hudakz	0:a04710facbb6	2874	#define EXTI_FTSR_TR12_Pos (12U)
hudakz	0:a04710facbb6	2875	#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	2876	#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /!< Falling trigger event configuration bit of line 12 /
hudakz	0:a04710facbb6	2877	#define EXTI_FTSR_TR13_Pos (13U)
hudakz	0:a04710facbb6	2878	#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	2879	#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /!< Falling trigger event configuration bit of line 13 /
hudakz	0:a04710facbb6	2880	#define EXTI_FTSR_TR14_Pos (14U)
hudakz	0:a04710facbb6	2881	#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	2882	#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /!< Falling trigger event configuration bit of line 14 /
hudakz	0:a04710facbb6	2883	#define EXTI_FTSR_TR15_Pos (15U)
hudakz	0:a04710facbb6	2884	#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	2885	#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /!< Falling trigger event configuration bit of line 15 /
hudakz	0:a04710facbb6	2886	#define EXTI_FTSR_TR16_Pos (16U)
hudakz	0:a04710facbb6	2887	#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	2888	#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /!< Falling trigger event configuration bit of line 16 /
hudakz	0:a04710facbb6	2889	#define EXTI_FTSR_TR17_Pos (17U)
hudakz	0:a04710facbb6	2890	#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	2891	#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /!< Falling trigger event configuration bit of line 17 /
hudakz	0:a04710facbb6	2892	#define EXTI_FTSR_TR18_Pos (18U)
hudakz	0:a04710facbb6	2893	#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	2894	#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /!< Falling trigger event configuration bit of line 18 /
hudakz	0:a04710facbb6	2895
hudakz	0:a04710facbb6	2896	/* References Defines */
hudakz	0:a04710facbb6	2897	#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
hudakz	0:a04710facbb6	2898	#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
hudakz	0:a04710facbb6	2899	#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
hudakz	0:a04710facbb6	2900	#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
hudakz	0:a04710facbb6	2901	#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
hudakz	0:a04710facbb6	2902	#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
hudakz	0:a04710facbb6	2903	#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
hudakz	0:a04710facbb6	2904	#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
hudakz	0:a04710facbb6	2905	#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
hudakz	0:a04710facbb6	2906	#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
hudakz	0:a04710facbb6	2907	#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
hudakz	0:a04710facbb6	2908	#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
hudakz	0:a04710facbb6	2909	#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
hudakz	0:a04710facbb6	2910	#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
hudakz	0:a04710facbb6	2911	#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
hudakz	0:a04710facbb6	2912	#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
hudakz	0:a04710facbb6	2913	#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
hudakz	0:a04710facbb6	2914	#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
hudakz	0:a04710facbb6	2915	#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
hudakz	0:a04710facbb6	2916
hudakz	0:a04710facbb6	2917	/**************** Bit definition for EXTI_SWIER register ****************/
hudakz	0:a04710facbb6	2918	#define EXTI_SWIER_SWIER0_Pos (0U)
hudakz	0:a04710facbb6	2919	#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	2920	#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /!< Software Interrupt on line 0 /
hudakz	0:a04710facbb6	2921	#define EXTI_SWIER_SWIER1_Pos (1U)
hudakz	0:a04710facbb6	2922	#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	2923	#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /!< Software Interrupt on line 1 /
hudakz	0:a04710facbb6	2924	#define EXTI_SWIER_SWIER2_Pos (2U)
hudakz	0:a04710facbb6	2925	#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	2926	#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /!< Software Interrupt on line 2 /
hudakz	0:a04710facbb6	2927	#define EXTI_SWIER_SWIER3_Pos (3U)
hudakz	0:a04710facbb6	2928	#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	2929	#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /!< Software Interrupt on line 3 /
hudakz	0:a04710facbb6	2930	#define EXTI_SWIER_SWIER4_Pos (4U)
hudakz	0:a04710facbb6	2931	#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	2932	#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /!< Software Interrupt on line 4 /
hudakz	0:a04710facbb6	2933	#define EXTI_SWIER_SWIER5_Pos (5U)
hudakz	0:a04710facbb6	2934	#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	2935	#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /!< Software Interrupt on line 5 /
hudakz	0:a04710facbb6	2936	#define EXTI_SWIER_SWIER6_Pos (6U)
hudakz	0:a04710facbb6	2937	#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	2938	#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /!< Software Interrupt on line 6 /
hudakz	0:a04710facbb6	2939	#define EXTI_SWIER_SWIER7_Pos (7U)
hudakz	0:a04710facbb6	2940	#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	2941	#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /!< Software Interrupt on line 7 /
hudakz	0:a04710facbb6	2942	#define EXTI_SWIER_SWIER8_Pos (8U)
hudakz	0:a04710facbb6	2943	#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	2944	#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /!< Software Interrupt on line 8 /
hudakz	0:a04710facbb6	2945	#define EXTI_SWIER_SWIER9_Pos (9U)
hudakz	0:a04710facbb6	2946	#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	2947	#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /!< Software Interrupt on line 9 /
hudakz	0:a04710facbb6	2948	#define EXTI_SWIER_SWIER10_Pos (10U)
hudakz	0:a04710facbb6	2949	#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	2950	#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /!< Software Interrupt on line 10 /
hudakz	0:a04710facbb6	2951	#define EXTI_SWIER_SWIER11_Pos (11U)
hudakz	0:a04710facbb6	2952	#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	2953	#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /!< Software Interrupt on line 11 /
hudakz	0:a04710facbb6	2954	#define EXTI_SWIER_SWIER12_Pos (12U)
hudakz	0:a04710facbb6	2955	#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	2956	#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /!< Software Interrupt on line 12 /
hudakz	0:a04710facbb6	2957	#define EXTI_SWIER_SWIER13_Pos (13U)
hudakz	0:a04710facbb6	2958	#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	2959	#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /!< Software Interrupt on line 13 /
hudakz	0:a04710facbb6	2960	#define EXTI_SWIER_SWIER14_Pos (14U)
hudakz	0:a04710facbb6	2961	#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	2962	#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /!< Software Interrupt on line 14 /
hudakz	0:a04710facbb6	2963	#define EXTI_SWIER_SWIER15_Pos (15U)
hudakz	0:a04710facbb6	2964	#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	2965	#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /!< Software Interrupt on line 15 /
hudakz	0:a04710facbb6	2966	#define EXTI_SWIER_SWIER16_Pos (16U)
hudakz	0:a04710facbb6	2967	#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	2968	#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /!< Software Interrupt on line 16 /
hudakz	0:a04710facbb6	2969	#define EXTI_SWIER_SWIER17_Pos (17U)
hudakz	0:a04710facbb6	2970	#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	2971	#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /!< Software Interrupt on line 17 /
hudakz	0:a04710facbb6	2972	#define EXTI_SWIER_SWIER18_Pos (18U)
hudakz	0:a04710facbb6	2973	#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	2974	#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /!< Software Interrupt on line 18 /
hudakz	0:a04710facbb6	2975
hudakz	0:a04710facbb6	2976	/* References Defines */
hudakz	0:a04710facbb6	2977	#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
hudakz	0:a04710facbb6	2978	#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
hudakz	0:a04710facbb6	2979	#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
hudakz	0:a04710facbb6	2980	#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
hudakz	0:a04710facbb6	2981	#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
hudakz	0:a04710facbb6	2982	#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
hudakz	0:a04710facbb6	2983	#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
hudakz	0:a04710facbb6	2984	#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
hudakz	0:a04710facbb6	2985	#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
hudakz	0:a04710facbb6	2986	#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
hudakz	0:a04710facbb6	2987	#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
hudakz	0:a04710facbb6	2988	#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
hudakz	0:a04710facbb6	2989	#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
hudakz	0:a04710facbb6	2990	#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
hudakz	0:a04710facbb6	2991	#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
hudakz	0:a04710facbb6	2992	#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
hudakz	0:a04710facbb6	2993	#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
hudakz	0:a04710facbb6	2994	#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
hudakz	0:a04710facbb6	2995	#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
hudakz	0:a04710facbb6	2996
hudakz	0:a04710facbb6	2997	/***************** Bit definition for EXTI_PR register ******************/
hudakz	0:a04710facbb6	2998	#define EXTI_PR_PR0_Pos (0U)
hudakz	0:a04710facbb6	2999	#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	3000	#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /!< Pending bit for line 0 /
hudakz	0:a04710facbb6	3001	#define EXTI_PR_PR1_Pos (1U)
hudakz	0:a04710facbb6	3002	#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	3003	#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /!< Pending bit for line 1 /
hudakz	0:a04710facbb6	3004	#define EXTI_PR_PR2_Pos (2U)
hudakz	0:a04710facbb6	3005	#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	3006	#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /!< Pending bit for line 2 /
hudakz	0:a04710facbb6	3007	#define EXTI_PR_PR3_Pos (3U)
hudakz	0:a04710facbb6	3008	#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	3009	#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /!< Pending bit for line 3 /
hudakz	0:a04710facbb6	3010	#define EXTI_PR_PR4_Pos (4U)
hudakz	0:a04710facbb6	3011	#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	3012	#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /!< Pending bit for line 4 /
hudakz	0:a04710facbb6	3013	#define EXTI_PR_PR5_Pos (5U)
hudakz	0:a04710facbb6	3014	#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	3015	#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /!< Pending bit for line 5 /
hudakz	0:a04710facbb6	3016	#define EXTI_PR_PR6_Pos (6U)
hudakz	0:a04710facbb6	3017	#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	3018	#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /!< Pending bit for line 6 /
hudakz	0:a04710facbb6	3019	#define EXTI_PR_PR7_Pos (7U)
hudakz	0:a04710facbb6	3020	#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	3021	#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /!< Pending bit for line 7 /
hudakz	0:a04710facbb6	3022	#define EXTI_PR_PR8_Pos (8U)
hudakz	0:a04710facbb6	3023	#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	3024	#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /!< Pending bit for line 8 /
hudakz	0:a04710facbb6	3025	#define EXTI_PR_PR9_Pos (9U)
hudakz	0:a04710facbb6	3026	#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	3027	#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /!< Pending bit for line 9 /
hudakz	0:a04710facbb6	3028	#define EXTI_PR_PR10_Pos (10U)
hudakz	0:a04710facbb6	3029	#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	3030	#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /!< Pending bit for line 10 /
hudakz	0:a04710facbb6	3031	#define EXTI_PR_PR11_Pos (11U)
hudakz	0:a04710facbb6	3032	#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	3033	#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /!< Pending bit for line 11 /
hudakz	0:a04710facbb6	3034	#define EXTI_PR_PR12_Pos (12U)
hudakz	0:a04710facbb6	3035	#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	3036	#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /!< Pending bit for line 12 /
hudakz	0:a04710facbb6	3037	#define EXTI_PR_PR13_Pos (13U)
hudakz	0:a04710facbb6	3038	#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	3039	#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /!< Pending bit for line 13 /
hudakz	0:a04710facbb6	3040	#define EXTI_PR_PR14_Pos (14U)
hudakz	0:a04710facbb6	3041	#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	3042	#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /!< Pending bit for line 14 /
hudakz	0:a04710facbb6	3043	#define EXTI_PR_PR15_Pos (15U)
hudakz	0:a04710facbb6	3044	#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	3045	#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /!< Pending bit for line 15 /
hudakz	0:a04710facbb6	3046	#define EXTI_PR_PR16_Pos (16U)
hudakz	0:a04710facbb6	3047	#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	3048	#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /!< Pending bit for line 16 /
hudakz	0:a04710facbb6	3049	#define EXTI_PR_PR17_Pos (17U)
hudakz	0:a04710facbb6	3050	#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	3051	#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /!< Pending bit for line 17 /
hudakz	0:a04710facbb6	3052	#define EXTI_PR_PR18_Pos (18U)
hudakz	0:a04710facbb6	3053	#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	3054	#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /!< Pending bit for line 18 /
hudakz	0:a04710facbb6	3055
hudakz	0:a04710facbb6	3056	/* References Defines */
hudakz	0:a04710facbb6	3057	#define EXTI_PR_PIF0 EXTI_PR_PR0
hudakz	0:a04710facbb6	3058	#define EXTI_PR_PIF1 EXTI_PR_PR1
hudakz	0:a04710facbb6	3059	#define EXTI_PR_PIF2 EXTI_PR_PR2
hudakz	0:a04710facbb6	3060	#define EXTI_PR_PIF3 EXTI_PR_PR3
hudakz	0:a04710facbb6	3061	#define EXTI_PR_PIF4 EXTI_PR_PR4
hudakz	0:a04710facbb6	3062	#define EXTI_PR_PIF5 EXTI_PR_PR5
hudakz	0:a04710facbb6	3063	#define EXTI_PR_PIF6 EXTI_PR_PR6
hudakz	0:a04710facbb6	3064	#define EXTI_PR_PIF7 EXTI_PR_PR7
hudakz	0:a04710facbb6	3065	#define EXTI_PR_PIF8 EXTI_PR_PR8
hudakz	0:a04710facbb6	3066	#define EXTI_PR_PIF9 EXTI_PR_PR9
hudakz	0:a04710facbb6	3067	#define EXTI_PR_PIF10 EXTI_PR_PR10
hudakz	0:a04710facbb6	3068	#define EXTI_PR_PIF11 EXTI_PR_PR11
hudakz	0:a04710facbb6	3069	#define EXTI_PR_PIF12 EXTI_PR_PR12
hudakz	0:a04710facbb6	3070	#define EXTI_PR_PIF13 EXTI_PR_PR13
hudakz	0:a04710facbb6	3071	#define EXTI_PR_PIF14 EXTI_PR_PR14
hudakz	0:a04710facbb6	3072	#define EXTI_PR_PIF15 EXTI_PR_PR15
hudakz	0:a04710facbb6	3073	#define EXTI_PR_PIF16 EXTI_PR_PR16
hudakz	0:a04710facbb6	3074	#define EXTI_PR_PIF17 EXTI_PR_PR17
hudakz	0:a04710facbb6	3075	#define EXTI_PR_PIF18 EXTI_PR_PR18
hudakz	0:a04710facbb6	3076
hudakz	0:a04710facbb6	3077	/******************************************************************************/
hudakz	0:a04710facbb6	3078	/* */
hudakz	0:a04710facbb6	3079	/* DMA Controller */
hudakz	0:a04710facbb6	3080	/* */
hudakz	0:a04710facbb6	3081	/******************************************************************************/
hudakz	0:a04710facbb6	3082
hudakz	0:a04710facbb6	3083	/***************** Bit definition for DMA_ISR register ******************/
hudakz	0:a04710facbb6	3084	#define DMA_ISR_GIF1_Pos (0U)
hudakz	0:a04710facbb6	3085	#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	3086	#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /!< Channel 1 Global interrupt flag /
hudakz	0:a04710facbb6	3087	#define DMA_ISR_TCIF1_Pos (1U)
hudakz	0:a04710facbb6	3088	#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	3089	#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /!< Channel 1 Transfer Complete flag /
hudakz	0:a04710facbb6	3090	#define DMA_ISR_HTIF1_Pos (2U)
hudakz	0:a04710facbb6	3091	#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	3092	#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /!< Channel 1 Half Transfer flag /
hudakz	0:a04710facbb6	3093	#define DMA_ISR_TEIF1_Pos (3U)
hudakz	0:a04710facbb6	3094	#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	3095	#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /!< Channel 1 Transfer Error flag /
hudakz	0:a04710facbb6	3096	#define DMA_ISR_GIF2_Pos (4U)
hudakz	0:a04710facbb6	3097	#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	3098	#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /!< Channel 2 Global interrupt flag /
hudakz	0:a04710facbb6	3099	#define DMA_ISR_TCIF2_Pos (5U)
hudakz	0:a04710facbb6	3100	#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	3101	#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /!< Channel 2 Transfer Complete flag /
hudakz	0:a04710facbb6	3102	#define DMA_ISR_HTIF2_Pos (6U)
hudakz	0:a04710facbb6	3103	#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	3104	#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /!< Channel 2 Half Transfer flag /
hudakz	0:a04710facbb6	3105	#define DMA_ISR_TEIF2_Pos (7U)
hudakz	0:a04710facbb6	3106	#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	3107	#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /!< Channel 2 Transfer Error flag /
hudakz	0:a04710facbb6	3108	#define DMA_ISR_GIF3_Pos (8U)
hudakz	0:a04710facbb6	3109	#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	3110	#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /!< Channel 3 Global interrupt flag /
hudakz	0:a04710facbb6	3111	#define DMA_ISR_TCIF3_Pos (9U)
hudakz	0:a04710facbb6	3112	#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	3113	#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /!< Channel 3 Transfer Complete flag /
hudakz	0:a04710facbb6	3114	#define DMA_ISR_HTIF3_Pos (10U)
hudakz	0:a04710facbb6	3115	#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	3116	#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /!< Channel 3 Half Transfer flag /
hudakz	0:a04710facbb6	3117	#define DMA_ISR_TEIF3_Pos (11U)
hudakz	0:a04710facbb6	3118	#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	3119	#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /!< Channel 3 Transfer Error flag /
hudakz	0:a04710facbb6	3120	#define DMA_ISR_GIF4_Pos (12U)
hudakz	0:a04710facbb6	3121	#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	3122	#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /!< Channel 4 Global interrupt flag /
hudakz	0:a04710facbb6	3123	#define DMA_ISR_TCIF4_Pos (13U)
hudakz	0:a04710facbb6	3124	#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	3125	#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /!< Channel 4 Transfer Complete flag /
hudakz	0:a04710facbb6	3126	#define DMA_ISR_HTIF4_Pos (14U)
hudakz	0:a04710facbb6	3127	#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	3128	#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /!< Channel 4 Half Transfer flag /
hudakz	0:a04710facbb6	3129	#define DMA_ISR_TEIF4_Pos (15U)
hudakz	0:a04710facbb6	3130	#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	3131	#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /!< Channel 4 Transfer Error flag /
hudakz	0:a04710facbb6	3132	#define DMA_ISR_GIF5_Pos (16U)
hudakz	0:a04710facbb6	3133	#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	3134	#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /!< Channel 5 Global interrupt flag /
hudakz	0:a04710facbb6	3135	#define DMA_ISR_TCIF5_Pos (17U)
hudakz	0:a04710facbb6	3136	#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	3137	#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /!< Channel 5 Transfer Complete flag /
hudakz	0:a04710facbb6	3138	#define DMA_ISR_HTIF5_Pos (18U)
hudakz	0:a04710facbb6	3139	#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	3140	#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /!< Channel 5 Half Transfer flag /
hudakz	0:a04710facbb6	3141	#define DMA_ISR_TEIF5_Pos (19U)
hudakz	0:a04710facbb6	3142	#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	3143	#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /!< Channel 5 Transfer Error flag /
hudakz	0:a04710facbb6	3144	#define DMA_ISR_GIF6_Pos (20U)
hudakz	0:a04710facbb6	3145	#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	3146	#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /!< Channel 6 Global interrupt flag /
hudakz	0:a04710facbb6	3147	#define DMA_ISR_TCIF6_Pos (21U)
hudakz	0:a04710facbb6	3148	#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	3149	#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /!< Channel 6 Transfer Complete flag /
hudakz	0:a04710facbb6	3150	#define DMA_ISR_HTIF6_Pos (22U)
hudakz	0:a04710facbb6	3151	#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	3152	#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /!< Channel 6 Half Transfer flag /
hudakz	0:a04710facbb6	3153	#define DMA_ISR_TEIF6_Pos (23U)
hudakz	0:a04710facbb6	3154	#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	3155	#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /!< Channel 6 Transfer Error flag /
hudakz	0:a04710facbb6	3156	#define DMA_ISR_GIF7_Pos (24U)
hudakz	0:a04710facbb6	3157	#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	3158	#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /!< Channel 7 Global interrupt flag /
hudakz	0:a04710facbb6	3159	#define DMA_ISR_TCIF7_Pos (25U)
hudakz	0:a04710facbb6	3160	#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	3161	#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /!< Channel 7 Transfer Complete flag /
hudakz	0:a04710facbb6	3162	#define DMA_ISR_HTIF7_Pos (26U)
hudakz	0:a04710facbb6	3163	#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	3164	#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /!< Channel 7 Half Transfer flag /
hudakz	0:a04710facbb6	3165	#define DMA_ISR_TEIF7_Pos (27U)
hudakz	0:a04710facbb6	3166	#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	3167	#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /!< Channel 7 Transfer Error flag /
hudakz	0:a04710facbb6	3168
hudakz	0:a04710facbb6	3169	/***************** Bit definition for DMA_IFCR register *****************/
hudakz	0:a04710facbb6	3170	#define DMA_IFCR_CGIF1_Pos (0U)
hudakz	0:a04710facbb6	3171	#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	3172	#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /!< Channel 1 Global interrupt clear /
hudakz	0:a04710facbb6	3173	#define DMA_IFCR_CTCIF1_Pos (1U)
hudakz	0:a04710facbb6	3174	#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	3175	#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /!< Channel 1 Transfer Complete clear /
hudakz	0:a04710facbb6	3176	#define DMA_IFCR_CHTIF1_Pos (2U)
hudakz	0:a04710facbb6	3177	#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	3178	#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /!< Channel 1 Half Transfer clear /
hudakz	0:a04710facbb6	3179	#define DMA_IFCR_CTEIF1_Pos (3U)
hudakz	0:a04710facbb6	3180	#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	3181	#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /!< Channel 1 Transfer Error clear /
hudakz	0:a04710facbb6	3182	#define DMA_IFCR_CGIF2_Pos (4U)
hudakz	0:a04710facbb6	3183	#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	3184	#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /!< Channel 2 Global interrupt clear /
hudakz	0:a04710facbb6	3185	#define DMA_IFCR_CTCIF2_Pos (5U)
hudakz	0:a04710facbb6	3186	#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	3187	#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /!< Channel 2 Transfer Complete clear /
hudakz	0:a04710facbb6	3188	#define DMA_IFCR_CHTIF2_Pos (6U)
hudakz	0:a04710facbb6	3189	#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	3190	#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /!< Channel 2 Half Transfer clear /
hudakz	0:a04710facbb6	3191	#define DMA_IFCR_CTEIF2_Pos (7U)
hudakz	0:a04710facbb6	3192	#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	3193	#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /!< Channel 2 Transfer Error clear /
hudakz	0:a04710facbb6	3194	#define DMA_IFCR_CGIF3_Pos (8U)
hudakz	0:a04710facbb6	3195	#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	3196	#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /!< Channel 3 Global interrupt clear /
hudakz	0:a04710facbb6	3197	#define DMA_IFCR_CTCIF3_Pos (9U)
hudakz	0:a04710facbb6	3198	#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	3199	#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /!< Channel 3 Transfer Complete clear /
hudakz	0:a04710facbb6	3200	#define DMA_IFCR_CHTIF3_Pos (10U)
hudakz	0:a04710facbb6	3201	#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	3202	#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /!< Channel 3 Half Transfer clear /
hudakz	0:a04710facbb6	3203	#define DMA_IFCR_CTEIF3_Pos (11U)
hudakz	0:a04710facbb6	3204	#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	3205	#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /!< Channel 3 Transfer Error clear /
hudakz	0:a04710facbb6	3206	#define DMA_IFCR_CGIF4_Pos (12U)
hudakz	0:a04710facbb6	3207	#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	3208	#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /!< Channel 4 Global interrupt clear /
hudakz	0:a04710facbb6	3209	#define DMA_IFCR_CTCIF4_Pos (13U)
hudakz	0:a04710facbb6	3210	#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	3211	#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /!< Channel 4 Transfer Complete clear /
hudakz	0:a04710facbb6	3212	#define DMA_IFCR_CHTIF4_Pos (14U)
hudakz	0:a04710facbb6	3213	#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	3214	#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /!< Channel 4 Half Transfer clear /
hudakz	0:a04710facbb6	3215	#define DMA_IFCR_CTEIF4_Pos (15U)
hudakz	0:a04710facbb6	3216	#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	3217	#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /!< Channel 4 Transfer Error clear /
hudakz	0:a04710facbb6	3218	#define DMA_IFCR_CGIF5_Pos (16U)
hudakz	0:a04710facbb6	3219	#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	3220	#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /!< Channel 5 Global interrupt clear /
hudakz	0:a04710facbb6	3221	#define DMA_IFCR_CTCIF5_Pos (17U)
hudakz	0:a04710facbb6	3222	#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	3223	#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /!< Channel 5 Transfer Complete clear /
hudakz	0:a04710facbb6	3224	#define DMA_IFCR_CHTIF5_Pos (18U)
hudakz	0:a04710facbb6	3225	#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	3226	#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /!< Channel 5 Half Transfer clear /
hudakz	0:a04710facbb6	3227	#define DMA_IFCR_CTEIF5_Pos (19U)
hudakz	0:a04710facbb6	3228	#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	3229	#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /!< Channel 5 Transfer Error clear /
hudakz	0:a04710facbb6	3230	#define DMA_IFCR_CGIF6_Pos (20U)
hudakz	0:a04710facbb6	3231	#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	3232	#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /!< Channel 6 Global interrupt clear /
hudakz	0:a04710facbb6	3233	#define DMA_IFCR_CTCIF6_Pos (21U)
hudakz	0:a04710facbb6	3234	#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	3235	#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /!< Channel 6 Transfer Complete clear /
hudakz	0:a04710facbb6	3236	#define DMA_IFCR_CHTIF6_Pos (22U)
hudakz	0:a04710facbb6	3237	#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	3238	#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /!< Channel 6 Half Transfer clear /
hudakz	0:a04710facbb6	3239	#define DMA_IFCR_CTEIF6_Pos (23U)
hudakz	0:a04710facbb6	3240	#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	3241	#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /!< Channel 6 Transfer Error clear /
hudakz	0:a04710facbb6	3242	#define DMA_IFCR_CGIF7_Pos (24U)
hudakz	0:a04710facbb6	3243	#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	3244	#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /!< Channel 7 Global interrupt clear /
hudakz	0:a04710facbb6	3245	#define DMA_IFCR_CTCIF7_Pos (25U)
hudakz	0:a04710facbb6	3246	#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	3247	#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /!< Channel 7 Transfer Complete clear /
hudakz	0:a04710facbb6	3248	#define DMA_IFCR_CHTIF7_Pos (26U)
hudakz	0:a04710facbb6	3249	#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	3250	#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /!< Channel 7 Half Transfer clear /
hudakz	0:a04710facbb6	3251	#define DMA_IFCR_CTEIF7_Pos (27U)
hudakz	0:a04710facbb6	3252	#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	3253	#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /!< Channel 7 Transfer Error clear /
hudakz	0:a04710facbb6	3254
hudakz	0:a04710facbb6	3255	/***************** Bit definition for DMA_CCR register *****************/
hudakz	0:a04710facbb6	3256	#define DMA_CCR_EN_Pos (0U)
hudakz	0:a04710facbb6	3257	#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	3258	#define DMA_CCR_EN DMA_CCR_EN_Msk /!< Channel enable /
hudakz	0:a04710facbb6	3259	#define DMA_CCR_TCIE_Pos (1U)
hudakz	0:a04710facbb6	3260	#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	3261	#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /!< Transfer complete interrupt enable /
hudakz	0:a04710facbb6	3262	#define DMA_CCR_HTIE_Pos (2U)
hudakz	0:a04710facbb6	3263	#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	3264	#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /!< Half Transfer interrupt enable /
hudakz	0:a04710facbb6	3265	#define DMA_CCR_TEIE_Pos (3U)
hudakz	0:a04710facbb6	3266	#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	3267	#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /!< Transfer error interrupt enable /
hudakz	0:a04710facbb6	3268	#define DMA_CCR_DIR_Pos (4U)
hudakz	0:a04710facbb6	3269	#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	3270	#define DMA_CCR_DIR DMA_CCR_DIR_Msk /!< Data transfer direction /
hudakz	0:a04710facbb6	3271	#define DMA_CCR_CIRC_Pos (5U)
hudakz	0:a04710facbb6	3272	#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	3273	#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /!< Circular mode /
hudakz	0:a04710facbb6	3274	#define DMA_CCR_PINC_Pos (6U)
hudakz	0:a04710facbb6	3275	#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	3276	#define DMA_CCR_PINC DMA_CCR_PINC_Msk /!< Peripheral increment mode /
hudakz	0:a04710facbb6	3277	#define DMA_CCR_MINC_Pos (7U)
hudakz	0:a04710facbb6	3278	#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	3279	#define DMA_CCR_MINC DMA_CCR_MINC_Msk /!< Memory increment mode /
hudakz	0:a04710facbb6	3280
hudakz	0:a04710facbb6	3281	#define DMA_CCR_PSIZE_Pos (8U)
hudakz	0:a04710facbb6	3282	#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /!< 0x00000300 /
hudakz	0:a04710facbb6	3283	#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /!< PSIZE[1:0] bits (Peripheral size) /
hudakz	0:a04710facbb6	3284	#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	3285	#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	3286
hudakz	0:a04710facbb6	3287	#define DMA_CCR_MSIZE_Pos (10U)
hudakz	0:a04710facbb6	3288	#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /!< 0x00000C00 /
hudakz	0:a04710facbb6	3289	#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /!< MSIZE[1:0] bits (Memory size) /
hudakz	0:a04710facbb6	3290	#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	3291	#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	3292
hudakz	0:a04710facbb6	3293	#define DMA_CCR_PL_Pos (12U)
hudakz	0:a04710facbb6	3294	#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /!< 0x00003000 /
hudakz	0:a04710facbb6	3295	#define DMA_CCR_PL DMA_CCR_PL_Msk /!< PL[1:0] bits(Channel Priority level) /
hudakz	0:a04710facbb6	3296	#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	3297	#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	3298
hudakz	0:a04710facbb6	3299	#define DMA_CCR_MEM2MEM_Pos (14U)
hudakz	0:a04710facbb6	3300	#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	3301	#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /!< Memory to memory mode /
hudakz	0:a04710facbb6	3302
hudakz	0:a04710facbb6	3303	/**************** Bit definition for DMA_CNDTR register ****************/
hudakz	0:a04710facbb6	3304	#define DMA_CNDTR_NDT_Pos (0U)
hudakz	0:a04710facbb6	3305	#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	3306	#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /!< Number of data to Transfer /
hudakz	0:a04710facbb6	3307
hudakz	0:a04710facbb6	3308	/**************** Bit definition for DMA_CPAR register *****************/
hudakz	0:a04710facbb6	3309	#define DMA_CPAR_PA_Pos (0U)
hudakz	0:a04710facbb6	3310	#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /!< 0xFFFFFFFF /
hudakz	0:a04710facbb6	3311	#define DMA_CPAR_PA DMA_CPAR_PA_Msk /!< Peripheral Address /
hudakz	0:a04710facbb6	3312
hudakz	0:a04710facbb6	3313	/**************** Bit definition for DMA_CMAR register *****************/
hudakz	0:a04710facbb6	3314	#define DMA_CMAR_MA_Pos (0U)
hudakz	0:a04710facbb6	3315	#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /!< 0xFFFFFFFF /
hudakz	0:a04710facbb6	3316	#define DMA_CMAR_MA DMA_CMAR_MA_Msk /!< Memory Address /
hudakz	0:a04710facbb6	3317
hudakz	0:a04710facbb6	3318	/******************************************************************************/
hudakz	0:a04710facbb6	3319	/* */
hudakz	0:a04710facbb6	3320	/* Analog to Digital Converter (ADC) */
hudakz	0:a04710facbb6	3321	/* */
hudakz	0:a04710facbb6	3322	/******************************************************************************/
hudakz	0:a04710facbb6	3323
hudakz	0:a04710facbb6	3324	/*
hudakz	0:a04710facbb6	3325	* @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
hudakz	0:a04710facbb6	3326	*/
hudakz	0:a04710facbb6	3327	#define ADC_MULTIMODE_SUPPORT /!< ADC feature available only on specific devices: multimode available on devices with several ADC instances /
hudakz	0:a04710facbb6	3328
hudakz	0:a04710facbb6	3329	/****************** Bit definition for ADC_SR register ******************/
hudakz	0:a04710facbb6	3330	#define ADC_SR_AWD_Pos (0U)
hudakz	0:a04710facbb6	3331	#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	3332	#define ADC_SR_AWD ADC_SR_AWD_Msk /!< ADC analog watchdog 1 flag /
hudakz	0:a04710facbb6	3333	#define ADC_SR_EOS_Pos (1U)
hudakz	0:a04710facbb6	3334	#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	3335	#define ADC_SR_EOS ADC_SR_EOS_Msk /!< ADC group regular end of sequence conversions flag /
hudakz	0:a04710facbb6	3336	#define ADC_SR_JEOS_Pos (2U)
hudakz	0:a04710facbb6	3337	#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	3338	#define ADC_SR_JEOS ADC_SR_JEOS_Msk /!< ADC group injected end of sequence conversions flag /
hudakz	0:a04710facbb6	3339	#define ADC_SR_JSTRT_Pos (3U)
hudakz	0:a04710facbb6	3340	#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	3341	#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /!< ADC group injected conversion start flag /
hudakz	0:a04710facbb6	3342	#define ADC_SR_STRT_Pos (4U)
hudakz	0:a04710facbb6	3343	#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	3344	#define ADC_SR_STRT ADC_SR_STRT_Msk /!< ADC group regular conversion start flag /
hudakz	0:a04710facbb6	3345
hudakz	0:a04710facbb6	3346	/* Legacy defines */
hudakz	0:a04710facbb6	3347	#define ADC_SR_EOC (ADC_SR_EOS)
hudakz	0:a04710facbb6	3348	#define ADC_SR_JEOC (ADC_SR_JEOS)
hudakz	0:a04710facbb6	3349
hudakz	0:a04710facbb6	3350	/***************** Bit definition for ADC_CR1 register ******************/
hudakz	0:a04710facbb6	3351	#define ADC_CR1_AWDCH_Pos (0U)
hudakz	0:a04710facbb6	3352	#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /!< 0x0000001F /
hudakz	0:a04710facbb6	3353	#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /!< ADC analog watchdog 1 monitored channel selection /
hudakz	0:a04710facbb6	3354	#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	3355	#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	3356	#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	3357	#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	3358	#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	3359
hudakz	0:a04710facbb6	3360	#define ADC_CR1_EOSIE_Pos (5U)
hudakz	0:a04710facbb6	3361	#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	3362	#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /!< ADC group regular end of sequence conversions interrupt /
hudakz	0:a04710facbb6	3363	#define ADC_CR1_AWDIE_Pos (6U)
hudakz	0:a04710facbb6	3364	#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	3365	#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /!< ADC analog watchdog 1 interrupt /
hudakz	0:a04710facbb6	3366	#define ADC_CR1_JEOSIE_Pos (7U)
hudakz	0:a04710facbb6	3367	#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	3368	#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /!< ADC group injected end of sequence conversions interrupt /
hudakz	0:a04710facbb6	3369	#define ADC_CR1_SCAN_Pos (8U)
hudakz	0:a04710facbb6	3370	#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	3371	#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /!< ADC scan mode /
hudakz	0:a04710facbb6	3372	#define ADC_CR1_AWDSGL_Pos (9U)
hudakz	0:a04710facbb6	3373	#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	3374	#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /!< ADC analog watchdog 1 monitoring a single channel or all channels /
hudakz	0:a04710facbb6	3375	#define ADC_CR1_JAUTO_Pos (10U)
hudakz	0:a04710facbb6	3376	#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	3377	#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /!< ADC group injected automatic trigger mode /
hudakz	0:a04710facbb6	3378	#define ADC_CR1_DISCEN_Pos (11U)
hudakz	0:a04710facbb6	3379	#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	3380	#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /!< ADC group regular sequencer discontinuous mode /
hudakz	0:a04710facbb6	3381	#define ADC_CR1_JDISCEN_Pos (12U)
hudakz	0:a04710facbb6	3382	#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	3383	#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /!< ADC group injected sequencer discontinuous mode /
hudakz	0:a04710facbb6	3384
hudakz	0:a04710facbb6	3385	#define ADC_CR1_DISCNUM_Pos (13U)
hudakz	0:a04710facbb6	3386	#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /!< 0x0000E000 /
hudakz	0:a04710facbb6	3387	#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /!< ADC group regular sequencer discontinuous number of ranks /
hudakz	0:a04710facbb6	3388	#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	3389	#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	3390	#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	3391
hudakz	0:a04710facbb6	3392	#define ADC_CR1_DUALMOD_Pos (16U)
hudakz	0:a04710facbb6	3393	#define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /!< 0x000F0000 /
hudakz	0:a04710facbb6	3394	#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /!< ADC multimode mode selection /
hudakz	0:a04710facbb6	3395	#define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	3396	#define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	3397	#define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	3398	#define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	3399
hudakz	0:a04710facbb6	3400	#define ADC_CR1_JAWDEN_Pos (22U)
hudakz	0:a04710facbb6	3401	#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	3402	#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /!< ADC analog watchdog 1 enable on scope ADC group injected /
hudakz	0:a04710facbb6	3403	#define ADC_CR1_AWDEN_Pos (23U)
hudakz	0:a04710facbb6	3404	#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	3405	#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /!< ADC analog watchdog 1 enable on scope ADC group regular /
hudakz	0:a04710facbb6	3406
hudakz	0:a04710facbb6	3407	/* Legacy defines */
hudakz	0:a04710facbb6	3408	#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
hudakz	0:a04710facbb6	3409	#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
hudakz	0:a04710facbb6	3410
hudakz	0:a04710facbb6	3411	/***************** Bit definition for ADC_CR2 register ******************/
hudakz	0:a04710facbb6	3412	#define ADC_CR2_ADON_Pos (0U)
hudakz	0:a04710facbb6	3413	#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	3414	#define ADC_CR2_ADON ADC_CR2_ADON_Msk /!< ADC enable /
hudakz	0:a04710facbb6	3415	#define ADC_CR2_CONT_Pos (1U)
hudakz	0:a04710facbb6	3416	#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	3417	#define ADC_CR2_CONT ADC_CR2_CONT_Msk /!< ADC group regular continuous conversion mode /
hudakz	0:a04710facbb6	3418	#define ADC_CR2_CAL_Pos (2U)
hudakz	0:a04710facbb6	3419	#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	3420	#define ADC_CR2_CAL ADC_CR2_CAL_Msk /!< ADC calibration start /
hudakz	0:a04710facbb6	3421	#define ADC_CR2_RSTCAL_Pos (3U)
hudakz	0:a04710facbb6	3422	#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	3423	#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /!< ADC calibration reset /
hudakz	0:a04710facbb6	3424	#define ADC_CR2_DMA_Pos (8U)
hudakz	0:a04710facbb6	3425	#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	3426	#define ADC_CR2_DMA ADC_CR2_DMA_Msk /!< ADC DMA transfer enable /
hudakz	0:a04710facbb6	3427	#define ADC_CR2_ALIGN_Pos (11U)
hudakz	0:a04710facbb6	3428	#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	3429	#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /!< ADC data alignement /
hudakz	0:a04710facbb6	3430
hudakz	0:a04710facbb6	3431	#define ADC_CR2_JEXTSEL_Pos (12U)
hudakz	0:a04710facbb6	3432	#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /!< 0x00007000 /
hudakz	0:a04710facbb6	3433	#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /!< ADC group injected external trigger source /
hudakz	0:a04710facbb6	3434	#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	3435	#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	3436	#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	3437
hudakz	0:a04710facbb6	3438	#define ADC_CR2_JEXTTRIG_Pos (15U)
hudakz	0:a04710facbb6	3439	#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	3440	#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /!< ADC group injected external trigger enable /
hudakz	0:a04710facbb6	3441
hudakz	0:a04710facbb6	3442	#define ADC_CR2_EXTSEL_Pos (17U)
hudakz	0:a04710facbb6	3443	#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /!< 0x000E0000 /
hudakz	0:a04710facbb6	3444	#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /!< ADC group regular external trigger source /
hudakz	0:a04710facbb6	3445	#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	3446	#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	3447	#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	3448
hudakz	0:a04710facbb6	3449	#define ADC_CR2_EXTTRIG_Pos (20U)
hudakz	0:a04710facbb6	3450	#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	3451	#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /!< ADC group regular external trigger enable /
hudakz	0:a04710facbb6	3452	#define ADC_CR2_JSWSTART_Pos (21U)
hudakz	0:a04710facbb6	3453	#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	3454	#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /!< ADC group injected conversion start /
hudakz	0:a04710facbb6	3455	#define ADC_CR2_SWSTART_Pos (22U)
hudakz	0:a04710facbb6	3456	#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	3457	#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /!< ADC group regular conversion start /
hudakz	0:a04710facbb6	3458	#define ADC_CR2_TSVREFE_Pos (23U)
hudakz	0:a04710facbb6	3459	#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	3460	#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /!< ADC internal path to VrefInt and temperature sensor enable /
hudakz	0:a04710facbb6	3461
hudakz	0:a04710facbb6	3462	/**************** Bit definition for ADC_SMPR1 register *****************/
hudakz	0:a04710facbb6	3463	#define ADC_SMPR1_SMP10_Pos (0U)
hudakz	0:a04710facbb6	3464	#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /!< 0x00000007 /
hudakz	0:a04710facbb6	3465	#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /!< ADC channel 10 sampling time selection /
hudakz	0:a04710facbb6	3466	#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	3467	#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	3468	#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	3469
hudakz	0:a04710facbb6	3470	#define ADC_SMPR1_SMP11_Pos (3U)
hudakz	0:a04710facbb6	3471	#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /!< 0x00000038 /
hudakz	0:a04710facbb6	3472	#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /!< ADC channel 11 sampling time selection /
hudakz	0:a04710facbb6	3473	#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	3474	#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	3475	#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	3476
hudakz	0:a04710facbb6	3477	#define ADC_SMPR1_SMP12_Pos (6U)
hudakz	0:a04710facbb6	3478	#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /!< 0x000001C0 /
hudakz	0:a04710facbb6	3479	#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /!< ADC channel 12 sampling time selection /
hudakz	0:a04710facbb6	3480	#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	3481	#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	3482	#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	3483
hudakz	0:a04710facbb6	3484	#define ADC_SMPR1_SMP13_Pos (9U)
hudakz	0:a04710facbb6	3485	#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /!< 0x00000E00 /
hudakz	0:a04710facbb6	3486	#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /!< ADC channel 13 sampling time selection /
hudakz	0:a04710facbb6	3487	#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	3488	#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	3489	#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	3490
hudakz	0:a04710facbb6	3491	#define ADC_SMPR1_SMP14_Pos (12U)
hudakz	0:a04710facbb6	3492	#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /!< 0x00007000 /
hudakz	0:a04710facbb6	3493	#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /!< ADC channel 14 sampling time selection /
hudakz	0:a04710facbb6	3494	#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	3495	#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	3496	#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	3497
hudakz	0:a04710facbb6	3498	#define ADC_SMPR1_SMP15_Pos (15U)
hudakz	0:a04710facbb6	3499	#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /!< 0x00038000 /
hudakz	0:a04710facbb6	3500	#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /!< ADC channel 15 sampling time selection /
hudakz	0:a04710facbb6	3501	#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	3502	#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	3503	#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	3504
hudakz	0:a04710facbb6	3505	#define ADC_SMPR1_SMP16_Pos (18U)
hudakz	0:a04710facbb6	3506	#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /!< 0x001C0000 /
hudakz	0:a04710facbb6	3507	#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /!< ADC channel 16 sampling time selection /
hudakz	0:a04710facbb6	3508	#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	3509	#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	3510	#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	3511
hudakz	0:a04710facbb6	3512	#define ADC_SMPR1_SMP17_Pos (21U)
hudakz	0:a04710facbb6	3513	#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /!< 0x00E00000 /
hudakz	0:a04710facbb6	3514	#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /!< ADC channel 17 sampling time selection /
hudakz	0:a04710facbb6	3515	#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	3516	#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	3517	#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	3518
hudakz	0:a04710facbb6	3519	/**************** Bit definition for ADC_SMPR2 register *****************/
hudakz	0:a04710facbb6	3520	#define ADC_SMPR2_SMP0_Pos (0U)
hudakz	0:a04710facbb6	3521	#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /!< 0x00000007 /
hudakz	0:a04710facbb6	3522	#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /!< ADC channel 0 sampling time selection /
hudakz	0:a04710facbb6	3523	#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	3524	#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	3525	#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	3526
hudakz	0:a04710facbb6	3527	#define ADC_SMPR2_SMP1_Pos (3U)
hudakz	0:a04710facbb6	3528	#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /!< 0x00000038 /
hudakz	0:a04710facbb6	3529	#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /!< ADC channel 1 sampling time selection /
hudakz	0:a04710facbb6	3530	#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	3531	#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	3532	#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	3533
hudakz	0:a04710facbb6	3534	#define ADC_SMPR2_SMP2_Pos (6U)
hudakz	0:a04710facbb6	3535	#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /!< 0x000001C0 /
hudakz	0:a04710facbb6	3536	#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /!< ADC channel 2 sampling time selection /
hudakz	0:a04710facbb6	3537	#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	3538	#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	3539	#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	3540
hudakz	0:a04710facbb6	3541	#define ADC_SMPR2_SMP3_Pos (9U)
hudakz	0:a04710facbb6	3542	#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /!< 0x00000E00 /
hudakz	0:a04710facbb6	3543	#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /!< ADC channel 3 sampling time selection /
hudakz	0:a04710facbb6	3544	#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	3545	#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	3546	#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	3547
hudakz	0:a04710facbb6	3548	#define ADC_SMPR2_SMP4_Pos (12U)
hudakz	0:a04710facbb6	3549	#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /!< 0x00007000 /
hudakz	0:a04710facbb6	3550	#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /!< ADC channel 4 sampling time selection /
hudakz	0:a04710facbb6	3551	#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	3552	#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	3553	#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	3554
hudakz	0:a04710facbb6	3555	#define ADC_SMPR2_SMP5_Pos (15U)
hudakz	0:a04710facbb6	3556	#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /!< 0x00038000 /
hudakz	0:a04710facbb6	3557	#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /!< ADC channel 5 sampling time selection /
hudakz	0:a04710facbb6	3558	#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	3559	#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	3560	#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	3561
hudakz	0:a04710facbb6	3562	#define ADC_SMPR2_SMP6_Pos (18U)
hudakz	0:a04710facbb6	3563	#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /!< 0x001C0000 /
hudakz	0:a04710facbb6	3564	#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /!< ADC channel 6 sampling time selection /
hudakz	0:a04710facbb6	3565	#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	3566	#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	3567	#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	3568
hudakz	0:a04710facbb6	3569	#define ADC_SMPR2_SMP7_Pos (21U)
hudakz	0:a04710facbb6	3570	#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /!< 0x00E00000 /
hudakz	0:a04710facbb6	3571	#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /!< ADC channel 7 sampling time selection /
hudakz	0:a04710facbb6	3572	#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	3573	#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	3574	#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	3575
hudakz	0:a04710facbb6	3576	#define ADC_SMPR2_SMP8_Pos (24U)
hudakz	0:a04710facbb6	3577	#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /!< 0x07000000 /
hudakz	0:a04710facbb6	3578	#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /!< ADC channel 8 sampling time selection /
hudakz	0:a04710facbb6	3579	#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	3580	#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	3581	#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	3582
hudakz	0:a04710facbb6	3583	#define ADC_SMPR2_SMP9_Pos (27U)
hudakz	0:a04710facbb6	3584	#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /!< 0x38000000 /
hudakz	0:a04710facbb6	3585	#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /!< ADC channel 9 sampling time selection /
hudakz	0:a04710facbb6	3586	#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	3587	#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	3588	#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	3589
hudakz	0:a04710facbb6	3590	/**************** Bit definition for ADC_JOFR1 register *****************/
hudakz	0:a04710facbb6	3591	#define ADC_JOFR1_JOFFSET1_Pos (0U)
hudakz	0:a04710facbb6	3592	#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /!< 0x00000FFF /
hudakz	0:a04710facbb6	3593	#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /!< ADC group injected sequencer rank 1 offset value /
hudakz	0:a04710facbb6	3594
hudakz	0:a04710facbb6	3595	/**************** Bit definition for ADC_JOFR2 register *****************/
hudakz	0:a04710facbb6	3596	#define ADC_JOFR2_JOFFSET2_Pos (0U)
hudakz	0:a04710facbb6	3597	#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /!< 0x00000FFF /
hudakz	0:a04710facbb6	3598	#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /!< ADC group injected sequencer rank 2 offset value /
hudakz	0:a04710facbb6	3599
hudakz	0:a04710facbb6	3600	/**************** Bit definition for ADC_JOFR3 register *****************/
hudakz	0:a04710facbb6	3601	#define ADC_JOFR3_JOFFSET3_Pos (0U)
hudakz	0:a04710facbb6	3602	#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /!< 0x00000FFF /
hudakz	0:a04710facbb6	3603	#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /!< ADC group injected sequencer rank 3 offset value /
hudakz	0:a04710facbb6	3604
hudakz	0:a04710facbb6	3605	/**************** Bit definition for ADC_JOFR4 register *****************/
hudakz	0:a04710facbb6	3606	#define ADC_JOFR4_JOFFSET4_Pos (0U)
hudakz	0:a04710facbb6	3607	#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /!< 0x00000FFF /
hudakz	0:a04710facbb6	3608	#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /!< ADC group injected sequencer rank 4 offset value /
hudakz	0:a04710facbb6	3609
hudakz	0:a04710facbb6	3610	/***************** Bit definition for ADC_HTR register ******************/
hudakz	0:a04710facbb6	3611	#define ADC_HTR_HT_Pos (0U)
hudakz	0:a04710facbb6	3612	#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /!< 0x00000FFF /
hudakz	0:a04710facbb6	3613	#define ADC_HTR_HT ADC_HTR_HT_Msk /!< ADC analog watchdog 1 threshold high /
hudakz	0:a04710facbb6	3614
hudakz	0:a04710facbb6	3615	/***************** Bit definition for ADC_LTR register ******************/
hudakz	0:a04710facbb6	3616	#define ADC_LTR_LT_Pos (0U)
hudakz	0:a04710facbb6	3617	#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /!< 0x00000FFF /
hudakz	0:a04710facbb6	3618	#define ADC_LTR_LT ADC_LTR_LT_Msk /!< ADC analog watchdog 1 threshold low /
hudakz	0:a04710facbb6	3619
hudakz	0:a04710facbb6	3620	/***************** Bit definition for ADC_SQR1 register *****************/
hudakz	0:a04710facbb6	3621	#define ADC_SQR1_SQ13_Pos (0U)
hudakz	0:a04710facbb6	3622	#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /!< 0x0000001F /
hudakz	0:a04710facbb6	3623	#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /!< ADC group regular sequencer rank 13 /
hudakz	0:a04710facbb6	3624	#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	3625	#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	3626	#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	3627	#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	3628	#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	3629
hudakz	0:a04710facbb6	3630	#define ADC_SQR1_SQ14_Pos (5U)
hudakz	0:a04710facbb6	3631	#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /!< 0x000003E0 /
hudakz	0:a04710facbb6	3632	#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /!< ADC group regular sequencer rank 14 /
hudakz	0:a04710facbb6	3633	#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	3634	#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	3635	#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	3636	#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	3637	#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	3638
hudakz	0:a04710facbb6	3639	#define ADC_SQR1_SQ15_Pos (10U)
hudakz	0:a04710facbb6	3640	#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /!< 0x00007C00 /
hudakz	0:a04710facbb6	3641	#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /!< ADC group regular sequencer rank 15 /
hudakz	0:a04710facbb6	3642	#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	3643	#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	3644	#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	3645	#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	3646	#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	3647
hudakz	0:a04710facbb6	3648	#define ADC_SQR1_SQ16_Pos (15U)
hudakz	0:a04710facbb6	3649	#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /!< 0x000F8000 /
hudakz	0:a04710facbb6	3650	#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /!< ADC group regular sequencer rank 16 /
hudakz	0:a04710facbb6	3651	#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	3652	#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	3653	#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	3654	#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	3655	#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	3656
hudakz	0:a04710facbb6	3657	#define ADC_SQR1_L_Pos (20U)
hudakz	0:a04710facbb6	3658	#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /!< 0x00F00000 /
hudakz	0:a04710facbb6	3659	#define ADC_SQR1_L ADC_SQR1_L_Msk /!< ADC group regular sequencer scan length /
hudakz	0:a04710facbb6	3660	#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	3661	#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	3662	#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	3663	#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	3664
hudakz	0:a04710facbb6	3665	/***************** Bit definition for ADC_SQR2 register *****************/
hudakz	0:a04710facbb6	3666	#define ADC_SQR2_SQ7_Pos (0U)
hudakz	0:a04710facbb6	3667	#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /!< 0x0000001F /
hudakz	0:a04710facbb6	3668	#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /!< ADC group regular sequencer rank 7 /
hudakz	0:a04710facbb6	3669	#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	3670	#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	3671	#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	3672	#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	3673	#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	3674
hudakz	0:a04710facbb6	3675	#define ADC_SQR2_SQ8_Pos (5U)
hudakz	0:a04710facbb6	3676	#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /!< 0x000003E0 /
hudakz	0:a04710facbb6	3677	#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /!< ADC group regular sequencer rank 8 /
hudakz	0:a04710facbb6	3678	#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	3679	#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	3680	#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	3681	#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	3682	#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	3683
hudakz	0:a04710facbb6	3684	#define ADC_SQR2_SQ9_Pos (10U)
hudakz	0:a04710facbb6	3685	#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /!< 0x00007C00 /
hudakz	0:a04710facbb6	3686	#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /!< ADC group regular sequencer rank 9 /
hudakz	0:a04710facbb6	3687	#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	3688	#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	3689	#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	3690	#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	3691	#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	3692
hudakz	0:a04710facbb6	3693	#define ADC_SQR2_SQ10_Pos (15U)
hudakz	0:a04710facbb6	3694	#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /!< 0x000F8000 /
hudakz	0:a04710facbb6	3695	#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /!< ADC group regular sequencer rank 10 /
hudakz	0:a04710facbb6	3696	#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	3697	#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	3698	#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	3699	#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	3700	#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	3701
hudakz	0:a04710facbb6	3702	#define ADC_SQR2_SQ11_Pos (20U)
hudakz	0:a04710facbb6	3703	#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /!< 0x01F00000 /
hudakz	0:a04710facbb6	3704	#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /!< ADC group regular sequencer rank 1 /
hudakz	0:a04710facbb6	3705	#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	3706	#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	3707	#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	3708	#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	3709	#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	3710
hudakz	0:a04710facbb6	3711	#define ADC_SQR2_SQ12_Pos (25U)
hudakz	0:a04710facbb6	3712	#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /!< 0x3E000000 /
hudakz	0:a04710facbb6	3713	#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /!< ADC group regular sequencer rank 12 /
hudakz	0:a04710facbb6	3714	#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	3715	#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	3716	#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	3717	#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	3718	#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	3719
hudakz	0:a04710facbb6	3720	/***************** Bit definition for ADC_SQR3 register *****************/
hudakz	0:a04710facbb6	3721	#define ADC_SQR3_SQ1_Pos (0U)
hudakz	0:a04710facbb6	3722	#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /!< 0x0000001F /
hudakz	0:a04710facbb6	3723	#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /!< ADC group regular sequencer rank 1 /
hudakz	0:a04710facbb6	3724	#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	3725	#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	3726	#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	3727	#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	3728	#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	3729
hudakz	0:a04710facbb6	3730	#define ADC_SQR3_SQ2_Pos (5U)
hudakz	0:a04710facbb6	3731	#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /!< 0x000003E0 /
hudakz	0:a04710facbb6	3732	#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /!< ADC group regular sequencer rank 2 /
hudakz	0:a04710facbb6	3733	#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	3734	#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	3735	#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	3736	#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	3737	#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	3738
hudakz	0:a04710facbb6	3739	#define ADC_SQR3_SQ3_Pos (10U)
hudakz	0:a04710facbb6	3740	#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /!< 0x00007C00 /
hudakz	0:a04710facbb6	3741	#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /!< ADC group regular sequencer rank 3 /
hudakz	0:a04710facbb6	3742	#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	3743	#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	3744	#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	3745	#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	3746	#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	3747
hudakz	0:a04710facbb6	3748	#define ADC_SQR3_SQ4_Pos (15U)
hudakz	0:a04710facbb6	3749	#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /!< 0x000F8000 /
hudakz	0:a04710facbb6	3750	#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /!< ADC group regular sequencer rank 4 /
hudakz	0:a04710facbb6	3751	#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	3752	#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	3753	#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	3754	#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	3755	#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	3756
hudakz	0:a04710facbb6	3757	#define ADC_SQR3_SQ5_Pos (20U)
hudakz	0:a04710facbb6	3758	#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /!< 0x01F00000 /
hudakz	0:a04710facbb6	3759	#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /!< ADC group regular sequencer rank 5 /
hudakz	0:a04710facbb6	3760	#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	3761	#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	3762	#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	3763	#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	3764	#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	3765
hudakz	0:a04710facbb6	3766	#define ADC_SQR3_SQ6_Pos (25U)
hudakz	0:a04710facbb6	3767	#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /!< 0x3E000000 /
hudakz	0:a04710facbb6	3768	#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /!< ADC group regular sequencer rank 6 /
hudakz	0:a04710facbb6	3769	#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	3770	#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	3771	#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	3772	#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	3773	#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	3774
hudakz	0:a04710facbb6	3775	/***************** Bit definition for ADC_JSQR register *****************/
hudakz	0:a04710facbb6	3776	#define ADC_JSQR_JSQ1_Pos (0U)
hudakz	0:a04710facbb6	3777	#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /!< 0x0000001F /
hudakz	0:a04710facbb6	3778	#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /!< ADC group injected sequencer rank 1 /
hudakz	0:a04710facbb6	3779	#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	3780	#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	3781	#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	3782	#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	3783	#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	3784
hudakz	0:a04710facbb6	3785	#define ADC_JSQR_JSQ2_Pos (5U)
hudakz	0:a04710facbb6	3786	#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /!< 0x000003E0 /
hudakz	0:a04710facbb6	3787	#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /!< ADC group injected sequencer rank 2 /
hudakz	0:a04710facbb6	3788	#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	3789	#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	3790	#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	3791	#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	3792	#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	3793
hudakz	0:a04710facbb6	3794	#define ADC_JSQR_JSQ3_Pos (10U)
hudakz	0:a04710facbb6	3795	#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /!< 0x00007C00 /
hudakz	0:a04710facbb6	3796	#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /!< ADC group injected sequencer rank 3 /
hudakz	0:a04710facbb6	3797	#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	3798	#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	3799	#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	3800	#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	3801	#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	3802
hudakz	0:a04710facbb6	3803	#define ADC_JSQR_JSQ4_Pos (15U)
hudakz	0:a04710facbb6	3804	#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /!< 0x000F8000 /
hudakz	0:a04710facbb6	3805	#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /!< ADC group injected sequencer rank 4 /
hudakz	0:a04710facbb6	3806	#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	3807	#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	3808	#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	3809	#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	3810	#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	3811
hudakz	0:a04710facbb6	3812	#define ADC_JSQR_JL_Pos (20U)
hudakz	0:a04710facbb6	3813	#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /!< 0x00300000 /
hudakz	0:a04710facbb6	3814	#define ADC_JSQR_JL ADC_JSQR_JL_Msk /!< ADC group injected sequencer scan length /
hudakz	0:a04710facbb6	3815	#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	3816	#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	3817
hudakz	0:a04710facbb6	3818	/***************** Bit definition for ADC_JDR1 register *****************/
hudakz	0:a04710facbb6	3819	#define ADC_JDR1_JDATA_Pos (0U)
hudakz	0:a04710facbb6	3820	#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	3821	#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /!< ADC group injected sequencer rank 1 conversion data /
hudakz	0:a04710facbb6	3822
hudakz	0:a04710facbb6	3823	/***************** Bit definition for ADC_JDR2 register *****************/
hudakz	0:a04710facbb6	3824	#define ADC_JDR2_JDATA_Pos (0U)
hudakz	0:a04710facbb6	3825	#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	3826	#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /!< ADC group injected sequencer rank 2 conversion data /
hudakz	0:a04710facbb6	3827
hudakz	0:a04710facbb6	3828	/***************** Bit definition for ADC_JDR3 register *****************/
hudakz	0:a04710facbb6	3829	#define ADC_JDR3_JDATA_Pos (0U)
hudakz	0:a04710facbb6	3830	#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	3831	#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /!< ADC group injected sequencer rank 3 conversion data /
hudakz	0:a04710facbb6	3832
hudakz	0:a04710facbb6	3833	/***************** Bit definition for ADC_JDR4 register *****************/
hudakz	0:a04710facbb6	3834	#define ADC_JDR4_JDATA_Pos (0U)
hudakz	0:a04710facbb6	3835	#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	3836	#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /!< ADC group injected sequencer rank 4 conversion data /
hudakz	0:a04710facbb6	3837
hudakz	0:a04710facbb6	3838	/****************** Bit definition for ADC_DR register ******************/
hudakz	0:a04710facbb6	3839	#define ADC_DR_DATA_Pos (0U)
hudakz	0:a04710facbb6	3840	#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	3841	#define ADC_DR_DATA ADC_DR_DATA_Msk /!< ADC group regular conversion data /
hudakz	0:a04710facbb6	3842	#define ADC_DR_ADC2DATA_Pos (16U)
hudakz	0:a04710facbb6	3843	#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /!< 0xFFFF0000 /
hudakz	0:a04710facbb6	3844	#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /!< ADC group regular conversion data for ADC slave, in multimode /
hudakz	0:a04710facbb6	3845
hudakz	0:a04710facbb6	3846
hudakz	0:a04710facbb6	3847	/*****************************************************************************/
hudakz	0:a04710facbb6	3848	/* */
hudakz	0:a04710facbb6	3849	/* Timers (TIM) */
hudakz	0:a04710facbb6	3850	/* */
hudakz	0:a04710facbb6	3851	/*****************************************************************************/
hudakz	0:a04710facbb6	3852	/***************** Bit definition for TIM_CR1 register *****************/
hudakz	0:a04710facbb6	3853	#define TIM_CR1_CEN_Pos (0U)
hudakz	0:a04710facbb6	3854	#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	3855	#define TIM_CR1_CEN TIM_CR1_CEN_Msk /!<Counter enable /
hudakz	0:a04710facbb6	3856	#define TIM_CR1_UDIS_Pos (1U)
hudakz	0:a04710facbb6	3857	#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	3858	#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /!<Update disable /
hudakz	0:a04710facbb6	3859	#define TIM_CR1_URS_Pos (2U)
hudakz	0:a04710facbb6	3860	#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	3861	#define TIM_CR1_URS TIM_CR1_URS_Msk /!<Update request source /
hudakz	0:a04710facbb6	3862	#define TIM_CR1_OPM_Pos (3U)
hudakz	0:a04710facbb6	3863	#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	3864	#define TIM_CR1_OPM TIM_CR1_OPM_Msk /!<One pulse mode /
hudakz	0:a04710facbb6	3865	#define TIM_CR1_DIR_Pos (4U)
hudakz	0:a04710facbb6	3866	#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	3867	#define TIM_CR1_DIR TIM_CR1_DIR_Msk /!<Direction /
hudakz	0:a04710facbb6	3868
hudakz	0:a04710facbb6	3869	#define TIM_CR1_CMS_Pos (5U)
hudakz	0:a04710facbb6	3870	#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /!< 0x00000060 /
hudakz	0:a04710facbb6	3871	#define TIM_CR1_CMS TIM_CR1_CMS_Msk /!<CMS[1:0] bits (Center-aligned mode selection) /
hudakz	0:a04710facbb6	3872	#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	3873	#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	3874
hudakz	0:a04710facbb6	3875	#define TIM_CR1_ARPE_Pos (7U)
hudakz	0:a04710facbb6	3876	#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	3877	#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /!<Auto-reload preload enable /
hudakz	0:a04710facbb6	3878
hudakz	0:a04710facbb6	3879	#define TIM_CR1_CKD_Pos (8U)
hudakz	0:a04710facbb6	3880	#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /!< 0x00000300 /
hudakz	0:a04710facbb6	3881	#define TIM_CR1_CKD TIM_CR1_CKD_Msk /!<CKD[1:0] bits (clock division) /
hudakz	0:a04710facbb6	3882	#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	3883	#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	3884
hudakz	0:a04710facbb6	3885	/***************** Bit definition for TIM_CR2 register *****************/
hudakz	0:a04710facbb6	3886	#define TIM_CR2_CCPC_Pos (0U)
hudakz	0:a04710facbb6	3887	#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	3888	#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /!<Capture/Compare Preloaded Control /
hudakz	0:a04710facbb6	3889	#define TIM_CR2_CCUS_Pos (2U)
hudakz	0:a04710facbb6	3890	#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	3891	#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /!<Capture/Compare Control Update Selection /
hudakz	0:a04710facbb6	3892	#define TIM_CR2_CCDS_Pos (3U)
hudakz	0:a04710facbb6	3893	#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	3894	#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /!<Capture/Compare DMA Selection /
hudakz	0:a04710facbb6	3895
hudakz	0:a04710facbb6	3896	#define TIM_CR2_MMS_Pos (4U)
hudakz	0:a04710facbb6	3897	#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /!< 0x00000070 /
hudakz	0:a04710facbb6	3898	#define TIM_CR2_MMS TIM_CR2_MMS_Msk /!<MMS[2:0] bits (Master Mode Selection) /
hudakz	0:a04710facbb6	3899	#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	3900	#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	3901	#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	3902
hudakz	0:a04710facbb6	3903	#define TIM_CR2_TI1S_Pos (7U)
hudakz	0:a04710facbb6	3904	#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	3905	#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /!<TI1 Selection /
hudakz	0:a04710facbb6	3906	#define TIM_CR2_OIS1_Pos (8U)
hudakz	0:a04710facbb6	3907	#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	3908	#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /!<Output Idle state 1 (OC1 output) /
hudakz	0:a04710facbb6	3909	#define TIM_CR2_OIS1N_Pos (9U)
hudakz	0:a04710facbb6	3910	#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	3911	#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /!<Output Idle state 1 (OC1N output) /
hudakz	0:a04710facbb6	3912	#define TIM_CR2_OIS2_Pos (10U)
hudakz	0:a04710facbb6	3913	#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	3914	#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /!<Output Idle state 2 (OC2 output) /
hudakz	0:a04710facbb6	3915	#define TIM_CR2_OIS2N_Pos (11U)
hudakz	0:a04710facbb6	3916	#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	3917	#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /!<Output Idle state 2 (OC2N output) /
hudakz	0:a04710facbb6	3918	#define TIM_CR2_OIS3_Pos (12U)
hudakz	0:a04710facbb6	3919	#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	3920	#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /!<Output Idle state 3 (OC3 output) /
hudakz	0:a04710facbb6	3921	#define TIM_CR2_OIS3N_Pos (13U)
hudakz	0:a04710facbb6	3922	#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	3923	#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /!<Output Idle state 3 (OC3N output) /
hudakz	0:a04710facbb6	3924	#define TIM_CR2_OIS4_Pos (14U)
hudakz	0:a04710facbb6	3925	#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	3926	#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /!<Output Idle state 4 (OC4 output) /
hudakz	0:a04710facbb6	3927
hudakz	0:a04710facbb6	3928	/***************** Bit definition for TIM_SMCR register ****************/
hudakz	0:a04710facbb6	3929	#define TIM_SMCR_SMS_Pos (0U)
hudakz	0:a04710facbb6	3930	#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /!< 0x00000007 /
hudakz	0:a04710facbb6	3931	#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /!<SMS[2:0] bits (Slave mode selection) /
hudakz	0:a04710facbb6	3932	#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	3933	#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	3934	#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	3935
hudakz	0:a04710facbb6	3936	#define TIM_SMCR_TS_Pos (4U)
hudakz	0:a04710facbb6	3937	#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /!< 0x00000070 /
hudakz	0:a04710facbb6	3938	#define TIM_SMCR_TS TIM_SMCR_TS_Msk /!<TS[2:0] bits (Trigger selection) /
hudakz	0:a04710facbb6	3939	#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	3940	#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	3941	#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	3942
hudakz	0:a04710facbb6	3943	#define TIM_SMCR_MSM_Pos (7U)
hudakz	0:a04710facbb6	3944	#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	3945	#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /!<Master/slave mode /
hudakz	0:a04710facbb6	3946
hudakz	0:a04710facbb6	3947	#define TIM_SMCR_ETF_Pos (8U)
hudakz	0:a04710facbb6	3948	#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /!< 0x00000F00 /
hudakz	0:a04710facbb6	3949	#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /!<ETF[3:0] bits (External trigger filter) /
hudakz	0:a04710facbb6	3950	#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	3951	#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	3952	#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	3953	#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	3954
hudakz	0:a04710facbb6	3955	#define TIM_SMCR_ETPS_Pos (12U)
hudakz	0:a04710facbb6	3956	#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /!< 0x00003000 /
hudakz	0:a04710facbb6	3957	#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /!<ETPS[1:0] bits (External trigger prescaler) /
hudakz	0:a04710facbb6	3958	#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	3959	#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	3960
hudakz	0:a04710facbb6	3961	#define TIM_SMCR_ECE_Pos (14U)
hudakz	0:a04710facbb6	3962	#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	3963	#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /!<External clock enable /
hudakz	0:a04710facbb6	3964	#define TIM_SMCR_ETP_Pos (15U)
hudakz	0:a04710facbb6	3965	#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	3966	#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /!<External trigger polarity /
hudakz	0:a04710facbb6	3967
hudakz	0:a04710facbb6	3968	/***************** Bit definition for TIM_DIER register ****************/
hudakz	0:a04710facbb6	3969	#define TIM_DIER_UIE_Pos (0U)
hudakz	0:a04710facbb6	3970	#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	3971	#define TIM_DIER_UIE TIM_DIER_UIE_Msk /!<Update interrupt enable /
hudakz	0:a04710facbb6	3972	#define TIM_DIER_CC1IE_Pos (1U)
hudakz	0:a04710facbb6	3973	#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	3974	#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /!<Capture/Compare 1 interrupt enable /
hudakz	0:a04710facbb6	3975	#define TIM_DIER_CC2IE_Pos (2U)
hudakz	0:a04710facbb6	3976	#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	3977	#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /!<Capture/Compare 2 interrupt enable /
hudakz	0:a04710facbb6	3978	#define TIM_DIER_CC3IE_Pos (3U)
hudakz	0:a04710facbb6	3979	#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	3980	#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /!<Capture/Compare 3 interrupt enable /
hudakz	0:a04710facbb6	3981	#define TIM_DIER_CC4IE_Pos (4U)
hudakz	0:a04710facbb6	3982	#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	3983	#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /!<Capture/Compare 4 interrupt enable /
hudakz	0:a04710facbb6	3984	#define TIM_DIER_COMIE_Pos (5U)
hudakz	0:a04710facbb6	3985	#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	3986	#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /!<COM interrupt enable /
hudakz	0:a04710facbb6	3987	#define TIM_DIER_TIE_Pos (6U)
hudakz	0:a04710facbb6	3988	#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	3989	#define TIM_DIER_TIE TIM_DIER_TIE_Msk /!<Trigger interrupt enable /
hudakz	0:a04710facbb6	3990	#define TIM_DIER_BIE_Pos (7U)
hudakz	0:a04710facbb6	3991	#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	3992	#define TIM_DIER_BIE TIM_DIER_BIE_Msk /!<Break interrupt enable /
hudakz	0:a04710facbb6	3993	#define TIM_DIER_UDE_Pos (8U)
hudakz	0:a04710facbb6	3994	#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	3995	#define TIM_DIER_UDE TIM_DIER_UDE_Msk /!<Update DMA request enable /
hudakz	0:a04710facbb6	3996	#define TIM_DIER_CC1DE_Pos (9U)
hudakz	0:a04710facbb6	3997	#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	3998	#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /!<Capture/Compare 1 DMA request enable /
hudakz	0:a04710facbb6	3999	#define TIM_DIER_CC2DE_Pos (10U)
hudakz	0:a04710facbb6	4000	#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	4001	#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /!<Capture/Compare 2 DMA request enable /
hudakz	0:a04710facbb6	4002	#define TIM_DIER_CC3DE_Pos (11U)
hudakz	0:a04710facbb6	4003	#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	4004	#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /!<Capture/Compare 3 DMA request enable /
hudakz	0:a04710facbb6	4005	#define TIM_DIER_CC4DE_Pos (12U)
hudakz	0:a04710facbb6	4006	#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	4007	#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /!<Capture/Compare 4 DMA request enable /
hudakz	0:a04710facbb6	4008	#define TIM_DIER_COMDE_Pos (13U)
hudakz	0:a04710facbb6	4009	#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	4010	#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /!<COM DMA request enable /
hudakz	0:a04710facbb6	4011	#define TIM_DIER_TDE_Pos (14U)
hudakz	0:a04710facbb6	4012	#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	4013	#define TIM_DIER_TDE TIM_DIER_TDE_Msk /!<Trigger DMA request enable /
hudakz	0:a04710facbb6	4014
hudakz	0:a04710facbb6	4015	/****************** Bit definition for TIM_SR register *****************/
hudakz	0:a04710facbb6	4016	#define TIM_SR_UIF_Pos (0U)
hudakz	0:a04710facbb6	4017	#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	4018	#define TIM_SR_UIF TIM_SR_UIF_Msk /!<Update interrupt Flag /
hudakz	0:a04710facbb6	4019	#define TIM_SR_CC1IF_Pos (1U)
hudakz	0:a04710facbb6	4020	#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	4021	#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /!<Capture/Compare 1 interrupt Flag /
hudakz	0:a04710facbb6	4022	#define TIM_SR_CC2IF_Pos (2U)
hudakz	0:a04710facbb6	4023	#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	4024	#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /!<Capture/Compare 2 interrupt Flag /
hudakz	0:a04710facbb6	4025	#define TIM_SR_CC3IF_Pos (3U)
hudakz	0:a04710facbb6	4026	#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	4027	#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /!<Capture/Compare 3 interrupt Flag /
hudakz	0:a04710facbb6	4028	#define TIM_SR_CC4IF_Pos (4U)
hudakz	0:a04710facbb6	4029	#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	4030	#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /!<Capture/Compare 4 interrupt Flag /
hudakz	0:a04710facbb6	4031	#define TIM_SR_COMIF_Pos (5U)
hudakz	0:a04710facbb6	4032	#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	4033	#define TIM_SR_COMIF TIM_SR_COMIF_Msk /!<COM interrupt Flag /
hudakz	0:a04710facbb6	4034	#define TIM_SR_TIF_Pos (6U)
hudakz	0:a04710facbb6	4035	#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	4036	#define TIM_SR_TIF TIM_SR_TIF_Msk /!<Trigger interrupt Flag /
hudakz	0:a04710facbb6	4037	#define TIM_SR_BIF_Pos (7U)
hudakz	0:a04710facbb6	4038	#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	4039	#define TIM_SR_BIF TIM_SR_BIF_Msk /!<Break interrupt Flag /
hudakz	0:a04710facbb6	4040	#define TIM_SR_CC1OF_Pos (9U)
hudakz	0:a04710facbb6	4041	#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	4042	#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /!<Capture/Compare 1 Overcapture Flag /
hudakz	0:a04710facbb6	4043	#define TIM_SR_CC2OF_Pos (10U)
hudakz	0:a04710facbb6	4044	#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	4045	#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /!<Capture/Compare 2 Overcapture Flag /
hudakz	0:a04710facbb6	4046	#define TIM_SR_CC3OF_Pos (11U)
hudakz	0:a04710facbb6	4047	#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	4048	#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /!<Capture/Compare 3 Overcapture Flag /
hudakz	0:a04710facbb6	4049	#define TIM_SR_CC4OF_Pos (12U)
hudakz	0:a04710facbb6	4050	#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	4051	#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /!<Capture/Compare 4 Overcapture Flag /
hudakz	0:a04710facbb6	4052
hudakz	0:a04710facbb6	4053	/***************** Bit definition for TIM_EGR register *****************/
hudakz	0:a04710facbb6	4054	#define TIM_EGR_UG_Pos (0U)
hudakz	0:a04710facbb6	4055	#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	4056	#define TIM_EGR_UG TIM_EGR_UG_Msk /!<Update Generation /
hudakz	0:a04710facbb6	4057	#define TIM_EGR_CC1G_Pos (1U)
hudakz	0:a04710facbb6	4058	#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	4059	#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /!<Capture/Compare 1 Generation /
hudakz	0:a04710facbb6	4060	#define TIM_EGR_CC2G_Pos (2U)
hudakz	0:a04710facbb6	4061	#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	4062	#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /!<Capture/Compare 2 Generation /
hudakz	0:a04710facbb6	4063	#define TIM_EGR_CC3G_Pos (3U)
hudakz	0:a04710facbb6	4064	#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	4065	#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /!<Capture/Compare 3 Generation /
hudakz	0:a04710facbb6	4066	#define TIM_EGR_CC4G_Pos (4U)
hudakz	0:a04710facbb6	4067	#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	4068	#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /!<Capture/Compare 4 Generation /
hudakz	0:a04710facbb6	4069	#define TIM_EGR_COMG_Pos (5U)
hudakz	0:a04710facbb6	4070	#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	4071	#define TIM_EGR_COMG TIM_EGR_COMG_Msk /!<Capture/Compare Control Update Generation /
hudakz	0:a04710facbb6	4072	#define TIM_EGR_TG_Pos (6U)
hudakz	0:a04710facbb6	4073	#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	4074	#define TIM_EGR_TG TIM_EGR_TG_Msk /!<Trigger Generation /
hudakz	0:a04710facbb6	4075	#define TIM_EGR_BG_Pos (7U)
hudakz	0:a04710facbb6	4076	#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	4077	#define TIM_EGR_BG TIM_EGR_BG_Msk /!<Break Generation /
hudakz	0:a04710facbb6	4078
hudakz	0:a04710facbb6	4079	/**************** Bit definition for TIM_CCMR1 register ****************/
hudakz	0:a04710facbb6	4080	#define TIM_CCMR1_CC1S_Pos (0U)
hudakz	0:a04710facbb6	4081	#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /!< 0x00000003 /
hudakz	0:a04710facbb6	4082	#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
hudakz	0:a04710facbb6	4083	#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	4084	#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	4085
hudakz	0:a04710facbb6	4086	#define TIM_CCMR1_OC1FE_Pos (2U)
hudakz	0:a04710facbb6	4087	#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	4088	#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /!<Output Compare 1 Fast enable /
hudakz	0:a04710facbb6	4089	#define TIM_CCMR1_OC1PE_Pos (3U)
hudakz	0:a04710facbb6	4090	#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	4091	#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /!<Output Compare 1 Preload enable /
hudakz	0:a04710facbb6	4092
hudakz	0:a04710facbb6	4093	#define TIM_CCMR1_OC1M_Pos (4U)
hudakz	0:a04710facbb6	4094	#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /!< 0x00000070 /
hudakz	0:a04710facbb6	4095	#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /!<OC1M[2:0] bits (Output Compare 1 Mode) /
hudakz	0:a04710facbb6	4096	#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	4097	#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	4098	#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	4099
hudakz	0:a04710facbb6	4100	#define TIM_CCMR1_OC1CE_Pos (7U)
hudakz	0:a04710facbb6	4101	#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	4102	#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /!<Output Compare 1Clear Enable /
hudakz	0:a04710facbb6	4103
hudakz	0:a04710facbb6	4104	#define TIM_CCMR1_CC2S_Pos (8U)
hudakz	0:a04710facbb6	4105	#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /!< 0x00000300 /
hudakz	0:a04710facbb6	4106	#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
hudakz	0:a04710facbb6	4107	#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	4108	#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	4109
hudakz	0:a04710facbb6	4110	#define TIM_CCMR1_OC2FE_Pos (10U)
hudakz	0:a04710facbb6	4111	#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	4112	#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /!<Output Compare 2 Fast enable /
hudakz	0:a04710facbb6	4113	#define TIM_CCMR1_OC2PE_Pos (11U)
hudakz	0:a04710facbb6	4114	#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	4115	#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /!<Output Compare 2 Preload enable /
hudakz	0:a04710facbb6	4116
hudakz	0:a04710facbb6	4117	#define TIM_CCMR1_OC2M_Pos (12U)
hudakz	0:a04710facbb6	4118	#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /!< 0x00007000 /
hudakz	0:a04710facbb6	4119	#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /!<OC2M[2:0] bits (Output Compare 2 Mode) /
hudakz	0:a04710facbb6	4120	#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	4121	#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	4122	#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	4123
hudakz	0:a04710facbb6	4124	#define TIM_CCMR1_OC2CE_Pos (15U)
hudakz	0:a04710facbb6	4125	#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	4126	#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /!<Output Compare 2 Clear Enable /
hudakz	0:a04710facbb6	4127
hudakz	0:a04710facbb6	4128	/---------------------------------------------------------------------------/
hudakz	0:a04710facbb6	4129
hudakz	0:a04710facbb6	4130	#define TIM_CCMR1_IC1PSC_Pos (2U)
hudakz	0:a04710facbb6	4131	#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /!< 0x0000000C /
hudakz	0:a04710facbb6	4132	#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
hudakz	0:a04710facbb6	4133	#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	4134	#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	4135
hudakz	0:a04710facbb6	4136	#define TIM_CCMR1_IC1F_Pos (4U)
hudakz	0:a04710facbb6	4137	#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /!< 0x000000F0 /
hudakz	0:a04710facbb6	4138	#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /!<IC1F[3:0] bits (Input Capture 1 Filter) /
hudakz	0:a04710facbb6	4139	#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	4140	#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	4141	#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	4142	#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	4143
hudakz	0:a04710facbb6	4144	#define TIM_CCMR1_IC2PSC_Pos (10U)
hudakz	0:a04710facbb6	4145	#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000C00 /
hudakz	0:a04710facbb6	4146	#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
hudakz	0:a04710facbb6	4147	#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	4148	#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	4149
hudakz	0:a04710facbb6	4150	#define TIM_CCMR1_IC2F_Pos (12U)
hudakz	0:a04710facbb6	4151	#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /!< 0x0000F000 /
hudakz	0:a04710facbb6	4152	#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /!<IC2F[3:0] bits (Input Capture 2 Filter) /
hudakz	0:a04710facbb6	4153	#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	4154	#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	4155	#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	4156	#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	4157
hudakz	0:a04710facbb6	4158	/**************** Bit definition for TIM_CCMR2 register ****************/
hudakz	0:a04710facbb6	4159	#define TIM_CCMR2_CC3S_Pos (0U)
hudakz	0:a04710facbb6	4160	#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /!< 0x00000003 /
hudakz	0:a04710facbb6	4161	#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
hudakz	0:a04710facbb6	4162	#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	4163	#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	4164
hudakz	0:a04710facbb6	4165	#define TIM_CCMR2_OC3FE_Pos (2U)
hudakz	0:a04710facbb6	4166	#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	4167	#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /!<Output Compare 3 Fast enable /
hudakz	0:a04710facbb6	4168	#define TIM_CCMR2_OC3PE_Pos (3U)
hudakz	0:a04710facbb6	4169	#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	4170	#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /!<Output Compare 3 Preload enable /
hudakz	0:a04710facbb6	4171
hudakz	0:a04710facbb6	4172	#define TIM_CCMR2_OC3M_Pos (4U)
hudakz	0:a04710facbb6	4173	#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /!< 0x00000070 /
hudakz	0:a04710facbb6	4174	#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /!<OC3M[2:0] bits (Output Compare 3 Mode) /
hudakz	0:a04710facbb6	4175	#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	4176	#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	4177	#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	4178
hudakz	0:a04710facbb6	4179	#define TIM_CCMR2_OC3CE_Pos (7U)
hudakz	0:a04710facbb6	4180	#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	4181	#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /!<Output Compare 3 Clear Enable /
hudakz	0:a04710facbb6	4182
hudakz	0:a04710facbb6	4183	#define TIM_CCMR2_CC4S_Pos (8U)
hudakz	0:a04710facbb6	4184	#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /!< 0x00000300 /
hudakz	0:a04710facbb6	4185	#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
hudakz	0:a04710facbb6	4186	#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	4187	#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	4188
hudakz	0:a04710facbb6	4189	#define TIM_CCMR2_OC4FE_Pos (10U)
hudakz	0:a04710facbb6	4190	#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	4191	#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /!<Output Compare 4 Fast enable /
hudakz	0:a04710facbb6	4192	#define TIM_CCMR2_OC4PE_Pos (11U)
hudakz	0:a04710facbb6	4193	#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	4194	#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /!<Output Compare 4 Preload enable /
hudakz	0:a04710facbb6	4195
hudakz	0:a04710facbb6	4196	#define TIM_CCMR2_OC4M_Pos (12U)
hudakz	0:a04710facbb6	4197	#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /!< 0x00007000 /
hudakz	0:a04710facbb6	4198	#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /!<OC4M[2:0] bits (Output Compare 4 Mode) /
hudakz	0:a04710facbb6	4199	#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	4200	#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	4201	#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	4202
hudakz	0:a04710facbb6	4203	#define TIM_CCMR2_OC4CE_Pos (15U)
hudakz	0:a04710facbb6	4204	#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	4205	#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /!<Output Compare 4 Clear Enable /
hudakz	0:a04710facbb6	4206
hudakz	0:a04710facbb6	4207	/---------------------------------------------------------------------------/
hudakz	0:a04710facbb6	4208
hudakz	0:a04710facbb6	4209	#define TIM_CCMR2_IC3PSC_Pos (2U)
hudakz	0:a04710facbb6	4210	#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /!< 0x0000000C /
hudakz	0:a04710facbb6	4211	#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
hudakz	0:a04710facbb6	4212	#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	4213	#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	4214
hudakz	0:a04710facbb6	4215	#define TIM_CCMR2_IC3F_Pos (4U)
hudakz	0:a04710facbb6	4216	#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /!< 0x000000F0 /
hudakz	0:a04710facbb6	4217	#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /!<IC3F[3:0] bits (Input Capture 3 Filter) /
hudakz	0:a04710facbb6	4218	#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	4219	#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	4220	#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	4221	#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	4222
hudakz	0:a04710facbb6	4223	#define TIM_CCMR2_IC4PSC_Pos (10U)
hudakz	0:a04710facbb6	4224	#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000C00 /
hudakz	0:a04710facbb6	4225	#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
hudakz	0:a04710facbb6	4226	#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	4227	#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	4228
hudakz	0:a04710facbb6	4229	#define TIM_CCMR2_IC4F_Pos (12U)
hudakz	0:a04710facbb6	4230	#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /!< 0x0000F000 /
hudakz	0:a04710facbb6	4231	#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /!<IC4F[3:0] bits (Input Capture 4 Filter) /
hudakz	0:a04710facbb6	4232	#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	4233	#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	4234	#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	4235	#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	4236
hudakz	0:a04710facbb6	4237	/***************** Bit definition for TIM_CCER register ****************/
hudakz	0:a04710facbb6	4238	#define TIM_CCER_CC1E_Pos (0U)
hudakz	0:a04710facbb6	4239	#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	4240	#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /!<Capture/Compare 1 output enable /
hudakz	0:a04710facbb6	4241	#define TIM_CCER_CC1P_Pos (1U)
hudakz	0:a04710facbb6	4242	#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	4243	#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /!<Capture/Compare 1 output Polarity /
hudakz	0:a04710facbb6	4244	#define TIM_CCER_CC1NE_Pos (2U)
hudakz	0:a04710facbb6	4245	#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	4246	#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /!<Capture/Compare 1 Complementary output enable /
hudakz	0:a04710facbb6	4247	#define TIM_CCER_CC1NP_Pos (3U)
hudakz	0:a04710facbb6	4248	#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	4249	#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /!<Capture/Compare 1 Complementary output Polarity /
hudakz	0:a04710facbb6	4250	#define TIM_CCER_CC2E_Pos (4U)
hudakz	0:a04710facbb6	4251	#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	4252	#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /!<Capture/Compare 2 output enable /
hudakz	0:a04710facbb6	4253	#define TIM_CCER_CC2P_Pos (5U)
hudakz	0:a04710facbb6	4254	#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	4255	#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /!<Capture/Compare 2 output Polarity /
hudakz	0:a04710facbb6	4256	#define TIM_CCER_CC2NE_Pos (6U)
hudakz	0:a04710facbb6	4257	#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	4258	#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /!<Capture/Compare 2 Complementary output enable /
hudakz	0:a04710facbb6	4259	#define TIM_CCER_CC2NP_Pos (7U)
hudakz	0:a04710facbb6	4260	#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	4261	#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /!<Capture/Compare 2 Complementary output Polarity /
hudakz	0:a04710facbb6	4262	#define TIM_CCER_CC3E_Pos (8U)
hudakz	0:a04710facbb6	4263	#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	4264	#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /!<Capture/Compare 3 output enable /
hudakz	0:a04710facbb6	4265	#define TIM_CCER_CC3P_Pos (9U)
hudakz	0:a04710facbb6	4266	#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	4267	#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /!<Capture/Compare 3 output Polarity /
hudakz	0:a04710facbb6	4268	#define TIM_CCER_CC3NE_Pos (10U)
hudakz	0:a04710facbb6	4269	#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	4270	#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /!<Capture/Compare 3 Complementary output enable /
hudakz	0:a04710facbb6	4271	#define TIM_CCER_CC3NP_Pos (11U)
hudakz	0:a04710facbb6	4272	#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	4273	#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /!<Capture/Compare 3 Complementary output Polarity /
hudakz	0:a04710facbb6	4274	#define TIM_CCER_CC4E_Pos (12U)
hudakz	0:a04710facbb6	4275	#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	4276	#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /!<Capture/Compare 4 output enable /
hudakz	0:a04710facbb6	4277	#define TIM_CCER_CC4P_Pos (13U)
hudakz	0:a04710facbb6	4278	#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	4279	#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /!<Capture/Compare 4 output Polarity /
hudakz	0:a04710facbb6	4280
hudakz	0:a04710facbb6	4281	/***************** Bit definition for TIM_CNT register *****************/
hudakz	0:a04710facbb6	4282	#define TIM_CNT_CNT_Pos (0U)
hudakz	0:a04710facbb6	4283	#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /!< 0xFFFFFFFF /
hudakz	0:a04710facbb6	4284	#define TIM_CNT_CNT TIM_CNT_CNT_Msk /!<Counter Value /
hudakz	0:a04710facbb6	4285
hudakz	0:a04710facbb6	4286	/***************** Bit definition for TIM_PSC register *****************/
hudakz	0:a04710facbb6	4287	#define TIM_PSC_PSC_Pos (0U)
hudakz	0:a04710facbb6	4288	#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	4289	#define TIM_PSC_PSC TIM_PSC_PSC_Msk /!<Prescaler Value /
hudakz	0:a04710facbb6	4290
hudakz	0:a04710facbb6	4291	/***************** Bit definition for TIM_ARR register *****************/
hudakz	0:a04710facbb6	4292	#define TIM_ARR_ARR_Pos (0U)
hudakz	0:a04710facbb6	4293	#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /!< 0xFFFFFFFF /
hudakz	0:a04710facbb6	4294	#define TIM_ARR_ARR TIM_ARR_ARR_Msk /!<actual auto-reload Value /
hudakz	0:a04710facbb6	4295
hudakz	0:a04710facbb6	4296	/***************** Bit definition for TIM_RCR register *****************/
hudakz	0:a04710facbb6	4297	#define TIM_RCR_REP_Pos (0U)
hudakz	0:a04710facbb6	4298	#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /!< 0x000000FF /
hudakz	0:a04710facbb6	4299	#define TIM_RCR_REP TIM_RCR_REP_Msk /!<Repetition Counter Value /
hudakz	0:a04710facbb6	4300
hudakz	0:a04710facbb6	4301	/***************** Bit definition for TIM_CCR1 register ****************/
hudakz	0:a04710facbb6	4302	#define TIM_CCR1_CCR1_Pos (0U)
hudakz	0:a04710facbb6	4303	#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	4304	#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /!<Capture/Compare 1 Value /
hudakz	0:a04710facbb6	4305
hudakz	0:a04710facbb6	4306	/***************** Bit definition for TIM_CCR2 register ****************/
hudakz	0:a04710facbb6	4307	#define TIM_CCR2_CCR2_Pos (0U)
hudakz	0:a04710facbb6	4308	#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	4309	#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /!<Capture/Compare 2 Value /
hudakz	0:a04710facbb6	4310
hudakz	0:a04710facbb6	4311	/***************** Bit definition for TIM_CCR3 register ****************/
hudakz	0:a04710facbb6	4312	#define TIM_CCR3_CCR3_Pos (0U)
hudakz	0:a04710facbb6	4313	#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	4314	#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /!<Capture/Compare 3 Value /
hudakz	0:a04710facbb6	4315
hudakz	0:a04710facbb6	4316	/***************** Bit definition for TIM_CCR4 register ****************/
hudakz	0:a04710facbb6	4317	#define TIM_CCR4_CCR4_Pos (0U)
hudakz	0:a04710facbb6	4318	#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	4319	#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /!<Capture/Compare 4 Value /
hudakz	0:a04710facbb6	4320
hudakz	0:a04710facbb6	4321	/***************** Bit definition for TIM_BDTR register ****************/
hudakz	0:a04710facbb6	4322	#define TIM_BDTR_DTG_Pos (0U)
hudakz	0:a04710facbb6	4323	#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /!< 0x000000FF /
hudakz	0:a04710facbb6	4324	#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /!<DTG[0:7] bits (Dead-Time Generator set-up) /
hudakz	0:a04710facbb6	4325	#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	4326	#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	4327	#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	4328	#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	4329	#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	4330	#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	4331	#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	4332	#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	4333
hudakz	0:a04710facbb6	4334	#define TIM_BDTR_LOCK_Pos (8U)
hudakz	0:a04710facbb6	4335	#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /!< 0x00000300 /
hudakz	0:a04710facbb6	4336	#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /!<LOCK[1:0] bits (Lock Configuration) /
hudakz	0:a04710facbb6	4337	#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	4338	#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	4339
hudakz	0:a04710facbb6	4340	#define TIM_BDTR_OSSI_Pos (10U)
hudakz	0:a04710facbb6	4341	#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	4342	#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /!<Off-State Selection for Idle mode /
hudakz	0:a04710facbb6	4343	#define TIM_BDTR_OSSR_Pos (11U)
hudakz	0:a04710facbb6	4344	#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	4345	#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /!<Off-State Selection for Run mode /
hudakz	0:a04710facbb6	4346	#define TIM_BDTR_BKE_Pos (12U)
hudakz	0:a04710facbb6	4347	#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	4348	#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /!<Break enable /
hudakz	0:a04710facbb6	4349	#define TIM_BDTR_BKP_Pos (13U)
hudakz	0:a04710facbb6	4350	#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	4351	#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /!<Break Polarity /
hudakz	0:a04710facbb6	4352	#define TIM_BDTR_AOE_Pos (14U)
hudakz	0:a04710facbb6	4353	#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	4354	#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /!<Automatic Output enable /
hudakz	0:a04710facbb6	4355	#define TIM_BDTR_MOE_Pos (15U)
hudakz	0:a04710facbb6	4356	#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	4357	#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /!<Main Output enable /
hudakz	0:a04710facbb6	4358
hudakz	0:a04710facbb6	4359	/***************** Bit definition for TIM_DCR register *****************/
hudakz	0:a04710facbb6	4360	#define TIM_DCR_DBA_Pos (0U)
hudakz	0:a04710facbb6	4361	#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /!< 0x0000001F /
hudakz	0:a04710facbb6	4362	#define TIM_DCR_DBA TIM_DCR_DBA_Msk /!<DBA[4:0] bits (DMA Base Address) /
hudakz	0:a04710facbb6	4363	#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	4364	#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	4365	#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	4366	#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	4367	#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	4368
hudakz	0:a04710facbb6	4369	#define TIM_DCR_DBL_Pos (8U)
hudakz	0:a04710facbb6	4370	#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /!< 0x00001F00 /
hudakz	0:a04710facbb6	4371	#define TIM_DCR_DBL TIM_DCR_DBL_Msk /!<DBL[4:0] bits (DMA Burst Length) /
hudakz	0:a04710facbb6	4372	#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	4373	#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	4374	#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	4375	#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	4376	#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	4377
hudakz	0:a04710facbb6	4378	/***************** Bit definition for TIM_DMAR register ****************/
hudakz	0:a04710facbb6	4379	#define TIM_DMAR_DMAB_Pos (0U)
hudakz	0:a04710facbb6	4380	#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	4381	#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /!<DMA register for burst accesses /
hudakz	0:a04710facbb6	4382
hudakz	0:a04710facbb6	4383	/******************************************************************************/
hudakz	0:a04710facbb6	4384	/* */
hudakz	0:a04710facbb6	4385	/* Real-Time Clock */
hudakz	0:a04710facbb6	4386	/* */
hudakz	0:a04710facbb6	4387	/******************************************************************************/
hudakz	0:a04710facbb6	4388
hudakz	0:a04710facbb6	4389	/***************** Bit definition for RTC_CRH register ******************/
hudakz	0:a04710facbb6	4390	#define RTC_CRH_SECIE_Pos (0U)
hudakz	0:a04710facbb6	4391	#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	4392	#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /!< Second Interrupt Enable /
hudakz	0:a04710facbb6	4393	#define RTC_CRH_ALRIE_Pos (1U)
hudakz	0:a04710facbb6	4394	#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	4395	#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /!< Alarm Interrupt Enable /
hudakz	0:a04710facbb6	4396	#define RTC_CRH_OWIE_Pos (2U)
hudakz	0:a04710facbb6	4397	#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	4398	#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /!< OverfloW Interrupt Enable /
hudakz	0:a04710facbb6	4399
hudakz	0:a04710facbb6	4400	/***************** Bit definition for RTC_CRL register ******************/
hudakz	0:a04710facbb6	4401	#define RTC_CRL_SECF_Pos (0U)
hudakz	0:a04710facbb6	4402	#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	4403	#define RTC_CRL_SECF RTC_CRL_SECF_Msk /!< Second Flag /
hudakz	0:a04710facbb6	4404	#define RTC_CRL_ALRF_Pos (1U)
hudakz	0:a04710facbb6	4405	#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	4406	#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /!< Alarm Flag /
hudakz	0:a04710facbb6	4407	#define RTC_CRL_OWF_Pos (2U)
hudakz	0:a04710facbb6	4408	#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	4409	#define RTC_CRL_OWF RTC_CRL_OWF_Msk /!< OverfloW Flag /
hudakz	0:a04710facbb6	4410	#define RTC_CRL_RSF_Pos (3U)
hudakz	0:a04710facbb6	4411	#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	4412	#define RTC_CRL_RSF RTC_CRL_RSF_Msk /!< Registers Synchronized Flag /
hudakz	0:a04710facbb6	4413	#define RTC_CRL_CNF_Pos (4U)
hudakz	0:a04710facbb6	4414	#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	4415	#define RTC_CRL_CNF RTC_CRL_CNF_Msk /!< Configuration Flag /
hudakz	0:a04710facbb6	4416	#define RTC_CRL_RTOFF_Pos (5U)
hudakz	0:a04710facbb6	4417	#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	4418	#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /!< RTC operation OFF /
hudakz	0:a04710facbb6	4419
hudakz	0:a04710facbb6	4420	/***************** Bit definition for RTC_PRLH register *****************/
hudakz	0:a04710facbb6	4421	#define RTC_PRLH_PRL_Pos (0U)
hudakz	0:a04710facbb6	4422	#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	4423	#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /!< RTC Prescaler Reload Value High /
hudakz	0:a04710facbb6	4424
hudakz	0:a04710facbb6	4425	/***************** Bit definition for RTC_PRLL register *****************/
hudakz	0:a04710facbb6	4426	#define RTC_PRLL_PRL_Pos (0U)
hudakz	0:a04710facbb6	4427	#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	4428	#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /!< RTC Prescaler Reload Value Low /
hudakz	0:a04710facbb6	4429
hudakz	0:a04710facbb6	4430	/***************** Bit definition for RTC_DIVH register *****************/
hudakz	0:a04710facbb6	4431	#define RTC_DIVH_RTC_DIV_Pos (0U)
hudakz	0:a04710facbb6	4432	#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	4433	#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /!< RTC Clock Divider High /
hudakz	0:a04710facbb6	4434
hudakz	0:a04710facbb6	4435	/***************** Bit definition for RTC_DIVL register *****************/
hudakz	0:a04710facbb6	4436	#define RTC_DIVL_RTC_DIV_Pos (0U)
hudakz	0:a04710facbb6	4437	#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	4438	#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /!< RTC Clock Divider Low /
hudakz	0:a04710facbb6	4439
hudakz	0:a04710facbb6	4440	/***************** Bit definition for RTC_CNTH register *****************/
hudakz	0:a04710facbb6	4441	#define RTC_CNTH_RTC_CNT_Pos (0U)
hudakz	0:a04710facbb6	4442	#define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	4443	#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /!< RTC Counter High /
hudakz	0:a04710facbb6	4444
hudakz	0:a04710facbb6	4445	/***************** Bit definition for RTC_CNTL register *****************/
hudakz	0:a04710facbb6	4446	#define RTC_CNTL_RTC_CNT_Pos (0U)
hudakz	0:a04710facbb6	4447	#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	4448	#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /!< RTC Counter Low /
hudakz	0:a04710facbb6	4449
hudakz	0:a04710facbb6	4450	/***************** Bit definition for RTC_ALRH register *****************/
hudakz	0:a04710facbb6	4451	#define RTC_ALRH_RTC_ALR_Pos (0U)
hudakz	0:a04710facbb6	4452	#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	4453	#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /!< RTC Alarm High /
hudakz	0:a04710facbb6	4454
hudakz	0:a04710facbb6	4455	/***************** Bit definition for RTC_ALRL register *****************/
hudakz	0:a04710facbb6	4456	#define RTC_ALRL_RTC_ALR_Pos (0U)
hudakz	0:a04710facbb6	4457	#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	4458	#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /!< RTC Alarm Low /
hudakz	0:a04710facbb6	4459
hudakz	0:a04710facbb6	4460	/******************************************************************************/
hudakz	0:a04710facbb6	4461	/* */
hudakz	0:a04710facbb6	4462	/* Independent WATCHDOG (IWDG) */
hudakz	0:a04710facbb6	4463	/* */
hudakz	0:a04710facbb6	4464	/******************************************************************************/
hudakz	0:a04710facbb6	4465
hudakz	0:a04710facbb6	4466	/***************** Bit definition for IWDG_KR register ******************/
hudakz	0:a04710facbb6	4467	#define IWDG_KR_KEY_Pos (0U)
hudakz	0:a04710facbb6	4468	#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	4469	#define IWDG_KR_KEY IWDG_KR_KEY_Msk /!< Key value (write only, read 0000h) /
hudakz	0:a04710facbb6	4470
hudakz	0:a04710facbb6	4471	/***************** Bit definition for IWDG_PR register ******************/
hudakz	0:a04710facbb6	4472	#define IWDG_PR_PR_Pos (0U)
hudakz	0:a04710facbb6	4473	#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /!< 0x00000007 /
hudakz	0:a04710facbb6	4474	#define IWDG_PR_PR IWDG_PR_PR_Msk /!< PR[2:0] (Prescaler divider) /
hudakz	0:a04710facbb6	4475	#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	4476	#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	4477	#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	4478
hudakz	0:a04710facbb6	4479	/***************** Bit definition for IWDG_RLR register *****************/
hudakz	0:a04710facbb6	4480	#define IWDG_RLR_RL_Pos (0U)
hudakz	0:a04710facbb6	4481	#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /!< 0x00000FFF /
hudakz	0:a04710facbb6	4482	#define IWDG_RLR_RL IWDG_RLR_RL_Msk /!< Watchdog counter reload value /
hudakz	0:a04710facbb6	4483
hudakz	0:a04710facbb6	4484	/***************** Bit definition for IWDG_SR register ******************/
hudakz	0:a04710facbb6	4485	#define IWDG_SR_PVU_Pos (0U)
hudakz	0:a04710facbb6	4486	#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	4487	#define IWDG_SR_PVU IWDG_SR_PVU_Msk /!< Watchdog prescaler value update /
hudakz	0:a04710facbb6	4488	#define IWDG_SR_RVU_Pos (1U)
hudakz	0:a04710facbb6	4489	#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	4490	#define IWDG_SR_RVU IWDG_SR_RVU_Msk /!< Watchdog counter reload value update /
hudakz	0:a04710facbb6	4491
hudakz	0:a04710facbb6	4492	/******************************************************************************/
hudakz	0:a04710facbb6	4493	/* */
hudakz	0:a04710facbb6	4494	/* Window WATCHDOG (WWDG) */
hudakz	0:a04710facbb6	4495	/* */
hudakz	0:a04710facbb6	4496	/******************************************************************************/
hudakz	0:a04710facbb6	4497
hudakz	0:a04710facbb6	4498	/***************** Bit definition for WWDG_CR register ******************/
hudakz	0:a04710facbb6	4499	#define WWDG_CR_T_Pos (0U)
hudakz	0:a04710facbb6	4500	#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /!< 0x0000007F /
hudakz	0:a04710facbb6	4501	#define WWDG_CR_T WWDG_CR_T_Msk /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
hudakz	0:a04710facbb6	4502	#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	4503	#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	4504	#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	4505	#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	4506	#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	4507	#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	4508	#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	4509
hudakz	0:a04710facbb6	4510	/* Legacy defines */
hudakz	0:a04710facbb6	4511	#define WWDG_CR_T0 WWDG_CR_T_0
hudakz	0:a04710facbb6	4512	#define WWDG_CR_T1 WWDG_CR_T_1
hudakz	0:a04710facbb6	4513	#define WWDG_CR_T2 WWDG_CR_T_2
hudakz	0:a04710facbb6	4514	#define WWDG_CR_T3 WWDG_CR_T_3
hudakz	0:a04710facbb6	4515	#define WWDG_CR_T4 WWDG_CR_T_4
hudakz	0:a04710facbb6	4516	#define WWDG_CR_T5 WWDG_CR_T_5
hudakz	0:a04710facbb6	4517	#define WWDG_CR_T6 WWDG_CR_T_6
hudakz	0:a04710facbb6	4518
hudakz	0:a04710facbb6	4519	#define WWDG_CR_WDGA_Pos (7U)
hudakz	0:a04710facbb6	4520	#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	4521	#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /!< Activation bit /
hudakz	0:a04710facbb6	4522
hudakz	0:a04710facbb6	4523	/***************** Bit definition for WWDG_CFR register *****************/
hudakz	0:a04710facbb6	4524	#define WWDG_CFR_W_Pos (0U)
hudakz	0:a04710facbb6	4525	#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /!< 0x0000007F /
hudakz	0:a04710facbb6	4526	#define WWDG_CFR_W WWDG_CFR_W_Msk /!< W[6:0] bits (7-bit window value) /
hudakz	0:a04710facbb6	4527	#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	4528	#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	4529	#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	4530	#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	4531	#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	4532	#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	4533	#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	4534
hudakz	0:a04710facbb6	4535	/* Legacy defines */
hudakz	0:a04710facbb6	4536	#define WWDG_CFR_W0 WWDG_CFR_W_0
hudakz	0:a04710facbb6	4537	#define WWDG_CFR_W1 WWDG_CFR_W_1
hudakz	0:a04710facbb6	4538	#define WWDG_CFR_W2 WWDG_CFR_W_2
hudakz	0:a04710facbb6	4539	#define WWDG_CFR_W3 WWDG_CFR_W_3
hudakz	0:a04710facbb6	4540	#define WWDG_CFR_W4 WWDG_CFR_W_4
hudakz	0:a04710facbb6	4541	#define WWDG_CFR_W5 WWDG_CFR_W_5
hudakz	0:a04710facbb6	4542	#define WWDG_CFR_W6 WWDG_CFR_W_6
hudakz	0:a04710facbb6	4543
hudakz	0:a04710facbb6	4544	#define WWDG_CFR_WDGTB_Pos (7U)
hudakz	0:a04710facbb6	4545	#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /!< 0x00000180 /
hudakz	0:a04710facbb6	4546	#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /!< WDGTB[1:0] bits (Timer Base) /
hudakz	0:a04710facbb6	4547	#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	4548	#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	4549
hudakz	0:a04710facbb6	4550	/* Legacy defines */
hudakz	0:a04710facbb6	4551	#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
hudakz	0:a04710facbb6	4552	#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
hudakz	0:a04710facbb6	4553
hudakz	0:a04710facbb6	4554	#define WWDG_CFR_EWI_Pos (9U)
hudakz	0:a04710facbb6	4555	#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	4556	#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /!< Early Wakeup Interrupt /
hudakz	0:a04710facbb6	4557
hudakz	0:a04710facbb6	4558	/***************** Bit definition for WWDG_SR register ******************/
hudakz	0:a04710facbb6	4559	#define WWDG_SR_EWIF_Pos (0U)
hudakz	0:a04710facbb6	4560	#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	4561	#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /!< Early Wakeup Interrupt Flag /
hudakz	0:a04710facbb6	4562
hudakz	0:a04710facbb6	4563
hudakz	0:a04710facbb6	4564	/******************************************************************************/
hudakz	0:a04710facbb6	4565	/* */
hudakz	0:a04710facbb6	4566	/* SD host Interface */
hudakz	0:a04710facbb6	4567	/* */
hudakz	0:a04710facbb6	4568	/******************************************************************************/
hudakz	0:a04710facbb6	4569
hudakz	0:a04710facbb6	4570	/**************** Bit definition for SDIO_POWER register ****************/
hudakz	0:a04710facbb6	4571	#define SDIO_POWER_PWRCTRL_Pos (0U)
hudakz	0:a04710facbb6	4572	#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /!< 0x00000003 /
hudakz	0:a04710facbb6	4573	#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /!< PWRCTRL[1:0] bits (Power supply control bits) /
hudakz	0:a04710facbb6	4574	#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /!< 0x01 /
hudakz	0:a04710facbb6	4575	#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /!< 0x02 /
hudakz	0:a04710facbb6	4576
hudakz	0:a04710facbb6	4577	/**************** Bit definition for SDIO_CLKCR register ****************/
hudakz	0:a04710facbb6	4578	#define SDIO_CLKCR_CLKDIV_Pos (0U)
hudakz	0:a04710facbb6	4579	#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /!< 0x000000FF /
hudakz	0:a04710facbb6	4580	#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /!< Clock divide factor /
hudakz	0:a04710facbb6	4581	#define SDIO_CLKCR_CLKEN_Pos (8U)
hudakz	0:a04710facbb6	4582	#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	4583	#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /!< Clock enable bit /
hudakz	0:a04710facbb6	4584	#define SDIO_CLKCR_PWRSAV_Pos (9U)
hudakz	0:a04710facbb6	4585	#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	4586	#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /!< Power saving configuration bit /
hudakz	0:a04710facbb6	4587	#define SDIO_CLKCR_BYPASS_Pos (10U)
hudakz	0:a04710facbb6	4588	#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	4589	#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /!< Clock divider bypass enable bit /
hudakz	0:a04710facbb6	4590
hudakz	0:a04710facbb6	4591	#define SDIO_CLKCR_WIDBUS_Pos (11U)
hudakz	0:a04710facbb6	4592	#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /!< 0x00001800 /
hudakz	0:a04710facbb6	4593	#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /!< WIDBUS[1:0] bits (Wide bus mode enable bit) /
hudakz	0:a04710facbb6	4594	#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /!< 0x0800 /
hudakz	0:a04710facbb6	4595	#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /!< 0x1000 /
hudakz	0:a04710facbb6	4596
hudakz	0:a04710facbb6	4597	#define SDIO_CLKCR_NEGEDGE_Pos (13U)
hudakz	0:a04710facbb6	4598	#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	4599	#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /!< SDIO_CK dephasing selection bit /
hudakz	0:a04710facbb6	4600	#define SDIO_CLKCR_HWFC_EN_Pos (14U)
hudakz	0:a04710facbb6	4601	#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	4602	#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /!< HW Flow Control enable /
hudakz	0:a04710facbb6	4603
hudakz	0:a04710facbb6	4604	/***************** Bit definition for SDIO_ARG register *****************/
hudakz	0:a04710facbb6	4605	#define SDIO_ARG_CMDARG_Pos (0U)
hudakz	0:a04710facbb6	4606	#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /!< 0xFFFFFFFF /
hudakz	0:a04710facbb6	4607	#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /!< Command argument /
hudakz	0:a04710facbb6	4608
hudakz	0:a04710facbb6	4609	/***************** Bit definition for SDIO_CMD register *****************/
hudakz	0:a04710facbb6	4610	#define SDIO_CMD_CMDINDEX_Pos (0U)
hudakz	0:a04710facbb6	4611	#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /!< 0x0000003F /
hudakz	0:a04710facbb6	4612	#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /!< Command Index /
hudakz	0:a04710facbb6	4613
hudakz	0:a04710facbb6	4614	#define SDIO_CMD_WAITRESP_Pos (6U)
hudakz	0:a04710facbb6	4615	#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /!< 0x000000C0 /
hudakz	0:a04710facbb6	4616	#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /!< WAITRESP[1:0] bits (Wait for response bits) /
hudakz	0:a04710facbb6	4617	#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /!< 0x0040 /
hudakz	0:a04710facbb6	4618	#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /!< 0x0080 /
hudakz	0:a04710facbb6	4619
hudakz	0:a04710facbb6	4620	#define SDIO_CMD_WAITINT_Pos (8U)
hudakz	0:a04710facbb6	4621	#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	4622	#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /!< CPSM Waits for Interrupt Request /
hudakz	0:a04710facbb6	4623	#define SDIO_CMD_WAITPEND_Pos (9U)
hudakz	0:a04710facbb6	4624	#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	4625	#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /!< CPSM Waits for ends of data transfer (CmdPend internal signal) /
hudakz	0:a04710facbb6	4626	#define SDIO_CMD_CPSMEN_Pos (10U)
hudakz	0:a04710facbb6	4627	#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	4628	#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /!< Command path state machine (CPSM) Enable bit /
hudakz	0:a04710facbb6	4629	#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
hudakz	0:a04710facbb6	4630	#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	4631	#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /!< SD I/O suspend command /
hudakz	0:a04710facbb6	4632	#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
hudakz	0:a04710facbb6	4633	#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	4634	#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /!< Enable CMD completion /
hudakz	0:a04710facbb6	4635	#define SDIO_CMD_NIEN_Pos (13U)
hudakz	0:a04710facbb6	4636	#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	4637	#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /!< Not Interrupt Enable /
hudakz	0:a04710facbb6	4638	#define SDIO_CMD_CEATACMD_Pos (14U)
hudakz	0:a04710facbb6	4639	#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	4640	#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /!< CE-ATA command /
hudakz	0:a04710facbb6	4641
hudakz	0:a04710facbb6	4642	/*************** Bit definition for SDIO_RESPCMD register ***************/
hudakz	0:a04710facbb6	4643	#define SDIO_RESPCMD_RESPCMD_Pos (0U)
hudakz	0:a04710facbb6	4644	#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /!< 0x0000003F /
hudakz	0:a04710facbb6	4645	#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /!< Response command index /
hudakz	0:a04710facbb6	4646
hudakz	0:a04710facbb6	4647	/**************** Bit definition for SDIO_RESP0 register ****************/
hudakz	0:a04710facbb6	4648	#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
hudakz	0:a04710facbb6	4649	#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /!< 0xFFFFFFFF /
hudakz	0:a04710facbb6	4650	#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /!< Card Status /
hudakz	0:a04710facbb6	4651
hudakz	0:a04710facbb6	4652	/**************** Bit definition for SDIO_RESP1 register ****************/
hudakz	0:a04710facbb6	4653	#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
hudakz	0:a04710facbb6	4654	#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /!< 0xFFFFFFFF /
hudakz	0:a04710facbb6	4655	#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /!< Card Status /
hudakz	0:a04710facbb6	4656
hudakz	0:a04710facbb6	4657	/**************** Bit definition for SDIO_RESP2 register ****************/
hudakz	0:a04710facbb6	4658	#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
hudakz	0:a04710facbb6	4659	#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /!< 0xFFFFFFFF /
hudakz	0:a04710facbb6	4660	#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /!< Card Status /
hudakz	0:a04710facbb6	4661
hudakz	0:a04710facbb6	4662	/**************** Bit definition for SDIO_RESP3 register ****************/
hudakz	0:a04710facbb6	4663	#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
hudakz	0:a04710facbb6	4664	#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /!< 0xFFFFFFFF /
hudakz	0:a04710facbb6	4665	#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /!< Card Status /
hudakz	0:a04710facbb6	4666
hudakz	0:a04710facbb6	4667	/**************** Bit definition for SDIO_RESP4 register ****************/
hudakz	0:a04710facbb6	4668	#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
hudakz	0:a04710facbb6	4669	#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /!< 0xFFFFFFFF /
hudakz	0:a04710facbb6	4670	#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /!< Card Status /
hudakz	0:a04710facbb6	4671
hudakz	0:a04710facbb6	4672	/**************** Bit definition for SDIO_DTIMER register ***************/
hudakz	0:a04710facbb6	4673	#define SDIO_DTIMER_DATATIME_Pos (0U)
hudakz	0:a04710facbb6	4674	#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /!< 0xFFFFFFFF /
hudakz	0:a04710facbb6	4675	#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /!< Data timeout period. /
hudakz	0:a04710facbb6	4676
hudakz	0:a04710facbb6	4677	/**************** Bit definition for SDIO_DLEN register *****************/
hudakz	0:a04710facbb6	4678	#define SDIO_DLEN_DATALENGTH_Pos (0U)
hudakz	0:a04710facbb6	4679	#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /!< 0x01FFFFFF /
hudakz	0:a04710facbb6	4680	#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /!< Data length value /
hudakz	0:a04710facbb6	4681
hudakz	0:a04710facbb6	4682	/**************** Bit definition for SDIO_DCTRL register ****************/
hudakz	0:a04710facbb6	4683	#define SDIO_DCTRL_DTEN_Pos (0U)
hudakz	0:a04710facbb6	4684	#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	4685	#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /!< Data transfer enabled bit /
hudakz	0:a04710facbb6	4686	#define SDIO_DCTRL_DTDIR_Pos (1U)
hudakz	0:a04710facbb6	4687	#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	4688	#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /!< Data transfer direction selection /
hudakz	0:a04710facbb6	4689	#define SDIO_DCTRL_DTMODE_Pos (2U)
hudakz	0:a04710facbb6	4690	#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	4691	#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /!< Data transfer mode selection /
hudakz	0:a04710facbb6	4692	#define SDIO_DCTRL_DMAEN_Pos (3U)
hudakz	0:a04710facbb6	4693	#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	4694	#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /!< DMA enabled bit /
hudakz	0:a04710facbb6	4695
hudakz	0:a04710facbb6	4696	#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
hudakz	0:a04710facbb6	4697	#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /!< 0x000000F0 /
hudakz	0:a04710facbb6	4698	#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /!< DBLOCKSIZE[3:0] bits (Data block size) /
hudakz	0:a04710facbb6	4699	#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /!< 0x0010 /
hudakz	0:a04710facbb6	4700	#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /!< 0x0020 /
hudakz	0:a04710facbb6	4701	#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /!< 0x0040 /
hudakz	0:a04710facbb6	4702	#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /!< 0x0080 /
hudakz	0:a04710facbb6	4703
hudakz	0:a04710facbb6	4704	#define SDIO_DCTRL_RWSTART_Pos (8U)
hudakz	0:a04710facbb6	4705	#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	4706	#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /!< Read wait start /
hudakz	0:a04710facbb6	4707	#define SDIO_DCTRL_RWSTOP_Pos (9U)
hudakz	0:a04710facbb6	4708	#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	4709	#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /!< Read wait stop /
hudakz	0:a04710facbb6	4710	#define SDIO_DCTRL_RWMOD_Pos (10U)
hudakz	0:a04710facbb6	4711	#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	4712	#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /!< Read wait mode /
hudakz	0:a04710facbb6	4713	#define SDIO_DCTRL_SDIOEN_Pos (11U)
hudakz	0:a04710facbb6	4714	#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	4715	#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /!< SD I/O enable functions /
hudakz	0:a04710facbb6	4716
hudakz	0:a04710facbb6	4717	/**************** Bit definition for SDIO_DCOUNT register ***************/
hudakz	0:a04710facbb6	4718	#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
hudakz	0:a04710facbb6	4719	#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /!< 0x01FFFFFF /
hudakz	0:a04710facbb6	4720	#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /!< Data count value /
hudakz	0:a04710facbb6	4721
hudakz	0:a04710facbb6	4722	/**************** Bit definition for SDIO_STA register ******************/
hudakz	0:a04710facbb6	4723	#define SDIO_STA_CCRCFAIL_Pos (0U)
hudakz	0:a04710facbb6	4724	#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	4725	#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /!< Command response received (CRC check failed) /
hudakz	0:a04710facbb6	4726	#define SDIO_STA_DCRCFAIL_Pos (1U)
hudakz	0:a04710facbb6	4727	#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	4728	#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /!< Data block sent/received (CRC check failed) /
hudakz	0:a04710facbb6	4729	#define SDIO_STA_CTIMEOUT_Pos (2U)
hudakz	0:a04710facbb6	4730	#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	4731	#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /!< Command response timeout /
hudakz	0:a04710facbb6	4732	#define SDIO_STA_DTIMEOUT_Pos (3U)
hudakz	0:a04710facbb6	4733	#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	4734	#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /!< Data timeout /
hudakz	0:a04710facbb6	4735	#define SDIO_STA_TXUNDERR_Pos (4U)
hudakz	0:a04710facbb6	4736	#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	4737	#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /!< Transmit FIFO underrun error /
hudakz	0:a04710facbb6	4738	#define SDIO_STA_RXOVERR_Pos (5U)
hudakz	0:a04710facbb6	4739	#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	4740	#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /!< Received FIFO overrun error /
hudakz	0:a04710facbb6	4741	#define SDIO_STA_CMDREND_Pos (6U)
hudakz	0:a04710facbb6	4742	#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	4743	#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /!< Command response received (CRC check passed) /
hudakz	0:a04710facbb6	4744	#define SDIO_STA_CMDSENT_Pos (7U)
hudakz	0:a04710facbb6	4745	#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	4746	#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /!< Command sent (no response required) /
hudakz	0:a04710facbb6	4747	#define SDIO_STA_DATAEND_Pos (8U)
hudakz	0:a04710facbb6	4748	#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	4749	#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /!< Data end (data counter, SDIDCOUNT, is zero) /
hudakz	0:a04710facbb6	4750	#define SDIO_STA_STBITERR_Pos (9U)
hudakz	0:a04710facbb6	4751	#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	4752	#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /!< Start bit not detected on all data signals in wide bus mode /
hudakz	0:a04710facbb6	4753	#define SDIO_STA_DBCKEND_Pos (10U)
hudakz	0:a04710facbb6	4754	#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	4755	#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /!< Data block sent/received (CRC check passed) /
hudakz	0:a04710facbb6	4756	#define SDIO_STA_CMDACT_Pos (11U)
hudakz	0:a04710facbb6	4757	#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	4758	#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /!< Command transfer in progress /
hudakz	0:a04710facbb6	4759	#define SDIO_STA_TXACT_Pos (12U)
hudakz	0:a04710facbb6	4760	#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	4761	#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /!< Data transmit in progress /
hudakz	0:a04710facbb6	4762	#define SDIO_STA_RXACT_Pos (13U)
hudakz	0:a04710facbb6	4763	#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	4764	#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /!< Data receive in progress /
hudakz	0:a04710facbb6	4765	#define SDIO_STA_TXFIFOHE_Pos (14U)
hudakz	0:a04710facbb6	4766	#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	4767	#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO /
hudakz	0:a04710facbb6	4768	#define SDIO_STA_RXFIFOHF_Pos (15U)
hudakz	0:a04710facbb6	4769	#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	4770	#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /!< Receive FIFO Half Full: there are at least 8 words in the FIFO /
hudakz	0:a04710facbb6	4771	#define SDIO_STA_TXFIFOF_Pos (16U)
hudakz	0:a04710facbb6	4772	#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	4773	#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /!< Transmit FIFO full /
hudakz	0:a04710facbb6	4774	#define SDIO_STA_RXFIFOF_Pos (17U)
hudakz	0:a04710facbb6	4775	#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	4776	#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /!< Receive FIFO full /
hudakz	0:a04710facbb6	4777	#define SDIO_STA_TXFIFOE_Pos (18U)
hudakz	0:a04710facbb6	4778	#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	4779	#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /!< Transmit FIFO empty /
hudakz	0:a04710facbb6	4780	#define SDIO_STA_RXFIFOE_Pos (19U)
hudakz	0:a04710facbb6	4781	#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	4782	#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /!< Receive FIFO empty /
hudakz	0:a04710facbb6	4783	#define SDIO_STA_TXDAVL_Pos (20U)
hudakz	0:a04710facbb6	4784	#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	4785	#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /!< Data available in transmit FIFO /
hudakz	0:a04710facbb6	4786	#define SDIO_STA_RXDAVL_Pos (21U)
hudakz	0:a04710facbb6	4787	#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	4788	#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /!< Data available in receive FIFO /
hudakz	0:a04710facbb6	4789	#define SDIO_STA_SDIOIT_Pos (22U)
hudakz	0:a04710facbb6	4790	#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	4791	#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /!< SDIO interrupt received /
hudakz	0:a04710facbb6	4792	#define SDIO_STA_CEATAEND_Pos (23U)
hudakz	0:a04710facbb6	4793	#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	4794	#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /!< CE-ATA command completion signal received for CMD61 /
hudakz	0:a04710facbb6	4795
hudakz	0:a04710facbb6	4796	/***************** Bit definition for SDIO_ICR register *****************/
hudakz	0:a04710facbb6	4797	#define SDIO_ICR_CCRCFAILC_Pos (0U)
hudakz	0:a04710facbb6	4798	#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	4799	#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /!< CCRCFAIL flag clear bit /
hudakz	0:a04710facbb6	4800	#define SDIO_ICR_DCRCFAILC_Pos (1U)
hudakz	0:a04710facbb6	4801	#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	4802	#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /!< DCRCFAIL flag clear bit /
hudakz	0:a04710facbb6	4803	#define SDIO_ICR_CTIMEOUTC_Pos (2U)
hudakz	0:a04710facbb6	4804	#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	4805	#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /!< CTIMEOUT flag clear bit /
hudakz	0:a04710facbb6	4806	#define SDIO_ICR_DTIMEOUTC_Pos (3U)
hudakz	0:a04710facbb6	4807	#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	4808	#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /!< DTIMEOUT flag clear bit /
hudakz	0:a04710facbb6	4809	#define SDIO_ICR_TXUNDERRC_Pos (4U)
hudakz	0:a04710facbb6	4810	#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	4811	#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /!< TXUNDERR flag clear bit /
hudakz	0:a04710facbb6	4812	#define SDIO_ICR_RXOVERRC_Pos (5U)
hudakz	0:a04710facbb6	4813	#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	4814	#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /!< RXOVERR flag clear bit /
hudakz	0:a04710facbb6	4815	#define SDIO_ICR_CMDRENDC_Pos (6U)
hudakz	0:a04710facbb6	4816	#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	4817	#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /!< CMDREND flag clear bit /
hudakz	0:a04710facbb6	4818	#define SDIO_ICR_CMDSENTC_Pos (7U)
hudakz	0:a04710facbb6	4819	#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	4820	#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /!< CMDSENT flag clear bit /
hudakz	0:a04710facbb6	4821	#define SDIO_ICR_DATAENDC_Pos (8U)
hudakz	0:a04710facbb6	4822	#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	4823	#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /!< DATAEND flag clear bit /
hudakz	0:a04710facbb6	4824	#define SDIO_ICR_STBITERRC_Pos (9U)
hudakz	0:a04710facbb6	4825	#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	4826	#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /!< STBITERR flag clear bit /
hudakz	0:a04710facbb6	4827	#define SDIO_ICR_DBCKENDC_Pos (10U)
hudakz	0:a04710facbb6	4828	#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	4829	#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /!< DBCKEND flag clear bit /
hudakz	0:a04710facbb6	4830	#define SDIO_ICR_SDIOITC_Pos (22U)
hudakz	0:a04710facbb6	4831	#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	4832	#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /!< SDIOIT flag clear bit /
hudakz	0:a04710facbb6	4833	#define SDIO_ICR_CEATAENDC_Pos (23U)
hudakz	0:a04710facbb6	4834	#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	4835	#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /!< CEATAEND flag clear bit /
hudakz	0:a04710facbb6	4836
hudakz	0:a04710facbb6	4837	/**************** Bit definition for SDIO_MASK register *****************/
hudakz	0:a04710facbb6	4838	#define SDIO_MASK_CCRCFAILIE_Pos (0U)
hudakz	0:a04710facbb6	4839	#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	4840	#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /!< Command CRC Fail Interrupt Enable /
hudakz	0:a04710facbb6	4841	#define SDIO_MASK_DCRCFAILIE_Pos (1U)
hudakz	0:a04710facbb6	4842	#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	4843	#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /!< Data CRC Fail Interrupt Enable /
hudakz	0:a04710facbb6	4844	#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
hudakz	0:a04710facbb6	4845	#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	4846	#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /!< Command TimeOut Interrupt Enable /
hudakz	0:a04710facbb6	4847	#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
hudakz	0:a04710facbb6	4848	#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	4849	#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /!< Data TimeOut Interrupt Enable /
hudakz	0:a04710facbb6	4850	#define SDIO_MASK_TXUNDERRIE_Pos (4U)
hudakz	0:a04710facbb6	4851	#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	4852	#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /!< Tx FIFO UnderRun Error Interrupt Enable /
hudakz	0:a04710facbb6	4853	#define SDIO_MASK_RXOVERRIE_Pos (5U)
hudakz	0:a04710facbb6	4854	#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	4855	#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /!< Rx FIFO OverRun Error Interrupt Enable /
hudakz	0:a04710facbb6	4856	#define SDIO_MASK_CMDRENDIE_Pos (6U)
hudakz	0:a04710facbb6	4857	#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	4858	#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /!< Command Response Received Interrupt Enable /
hudakz	0:a04710facbb6	4859	#define SDIO_MASK_CMDSENTIE_Pos (7U)
hudakz	0:a04710facbb6	4860	#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	4861	#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /!< Command Sent Interrupt Enable /
hudakz	0:a04710facbb6	4862	#define SDIO_MASK_DATAENDIE_Pos (8U)
hudakz	0:a04710facbb6	4863	#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	4864	#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /!< Data End Interrupt Enable /
hudakz	0:a04710facbb6	4865	#define SDIO_MASK_STBITERRIE_Pos (9U)
hudakz	0:a04710facbb6	4866	#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	4867	#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /!< Start Bit Error Interrupt Enable /
hudakz	0:a04710facbb6	4868	#define SDIO_MASK_DBCKENDIE_Pos (10U)
hudakz	0:a04710facbb6	4869	#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	4870	#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /!< Data Block End Interrupt Enable /
hudakz	0:a04710facbb6	4871	#define SDIO_MASK_CMDACTIE_Pos (11U)
hudakz	0:a04710facbb6	4872	#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	4873	#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /!< Command Acting Interrupt Enable /
hudakz	0:a04710facbb6	4874	#define SDIO_MASK_TXACTIE_Pos (12U)
hudakz	0:a04710facbb6	4875	#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	4876	#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /!< Data Transmit Acting Interrupt Enable /
hudakz	0:a04710facbb6	4877	#define SDIO_MASK_RXACTIE_Pos (13U)
hudakz	0:a04710facbb6	4878	#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	4879	#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /!< Data receive acting interrupt enabled /
hudakz	0:a04710facbb6	4880	#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
hudakz	0:a04710facbb6	4881	#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	4882	#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /!< Tx FIFO Half Empty interrupt Enable /
hudakz	0:a04710facbb6	4883	#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
hudakz	0:a04710facbb6	4884	#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	4885	#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /!< Rx FIFO Half Full interrupt Enable /
hudakz	0:a04710facbb6	4886	#define SDIO_MASK_TXFIFOFIE_Pos (16U)
hudakz	0:a04710facbb6	4887	#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	4888	#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /!< Tx FIFO Full interrupt Enable /
hudakz	0:a04710facbb6	4889	#define SDIO_MASK_RXFIFOFIE_Pos (17U)
hudakz	0:a04710facbb6	4890	#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	4891	#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /!< Rx FIFO Full interrupt Enable /
hudakz	0:a04710facbb6	4892	#define SDIO_MASK_TXFIFOEIE_Pos (18U)
hudakz	0:a04710facbb6	4893	#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	4894	#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /!< Tx FIFO Empty interrupt Enable /
hudakz	0:a04710facbb6	4895	#define SDIO_MASK_RXFIFOEIE_Pos (19U)
hudakz	0:a04710facbb6	4896	#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	4897	#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /!< Rx FIFO Empty interrupt Enable /
hudakz	0:a04710facbb6	4898	#define SDIO_MASK_TXDAVLIE_Pos (20U)
hudakz	0:a04710facbb6	4899	#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	4900	#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /!< Data available in Tx FIFO interrupt Enable /
hudakz	0:a04710facbb6	4901	#define SDIO_MASK_RXDAVLIE_Pos (21U)
hudakz	0:a04710facbb6	4902	#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	4903	#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /!< Data available in Rx FIFO interrupt Enable /
hudakz	0:a04710facbb6	4904	#define SDIO_MASK_SDIOITIE_Pos (22U)
hudakz	0:a04710facbb6	4905	#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	4906	#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /!< SDIO Mode Interrupt Received interrupt Enable /
hudakz	0:a04710facbb6	4907	#define SDIO_MASK_CEATAENDIE_Pos (23U)
hudakz	0:a04710facbb6	4908	#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	4909	#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /!< CE-ATA command completion signal received Interrupt Enable /
hudakz	0:a04710facbb6	4910
hudakz	0:a04710facbb6	4911	/*************** Bit definition for SDIO_FIFOCNT register ***************/
hudakz	0:a04710facbb6	4912	#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
hudakz	0:a04710facbb6	4913	#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /!< 0x00FFFFFF /
hudakz	0:a04710facbb6	4914	#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /!< Remaining number of words to be written to or read from the FIFO /
hudakz	0:a04710facbb6	4915
hudakz	0:a04710facbb6	4916	/**************** Bit definition for SDIO_FIFO register *****************/
hudakz	0:a04710facbb6	4917	#define SDIO_FIFO_FIFODATA_Pos (0U)
hudakz	0:a04710facbb6	4918	#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /!< 0xFFFFFFFF /
hudakz	0:a04710facbb6	4919	#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /!< Receive and transmit FIFO data /
hudakz	0:a04710facbb6	4920
hudakz	0:a04710facbb6	4921	/******************************************************************************/
hudakz	0:a04710facbb6	4922	/* */
hudakz	0:a04710facbb6	4923	/* USB Device FS */
hudakz	0:a04710facbb6	4924	/* */
hudakz	0:a04710facbb6	4925	/******************************************************************************/
hudakz	0:a04710facbb6	4926
hudakz	0:a04710facbb6	4927	/!< Endpoint-specific registers /
hudakz	0:a04710facbb6	4928	#define USB_EP0R USB_BASE /!< Endpoint 0 register address /
hudakz	0:a04710facbb6	4929	#define USB_EP1R (USB_BASE + 0x00000004) /!< Endpoint 1 register address /
hudakz	0:a04710facbb6	4930	#define USB_EP2R (USB_BASE + 0x00000008) /!< Endpoint 2 register address /
hudakz	0:a04710facbb6	4931	#define USB_EP3R (USB_BASE + 0x0000000C) /!< Endpoint 3 register address /
hudakz	0:a04710facbb6	4932	#define USB_EP4R (USB_BASE + 0x00000010) /!< Endpoint 4 register address /
hudakz	0:a04710facbb6	4933	#define USB_EP5R (USB_BASE + 0x00000014) /!< Endpoint 5 register address /
hudakz	0:a04710facbb6	4934	#define USB_EP6R (USB_BASE + 0x00000018) /!< Endpoint 6 register address /
hudakz	0:a04710facbb6	4935	#define USB_EP7R (USB_BASE + 0x0000001C) /!< Endpoint 7 register address /
hudakz	0:a04710facbb6	4936
hudakz	0:a04710facbb6	4937	/* bit positions */
hudakz	0:a04710facbb6	4938	#define USB_EP_CTR_RX_Pos (15U)
hudakz	0:a04710facbb6	4939	#define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	4940	#define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /!< EndPoint Correct TRansfer RX /
hudakz	0:a04710facbb6	4941	#define USB_EP_DTOG_RX_Pos (14U)
hudakz	0:a04710facbb6	4942	#define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	4943	#define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /!< EndPoint Data TOGGLE RX /
hudakz	0:a04710facbb6	4944	#define USB_EPRX_STAT_Pos (12U)
hudakz	0:a04710facbb6	4945	#define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /!< 0x00003000 /
hudakz	0:a04710facbb6	4946	#define USB_EPRX_STAT USB_EPRX_STAT_Msk /!< EndPoint RX STATus bit field /
hudakz	0:a04710facbb6	4947	#define USB_EP_SETUP_Pos (11U)
hudakz	0:a04710facbb6	4948	#define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	4949	#define USB_EP_SETUP USB_EP_SETUP_Msk /!< EndPoint SETUP /
hudakz	0:a04710facbb6	4950	#define USB_EP_T_FIELD_Pos (9U)
hudakz	0:a04710facbb6	4951	#define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /!< 0x00000600 /
hudakz	0:a04710facbb6	4952	#define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /!< EndPoint TYPE /
hudakz	0:a04710facbb6	4953	#define USB_EP_KIND_Pos (8U)
hudakz	0:a04710facbb6	4954	#define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	4955	#define USB_EP_KIND USB_EP_KIND_Msk /!< EndPoint KIND /
hudakz	0:a04710facbb6	4956	#define USB_EP_CTR_TX_Pos (7U)
hudakz	0:a04710facbb6	4957	#define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	4958	#define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /!< EndPoint Correct TRansfer TX /
hudakz	0:a04710facbb6	4959	#define USB_EP_DTOG_TX_Pos (6U)
hudakz	0:a04710facbb6	4960	#define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	4961	#define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /!< EndPoint Data TOGGLE TX /
hudakz	0:a04710facbb6	4962	#define USB_EPTX_STAT_Pos (4U)
hudakz	0:a04710facbb6	4963	#define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /!< 0x00000030 /
hudakz	0:a04710facbb6	4964	#define USB_EPTX_STAT USB_EPTX_STAT_Msk /!< EndPoint TX STATus bit field /
hudakz	0:a04710facbb6	4965	#define USB_EPADDR_FIELD_Pos (0U)
hudakz	0:a04710facbb6	4966	#define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	4967	#define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /!< EndPoint ADDRess FIELD /
hudakz	0:a04710facbb6	4968
hudakz	0:a04710facbb6	4969	/* EndPoint REGister MASK (no toggle fields) */
hudakz	0:a04710facbb6	4970	#define USB_EPREG_MASK (USB_EP_CTR_RX\|USB_EP_SETUP\|USB_EP_T_FIELD\|USB_EP_KIND\|USB_EP_CTR_TX\|USB_EPADDR_FIELD)
hudakz	0:a04710facbb6	4971	/!< EP_TYPE[1:0] EndPoint TYPE /
hudakz	0:a04710facbb6	4972	#define USB_EP_TYPE_MASK_Pos (9U)
hudakz	0:a04710facbb6	4973	#define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /!< 0x00000600 /
hudakz	0:a04710facbb6	4974	#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /!< EndPoint TYPE Mask /
hudakz	0:a04710facbb6	4975	#define USB_EP_BULK 0x00000000U /!< EndPoint BULK /
hudakz	0:a04710facbb6	4976	#define USB_EP_CONTROL 0x00000200U /!< EndPoint CONTROL /
hudakz	0:a04710facbb6	4977	#define USB_EP_ISOCHRONOUS 0x00000400U /!< EndPoint ISOCHRONOUS /
hudakz	0:a04710facbb6	4978	#define USB_EP_INTERRUPT 0x00000600U /!< EndPoint INTERRUPT /
hudakz	0:a04710facbb6	4979	#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
hudakz	0:a04710facbb6	4980
hudakz	0:a04710facbb6	4981	#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /!< EP_KIND EndPoint KIND /
hudakz	0:a04710facbb6	4982	/!< STAT_TX[1:0] STATus for TX transfer /
hudakz	0:a04710facbb6	4983	#define USB_EP_TX_DIS 0x00000000U /!< EndPoint TX DISabled /
hudakz	0:a04710facbb6	4984	#define USB_EP_TX_STALL 0x00000010U /!< EndPoint TX STALLed /
hudakz	0:a04710facbb6	4985	#define USB_EP_TX_NAK 0x00000020U /!< EndPoint TX NAKed /
hudakz	0:a04710facbb6	4986	#define USB_EP_TX_VALID 0x00000030U /!< EndPoint TX VALID /
hudakz	0:a04710facbb6	4987	#define USB_EPTX_DTOG1 0x00000010U /!< EndPoint TX Data TOGgle bit1 /
hudakz	0:a04710facbb6	4988	#define USB_EPTX_DTOG2 0x00000020U /!< EndPoint TX Data TOGgle bit2 /
hudakz	0:a04710facbb6	4989	#define USB_EPTX_DTOGMASK (USB_EPTX_STAT\|USB_EPREG_MASK)
hudakz	0:a04710facbb6	4990	/!< STAT_RX[1:0] STATus for RX transfer /
hudakz	0:a04710facbb6	4991	#define USB_EP_RX_DIS 0x00000000U /!< EndPoint RX DISabled /
hudakz	0:a04710facbb6	4992	#define USB_EP_RX_STALL 0x00001000U /!< EndPoint RX STALLed /
hudakz	0:a04710facbb6	4993	#define USB_EP_RX_NAK 0x00002000U /!< EndPoint RX NAKed /
hudakz	0:a04710facbb6	4994	#define USB_EP_RX_VALID 0x00003000U /!< EndPoint RX VALID /
hudakz	0:a04710facbb6	4995	#define USB_EPRX_DTOG1 0x00001000U /!< EndPoint RX Data TOGgle bit1 /
hudakz	0:a04710facbb6	4996	#define USB_EPRX_DTOG2 0x00002000U /!< EndPoint RX Data TOGgle bit1 /
hudakz	0:a04710facbb6	4997	#define USB_EPRX_DTOGMASK (USB_EPRX_STAT\|USB_EPREG_MASK)
hudakz	0:a04710facbb6	4998
hudakz	0:a04710facbb6	4999	/***************** Bit definition for USB_EP0R register *****************/
hudakz	0:a04710facbb6	5000	#define USB_EP0R_EA_Pos (0U)
hudakz	0:a04710facbb6	5001	#define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	5002	#define USB_EP0R_EA USB_EP0R_EA_Msk /!< Endpoint Address /
hudakz	0:a04710facbb6	5003
hudakz	0:a04710facbb6	5004	#define USB_EP0R_STAT_TX_Pos (4U)
hudakz	0:a04710facbb6	5005	#define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /!< 0x00000030 /
hudakz	0:a04710facbb6	5006	#define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
hudakz	0:a04710facbb6	5007	#define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	5008	#define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	5009
hudakz	0:a04710facbb6	5010	#define USB_EP0R_DTOG_TX_Pos (6U)
hudakz	0:a04710facbb6	5011	#define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	5012	#define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /!< Data Toggle, for transmission transfers /
hudakz	0:a04710facbb6	5013	#define USB_EP0R_CTR_TX_Pos (7U)
hudakz	0:a04710facbb6	5014	#define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	5015	#define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /!< Correct Transfer for transmission /
hudakz	0:a04710facbb6	5016	#define USB_EP0R_EP_KIND_Pos (8U)
hudakz	0:a04710facbb6	5017	#define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	5018	#define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /!< Endpoint Kind /
hudakz	0:a04710facbb6	5019
hudakz	0:a04710facbb6	5020	#define USB_EP0R_EP_TYPE_Pos (9U)
hudakz	0:a04710facbb6	5021	#define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /!< 0x00000600 /
hudakz	0:a04710facbb6	5022	#define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /!< EP_TYPE[1:0] bits (Endpoint type) /
hudakz	0:a04710facbb6	5023	#define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	5024	#define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	5025
hudakz	0:a04710facbb6	5026	#define USB_EP0R_SETUP_Pos (11U)
hudakz	0:a04710facbb6	5027	#define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	5028	#define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /!< Setup transaction completed /
hudakz	0:a04710facbb6	5029
hudakz	0:a04710facbb6	5030	#define USB_EP0R_STAT_RX_Pos (12U)
hudakz	0:a04710facbb6	5031	#define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /!< 0x00003000 /
hudakz	0:a04710facbb6	5032	#define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
hudakz	0:a04710facbb6	5033	#define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	5034	#define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	5035
hudakz	0:a04710facbb6	5036	#define USB_EP0R_DTOG_RX_Pos (14U)
hudakz	0:a04710facbb6	5037	#define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	5038	#define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /!< Data Toggle, for reception transfers /
hudakz	0:a04710facbb6	5039	#define USB_EP0R_CTR_RX_Pos (15U)
hudakz	0:a04710facbb6	5040	#define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	5041	#define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /!< Correct Transfer for reception /
hudakz	0:a04710facbb6	5042
hudakz	0:a04710facbb6	5043	/***************** Bit definition for USB_EP1R register *****************/
hudakz	0:a04710facbb6	5044	#define USB_EP1R_EA_Pos (0U)
hudakz	0:a04710facbb6	5045	#define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	5046	#define USB_EP1R_EA USB_EP1R_EA_Msk /!< Endpoint Address /
hudakz	0:a04710facbb6	5047
hudakz	0:a04710facbb6	5048	#define USB_EP1R_STAT_TX_Pos (4U)
hudakz	0:a04710facbb6	5049	#define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /!< 0x00000030 /
hudakz	0:a04710facbb6	5050	#define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
hudakz	0:a04710facbb6	5051	#define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	5052	#define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	5053
hudakz	0:a04710facbb6	5054	#define USB_EP1R_DTOG_TX_Pos (6U)
hudakz	0:a04710facbb6	5055	#define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	5056	#define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /!< Data Toggle, for transmission transfers /
hudakz	0:a04710facbb6	5057	#define USB_EP1R_CTR_TX_Pos (7U)
hudakz	0:a04710facbb6	5058	#define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	5059	#define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /!< Correct Transfer for transmission /
hudakz	0:a04710facbb6	5060	#define USB_EP1R_EP_KIND_Pos (8U)
hudakz	0:a04710facbb6	5061	#define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	5062	#define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /!< Endpoint Kind /
hudakz	0:a04710facbb6	5063
hudakz	0:a04710facbb6	5064	#define USB_EP1R_EP_TYPE_Pos (9U)
hudakz	0:a04710facbb6	5065	#define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /!< 0x00000600 /
hudakz	0:a04710facbb6	5066	#define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /!< EP_TYPE[1:0] bits (Endpoint type) /
hudakz	0:a04710facbb6	5067	#define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	5068	#define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	5069
hudakz	0:a04710facbb6	5070	#define USB_EP1R_SETUP_Pos (11U)
hudakz	0:a04710facbb6	5071	#define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	5072	#define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /!< Setup transaction completed /
hudakz	0:a04710facbb6	5073
hudakz	0:a04710facbb6	5074	#define USB_EP1R_STAT_RX_Pos (12U)
hudakz	0:a04710facbb6	5075	#define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /!< 0x00003000 /
hudakz	0:a04710facbb6	5076	#define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
hudakz	0:a04710facbb6	5077	#define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	5078	#define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	5079
hudakz	0:a04710facbb6	5080	#define USB_EP1R_DTOG_RX_Pos (14U)
hudakz	0:a04710facbb6	5081	#define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	5082	#define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /!< Data Toggle, for reception transfers /
hudakz	0:a04710facbb6	5083	#define USB_EP1R_CTR_RX_Pos (15U)
hudakz	0:a04710facbb6	5084	#define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	5085	#define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /!< Correct Transfer for reception /
hudakz	0:a04710facbb6	5086
hudakz	0:a04710facbb6	5087	/***************** Bit definition for USB_EP2R register *****************/
hudakz	0:a04710facbb6	5088	#define USB_EP2R_EA_Pos (0U)
hudakz	0:a04710facbb6	5089	#define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	5090	#define USB_EP2R_EA USB_EP2R_EA_Msk /!< Endpoint Address /
hudakz	0:a04710facbb6	5091
hudakz	0:a04710facbb6	5092	#define USB_EP2R_STAT_TX_Pos (4U)
hudakz	0:a04710facbb6	5093	#define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /!< 0x00000030 /
hudakz	0:a04710facbb6	5094	#define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
hudakz	0:a04710facbb6	5095	#define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	5096	#define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	5097
hudakz	0:a04710facbb6	5098	#define USB_EP2R_DTOG_TX_Pos (6U)
hudakz	0:a04710facbb6	5099	#define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	5100	#define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /!< Data Toggle, for transmission transfers /
hudakz	0:a04710facbb6	5101	#define USB_EP2R_CTR_TX_Pos (7U)
hudakz	0:a04710facbb6	5102	#define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	5103	#define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /!< Correct Transfer for transmission /
hudakz	0:a04710facbb6	5104	#define USB_EP2R_EP_KIND_Pos (8U)
hudakz	0:a04710facbb6	5105	#define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	5106	#define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /!< Endpoint Kind /
hudakz	0:a04710facbb6	5107
hudakz	0:a04710facbb6	5108	#define USB_EP2R_EP_TYPE_Pos (9U)
hudakz	0:a04710facbb6	5109	#define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /!< 0x00000600 /
hudakz	0:a04710facbb6	5110	#define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /!< EP_TYPE[1:0] bits (Endpoint type) /
hudakz	0:a04710facbb6	5111	#define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	5112	#define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	5113
hudakz	0:a04710facbb6	5114	#define USB_EP2R_SETUP_Pos (11U)
hudakz	0:a04710facbb6	5115	#define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	5116	#define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /!< Setup transaction completed /
hudakz	0:a04710facbb6	5117
hudakz	0:a04710facbb6	5118	#define USB_EP2R_STAT_RX_Pos (12U)
hudakz	0:a04710facbb6	5119	#define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /!< 0x00003000 /
hudakz	0:a04710facbb6	5120	#define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
hudakz	0:a04710facbb6	5121	#define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	5122	#define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	5123
hudakz	0:a04710facbb6	5124	#define USB_EP2R_DTOG_RX_Pos (14U)
hudakz	0:a04710facbb6	5125	#define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	5126	#define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /!< Data Toggle, for reception transfers /
hudakz	0:a04710facbb6	5127	#define USB_EP2R_CTR_RX_Pos (15U)
hudakz	0:a04710facbb6	5128	#define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	5129	#define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /!< Correct Transfer for reception /
hudakz	0:a04710facbb6	5130
hudakz	0:a04710facbb6	5131	/***************** Bit definition for USB_EP3R register *****************/
hudakz	0:a04710facbb6	5132	#define USB_EP3R_EA_Pos (0U)
hudakz	0:a04710facbb6	5133	#define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	5134	#define USB_EP3R_EA USB_EP3R_EA_Msk /!< Endpoint Address /
hudakz	0:a04710facbb6	5135
hudakz	0:a04710facbb6	5136	#define USB_EP3R_STAT_TX_Pos (4U)
hudakz	0:a04710facbb6	5137	#define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /!< 0x00000030 /
hudakz	0:a04710facbb6	5138	#define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
hudakz	0:a04710facbb6	5139	#define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	5140	#define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	5141
hudakz	0:a04710facbb6	5142	#define USB_EP3R_DTOG_TX_Pos (6U)
hudakz	0:a04710facbb6	5143	#define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	5144	#define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /!< Data Toggle, for transmission transfers /
hudakz	0:a04710facbb6	5145	#define USB_EP3R_CTR_TX_Pos (7U)
hudakz	0:a04710facbb6	5146	#define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	5147	#define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /!< Correct Transfer for transmission /
hudakz	0:a04710facbb6	5148	#define USB_EP3R_EP_KIND_Pos (8U)
hudakz	0:a04710facbb6	5149	#define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	5150	#define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /!< Endpoint Kind /
hudakz	0:a04710facbb6	5151
hudakz	0:a04710facbb6	5152	#define USB_EP3R_EP_TYPE_Pos (9U)
hudakz	0:a04710facbb6	5153	#define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /!< 0x00000600 /
hudakz	0:a04710facbb6	5154	#define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /!< EP_TYPE[1:0] bits (Endpoint type) /
hudakz	0:a04710facbb6	5155	#define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	5156	#define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	5157
hudakz	0:a04710facbb6	5158	#define USB_EP3R_SETUP_Pos (11U)
hudakz	0:a04710facbb6	5159	#define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	5160	#define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /!< Setup transaction completed /
hudakz	0:a04710facbb6	5161
hudakz	0:a04710facbb6	5162	#define USB_EP3R_STAT_RX_Pos (12U)
hudakz	0:a04710facbb6	5163	#define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /!< 0x00003000 /
hudakz	0:a04710facbb6	5164	#define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
hudakz	0:a04710facbb6	5165	#define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	5166	#define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	5167
hudakz	0:a04710facbb6	5168	#define USB_EP3R_DTOG_RX_Pos (14U)
hudakz	0:a04710facbb6	5169	#define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	5170	#define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /!< Data Toggle, for reception transfers /
hudakz	0:a04710facbb6	5171	#define USB_EP3R_CTR_RX_Pos (15U)
hudakz	0:a04710facbb6	5172	#define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	5173	#define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /!< Correct Transfer for reception /
hudakz	0:a04710facbb6	5174
hudakz	0:a04710facbb6	5175	/***************** Bit definition for USB_EP4R register *****************/
hudakz	0:a04710facbb6	5176	#define USB_EP4R_EA_Pos (0U)
hudakz	0:a04710facbb6	5177	#define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	5178	#define USB_EP4R_EA USB_EP4R_EA_Msk /!< Endpoint Address /
hudakz	0:a04710facbb6	5179
hudakz	0:a04710facbb6	5180	#define USB_EP4R_STAT_TX_Pos (4U)
hudakz	0:a04710facbb6	5181	#define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /!< 0x00000030 /
hudakz	0:a04710facbb6	5182	#define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
hudakz	0:a04710facbb6	5183	#define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	5184	#define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	5185
hudakz	0:a04710facbb6	5186	#define USB_EP4R_DTOG_TX_Pos (6U)
hudakz	0:a04710facbb6	5187	#define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	5188	#define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /!< Data Toggle, for transmission transfers /
hudakz	0:a04710facbb6	5189	#define USB_EP4R_CTR_TX_Pos (7U)
hudakz	0:a04710facbb6	5190	#define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	5191	#define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /!< Correct Transfer for transmission /
hudakz	0:a04710facbb6	5192	#define USB_EP4R_EP_KIND_Pos (8U)
hudakz	0:a04710facbb6	5193	#define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	5194	#define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /!< Endpoint Kind /
hudakz	0:a04710facbb6	5195
hudakz	0:a04710facbb6	5196	#define USB_EP4R_EP_TYPE_Pos (9U)
hudakz	0:a04710facbb6	5197	#define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /!< 0x00000600 /
hudakz	0:a04710facbb6	5198	#define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /!< EP_TYPE[1:0] bits (Endpoint type) /
hudakz	0:a04710facbb6	5199	#define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	5200	#define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	5201
hudakz	0:a04710facbb6	5202	#define USB_EP4R_SETUP_Pos (11U)
hudakz	0:a04710facbb6	5203	#define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	5204	#define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /!< Setup transaction completed /
hudakz	0:a04710facbb6	5205
hudakz	0:a04710facbb6	5206	#define USB_EP4R_STAT_RX_Pos (12U)
hudakz	0:a04710facbb6	5207	#define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /!< 0x00003000 /
hudakz	0:a04710facbb6	5208	#define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
hudakz	0:a04710facbb6	5209	#define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	5210	#define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	5211
hudakz	0:a04710facbb6	5212	#define USB_EP4R_DTOG_RX_Pos (14U)
hudakz	0:a04710facbb6	5213	#define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	5214	#define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /!< Data Toggle, for reception transfers /
hudakz	0:a04710facbb6	5215	#define USB_EP4R_CTR_RX_Pos (15U)
hudakz	0:a04710facbb6	5216	#define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	5217	#define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /!< Correct Transfer for reception /
hudakz	0:a04710facbb6	5218
hudakz	0:a04710facbb6	5219	/***************** Bit definition for USB_EP5R register *****************/
hudakz	0:a04710facbb6	5220	#define USB_EP5R_EA_Pos (0U)
hudakz	0:a04710facbb6	5221	#define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	5222	#define USB_EP5R_EA USB_EP5R_EA_Msk /!< Endpoint Address /
hudakz	0:a04710facbb6	5223
hudakz	0:a04710facbb6	5224	#define USB_EP5R_STAT_TX_Pos (4U)
hudakz	0:a04710facbb6	5225	#define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /!< 0x00000030 /
hudakz	0:a04710facbb6	5226	#define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
hudakz	0:a04710facbb6	5227	#define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	5228	#define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	5229
hudakz	0:a04710facbb6	5230	#define USB_EP5R_DTOG_TX_Pos (6U)
hudakz	0:a04710facbb6	5231	#define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	5232	#define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /!< Data Toggle, for transmission transfers /
hudakz	0:a04710facbb6	5233	#define USB_EP5R_CTR_TX_Pos (7U)
hudakz	0:a04710facbb6	5234	#define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	5235	#define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /!< Correct Transfer for transmission /
hudakz	0:a04710facbb6	5236	#define USB_EP5R_EP_KIND_Pos (8U)
hudakz	0:a04710facbb6	5237	#define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	5238	#define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /!< Endpoint Kind /
hudakz	0:a04710facbb6	5239
hudakz	0:a04710facbb6	5240	#define USB_EP5R_EP_TYPE_Pos (9U)
hudakz	0:a04710facbb6	5241	#define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /!< 0x00000600 /
hudakz	0:a04710facbb6	5242	#define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /!< EP_TYPE[1:0] bits (Endpoint type) /
hudakz	0:a04710facbb6	5243	#define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	5244	#define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	5245
hudakz	0:a04710facbb6	5246	#define USB_EP5R_SETUP_Pos (11U)
hudakz	0:a04710facbb6	5247	#define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	5248	#define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /!< Setup transaction completed /
hudakz	0:a04710facbb6	5249
hudakz	0:a04710facbb6	5250	#define USB_EP5R_STAT_RX_Pos (12U)
hudakz	0:a04710facbb6	5251	#define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /!< 0x00003000 /
hudakz	0:a04710facbb6	5252	#define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
hudakz	0:a04710facbb6	5253	#define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	5254	#define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	5255
hudakz	0:a04710facbb6	5256	#define USB_EP5R_DTOG_RX_Pos (14U)
hudakz	0:a04710facbb6	5257	#define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	5258	#define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /!< Data Toggle, for reception transfers /
hudakz	0:a04710facbb6	5259	#define USB_EP5R_CTR_RX_Pos (15U)
hudakz	0:a04710facbb6	5260	#define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	5261	#define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /!< Correct Transfer for reception /
hudakz	0:a04710facbb6	5262
hudakz	0:a04710facbb6	5263	/***************** Bit definition for USB_EP6R register *****************/
hudakz	0:a04710facbb6	5264	#define USB_EP6R_EA_Pos (0U)
hudakz	0:a04710facbb6	5265	#define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	5266	#define USB_EP6R_EA USB_EP6R_EA_Msk /!< Endpoint Address /
hudakz	0:a04710facbb6	5267
hudakz	0:a04710facbb6	5268	#define USB_EP6R_STAT_TX_Pos (4U)
hudakz	0:a04710facbb6	5269	#define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /!< 0x00000030 /
hudakz	0:a04710facbb6	5270	#define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
hudakz	0:a04710facbb6	5271	#define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	5272	#define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	5273
hudakz	0:a04710facbb6	5274	#define USB_EP6R_DTOG_TX_Pos (6U)
hudakz	0:a04710facbb6	5275	#define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	5276	#define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /!< Data Toggle, for transmission transfers /
hudakz	0:a04710facbb6	5277	#define USB_EP6R_CTR_TX_Pos (7U)
hudakz	0:a04710facbb6	5278	#define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	5279	#define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /!< Correct Transfer for transmission /
hudakz	0:a04710facbb6	5280	#define USB_EP6R_EP_KIND_Pos (8U)
hudakz	0:a04710facbb6	5281	#define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	5282	#define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /!< Endpoint Kind /
hudakz	0:a04710facbb6	5283
hudakz	0:a04710facbb6	5284	#define USB_EP6R_EP_TYPE_Pos (9U)
hudakz	0:a04710facbb6	5285	#define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /!< 0x00000600 /
hudakz	0:a04710facbb6	5286	#define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /!< EP_TYPE[1:0] bits (Endpoint type) /
hudakz	0:a04710facbb6	5287	#define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	5288	#define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	5289
hudakz	0:a04710facbb6	5290	#define USB_EP6R_SETUP_Pos (11U)
hudakz	0:a04710facbb6	5291	#define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	5292	#define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /!< Setup transaction completed /
hudakz	0:a04710facbb6	5293
hudakz	0:a04710facbb6	5294	#define USB_EP6R_STAT_RX_Pos (12U)
hudakz	0:a04710facbb6	5295	#define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /!< 0x00003000 /
hudakz	0:a04710facbb6	5296	#define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
hudakz	0:a04710facbb6	5297	#define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	5298	#define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	5299
hudakz	0:a04710facbb6	5300	#define USB_EP6R_DTOG_RX_Pos (14U)
hudakz	0:a04710facbb6	5301	#define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	5302	#define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /!< Data Toggle, for reception transfers /
hudakz	0:a04710facbb6	5303	#define USB_EP6R_CTR_RX_Pos (15U)
hudakz	0:a04710facbb6	5304	#define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	5305	#define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /!< Correct Transfer for reception /
hudakz	0:a04710facbb6	5306
hudakz	0:a04710facbb6	5307	/***************** Bit definition for USB_EP7R register *****************/
hudakz	0:a04710facbb6	5308	#define USB_EP7R_EA_Pos (0U)
hudakz	0:a04710facbb6	5309	#define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	5310	#define USB_EP7R_EA USB_EP7R_EA_Msk /!< Endpoint Address /
hudakz	0:a04710facbb6	5311
hudakz	0:a04710facbb6	5312	#define USB_EP7R_STAT_TX_Pos (4U)
hudakz	0:a04710facbb6	5313	#define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /!< 0x00000030 /
hudakz	0:a04710facbb6	5314	#define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
hudakz	0:a04710facbb6	5315	#define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	5316	#define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	5317
hudakz	0:a04710facbb6	5318	#define USB_EP7R_DTOG_TX_Pos (6U)
hudakz	0:a04710facbb6	5319	#define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	5320	#define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /!< Data Toggle, for transmission transfers /
hudakz	0:a04710facbb6	5321	#define USB_EP7R_CTR_TX_Pos (7U)
hudakz	0:a04710facbb6	5322	#define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	5323	#define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /!< Correct Transfer for transmission /
hudakz	0:a04710facbb6	5324	#define USB_EP7R_EP_KIND_Pos (8U)
hudakz	0:a04710facbb6	5325	#define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	5326	#define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /!< Endpoint Kind /
hudakz	0:a04710facbb6	5327
hudakz	0:a04710facbb6	5328	#define USB_EP7R_EP_TYPE_Pos (9U)
hudakz	0:a04710facbb6	5329	#define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /!< 0x00000600 /
hudakz	0:a04710facbb6	5330	#define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /!< EP_TYPE[1:0] bits (Endpoint type) /
hudakz	0:a04710facbb6	5331	#define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	5332	#define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	5333
hudakz	0:a04710facbb6	5334	#define USB_EP7R_SETUP_Pos (11U)
hudakz	0:a04710facbb6	5335	#define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	5336	#define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /!< Setup transaction completed /
hudakz	0:a04710facbb6	5337
hudakz	0:a04710facbb6	5338	#define USB_EP7R_STAT_RX_Pos (12U)
hudakz	0:a04710facbb6	5339	#define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /!< 0x00003000 /
hudakz	0:a04710facbb6	5340	#define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
hudakz	0:a04710facbb6	5341	#define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	5342	#define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	5343
hudakz	0:a04710facbb6	5344	#define USB_EP7R_DTOG_RX_Pos (14U)
hudakz	0:a04710facbb6	5345	#define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	5346	#define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /!< Data Toggle, for reception transfers /
hudakz	0:a04710facbb6	5347	#define USB_EP7R_CTR_RX_Pos (15U)
hudakz	0:a04710facbb6	5348	#define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	5349	#define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /!< Correct Transfer for reception /
hudakz	0:a04710facbb6	5350
hudakz	0:a04710facbb6	5351	/!< Common registers /
hudakz	0:a04710facbb6	5352	/***************** Bit definition for USB_CNTR register *****************/
hudakz	0:a04710facbb6	5353	#define USB_CNTR_FRES_Pos (0U)
hudakz	0:a04710facbb6	5354	#define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	5355	#define USB_CNTR_FRES USB_CNTR_FRES_Msk /!< Force USB Reset /
hudakz	0:a04710facbb6	5356	#define USB_CNTR_PDWN_Pos (1U)
hudakz	0:a04710facbb6	5357	#define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	5358	#define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /!< Power down /
hudakz	0:a04710facbb6	5359	#define USB_CNTR_LP_MODE_Pos (2U)
hudakz	0:a04710facbb6	5360	#define USB_CNTR_LP_MODE_Msk (0x1U << USB_CNTR_LP_MODE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	5361	#define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /!< Low-power mode /
hudakz	0:a04710facbb6	5362	#define USB_CNTR_FSUSP_Pos (3U)
hudakz	0:a04710facbb6	5363	#define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	5364	#define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /!< Force suspend /
hudakz	0:a04710facbb6	5365	#define USB_CNTR_RESUME_Pos (4U)
hudakz	0:a04710facbb6	5366	#define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	5367	#define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /!< Resume request /
hudakz	0:a04710facbb6	5368	#define USB_CNTR_ESOFM_Pos (8U)
hudakz	0:a04710facbb6	5369	#define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	5370	#define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /!< Expected Start Of Frame Interrupt Mask /
hudakz	0:a04710facbb6	5371	#define USB_CNTR_SOFM_Pos (9U)
hudakz	0:a04710facbb6	5372	#define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	5373	#define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /!< Start Of Frame Interrupt Mask /
hudakz	0:a04710facbb6	5374	#define USB_CNTR_RESETM_Pos (10U)
hudakz	0:a04710facbb6	5375	#define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	5376	#define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /!< RESET Interrupt Mask /
hudakz	0:a04710facbb6	5377	#define USB_CNTR_SUSPM_Pos (11U)
hudakz	0:a04710facbb6	5378	#define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	5379	#define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /!< Suspend mode Interrupt Mask /
hudakz	0:a04710facbb6	5380	#define USB_CNTR_WKUPM_Pos (12U)
hudakz	0:a04710facbb6	5381	#define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	5382	#define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /!< Wakeup Interrupt Mask /
hudakz	0:a04710facbb6	5383	#define USB_CNTR_ERRM_Pos (13U)
hudakz	0:a04710facbb6	5384	#define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	5385	#define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /!< Error Interrupt Mask /
hudakz	0:a04710facbb6	5386	#define USB_CNTR_PMAOVRM_Pos (14U)
hudakz	0:a04710facbb6	5387	#define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	5388	#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /!< Packet Memory Area Over / Underrun Interrupt Mask /
hudakz	0:a04710facbb6	5389	#define USB_CNTR_CTRM_Pos (15U)
hudakz	0:a04710facbb6	5390	#define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	5391	#define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /!< Correct Transfer Interrupt Mask /
hudakz	0:a04710facbb6	5392
hudakz	0:a04710facbb6	5393	/***************** Bit definition for USB_ISTR register *****************/
hudakz	0:a04710facbb6	5394	#define USB_ISTR_EP_ID_Pos (0U)
hudakz	0:a04710facbb6	5395	#define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	5396	#define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /!< Endpoint Identifier /
hudakz	0:a04710facbb6	5397	#define USB_ISTR_DIR_Pos (4U)
hudakz	0:a04710facbb6	5398	#define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	5399	#define USB_ISTR_DIR USB_ISTR_DIR_Msk /!< Direction of transaction /
hudakz	0:a04710facbb6	5400	#define USB_ISTR_ESOF_Pos (8U)
hudakz	0:a04710facbb6	5401	#define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	5402	#define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /!< Expected Start Of Frame /
hudakz	0:a04710facbb6	5403	#define USB_ISTR_SOF_Pos (9U)
hudakz	0:a04710facbb6	5404	#define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	5405	#define USB_ISTR_SOF USB_ISTR_SOF_Msk /!< Start Of Frame /
hudakz	0:a04710facbb6	5406	#define USB_ISTR_RESET_Pos (10U)
hudakz	0:a04710facbb6	5407	#define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	5408	#define USB_ISTR_RESET USB_ISTR_RESET_Msk /!< USB RESET request /
hudakz	0:a04710facbb6	5409	#define USB_ISTR_SUSP_Pos (11U)
hudakz	0:a04710facbb6	5410	#define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	5411	#define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /!< Suspend mode request /
hudakz	0:a04710facbb6	5412	#define USB_ISTR_WKUP_Pos (12U)
hudakz	0:a04710facbb6	5413	#define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	5414	#define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /!< Wake up /
hudakz	0:a04710facbb6	5415	#define USB_ISTR_ERR_Pos (13U)
hudakz	0:a04710facbb6	5416	#define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	5417	#define USB_ISTR_ERR USB_ISTR_ERR_Msk /!< Error /
hudakz	0:a04710facbb6	5418	#define USB_ISTR_PMAOVR_Pos (14U)
hudakz	0:a04710facbb6	5419	#define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	5420	#define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /!< Packet Memory Area Over / Underrun /
hudakz	0:a04710facbb6	5421	#define USB_ISTR_CTR_Pos (15U)
hudakz	0:a04710facbb6	5422	#define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	5423	#define USB_ISTR_CTR USB_ISTR_CTR_Msk /!< Correct Transfer /
hudakz	0:a04710facbb6	5424
hudakz	0:a04710facbb6	5425	/***************** Bit definition for USB_FNR register ******************/
hudakz	0:a04710facbb6	5426	#define USB_FNR_FN_Pos (0U)
hudakz	0:a04710facbb6	5427	#define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /!< 0x000007FF /
hudakz	0:a04710facbb6	5428	#define USB_FNR_FN USB_FNR_FN_Msk /!< Frame Number /
hudakz	0:a04710facbb6	5429	#define USB_FNR_LSOF_Pos (11U)
hudakz	0:a04710facbb6	5430	#define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /!< 0x00001800 /
hudakz	0:a04710facbb6	5431	#define USB_FNR_LSOF USB_FNR_LSOF_Msk /!< Lost SOF /
hudakz	0:a04710facbb6	5432	#define USB_FNR_LCK_Pos (13U)
hudakz	0:a04710facbb6	5433	#define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	5434	#define USB_FNR_LCK USB_FNR_LCK_Msk /!< Locked /
hudakz	0:a04710facbb6	5435	#define USB_FNR_RXDM_Pos (14U)
hudakz	0:a04710facbb6	5436	#define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	5437	#define USB_FNR_RXDM USB_FNR_RXDM_Msk /!< Receive Data - Line Status /
hudakz	0:a04710facbb6	5438	#define USB_FNR_RXDP_Pos (15U)
hudakz	0:a04710facbb6	5439	#define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	5440	#define USB_FNR_RXDP USB_FNR_RXDP_Msk /!< Receive Data + Line Status /
hudakz	0:a04710facbb6	5441
hudakz	0:a04710facbb6	5442	/**************** Bit definition for USB_DADDR register *****************/
hudakz	0:a04710facbb6	5443	#define USB_DADDR_ADD_Pos (0U)
hudakz	0:a04710facbb6	5444	#define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /!< 0x0000007F /
hudakz	0:a04710facbb6	5445	#define USB_DADDR_ADD USB_DADDR_ADD_Msk /!< ADD[6:0] bits (Device Address) /
hudakz	0:a04710facbb6	5446	#define USB_DADDR_ADD0_Pos (0U)
hudakz	0:a04710facbb6	5447	#define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	5448	#define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /!< Bit 0 /
hudakz	0:a04710facbb6	5449	#define USB_DADDR_ADD1_Pos (1U)
hudakz	0:a04710facbb6	5450	#define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	5451	#define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /!< Bit 1 /
hudakz	0:a04710facbb6	5452	#define USB_DADDR_ADD2_Pos (2U)
hudakz	0:a04710facbb6	5453	#define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	5454	#define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /!< Bit 2 /
hudakz	0:a04710facbb6	5455	#define USB_DADDR_ADD3_Pos (3U)
hudakz	0:a04710facbb6	5456	#define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	5457	#define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /!< Bit 3 /
hudakz	0:a04710facbb6	5458	#define USB_DADDR_ADD4_Pos (4U)
hudakz	0:a04710facbb6	5459	#define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	5460	#define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /!< Bit 4 /
hudakz	0:a04710facbb6	5461	#define USB_DADDR_ADD5_Pos (5U)
hudakz	0:a04710facbb6	5462	#define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	5463	#define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /!< Bit 5 /
hudakz	0:a04710facbb6	5464	#define USB_DADDR_ADD6_Pos (6U)
hudakz	0:a04710facbb6	5465	#define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	5466	#define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /!< Bit 6 /
hudakz	0:a04710facbb6	5467
hudakz	0:a04710facbb6	5468	#define USB_DADDR_EF_Pos (7U)
hudakz	0:a04710facbb6	5469	#define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	5470	#define USB_DADDR_EF USB_DADDR_EF_Msk /!< Enable Function /
hudakz	0:a04710facbb6	5471
hudakz	0:a04710facbb6	5472	/**************** Bit definition for USB_BTABLE register ****************/
hudakz	0:a04710facbb6	5473	#define USB_BTABLE_BTABLE_Pos (3U)
hudakz	0:a04710facbb6	5474	#define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /!< 0x0000FFF8 /
hudakz	0:a04710facbb6	5475	#define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /!< Buffer Table /
hudakz	0:a04710facbb6	5476
hudakz	0:a04710facbb6	5477	/!< Buffer descriptor table /
hudakz	0:a04710facbb6	5478	/*************** Bit definition for USB_ADDR0_TX register ***************/
hudakz	0:a04710facbb6	5479	#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
hudakz	0:a04710facbb6	5480	#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /!< 0x0000FFFE /
hudakz	0:a04710facbb6	5481	#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /!< Transmission Buffer Address 0 /
hudakz	0:a04710facbb6	5482
hudakz	0:a04710facbb6	5483	/*************** Bit definition for USB_ADDR1_TX register ***************/
hudakz	0:a04710facbb6	5484	#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
hudakz	0:a04710facbb6	5485	#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /!< 0x0000FFFE /
hudakz	0:a04710facbb6	5486	#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /!< Transmission Buffer Address 1 /
hudakz	0:a04710facbb6	5487
hudakz	0:a04710facbb6	5488	/*************** Bit definition for USB_ADDR2_TX register ***************/
hudakz	0:a04710facbb6	5489	#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
hudakz	0:a04710facbb6	5490	#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /!< 0x0000FFFE /
hudakz	0:a04710facbb6	5491	#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /!< Transmission Buffer Address 2 /
hudakz	0:a04710facbb6	5492
hudakz	0:a04710facbb6	5493	/*************** Bit definition for USB_ADDR3_TX register ***************/
hudakz	0:a04710facbb6	5494	#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
hudakz	0:a04710facbb6	5495	#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /!< 0x0000FFFE /
hudakz	0:a04710facbb6	5496	#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /!< Transmission Buffer Address 3 /
hudakz	0:a04710facbb6	5497
hudakz	0:a04710facbb6	5498	/*************** Bit definition for USB_ADDR4_TX register ***************/
hudakz	0:a04710facbb6	5499	#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
hudakz	0:a04710facbb6	5500	#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /!< 0x0000FFFE /
hudakz	0:a04710facbb6	5501	#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /!< Transmission Buffer Address 4 /
hudakz	0:a04710facbb6	5502
hudakz	0:a04710facbb6	5503	/*************** Bit definition for USB_ADDR5_TX register ***************/
hudakz	0:a04710facbb6	5504	#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
hudakz	0:a04710facbb6	5505	#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /!< 0x0000FFFE /
hudakz	0:a04710facbb6	5506	#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /!< Transmission Buffer Address 5 /
hudakz	0:a04710facbb6	5507
hudakz	0:a04710facbb6	5508	/*************** Bit definition for USB_ADDR6_TX register ***************/
hudakz	0:a04710facbb6	5509	#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
hudakz	0:a04710facbb6	5510	#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /!< 0x0000FFFE /
hudakz	0:a04710facbb6	5511	#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /!< Transmission Buffer Address 6 /
hudakz	0:a04710facbb6	5512
hudakz	0:a04710facbb6	5513	/*************** Bit definition for USB_ADDR7_TX register ***************/
hudakz	0:a04710facbb6	5514	#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
hudakz	0:a04710facbb6	5515	#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /!< 0x0000FFFE /
hudakz	0:a04710facbb6	5516	#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /!< Transmission Buffer Address 7 /
hudakz	0:a04710facbb6	5517
hudakz	0:a04710facbb6	5518	/----------------------------------------------------------------------------/
hudakz	0:a04710facbb6	5519
hudakz	0:a04710facbb6	5520	/*************** Bit definition for USB_COUNT0_TX register **************/
hudakz	0:a04710facbb6	5521	#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
hudakz	0:a04710facbb6	5522	#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /!< 0x000003FF /
hudakz	0:a04710facbb6	5523	#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /!< Transmission Byte Count 0 /
hudakz	0:a04710facbb6	5524
hudakz	0:a04710facbb6	5525	/*************** Bit definition for USB_COUNT1_TX register **************/
hudakz	0:a04710facbb6	5526	#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
hudakz	0:a04710facbb6	5527	#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /!< 0x000003FF /
hudakz	0:a04710facbb6	5528	#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /!< Transmission Byte Count 1 /
hudakz	0:a04710facbb6	5529
hudakz	0:a04710facbb6	5530	/*************** Bit definition for USB_COUNT2_TX register **************/
hudakz	0:a04710facbb6	5531	#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
hudakz	0:a04710facbb6	5532	#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /!< 0x000003FF /
hudakz	0:a04710facbb6	5533	#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /!< Transmission Byte Count 2 /
hudakz	0:a04710facbb6	5534
hudakz	0:a04710facbb6	5535	/*************** Bit definition for USB_COUNT3_TX register **************/
hudakz	0:a04710facbb6	5536	#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
hudakz	0:a04710facbb6	5537	#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /!< 0x000003FF /
hudakz	0:a04710facbb6	5538	#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /!< Transmission Byte Count 3 /
hudakz	0:a04710facbb6	5539
hudakz	0:a04710facbb6	5540	/*************** Bit definition for USB_COUNT4_TX register **************/
hudakz	0:a04710facbb6	5541	#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
hudakz	0:a04710facbb6	5542	#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /!< 0x000003FF /
hudakz	0:a04710facbb6	5543	#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /!< Transmission Byte Count 4 /
hudakz	0:a04710facbb6	5544
hudakz	0:a04710facbb6	5545	/*************** Bit definition for USB_COUNT5_TX register **************/
hudakz	0:a04710facbb6	5546	#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
hudakz	0:a04710facbb6	5547	#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /!< 0x000003FF /
hudakz	0:a04710facbb6	5548	#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /!< Transmission Byte Count 5 /
hudakz	0:a04710facbb6	5549
hudakz	0:a04710facbb6	5550	/*************** Bit definition for USB_COUNT6_TX register **************/
hudakz	0:a04710facbb6	5551	#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
hudakz	0:a04710facbb6	5552	#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /!< 0x000003FF /
hudakz	0:a04710facbb6	5553	#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /!< Transmission Byte Count 6 /
hudakz	0:a04710facbb6	5554
hudakz	0:a04710facbb6	5555	/*************** Bit definition for USB_COUNT7_TX register **************/
hudakz	0:a04710facbb6	5556	#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
hudakz	0:a04710facbb6	5557	#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /!< 0x000003FF /
hudakz	0:a04710facbb6	5558	#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /!< Transmission Byte Count 7 /
hudakz	0:a04710facbb6	5559
hudakz	0:a04710facbb6	5560	/----------------------------------------------------------------------------/
hudakz	0:a04710facbb6	5561
hudakz	0:a04710facbb6	5562	/************** Bit definition for USB_COUNT0_TX_0 register *************/
hudakz	0:a04710facbb6	5563	#define USB_COUNT0_TX_0_COUNT0_TX_0 0x000003FFU /!< Transmission Byte Count 0 (low) /
hudakz	0:a04710facbb6	5564
hudakz	0:a04710facbb6	5565	/************** Bit definition for USB_COUNT0_TX_1 register *************/
hudakz	0:a04710facbb6	5566	#define USB_COUNT0_TX_1_COUNT0_TX_1 0x03FF0000U /!< Transmission Byte Count 0 (high) /
hudakz	0:a04710facbb6	5567
hudakz	0:a04710facbb6	5568	/************** Bit definition for USB_COUNT1_TX_0 register *************/
hudakz	0:a04710facbb6	5569	#define USB_COUNT1_TX_0_COUNT1_TX_0 0x000003FFU /!< Transmission Byte Count 1 (low) /
hudakz	0:a04710facbb6	5570
hudakz	0:a04710facbb6	5571	/************** Bit definition for USB_COUNT1_TX_1 register *************/
hudakz	0:a04710facbb6	5572	#define USB_COUNT1_TX_1_COUNT1_TX_1 0x03FF0000U /!< Transmission Byte Count 1 (high) /
hudakz	0:a04710facbb6	5573
hudakz	0:a04710facbb6	5574	/************** Bit definition for USB_COUNT2_TX_0 register *************/
hudakz	0:a04710facbb6	5575	#define USB_COUNT2_TX_0_COUNT2_TX_0 0x000003FFU /!< Transmission Byte Count 2 (low) /
hudakz	0:a04710facbb6	5576
hudakz	0:a04710facbb6	5577	/************** Bit definition for USB_COUNT2_TX_1 register *************/
hudakz	0:a04710facbb6	5578	#define USB_COUNT2_TX_1_COUNT2_TX_1 0x03FF0000U /!< Transmission Byte Count 2 (high) /
hudakz	0:a04710facbb6	5579
hudakz	0:a04710facbb6	5580	/************** Bit definition for USB_COUNT3_TX_0 register *************/
hudakz	0:a04710facbb6	5581	#define USB_COUNT3_TX_0_COUNT3_TX_0 0x000003FFU /!< Transmission Byte Count 3 (low) /
hudakz	0:a04710facbb6	5582
hudakz	0:a04710facbb6	5583	/************** Bit definition for USB_COUNT3_TX_1 register *************/
hudakz	0:a04710facbb6	5584	#define USB_COUNT3_TX_1_COUNT3_TX_1 0x03FF0000U /!< Transmission Byte Count 3 (high) /
hudakz	0:a04710facbb6	5585
hudakz	0:a04710facbb6	5586	/************** Bit definition for USB_COUNT4_TX_0 register *************/
hudakz	0:a04710facbb6	5587	#define USB_COUNT4_TX_0_COUNT4_TX_0 0x000003FFU /!< Transmission Byte Count 4 (low) /
hudakz	0:a04710facbb6	5588
hudakz	0:a04710facbb6	5589	/************** Bit definition for USB_COUNT4_TX_1 register *************/
hudakz	0:a04710facbb6	5590	#define USB_COUNT4_TX_1_COUNT4_TX_1 0x03FF0000U /!< Transmission Byte Count 4 (high) /
hudakz	0:a04710facbb6	5591
hudakz	0:a04710facbb6	5592	/************** Bit definition for USB_COUNT5_TX_0 register *************/
hudakz	0:a04710facbb6	5593	#define USB_COUNT5_TX_0_COUNT5_TX_0 0x000003FFU /!< Transmission Byte Count 5 (low) /
hudakz	0:a04710facbb6	5594
hudakz	0:a04710facbb6	5595	/************** Bit definition for USB_COUNT5_TX_1 register *************/
hudakz	0:a04710facbb6	5596	#define USB_COUNT5_TX_1_COUNT5_TX_1 0x03FF0000U /!< Transmission Byte Count 5 (high) /
hudakz	0:a04710facbb6	5597
hudakz	0:a04710facbb6	5598	/************** Bit definition for USB_COUNT6_TX_0 register *************/
hudakz	0:a04710facbb6	5599	#define USB_COUNT6_TX_0_COUNT6_TX_0 0x000003FFU /!< Transmission Byte Count 6 (low) /
hudakz	0:a04710facbb6	5600
hudakz	0:a04710facbb6	5601	/************** Bit definition for USB_COUNT6_TX_1 register *************/
hudakz	0:a04710facbb6	5602	#define USB_COUNT6_TX_1_COUNT6_TX_1 0x03FF0000U /!< Transmission Byte Count 6 (high) /
hudakz	0:a04710facbb6	5603
hudakz	0:a04710facbb6	5604	/************** Bit definition for USB_COUNT7_TX_0 register *************/
hudakz	0:a04710facbb6	5605	#define USB_COUNT7_TX_0_COUNT7_TX_0 0x000003FFU /!< Transmission Byte Count 7 (low) /
hudakz	0:a04710facbb6	5606
hudakz	0:a04710facbb6	5607	/************** Bit definition for USB_COUNT7_TX_1 register *************/
hudakz	0:a04710facbb6	5608	#define USB_COUNT7_TX_1_COUNT7_TX_1 0x03FF0000U /!< Transmission Byte Count 7 (high) /
hudakz	0:a04710facbb6	5609
hudakz	0:a04710facbb6	5610	/----------------------------------------------------------------------------/
hudakz	0:a04710facbb6	5611
hudakz	0:a04710facbb6	5612	/*************** Bit definition for USB_ADDR0_RX register ***************/
hudakz	0:a04710facbb6	5613	#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
hudakz	0:a04710facbb6	5614	#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /!< 0x0000FFFE /
hudakz	0:a04710facbb6	5615	#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /!< Reception Buffer Address 0 /
hudakz	0:a04710facbb6	5616
hudakz	0:a04710facbb6	5617	/*************** Bit definition for USB_ADDR1_RX register ***************/
hudakz	0:a04710facbb6	5618	#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
hudakz	0:a04710facbb6	5619	#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /!< 0x0000FFFE /
hudakz	0:a04710facbb6	5620	#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /!< Reception Buffer Address 1 /
hudakz	0:a04710facbb6	5621
hudakz	0:a04710facbb6	5622	/*************** Bit definition for USB_ADDR2_RX register ***************/
hudakz	0:a04710facbb6	5623	#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
hudakz	0:a04710facbb6	5624	#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /!< 0x0000FFFE /
hudakz	0:a04710facbb6	5625	#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /!< Reception Buffer Address 2 /
hudakz	0:a04710facbb6	5626
hudakz	0:a04710facbb6	5627	/*************** Bit definition for USB_ADDR3_RX register ***************/
hudakz	0:a04710facbb6	5628	#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
hudakz	0:a04710facbb6	5629	#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /!< 0x0000FFFE /
hudakz	0:a04710facbb6	5630	#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /!< Reception Buffer Address 3 /
hudakz	0:a04710facbb6	5631
hudakz	0:a04710facbb6	5632	/*************** Bit definition for USB_ADDR4_RX register ***************/
hudakz	0:a04710facbb6	5633	#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
hudakz	0:a04710facbb6	5634	#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /!< 0x0000FFFE /
hudakz	0:a04710facbb6	5635	#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /!< Reception Buffer Address 4 /
hudakz	0:a04710facbb6	5636
hudakz	0:a04710facbb6	5637	/*************** Bit definition for USB_ADDR5_RX register ***************/
hudakz	0:a04710facbb6	5638	#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
hudakz	0:a04710facbb6	5639	#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /!< 0x0000FFFE /
hudakz	0:a04710facbb6	5640	#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /!< Reception Buffer Address 5 /
hudakz	0:a04710facbb6	5641
hudakz	0:a04710facbb6	5642	/*************** Bit definition for USB_ADDR6_RX register ***************/
hudakz	0:a04710facbb6	5643	#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
hudakz	0:a04710facbb6	5644	#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /!< 0x0000FFFE /
hudakz	0:a04710facbb6	5645	#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /!< Reception Buffer Address 6 /
hudakz	0:a04710facbb6	5646
hudakz	0:a04710facbb6	5647	/*************** Bit definition for USB_ADDR7_RX register ***************/
hudakz	0:a04710facbb6	5648	#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
hudakz	0:a04710facbb6	5649	#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /!< 0x0000FFFE /
hudakz	0:a04710facbb6	5650	#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /!< Reception Buffer Address 7 /
hudakz	0:a04710facbb6	5651
hudakz	0:a04710facbb6	5652	/----------------------------------------------------------------------------/
hudakz	0:a04710facbb6	5653
hudakz	0:a04710facbb6	5654	/*************** Bit definition for USB_COUNT0_RX register **************/
hudakz	0:a04710facbb6	5655	#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
hudakz	0:a04710facbb6	5656	#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /!< 0x000003FF /
hudakz	0:a04710facbb6	5657	#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /!< Reception Byte Count /
hudakz	0:a04710facbb6	5658
hudakz	0:a04710facbb6	5659	#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
hudakz	0:a04710facbb6	5660	#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
hudakz	0:a04710facbb6	5661	#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
hudakz	0:a04710facbb6	5662	#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	5663	#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	5664	#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	5665	#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	5666	#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	5667
hudakz	0:a04710facbb6	5668	#define USB_COUNT0_RX_BLSIZE_Pos (15U)
hudakz	0:a04710facbb6	5669	#define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	5670	#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /!< BLock SIZE /
hudakz	0:a04710facbb6	5671
hudakz	0:a04710facbb6	5672	/*************** Bit definition for USB_COUNT1_RX register **************/
hudakz	0:a04710facbb6	5673	#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
hudakz	0:a04710facbb6	5674	#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /!< 0x000003FF /
hudakz	0:a04710facbb6	5675	#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /!< Reception Byte Count /
hudakz	0:a04710facbb6	5676
hudakz	0:a04710facbb6	5677	#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
hudakz	0:a04710facbb6	5678	#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
hudakz	0:a04710facbb6	5679	#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
hudakz	0:a04710facbb6	5680	#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	5681	#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	5682	#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	5683	#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	5684	#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	5685
hudakz	0:a04710facbb6	5686	#define USB_COUNT1_RX_BLSIZE_Pos (15U)
hudakz	0:a04710facbb6	5687	#define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	5688	#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /!< BLock SIZE /
hudakz	0:a04710facbb6	5689
hudakz	0:a04710facbb6	5690	/*************** Bit definition for USB_COUNT2_RX register **************/
hudakz	0:a04710facbb6	5691	#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
hudakz	0:a04710facbb6	5692	#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /!< 0x000003FF /
hudakz	0:a04710facbb6	5693	#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /!< Reception Byte Count /
hudakz	0:a04710facbb6	5694
hudakz	0:a04710facbb6	5695	#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
hudakz	0:a04710facbb6	5696	#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
hudakz	0:a04710facbb6	5697	#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
hudakz	0:a04710facbb6	5698	#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	5699	#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	5700	#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	5701	#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	5702	#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	5703
hudakz	0:a04710facbb6	5704	#define USB_COUNT2_RX_BLSIZE_Pos (15U)
hudakz	0:a04710facbb6	5705	#define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	5706	#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /!< BLock SIZE /
hudakz	0:a04710facbb6	5707
hudakz	0:a04710facbb6	5708	/*************** Bit definition for USB_COUNT3_RX register **************/
hudakz	0:a04710facbb6	5709	#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
hudakz	0:a04710facbb6	5710	#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /!< 0x000003FF /
hudakz	0:a04710facbb6	5711	#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /!< Reception Byte Count /
hudakz	0:a04710facbb6	5712
hudakz	0:a04710facbb6	5713	#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
hudakz	0:a04710facbb6	5714	#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
hudakz	0:a04710facbb6	5715	#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
hudakz	0:a04710facbb6	5716	#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	5717	#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	5718	#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	5719	#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	5720	#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	5721
hudakz	0:a04710facbb6	5722	#define USB_COUNT3_RX_BLSIZE_Pos (15U)
hudakz	0:a04710facbb6	5723	#define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	5724	#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /!< BLock SIZE /
hudakz	0:a04710facbb6	5725
hudakz	0:a04710facbb6	5726	/*************** Bit definition for USB_COUNT4_RX register **************/
hudakz	0:a04710facbb6	5727	#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
hudakz	0:a04710facbb6	5728	#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /!< 0x000003FF /
hudakz	0:a04710facbb6	5729	#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /!< Reception Byte Count /
hudakz	0:a04710facbb6	5730
hudakz	0:a04710facbb6	5731	#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
hudakz	0:a04710facbb6	5732	#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
hudakz	0:a04710facbb6	5733	#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
hudakz	0:a04710facbb6	5734	#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	5735	#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	5736	#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	5737	#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	5738	#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	5739
hudakz	0:a04710facbb6	5740	#define USB_COUNT4_RX_BLSIZE_Pos (15U)
hudakz	0:a04710facbb6	5741	#define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	5742	#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /!< BLock SIZE /
hudakz	0:a04710facbb6	5743
hudakz	0:a04710facbb6	5744	/*************** Bit definition for USB_COUNT5_RX register **************/
hudakz	0:a04710facbb6	5745	#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
hudakz	0:a04710facbb6	5746	#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /!< 0x000003FF /
hudakz	0:a04710facbb6	5747	#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /!< Reception Byte Count /
hudakz	0:a04710facbb6	5748
hudakz	0:a04710facbb6	5749	#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
hudakz	0:a04710facbb6	5750	#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
hudakz	0:a04710facbb6	5751	#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
hudakz	0:a04710facbb6	5752	#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	5753	#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	5754	#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	5755	#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	5756	#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	5757
hudakz	0:a04710facbb6	5758	#define USB_COUNT5_RX_BLSIZE_Pos (15U)
hudakz	0:a04710facbb6	5759	#define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	5760	#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /!< BLock SIZE /
hudakz	0:a04710facbb6	5761
hudakz	0:a04710facbb6	5762	/*************** Bit definition for USB_COUNT6_RX register **************/
hudakz	0:a04710facbb6	5763	#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
hudakz	0:a04710facbb6	5764	#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /!< 0x000003FF /
hudakz	0:a04710facbb6	5765	#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /!< Reception Byte Count /
hudakz	0:a04710facbb6	5766
hudakz	0:a04710facbb6	5767	#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
hudakz	0:a04710facbb6	5768	#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
hudakz	0:a04710facbb6	5769	#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
hudakz	0:a04710facbb6	5770	#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	5771	#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	5772	#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	5773	#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	5774	#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	5775
hudakz	0:a04710facbb6	5776	#define USB_COUNT6_RX_BLSIZE_Pos (15U)
hudakz	0:a04710facbb6	5777	#define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	5778	#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /!< BLock SIZE /
hudakz	0:a04710facbb6	5779
hudakz	0:a04710facbb6	5780	/*************** Bit definition for USB_COUNT7_RX register **************/
hudakz	0:a04710facbb6	5781	#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
hudakz	0:a04710facbb6	5782	#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /!< 0x000003FF /
hudakz	0:a04710facbb6	5783	#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /!< Reception Byte Count /
hudakz	0:a04710facbb6	5784
hudakz	0:a04710facbb6	5785	#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
hudakz	0:a04710facbb6	5786	#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
hudakz	0:a04710facbb6	5787	#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
hudakz	0:a04710facbb6	5788	#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	5789	#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	5790	#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	5791	#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	5792	#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	5793
hudakz	0:a04710facbb6	5794	#define USB_COUNT7_RX_BLSIZE_Pos (15U)
hudakz	0:a04710facbb6	5795	#define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	5796	#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /!< BLock SIZE /
hudakz	0:a04710facbb6	5797
hudakz	0:a04710facbb6	5798	/----------------------------------------------------------------------------/
hudakz	0:a04710facbb6	5799
hudakz	0:a04710facbb6	5800	/************** Bit definition for USB_COUNT0_RX_0 register *************/
hudakz	0:a04710facbb6	5801	#define USB_COUNT0_RX_0_COUNT0_RX_0 0x000003FFU /!< Reception Byte Count (low) /
hudakz	0:a04710facbb6	5802
hudakz	0:a04710facbb6	5803	#define USB_COUNT0_RX_0_NUM_BLOCK_0 0x00007C00U /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
hudakz	0:a04710facbb6	5804	#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 0x00000400U /!< Bit 0 /
hudakz	0:a04710facbb6	5805	#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 0x00000800U /!< Bit 1 /
hudakz	0:a04710facbb6	5806	#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 0x00001000U /!< Bit 2 /
hudakz	0:a04710facbb6	5807	#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 0x00002000U /!< Bit 3 /
hudakz	0:a04710facbb6	5808	#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 0x00004000U /!< Bit 4 /
hudakz	0:a04710facbb6	5809
hudakz	0:a04710facbb6	5810	#define USB_COUNT0_RX_0_BLSIZE_0 0x00008000U /!< BLock SIZE (low) /
hudakz	0:a04710facbb6	5811
hudakz	0:a04710facbb6	5812	/************** Bit definition for USB_COUNT0_RX_1 register *************/
hudakz	0:a04710facbb6	5813	#define USB_COUNT0_RX_1_COUNT0_RX_1 0x03FF0000U /!< Reception Byte Count (high) /
hudakz	0:a04710facbb6	5814
hudakz	0:a04710facbb6	5815	#define USB_COUNT0_RX_1_NUM_BLOCK_1 0x7C000000U /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
hudakz	0:a04710facbb6	5816	#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 0x04000000U /!< Bit 1 /
hudakz	0:a04710facbb6	5817	#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 0x08000000U /!< Bit 1 /
hudakz	0:a04710facbb6	5818	#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 0x10000000U /!< Bit 2 /
hudakz	0:a04710facbb6	5819	#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 0x20000000U /!< Bit 3 /
hudakz	0:a04710facbb6	5820	#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 0x40000000U /!< Bit 4 /
hudakz	0:a04710facbb6	5821
hudakz	0:a04710facbb6	5822	#define USB_COUNT0_RX_1_BLSIZE_1 0x80000000U /!< BLock SIZE (high) /
hudakz	0:a04710facbb6	5823
hudakz	0:a04710facbb6	5824	/************** Bit definition for USB_COUNT1_RX_0 register *************/
hudakz	0:a04710facbb6	5825	#define USB_COUNT1_RX_0_COUNT1_RX_0 0x000003FFU /!< Reception Byte Count (low) /
hudakz	0:a04710facbb6	5826
hudakz	0:a04710facbb6	5827	#define USB_COUNT1_RX_0_NUM_BLOCK_0 0x00007C00U /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
hudakz	0:a04710facbb6	5828	#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 0x00000400U /!< Bit 0 /
hudakz	0:a04710facbb6	5829	#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 0x00000800U /!< Bit 1 /
hudakz	0:a04710facbb6	5830	#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 0x00001000U /!< Bit 2 /
hudakz	0:a04710facbb6	5831	#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 0x00002000U /!< Bit 3 /
hudakz	0:a04710facbb6	5832	#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 0x00004000U /!< Bit 4 /
hudakz	0:a04710facbb6	5833
hudakz	0:a04710facbb6	5834	#define USB_COUNT1_RX_0_BLSIZE_0 0x00008000U /!< BLock SIZE (low) /
hudakz	0:a04710facbb6	5835
hudakz	0:a04710facbb6	5836	/************** Bit definition for USB_COUNT1_RX_1 register *************/
hudakz	0:a04710facbb6	5837	#define USB_COUNT1_RX_1_COUNT1_RX_1 0x03FF0000U /!< Reception Byte Count (high) /
hudakz	0:a04710facbb6	5838
hudakz	0:a04710facbb6	5839	#define USB_COUNT1_RX_1_NUM_BLOCK_1 0x7C000000U /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
hudakz	0:a04710facbb6	5840	#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 0x04000000U /!< Bit 0 /
hudakz	0:a04710facbb6	5841	#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 0x08000000U /!< Bit 1 /
hudakz	0:a04710facbb6	5842	#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 0x10000000U /!< Bit 2 /
hudakz	0:a04710facbb6	5843	#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 0x20000000U /!< Bit 3 /
hudakz	0:a04710facbb6	5844	#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 0x40000000U /!< Bit 4 /
hudakz	0:a04710facbb6	5845
hudakz	0:a04710facbb6	5846	#define USB_COUNT1_RX_1_BLSIZE_1 0x80000000U /!< BLock SIZE (high) /
hudakz	0:a04710facbb6	5847
hudakz	0:a04710facbb6	5848	/************** Bit definition for USB_COUNT2_RX_0 register *************/
hudakz	0:a04710facbb6	5849	#define USB_COUNT2_RX_0_COUNT2_RX_0 0x000003FFU /!< Reception Byte Count (low) /
hudakz	0:a04710facbb6	5850
hudakz	0:a04710facbb6	5851	#define USB_COUNT2_RX_0_NUM_BLOCK_0 0x00007C00U /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
hudakz	0:a04710facbb6	5852	#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 0x00000400U /!< Bit 0 /
hudakz	0:a04710facbb6	5853	#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 0x00000800U /!< Bit 1 /
hudakz	0:a04710facbb6	5854	#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 0x00001000U /!< Bit 2 /
hudakz	0:a04710facbb6	5855	#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 0x00002000U /!< Bit 3 /
hudakz	0:a04710facbb6	5856	#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 0x00004000U /!< Bit 4 /
hudakz	0:a04710facbb6	5857
hudakz	0:a04710facbb6	5858	#define USB_COUNT2_RX_0_BLSIZE_0 0x00008000U /!< BLock SIZE (low) /
hudakz	0:a04710facbb6	5859
hudakz	0:a04710facbb6	5860	/************** Bit definition for USB_COUNT2_RX_1 register *************/
hudakz	0:a04710facbb6	5861	#define USB_COUNT2_RX_1_COUNT2_RX_1 0x03FF0000U /!< Reception Byte Count (high) /
hudakz	0:a04710facbb6	5862
hudakz	0:a04710facbb6	5863	#define USB_COUNT2_RX_1_NUM_BLOCK_1 0x7C000000U /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
hudakz	0:a04710facbb6	5864	#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 0x04000000U /!< Bit 0 /
hudakz	0:a04710facbb6	5865	#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 0x08000000U /!< Bit 1 /
hudakz	0:a04710facbb6	5866	#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 0x10000000U /!< Bit 2 /
hudakz	0:a04710facbb6	5867	#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 0x20000000U /!< Bit 3 /
hudakz	0:a04710facbb6	5868	#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 0x40000000U /!< Bit 4 /
hudakz	0:a04710facbb6	5869
hudakz	0:a04710facbb6	5870	#define USB_COUNT2_RX_1_BLSIZE_1 0x80000000U /!< BLock SIZE (high) /
hudakz	0:a04710facbb6	5871
hudakz	0:a04710facbb6	5872	/************** Bit definition for USB_COUNT3_RX_0 register *************/
hudakz	0:a04710facbb6	5873	#define USB_COUNT3_RX_0_COUNT3_RX_0 0x000003FFU /!< Reception Byte Count (low) /
hudakz	0:a04710facbb6	5874
hudakz	0:a04710facbb6	5875	#define USB_COUNT3_RX_0_NUM_BLOCK_0 0x00007C00U /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
hudakz	0:a04710facbb6	5876	#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 0x00000400U /!< Bit 0 /
hudakz	0:a04710facbb6	5877	#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 0x00000800U /!< Bit 1 /
hudakz	0:a04710facbb6	5878	#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 0x00001000U /!< Bit 2 /
hudakz	0:a04710facbb6	5879	#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 0x00002000U /!< Bit 3 /
hudakz	0:a04710facbb6	5880	#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 0x00004000U /!< Bit 4 /
hudakz	0:a04710facbb6	5881
hudakz	0:a04710facbb6	5882	#define USB_COUNT3_RX_0_BLSIZE_0 0x00008000U /!< BLock SIZE (low) /
hudakz	0:a04710facbb6	5883
hudakz	0:a04710facbb6	5884	/************** Bit definition for USB_COUNT3_RX_1 register *************/
hudakz	0:a04710facbb6	5885	#define USB_COUNT3_RX_1_COUNT3_RX_1 0x03FF0000U /!< Reception Byte Count (high) /
hudakz	0:a04710facbb6	5886
hudakz	0:a04710facbb6	5887	#define USB_COUNT3_RX_1_NUM_BLOCK_1 0x7C000000U /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
hudakz	0:a04710facbb6	5888	#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 0x04000000U /!< Bit 0 /
hudakz	0:a04710facbb6	5889	#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 0x08000000U /!< Bit 1 /
hudakz	0:a04710facbb6	5890	#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 0x10000000U /!< Bit 2 /
hudakz	0:a04710facbb6	5891	#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 0x20000000U /!< Bit 3 /
hudakz	0:a04710facbb6	5892	#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 0x40000000U /!< Bit 4 /
hudakz	0:a04710facbb6	5893
hudakz	0:a04710facbb6	5894	#define USB_COUNT3_RX_1_BLSIZE_1 0x80000000U /!< BLock SIZE (high) /
hudakz	0:a04710facbb6	5895
hudakz	0:a04710facbb6	5896	/************** Bit definition for USB_COUNT4_RX_0 register *************/
hudakz	0:a04710facbb6	5897	#define USB_COUNT4_RX_0_COUNT4_RX_0 0x000003FFU /!< Reception Byte Count (low) /
hudakz	0:a04710facbb6	5898
hudakz	0:a04710facbb6	5899	#define USB_COUNT4_RX_0_NUM_BLOCK_0 0x00007C00U /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
hudakz	0:a04710facbb6	5900	#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 0x00000400U /!< Bit 0 /
hudakz	0:a04710facbb6	5901	#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 0x00000800U /!< Bit 1 /
hudakz	0:a04710facbb6	5902	#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 0x00001000U /!< Bit 2 /
hudakz	0:a04710facbb6	5903	#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 0x00002000U /!< Bit 3 /
hudakz	0:a04710facbb6	5904	#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 0x00004000U /!< Bit 4 /
hudakz	0:a04710facbb6	5905
hudakz	0:a04710facbb6	5906	#define USB_COUNT4_RX_0_BLSIZE_0 0x00008000U /!< BLock SIZE (low) /
hudakz	0:a04710facbb6	5907
hudakz	0:a04710facbb6	5908	/************** Bit definition for USB_COUNT4_RX_1 register *************/
hudakz	0:a04710facbb6	5909	#define USB_COUNT4_RX_1_COUNT4_RX_1 0x03FF0000U /!< Reception Byte Count (high) /
hudakz	0:a04710facbb6	5910
hudakz	0:a04710facbb6	5911	#define USB_COUNT4_RX_1_NUM_BLOCK_1 0x7C000000U /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
hudakz	0:a04710facbb6	5912	#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 0x04000000U /!< Bit 0 /
hudakz	0:a04710facbb6	5913	#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 0x08000000U /!< Bit 1 /
hudakz	0:a04710facbb6	5914	#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 0x10000000U /!< Bit 2 /
hudakz	0:a04710facbb6	5915	#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 0x20000000U /!< Bit 3 /
hudakz	0:a04710facbb6	5916	#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 0x40000000U /!< Bit 4 /
hudakz	0:a04710facbb6	5917
hudakz	0:a04710facbb6	5918	#define USB_COUNT4_RX_1_BLSIZE_1 0x80000000U /!< BLock SIZE (high) /
hudakz	0:a04710facbb6	5919
hudakz	0:a04710facbb6	5920	/************** Bit definition for USB_COUNT5_RX_0 register *************/
hudakz	0:a04710facbb6	5921	#define USB_COUNT5_RX_0_COUNT5_RX_0 0x000003FFU /!< Reception Byte Count (low) /
hudakz	0:a04710facbb6	5922
hudakz	0:a04710facbb6	5923	#define USB_COUNT5_RX_0_NUM_BLOCK_0 0x00007C00U /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
hudakz	0:a04710facbb6	5924	#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 0x00000400U /!< Bit 0 /
hudakz	0:a04710facbb6	5925	#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 0x00000800U /!< Bit 1 /
hudakz	0:a04710facbb6	5926	#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 0x00001000U /!< Bit 2 /
hudakz	0:a04710facbb6	5927	#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 0x00002000U /!< Bit 3 /
hudakz	0:a04710facbb6	5928	#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 0x00004000U /!< Bit 4 /
hudakz	0:a04710facbb6	5929
hudakz	0:a04710facbb6	5930	#define USB_COUNT5_RX_0_BLSIZE_0 0x00008000U /!< BLock SIZE (low) /
hudakz	0:a04710facbb6	5931
hudakz	0:a04710facbb6	5932	/************** Bit definition for USB_COUNT5_RX_1 register *************/
hudakz	0:a04710facbb6	5933	#define USB_COUNT5_RX_1_COUNT5_RX_1 0x03FF0000U /!< Reception Byte Count (high) /
hudakz	0:a04710facbb6	5934
hudakz	0:a04710facbb6	5935	#define USB_COUNT5_RX_1_NUM_BLOCK_1 0x7C000000U /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
hudakz	0:a04710facbb6	5936	#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 0x04000000U /!< Bit 0 /
hudakz	0:a04710facbb6	5937	#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 0x08000000U /!< Bit 1 /
hudakz	0:a04710facbb6	5938	#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 0x10000000U /!< Bit 2 /
hudakz	0:a04710facbb6	5939	#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 0x20000000U /!< Bit 3 /
hudakz	0:a04710facbb6	5940	#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 0x40000000U /!< Bit 4 /
hudakz	0:a04710facbb6	5941
hudakz	0:a04710facbb6	5942	#define USB_COUNT5_RX_1_BLSIZE_1 0x80000000U /!< BLock SIZE (high) /
hudakz	0:a04710facbb6	5943
hudakz	0:a04710facbb6	5944	/************* Bit definition for USB_COUNT6_RX_0 register *************/
hudakz	0:a04710facbb6	5945	#define USB_COUNT6_RX_0_COUNT6_RX_0 0x000003FFU /!< Reception Byte Count (low) /
hudakz	0:a04710facbb6	5946
hudakz	0:a04710facbb6	5947	#define USB_COUNT6_RX_0_NUM_BLOCK_0 0x00007C00U /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
hudakz	0:a04710facbb6	5948	#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 0x00000400U /!< Bit 0 /
hudakz	0:a04710facbb6	5949	#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 0x00000800U /!< Bit 1 /
hudakz	0:a04710facbb6	5950	#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 0x00001000U /!< Bit 2 /
hudakz	0:a04710facbb6	5951	#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 0x00002000U /!< Bit 3 /
hudakz	0:a04710facbb6	5952	#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 0x00004000U /!< Bit 4 /
hudakz	0:a04710facbb6	5953
hudakz	0:a04710facbb6	5954	#define USB_COUNT6_RX_0_BLSIZE_0 0x00008000U /!< BLock SIZE (low) /
hudakz	0:a04710facbb6	5955
hudakz	0:a04710facbb6	5956	/************** Bit definition for USB_COUNT6_RX_1 register *************/
hudakz	0:a04710facbb6	5957	#define USB_COUNT6_RX_1_COUNT6_RX_1 0x03FF0000U /!< Reception Byte Count (high) /
hudakz	0:a04710facbb6	5958
hudakz	0:a04710facbb6	5959	#define USB_COUNT6_RX_1_NUM_BLOCK_1 0x7C000000U /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
hudakz	0:a04710facbb6	5960	#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 0x04000000U /!< Bit 0 /
hudakz	0:a04710facbb6	5961	#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 0x08000000U /!< Bit 1 /
hudakz	0:a04710facbb6	5962	#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 0x10000000U /!< Bit 2 /
hudakz	0:a04710facbb6	5963	#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 0x20000000U /!< Bit 3 /
hudakz	0:a04710facbb6	5964	#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 0x40000000U /!< Bit 4 /
hudakz	0:a04710facbb6	5965
hudakz	0:a04710facbb6	5966	#define USB_COUNT6_RX_1_BLSIZE_1 0x80000000U /!< BLock SIZE (high) /
hudakz	0:a04710facbb6	5967
hudakz	0:a04710facbb6	5968	/************* Bit definition for USB_COUNT7_RX_0 register **************/
hudakz	0:a04710facbb6	5969	#define USB_COUNT7_RX_0_COUNT7_RX_0 0x000003FFU /!< Reception Byte Count (low) /
hudakz	0:a04710facbb6	5970
hudakz	0:a04710facbb6	5971	#define USB_COUNT7_RX_0_NUM_BLOCK_0 0x00007C00U /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
hudakz	0:a04710facbb6	5972	#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 0x00000400U /!< Bit 0 /
hudakz	0:a04710facbb6	5973	#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 0x00000800U /!< Bit 1 /
hudakz	0:a04710facbb6	5974	#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 0x00001000U /!< Bit 2 /
hudakz	0:a04710facbb6	5975	#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 0x00002000U /!< Bit 3 /
hudakz	0:a04710facbb6	5976	#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 0x00004000U /!< Bit 4 /
hudakz	0:a04710facbb6	5977
hudakz	0:a04710facbb6	5978	#define USB_COUNT7_RX_0_BLSIZE_0 0x00008000U /!< BLock SIZE (low) /
hudakz	0:a04710facbb6	5979
hudakz	0:a04710facbb6	5980	/************* Bit definition for USB_COUNT7_RX_1 register **************/
hudakz	0:a04710facbb6	5981	#define USB_COUNT7_RX_1_COUNT7_RX_1 0x03FF0000U /!< Reception Byte Count (high) /
hudakz	0:a04710facbb6	5982
hudakz	0:a04710facbb6	5983	#define USB_COUNT7_RX_1_NUM_BLOCK_1 0x7C000000U /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
hudakz	0:a04710facbb6	5984	#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 0x04000000U /!< Bit 0 /
hudakz	0:a04710facbb6	5985	#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 0x08000000U /!< Bit 1 /
hudakz	0:a04710facbb6	5986	#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 0x10000000U /!< Bit 2 /
hudakz	0:a04710facbb6	5987	#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 0x20000000U /!< Bit 3 /
hudakz	0:a04710facbb6	5988	#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 0x40000000U /!< Bit 4 /
hudakz	0:a04710facbb6	5989
hudakz	0:a04710facbb6	5990	#define USB_COUNT7_RX_1_BLSIZE_1 0x80000000U /!< BLock SIZE (high) /
hudakz	0:a04710facbb6	5991
hudakz	0:a04710facbb6	5992	/******************************************************************************/
hudakz	0:a04710facbb6	5993	/* */
hudakz	0:a04710facbb6	5994	/* Controller Area Network */
hudakz	0:a04710facbb6	5995	/* */
hudakz	0:a04710facbb6	5996	/******************************************************************************/
hudakz	0:a04710facbb6	5997
hudakz	0:a04710facbb6	5998	/!< CAN control and status registers /
hudakz	0:a04710facbb6	5999	/***************** Bit definition for CAN_MCR register ******************/
hudakz	0:a04710facbb6	6000	#define CAN_MCR_INRQ_Pos (0U)
hudakz	0:a04710facbb6	6001	#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	6002	#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /!< Initialization Request /
hudakz	0:a04710facbb6	6003	#define CAN_MCR_SLEEP_Pos (1U)
hudakz	0:a04710facbb6	6004	#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	6005	#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /!< Sleep Mode Request /
hudakz	0:a04710facbb6	6006	#define CAN_MCR_TXFP_Pos (2U)
hudakz	0:a04710facbb6	6007	#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	6008	#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /!< Transmit FIFO Priority /
hudakz	0:a04710facbb6	6009	#define CAN_MCR_RFLM_Pos (3U)
hudakz	0:a04710facbb6	6010	#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	6011	#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /!< Receive FIFO Locked Mode /
hudakz	0:a04710facbb6	6012	#define CAN_MCR_NART_Pos (4U)
hudakz	0:a04710facbb6	6013	#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	6014	#define CAN_MCR_NART CAN_MCR_NART_Msk /!< No Automatic Retransmission /
hudakz	0:a04710facbb6	6015	#define CAN_MCR_AWUM_Pos (5U)
hudakz	0:a04710facbb6	6016	#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	6017	#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /!< Automatic Wakeup Mode /
hudakz	0:a04710facbb6	6018	#define CAN_MCR_ABOM_Pos (6U)
hudakz	0:a04710facbb6	6019	#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	6020	#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /!< Automatic Bus-Off Management /
hudakz	0:a04710facbb6	6021	#define CAN_MCR_TTCM_Pos (7U)
hudakz	0:a04710facbb6	6022	#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	6023	#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /!< Time Triggered Communication Mode /
hudakz	0:a04710facbb6	6024	#define CAN_MCR_RESET_Pos (15U)
hudakz	0:a04710facbb6	6025	#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	6026	#define CAN_MCR_RESET CAN_MCR_RESET_Msk /!< CAN software master reset /
hudakz	0:a04710facbb6	6027	#define CAN_MCR_DBF_Pos (16U)
hudakz	0:a04710facbb6	6028	#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	6029	#define CAN_MCR_DBF CAN_MCR_DBF_Msk /!< CAN Debug freeze /
hudakz	0:a04710facbb6	6030
hudakz	0:a04710facbb6	6031	/***************** Bit definition for CAN_MSR register ******************/
hudakz	0:a04710facbb6	6032	#define CAN_MSR_INAK_Pos (0U)
hudakz	0:a04710facbb6	6033	#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	6034	#define CAN_MSR_INAK CAN_MSR_INAK_Msk /!< Initialization Acknowledge /
hudakz	0:a04710facbb6	6035	#define CAN_MSR_SLAK_Pos (1U)
hudakz	0:a04710facbb6	6036	#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	6037	#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /!< Sleep Acknowledge /
hudakz	0:a04710facbb6	6038	#define CAN_MSR_ERRI_Pos (2U)
hudakz	0:a04710facbb6	6039	#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	6040	#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /!< Error Interrupt /
hudakz	0:a04710facbb6	6041	#define CAN_MSR_WKUI_Pos (3U)
hudakz	0:a04710facbb6	6042	#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	6043	#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /!< Wakeup Interrupt /
hudakz	0:a04710facbb6	6044	#define CAN_MSR_SLAKI_Pos (4U)
hudakz	0:a04710facbb6	6045	#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	6046	#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /!< Sleep Acknowledge Interrupt /
hudakz	0:a04710facbb6	6047	#define CAN_MSR_TXM_Pos (8U)
hudakz	0:a04710facbb6	6048	#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	6049	#define CAN_MSR_TXM CAN_MSR_TXM_Msk /!< Transmit Mode /
hudakz	0:a04710facbb6	6050	#define CAN_MSR_RXM_Pos (9U)
hudakz	0:a04710facbb6	6051	#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	6052	#define CAN_MSR_RXM CAN_MSR_RXM_Msk /!< Receive Mode /
hudakz	0:a04710facbb6	6053	#define CAN_MSR_SAMP_Pos (10U)
hudakz	0:a04710facbb6	6054	#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	6055	#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /!< Last Sample Point /
hudakz	0:a04710facbb6	6056	#define CAN_MSR_RX_Pos (11U)
hudakz	0:a04710facbb6	6057	#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	6058	#define CAN_MSR_RX CAN_MSR_RX_Msk /!< CAN Rx Signal /
hudakz	0:a04710facbb6	6059
hudakz	0:a04710facbb6	6060	/***************** Bit definition for CAN_TSR register ******************/
hudakz	0:a04710facbb6	6061	#define CAN_TSR_RQCP0_Pos (0U)
hudakz	0:a04710facbb6	6062	#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	6063	#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /!< Request Completed Mailbox0 /
hudakz	0:a04710facbb6	6064	#define CAN_TSR_TXOK0_Pos (1U)
hudakz	0:a04710facbb6	6065	#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	6066	#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /!< Transmission OK of Mailbox0 /
hudakz	0:a04710facbb6	6067	#define CAN_TSR_ALST0_Pos (2U)
hudakz	0:a04710facbb6	6068	#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	6069	#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /!< Arbitration Lost for Mailbox0 /
hudakz	0:a04710facbb6	6070	#define CAN_TSR_TERR0_Pos (3U)
hudakz	0:a04710facbb6	6071	#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	6072	#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /!< Transmission Error of Mailbox0 /
hudakz	0:a04710facbb6	6073	#define CAN_TSR_ABRQ0_Pos (7U)
hudakz	0:a04710facbb6	6074	#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	6075	#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /!< Abort Request for Mailbox0 /
hudakz	0:a04710facbb6	6076	#define CAN_TSR_RQCP1_Pos (8U)
hudakz	0:a04710facbb6	6077	#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	6078	#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /!< Request Completed Mailbox1 /
hudakz	0:a04710facbb6	6079	#define CAN_TSR_TXOK1_Pos (9U)
hudakz	0:a04710facbb6	6080	#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	6081	#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /!< Transmission OK of Mailbox1 /
hudakz	0:a04710facbb6	6082	#define CAN_TSR_ALST1_Pos (10U)
hudakz	0:a04710facbb6	6083	#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	6084	#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /!< Arbitration Lost for Mailbox1 /
hudakz	0:a04710facbb6	6085	#define CAN_TSR_TERR1_Pos (11U)
hudakz	0:a04710facbb6	6086	#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	6087	#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /!< Transmission Error of Mailbox1 /
hudakz	0:a04710facbb6	6088	#define CAN_TSR_ABRQ1_Pos (15U)
hudakz	0:a04710facbb6	6089	#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	6090	#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /!< Abort Request for Mailbox 1 /
hudakz	0:a04710facbb6	6091	#define CAN_TSR_RQCP2_Pos (16U)
hudakz	0:a04710facbb6	6092	#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	6093	#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /!< Request Completed Mailbox2 /
hudakz	0:a04710facbb6	6094	#define CAN_TSR_TXOK2_Pos (17U)
hudakz	0:a04710facbb6	6095	#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	6096	#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /!< Transmission OK of Mailbox 2 /
hudakz	0:a04710facbb6	6097	#define CAN_TSR_ALST2_Pos (18U)
hudakz	0:a04710facbb6	6098	#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	6099	#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /!< Arbitration Lost for mailbox 2 /
hudakz	0:a04710facbb6	6100	#define CAN_TSR_TERR2_Pos (19U)
hudakz	0:a04710facbb6	6101	#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	6102	#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /!< Transmission Error of Mailbox 2 /
hudakz	0:a04710facbb6	6103	#define CAN_TSR_ABRQ2_Pos (23U)
hudakz	0:a04710facbb6	6104	#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	6105	#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /!< Abort Request for Mailbox 2 /
hudakz	0:a04710facbb6	6106	#define CAN_TSR_CODE_Pos (24U)
hudakz	0:a04710facbb6	6107	#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /!< 0x03000000 /
hudakz	0:a04710facbb6	6108	#define CAN_TSR_CODE CAN_TSR_CODE_Msk /!< Mailbox Code /
hudakz	0:a04710facbb6	6109
hudakz	0:a04710facbb6	6110	#define CAN_TSR_TME_Pos (26U)
hudakz	0:a04710facbb6	6111	#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /!< 0x1C000000 /
hudakz	0:a04710facbb6	6112	#define CAN_TSR_TME CAN_TSR_TME_Msk /!< TME[2:0] bits /
hudakz	0:a04710facbb6	6113	#define CAN_TSR_TME0_Pos (26U)
hudakz	0:a04710facbb6	6114	#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	6115	#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /!< Transmit Mailbox 0 Empty /
hudakz	0:a04710facbb6	6116	#define CAN_TSR_TME1_Pos (27U)
hudakz	0:a04710facbb6	6117	#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	6118	#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /!< Transmit Mailbox 1 Empty /
hudakz	0:a04710facbb6	6119	#define CAN_TSR_TME2_Pos (28U)
hudakz	0:a04710facbb6	6120	#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	6121	#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /!< Transmit Mailbox 2 Empty /
hudakz	0:a04710facbb6	6122
hudakz	0:a04710facbb6	6123	#define CAN_TSR_LOW_Pos (29U)
hudakz	0:a04710facbb6	6124	#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /!< 0xE0000000 /
hudakz	0:a04710facbb6	6125	#define CAN_TSR_LOW CAN_TSR_LOW_Msk /!< LOW[2:0] bits /
hudakz	0:a04710facbb6	6126	#define CAN_TSR_LOW0_Pos (29U)
hudakz	0:a04710facbb6	6127	#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	6128	#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /!< Lowest Priority Flag for Mailbox 0 /
hudakz	0:a04710facbb6	6129	#define CAN_TSR_LOW1_Pos (30U)
hudakz	0:a04710facbb6	6130	#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	6131	#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /!< Lowest Priority Flag for Mailbox 1 /
hudakz	0:a04710facbb6	6132	#define CAN_TSR_LOW2_Pos (31U)
hudakz	0:a04710facbb6	6133	#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	6134	#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /!< Lowest Priority Flag for Mailbox 2 /
hudakz	0:a04710facbb6	6135
hudakz	0:a04710facbb6	6136	/***************** Bit definition for CAN_RF0R register *****************/
hudakz	0:a04710facbb6	6137	#define CAN_RF0R_FMP0_Pos (0U)
hudakz	0:a04710facbb6	6138	#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /!< 0x00000003 /
hudakz	0:a04710facbb6	6139	#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /!< FIFO 0 Message Pending /
hudakz	0:a04710facbb6	6140	#define CAN_RF0R_FULL0_Pos (3U)
hudakz	0:a04710facbb6	6141	#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	6142	#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /!< FIFO 0 Full /
hudakz	0:a04710facbb6	6143	#define CAN_RF0R_FOVR0_Pos (4U)
hudakz	0:a04710facbb6	6144	#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	6145	#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /!< FIFO 0 Overrun /
hudakz	0:a04710facbb6	6146	#define CAN_RF0R_RFOM0_Pos (5U)
hudakz	0:a04710facbb6	6147	#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	6148	#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /!< Release FIFO 0 Output Mailbox /
hudakz	0:a04710facbb6	6149
hudakz	0:a04710facbb6	6150	/***************** Bit definition for CAN_RF1R register *****************/
hudakz	0:a04710facbb6	6151	#define CAN_RF1R_FMP1_Pos (0U)
hudakz	0:a04710facbb6	6152	#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /!< 0x00000003 /
hudakz	0:a04710facbb6	6153	#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /!< FIFO 1 Message Pending /
hudakz	0:a04710facbb6	6154	#define CAN_RF1R_FULL1_Pos (3U)
hudakz	0:a04710facbb6	6155	#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	6156	#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /!< FIFO 1 Full /
hudakz	0:a04710facbb6	6157	#define CAN_RF1R_FOVR1_Pos (4U)
hudakz	0:a04710facbb6	6158	#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	6159	#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /!< FIFO 1 Overrun /
hudakz	0:a04710facbb6	6160	#define CAN_RF1R_RFOM1_Pos (5U)
hudakz	0:a04710facbb6	6161	#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	6162	#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /!< Release FIFO 1 Output Mailbox /
hudakz	0:a04710facbb6	6163
hudakz	0:a04710facbb6	6164	/****************** Bit definition for CAN_IER register *****************/
hudakz	0:a04710facbb6	6165	#define CAN_IER_TMEIE_Pos (0U)
hudakz	0:a04710facbb6	6166	#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	6167	#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /!< Transmit Mailbox Empty Interrupt Enable /
hudakz	0:a04710facbb6	6168	#define CAN_IER_FMPIE0_Pos (1U)
hudakz	0:a04710facbb6	6169	#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	6170	#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /!< FIFO Message Pending Interrupt Enable /
hudakz	0:a04710facbb6	6171	#define CAN_IER_FFIE0_Pos (2U)
hudakz	0:a04710facbb6	6172	#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	6173	#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /!< FIFO Full Interrupt Enable /
hudakz	0:a04710facbb6	6174	#define CAN_IER_FOVIE0_Pos (3U)
hudakz	0:a04710facbb6	6175	#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	6176	#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /!< FIFO Overrun Interrupt Enable /
hudakz	0:a04710facbb6	6177	#define CAN_IER_FMPIE1_Pos (4U)
hudakz	0:a04710facbb6	6178	#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	6179	#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /!< FIFO Message Pending Interrupt Enable /
hudakz	0:a04710facbb6	6180	#define CAN_IER_FFIE1_Pos (5U)
hudakz	0:a04710facbb6	6181	#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	6182	#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /!< FIFO Full Interrupt Enable /
hudakz	0:a04710facbb6	6183	#define CAN_IER_FOVIE1_Pos (6U)
hudakz	0:a04710facbb6	6184	#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	6185	#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /!< FIFO Overrun Interrupt Enable /
hudakz	0:a04710facbb6	6186	#define CAN_IER_EWGIE_Pos (8U)
hudakz	0:a04710facbb6	6187	#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	6188	#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /!< Error Warning Interrupt Enable /
hudakz	0:a04710facbb6	6189	#define CAN_IER_EPVIE_Pos (9U)
hudakz	0:a04710facbb6	6190	#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	6191	#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /!< Error Passive Interrupt Enable /
hudakz	0:a04710facbb6	6192	#define CAN_IER_BOFIE_Pos (10U)
hudakz	0:a04710facbb6	6193	#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	6194	#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /!< Bus-Off Interrupt Enable /
hudakz	0:a04710facbb6	6195	#define CAN_IER_LECIE_Pos (11U)
hudakz	0:a04710facbb6	6196	#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	6197	#define CAN_IER_LECIE CAN_IER_LECIE_Msk /!< Last Error Code Interrupt Enable /
hudakz	0:a04710facbb6	6198	#define CAN_IER_ERRIE_Pos (15U)
hudakz	0:a04710facbb6	6199	#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	6200	#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /!< Error Interrupt Enable /
hudakz	0:a04710facbb6	6201	#define CAN_IER_WKUIE_Pos (16U)
hudakz	0:a04710facbb6	6202	#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	6203	#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /!< Wakeup Interrupt Enable /
hudakz	0:a04710facbb6	6204	#define CAN_IER_SLKIE_Pos (17U)
hudakz	0:a04710facbb6	6205	#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	6206	#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /!< Sleep Interrupt Enable /
hudakz	0:a04710facbb6	6207
hudakz	0:a04710facbb6	6208	/****************** Bit definition for CAN_ESR register *****************/
hudakz	0:a04710facbb6	6209	#define CAN_ESR_EWGF_Pos (0U)
hudakz	0:a04710facbb6	6210	#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	6211	#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /!< Error Warning Flag /
hudakz	0:a04710facbb6	6212	#define CAN_ESR_EPVF_Pos (1U)
hudakz	0:a04710facbb6	6213	#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	6214	#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /!< Error Passive Flag /
hudakz	0:a04710facbb6	6215	#define CAN_ESR_BOFF_Pos (2U)
hudakz	0:a04710facbb6	6216	#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	6217	#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /!< Bus-Off Flag /
hudakz	0:a04710facbb6	6218
hudakz	0:a04710facbb6	6219	#define CAN_ESR_LEC_Pos (4U)
hudakz	0:a04710facbb6	6220	#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /!< 0x00000070 /
hudakz	0:a04710facbb6	6221	#define CAN_ESR_LEC CAN_ESR_LEC_Msk /!< LEC[2:0] bits (Last Error Code) /
hudakz	0:a04710facbb6	6222	#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	6223	#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	6224	#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	6225
hudakz	0:a04710facbb6	6226	#define CAN_ESR_TEC_Pos (16U)
hudakz	0:a04710facbb6	6227	#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /!< 0x00FF0000 /
hudakz	0:a04710facbb6	6228	#define CAN_ESR_TEC CAN_ESR_TEC_Msk /!< Least significant byte of the 9-bit Transmit Error Counter /
hudakz	0:a04710facbb6	6229	#define CAN_ESR_REC_Pos (24U)
hudakz	0:a04710facbb6	6230	#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /!< 0xFF000000 /
hudakz	0:a04710facbb6	6231	#define CAN_ESR_REC CAN_ESR_REC_Msk /!< Receive Error Counter /
hudakz	0:a04710facbb6	6232
hudakz	0:a04710facbb6	6233	/***************** Bit definition for CAN_BTR register ******************/
hudakz	0:a04710facbb6	6234	#define CAN_BTR_BRP_Pos (0U)
hudakz	0:a04710facbb6	6235	#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /!< 0x000003FF /
hudakz	0:a04710facbb6	6236	#define CAN_BTR_BRP CAN_BTR_BRP_Msk /!<Baud Rate Prescaler /
hudakz	0:a04710facbb6	6237	#define CAN_BTR_TS1_Pos (16U)
hudakz	0:a04710facbb6	6238	#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /!< 0x000F0000 /
hudakz	0:a04710facbb6	6239	#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /!<Time Segment 1 /
hudakz	0:a04710facbb6	6240	#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	6241	#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	6242	#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	6243	#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	6244	#define CAN_BTR_TS2_Pos (20U)
hudakz	0:a04710facbb6	6245	#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /!< 0x00700000 /
hudakz	0:a04710facbb6	6246	#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /!<Time Segment 2 /
hudakz	0:a04710facbb6	6247	#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	6248	#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	6249	#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	6250	#define CAN_BTR_SJW_Pos (24U)
hudakz	0:a04710facbb6	6251	#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /!< 0x03000000 /
hudakz	0:a04710facbb6	6252	#define CAN_BTR_SJW CAN_BTR_SJW_Msk /!<Resynchronization Jump Width /
hudakz	0:a04710facbb6	6253	#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	6254	#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	6255	#define CAN_BTR_LBKM_Pos (30U)
hudakz	0:a04710facbb6	6256	#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	6257	#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /!<Loop Back Mode (Debug) /
hudakz	0:a04710facbb6	6258	#define CAN_BTR_SILM_Pos (31U)
hudakz	0:a04710facbb6	6259	#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	6260	#define CAN_BTR_SILM CAN_BTR_SILM_Msk /!<Silent Mode /
hudakz	0:a04710facbb6	6261
hudakz	0:a04710facbb6	6262	/!< Mailbox registers /
hudakz	0:a04710facbb6	6263	/**************** Bit definition for CAN_TI0R register ******************/
hudakz	0:a04710facbb6	6264	#define CAN_TI0R_TXRQ_Pos (0U)
hudakz	0:a04710facbb6	6265	#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	6266	#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /!< Transmit Mailbox Request /
hudakz	0:a04710facbb6	6267	#define CAN_TI0R_RTR_Pos (1U)
hudakz	0:a04710facbb6	6268	#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	6269	#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /!< Remote Transmission Request /
hudakz	0:a04710facbb6	6270	#define CAN_TI0R_IDE_Pos (2U)
hudakz	0:a04710facbb6	6271	#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	6272	#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /!< Identifier Extension /
hudakz	0:a04710facbb6	6273	#define CAN_TI0R_EXID_Pos (3U)
hudakz	0:a04710facbb6	6274	#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /!< 0x001FFFF8 /
hudakz	0:a04710facbb6	6275	#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /!< Extended Identifier /
hudakz	0:a04710facbb6	6276	#define CAN_TI0R_STID_Pos (21U)
hudakz	0:a04710facbb6	6277	#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /!< 0xFFE00000 /
hudakz	0:a04710facbb6	6278	#define CAN_TI0R_STID CAN_TI0R_STID_Msk /!< Standard Identifier or Extended Identifier /
hudakz	0:a04710facbb6	6279
hudakz	0:a04710facbb6	6280	/**************** Bit definition for CAN_TDT0R register *****************/
hudakz	0:a04710facbb6	6281	#define CAN_TDT0R_DLC_Pos (0U)
hudakz	0:a04710facbb6	6282	#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	6283	#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /!< Data Length Code /
hudakz	0:a04710facbb6	6284	#define CAN_TDT0R_TGT_Pos (8U)
hudakz	0:a04710facbb6	6285	#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	6286	#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /!< Transmit Global Time /
hudakz	0:a04710facbb6	6287	#define CAN_TDT0R_TIME_Pos (16U)
hudakz	0:a04710facbb6	6288	#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /!< 0xFFFF0000 /
hudakz	0:a04710facbb6	6289	#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /!< Message Time Stamp /
hudakz	0:a04710facbb6	6290
hudakz	0:a04710facbb6	6291	/**************** Bit definition for CAN_TDL0R register *****************/
hudakz	0:a04710facbb6	6292	#define CAN_TDL0R_DATA0_Pos (0U)
hudakz	0:a04710facbb6	6293	#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /!< 0x000000FF /
hudakz	0:a04710facbb6	6294	#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /!< Data byte 0 /
hudakz	0:a04710facbb6	6295	#define CAN_TDL0R_DATA1_Pos (8U)
hudakz	0:a04710facbb6	6296	#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /!< 0x0000FF00 /
hudakz	0:a04710facbb6	6297	#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /!< Data byte 1 /
hudakz	0:a04710facbb6	6298	#define CAN_TDL0R_DATA2_Pos (16U)
hudakz	0:a04710facbb6	6299	#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /!< 0x00FF0000 /
hudakz	0:a04710facbb6	6300	#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /!< Data byte 2 /
hudakz	0:a04710facbb6	6301	#define CAN_TDL0R_DATA3_Pos (24U)
hudakz	0:a04710facbb6	6302	#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /!< 0xFF000000 /
hudakz	0:a04710facbb6	6303	#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /!< Data byte 3 /
hudakz	0:a04710facbb6	6304
hudakz	0:a04710facbb6	6305	/**************** Bit definition for CAN_TDH0R register *****************/
hudakz	0:a04710facbb6	6306	#define CAN_TDH0R_DATA4_Pos (0U)
hudakz	0:a04710facbb6	6307	#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /!< 0x000000FF /
hudakz	0:a04710facbb6	6308	#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /!< Data byte 4 /
hudakz	0:a04710facbb6	6309	#define CAN_TDH0R_DATA5_Pos (8U)
hudakz	0:a04710facbb6	6310	#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /!< 0x0000FF00 /
hudakz	0:a04710facbb6	6311	#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /!< Data byte 5 /
hudakz	0:a04710facbb6	6312	#define CAN_TDH0R_DATA6_Pos (16U)
hudakz	0:a04710facbb6	6313	#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /!< 0x00FF0000 /
hudakz	0:a04710facbb6	6314	#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /!< Data byte 6 /
hudakz	0:a04710facbb6	6315	#define CAN_TDH0R_DATA7_Pos (24U)
hudakz	0:a04710facbb6	6316	#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /!< 0xFF000000 /
hudakz	0:a04710facbb6	6317	#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /!< Data byte 7 /
hudakz	0:a04710facbb6	6318
hudakz	0:a04710facbb6	6319	/***************** Bit definition for CAN_TI1R register *****************/
hudakz	0:a04710facbb6	6320	#define CAN_TI1R_TXRQ_Pos (0U)
hudakz	0:a04710facbb6	6321	#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	6322	#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /!< Transmit Mailbox Request /
hudakz	0:a04710facbb6	6323	#define CAN_TI1R_RTR_Pos (1U)
hudakz	0:a04710facbb6	6324	#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	6325	#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /!< Remote Transmission Request /
hudakz	0:a04710facbb6	6326	#define CAN_TI1R_IDE_Pos (2U)
hudakz	0:a04710facbb6	6327	#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	6328	#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /!< Identifier Extension /
hudakz	0:a04710facbb6	6329	#define CAN_TI1R_EXID_Pos (3U)
hudakz	0:a04710facbb6	6330	#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /!< 0x001FFFF8 /
hudakz	0:a04710facbb6	6331	#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /!< Extended Identifier /
hudakz	0:a04710facbb6	6332	#define CAN_TI1R_STID_Pos (21U)
hudakz	0:a04710facbb6	6333	#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /!< 0xFFE00000 /
hudakz	0:a04710facbb6	6334	#define CAN_TI1R_STID CAN_TI1R_STID_Msk /!< Standard Identifier or Extended Identifier /
hudakz	0:a04710facbb6	6335
hudakz	0:a04710facbb6	6336	/***************** Bit definition for CAN_TDT1R register ****************/
hudakz	0:a04710facbb6	6337	#define CAN_TDT1R_DLC_Pos (0U)
hudakz	0:a04710facbb6	6338	#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	6339	#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /!< Data Length Code /
hudakz	0:a04710facbb6	6340	#define CAN_TDT1R_TGT_Pos (8U)
hudakz	0:a04710facbb6	6341	#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	6342	#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /!< Transmit Global Time /
hudakz	0:a04710facbb6	6343	#define CAN_TDT1R_TIME_Pos (16U)
hudakz	0:a04710facbb6	6344	#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /!< 0xFFFF0000 /
hudakz	0:a04710facbb6	6345	#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /!< Message Time Stamp /
hudakz	0:a04710facbb6	6346
hudakz	0:a04710facbb6	6347	/***************** Bit definition for CAN_TDL1R register ****************/
hudakz	0:a04710facbb6	6348	#define CAN_TDL1R_DATA0_Pos (0U)
hudakz	0:a04710facbb6	6349	#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /!< 0x000000FF /
hudakz	0:a04710facbb6	6350	#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /!< Data byte 0 /
hudakz	0:a04710facbb6	6351	#define CAN_TDL1R_DATA1_Pos (8U)
hudakz	0:a04710facbb6	6352	#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /!< 0x0000FF00 /
hudakz	0:a04710facbb6	6353	#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /!< Data byte 1 /
hudakz	0:a04710facbb6	6354	#define CAN_TDL1R_DATA2_Pos (16U)
hudakz	0:a04710facbb6	6355	#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /!< 0x00FF0000 /
hudakz	0:a04710facbb6	6356	#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /!< Data byte 2 /
hudakz	0:a04710facbb6	6357	#define CAN_TDL1R_DATA3_Pos (24U)
hudakz	0:a04710facbb6	6358	#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /!< 0xFF000000 /
hudakz	0:a04710facbb6	6359	#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /!< Data byte 3 /
hudakz	0:a04710facbb6	6360
hudakz	0:a04710facbb6	6361	/***************** Bit definition for CAN_TDH1R register ****************/
hudakz	0:a04710facbb6	6362	#define CAN_TDH1R_DATA4_Pos (0U)
hudakz	0:a04710facbb6	6363	#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /!< 0x000000FF /
hudakz	0:a04710facbb6	6364	#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /!< Data byte 4 /
hudakz	0:a04710facbb6	6365	#define CAN_TDH1R_DATA5_Pos (8U)
hudakz	0:a04710facbb6	6366	#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /!< 0x0000FF00 /
hudakz	0:a04710facbb6	6367	#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /!< Data byte 5 /
hudakz	0:a04710facbb6	6368	#define CAN_TDH1R_DATA6_Pos (16U)
hudakz	0:a04710facbb6	6369	#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /!< 0x00FF0000 /
hudakz	0:a04710facbb6	6370	#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /!< Data byte 6 /
hudakz	0:a04710facbb6	6371	#define CAN_TDH1R_DATA7_Pos (24U)
hudakz	0:a04710facbb6	6372	#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /!< 0xFF000000 /
hudakz	0:a04710facbb6	6373	#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /!< Data byte 7 /
hudakz	0:a04710facbb6	6374
hudakz	0:a04710facbb6	6375	/***************** Bit definition for CAN_TI2R register *****************/
hudakz	0:a04710facbb6	6376	#define CAN_TI2R_TXRQ_Pos (0U)
hudakz	0:a04710facbb6	6377	#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	6378	#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /!< Transmit Mailbox Request /
hudakz	0:a04710facbb6	6379	#define CAN_TI2R_RTR_Pos (1U)
hudakz	0:a04710facbb6	6380	#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	6381	#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /!< Remote Transmission Request /
hudakz	0:a04710facbb6	6382	#define CAN_TI2R_IDE_Pos (2U)
hudakz	0:a04710facbb6	6383	#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	6384	#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /!< Identifier Extension /
hudakz	0:a04710facbb6	6385	#define CAN_TI2R_EXID_Pos (3U)
hudakz	0:a04710facbb6	6386	#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /!< 0x001FFFF8 /
hudakz	0:a04710facbb6	6387	#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /!< Extended identifier /
hudakz	0:a04710facbb6	6388	#define CAN_TI2R_STID_Pos (21U)
hudakz	0:a04710facbb6	6389	#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /!< 0xFFE00000 /
hudakz	0:a04710facbb6	6390	#define CAN_TI2R_STID CAN_TI2R_STID_Msk /!< Standard Identifier or Extended Identifier /
hudakz	0:a04710facbb6	6391
hudakz	0:a04710facbb6	6392	/***************** Bit definition for CAN_TDT2R register ****************/
hudakz	0:a04710facbb6	6393	#define CAN_TDT2R_DLC_Pos (0U)
hudakz	0:a04710facbb6	6394	#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	6395	#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /!< Data Length Code /
hudakz	0:a04710facbb6	6396	#define CAN_TDT2R_TGT_Pos (8U)
hudakz	0:a04710facbb6	6397	#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	6398	#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /!< Transmit Global Time /
hudakz	0:a04710facbb6	6399	#define CAN_TDT2R_TIME_Pos (16U)
hudakz	0:a04710facbb6	6400	#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /!< 0xFFFF0000 /
hudakz	0:a04710facbb6	6401	#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /!< Message Time Stamp /
hudakz	0:a04710facbb6	6402
hudakz	0:a04710facbb6	6403	/***************** Bit definition for CAN_TDL2R register ****************/
hudakz	0:a04710facbb6	6404	#define CAN_TDL2R_DATA0_Pos (0U)
hudakz	0:a04710facbb6	6405	#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /!< 0x000000FF /
hudakz	0:a04710facbb6	6406	#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /!< Data byte 0 /
hudakz	0:a04710facbb6	6407	#define CAN_TDL2R_DATA1_Pos (8U)
hudakz	0:a04710facbb6	6408	#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /!< 0x0000FF00 /
hudakz	0:a04710facbb6	6409	#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /!< Data byte 1 /
hudakz	0:a04710facbb6	6410	#define CAN_TDL2R_DATA2_Pos (16U)
hudakz	0:a04710facbb6	6411	#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /!< 0x00FF0000 /
hudakz	0:a04710facbb6	6412	#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /!< Data byte 2 /
hudakz	0:a04710facbb6	6413	#define CAN_TDL2R_DATA3_Pos (24U)
hudakz	0:a04710facbb6	6414	#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /!< 0xFF000000 /
hudakz	0:a04710facbb6	6415	#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /!< Data byte 3 /
hudakz	0:a04710facbb6	6416
hudakz	0:a04710facbb6	6417	/***************** Bit definition for CAN_TDH2R register ****************/
hudakz	0:a04710facbb6	6418	#define CAN_TDH2R_DATA4_Pos (0U)
hudakz	0:a04710facbb6	6419	#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /!< 0x000000FF /
hudakz	0:a04710facbb6	6420	#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /!< Data byte 4 /
hudakz	0:a04710facbb6	6421	#define CAN_TDH2R_DATA5_Pos (8U)
hudakz	0:a04710facbb6	6422	#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /!< 0x0000FF00 /
hudakz	0:a04710facbb6	6423	#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /!< Data byte 5 /
hudakz	0:a04710facbb6	6424	#define CAN_TDH2R_DATA6_Pos (16U)
hudakz	0:a04710facbb6	6425	#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /!< 0x00FF0000 /
hudakz	0:a04710facbb6	6426	#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /!< Data byte 6 /
hudakz	0:a04710facbb6	6427	#define CAN_TDH2R_DATA7_Pos (24U)
hudakz	0:a04710facbb6	6428	#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /!< 0xFF000000 /
hudakz	0:a04710facbb6	6429	#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /!< Data byte 7 /
hudakz	0:a04710facbb6	6430
hudakz	0:a04710facbb6	6431	/***************** Bit definition for CAN_RI0R register *****************/
hudakz	0:a04710facbb6	6432	#define CAN_RI0R_RTR_Pos (1U)
hudakz	0:a04710facbb6	6433	#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	6434	#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /!< Remote Transmission Request /
hudakz	0:a04710facbb6	6435	#define CAN_RI0R_IDE_Pos (2U)
hudakz	0:a04710facbb6	6436	#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	6437	#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /!< Identifier Extension /
hudakz	0:a04710facbb6	6438	#define CAN_RI0R_EXID_Pos (3U)
hudakz	0:a04710facbb6	6439	#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /!< 0x001FFFF8 /
hudakz	0:a04710facbb6	6440	#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /!< Extended Identifier /
hudakz	0:a04710facbb6	6441	#define CAN_RI0R_STID_Pos (21U)
hudakz	0:a04710facbb6	6442	#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /!< 0xFFE00000 /
hudakz	0:a04710facbb6	6443	#define CAN_RI0R_STID CAN_RI0R_STID_Msk /!< Standard Identifier or Extended Identifier /
hudakz	0:a04710facbb6	6444
hudakz	0:a04710facbb6	6445	/***************** Bit definition for CAN_RDT0R register ****************/
hudakz	0:a04710facbb6	6446	#define CAN_RDT0R_DLC_Pos (0U)
hudakz	0:a04710facbb6	6447	#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	6448	#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /!< Data Length Code /
hudakz	0:a04710facbb6	6449	#define CAN_RDT0R_FMI_Pos (8U)
hudakz	0:a04710facbb6	6450	#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /!< 0x0000FF00 /
hudakz	0:a04710facbb6	6451	#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /!< Filter Match Index /
hudakz	0:a04710facbb6	6452	#define CAN_RDT0R_TIME_Pos (16U)
hudakz	0:a04710facbb6	6453	#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /!< 0xFFFF0000 /
hudakz	0:a04710facbb6	6454	#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /!< Message Time Stamp /
hudakz	0:a04710facbb6	6455
hudakz	0:a04710facbb6	6456	/***************** Bit definition for CAN_RDL0R register ****************/
hudakz	0:a04710facbb6	6457	#define CAN_RDL0R_DATA0_Pos (0U)
hudakz	0:a04710facbb6	6458	#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /!< 0x000000FF /
hudakz	0:a04710facbb6	6459	#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /!< Data byte 0 /
hudakz	0:a04710facbb6	6460	#define CAN_RDL0R_DATA1_Pos (8U)
hudakz	0:a04710facbb6	6461	#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /!< 0x0000FF00 /
hudakz	0:a04710facbb6	6462	#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /!< Data byte 1 /
hudakz	0:a04710facbb6	6463	#define CAN_RDL0R_DATA2_Pos (16U)
hudakz	0:a04710facbb6	6464	#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /!< 0x00FF0000 /
hudakz	0:a04710facbb6	6465	#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /!< Data byte 2 /
hudakz	0:a04710facbb6	6466	#define CAN_RDL0R_DATA3_Pos (24U)
hudakz	0:a04710facbb6	6467	#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /!< 0xFF000000 /
hudakz	0:a04710facbb6	6468	#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /!< Data byte 3 /
hudakz	0:a04710facbb6	6469
hudakz	0:a04710facbb6	6470	/***************** Bit definition for CAN_RDH0R register ****************/
hudakz	0:a04710facbb6	6471	#define CAN_RDH0R_DATA4_Pos (0U)
hudakz	0:a04710facbb6	6472	#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /!< 0x000000FF /
hudakz	0:a04710facbb6	6473	#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /!< Data byte 4 /
hudakz	0:a04710facbb6	6474	#define CAN_RDH0R_DATA5_Pos (8U)
hudakz	0:a04710facbb6	6475	#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /!< 0x0000FF00 /
hudakz	0:a04710facbb6	6476	#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /!< Data byte 5 /
hudakz	0:a04710facbb6	6477	#define CAN_RDH0R_DATA6_Pos (16U)
hudakz	0:a04710facbb6	6478	#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /!< 0x00FF0000 /
hudakz	0:a04710facbb6	6479	#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /!< Data byte 6 /
hudakz	0:a04710facbb6	6480	#define CAN_RDH0R_DATA7_Pos (24U)
hudakz	0:a04710facbb6	6481	#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /!< 0xFF000000 /
hudakz	0:a04710facbb6	6482	#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /!< Data byte 7 /
hudakz	0:a04710facbb6	6483
hudakz	0:a04710facbb6	6484	/***************** Bit definition for CAN_RI1R register *****************/
hudakz	0:a04710facbb6	6485	#define CAN_RI1R_RTR_Pos (1U)
hudakz	0:a04710facbb6	6486	#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	6487	#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /!< Remote Transmission Request /
hudakz	0:a04710facbb6	6488	#define CAN_RI1R_IDE_Pos (2U)
hudakz	0:a04710facbb6	6489	#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	6490	#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /!< Identifier Extension /
hudakz	0:a04710facbb6	6491	#define CAN_RI1R_EXID_Pos (3U)
hudakz	0:a04710facbb6	6492	#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /!< 0x001FFFF8 /
hudakz	0:a04710facbb6	6493	#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /!< Extended identifier /
hudakz	0:a04710facbb6	6494	#define CAN_RI1R_STID_Pos (21U)
hudakz	0:a04710facbb6	6495	#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /!< 0xFFE00000 /
hudakz	0:a04710facbb6	6496	#define CAN_RI1R_STID CAN_RI1R_STID_Msk /!< Standard Identifier or Extended Identifier /
hudakz	0:a04710facbb6	6497
hudakz	0:a04710facbb6	6498	/***************** Bit definition for CAN_RDT1R register ****************/
hudakz	0:a04710facbb6	6499	#define CAN_RDT1R_DLC_Pos (0U)
hudakz	0:a04710facbb6	6500	#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	6501	#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /!< Data Length Code /
hudakz	0:a04710facbb6	6502	#define CAN_RDT1R_FMI_Pos (8U)
hudakz	0:a04710facbb6	6503	#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /!< 0x0000FF00 /
hudakz	0:a04710facbb6	6504	#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /!< Filter Match Index /
hudakz	0:a04710facbb6	6505	#define CAN_RDT1R_TIME_Pos (16U)
hudakz	0:a04710facbb6	6506	#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /!< 0xFFFF0000 /
hudakz	0:a04710facbb6	6507	#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /!< Message Time Stamp /
hudakz	0:a04710facbb6	6508
hudakz	0:a04710facbb6	6509	/***************** Bit definition for CAN_RDL1R register ****************/
hudakz	0:a04710facbb6	6510	#define CAN_RDL1R_DATA0_Pos (0U)
hudakz	0:a04710facbb6	6511	#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /!< 0x000000FF /
hudakz	0:a04710facbb6	6512	#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /!< Data byte 0 /
hudakz	0:a04710facbb6	6513	#define CAN_RDL1R_DATA1_Pos (8U)
hudakz	0:a04710facbb6	6514	#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /!< 0x0000FF00 /
hudakz	0:a04710facbb6	6515	#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /!< Data byte 1 /
hudakz	0:a04710facbb6	6516	#define CAN_RDL1R_DATA2_Pos (16U)
hudakz	0:a04710facbb6	6517	#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /!< 0x00FF0000 /
hudakz	0:a04710facbb6	6518	#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /!< Data byte 2 /
hudakz	0:a04710facbb6	6519	#define CAN_RDL1R_DATA3_Pos (24U)
hudakz	0:a04710facbb6	6520	#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /!< 0xFF000000 /
hudakz	0:a04710facbb6	6521	#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /!< Data byte 3 /
hudakz	0:a04710facbb6	6522
hudakz	0:a04710facbb6	6523	/***************** Bit definition for CAN_RDH1R register ****************/
hudakz	0:a04710facbb6	6524	#define CAN_RDH1R_DATA4_Pos (0U)
hudakz	0:a04710facbb6	6525	#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /!< 0x000000FF /
hudakz	0:a04710facbb6	6526	#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /!< Data byte 4 /
hudakz	0:a04710facbb6	6527	#define CAN_RDH1R_DATA5_Pos (8U)
hudakz	0:a04710facbb6	6528	#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /!< 0x0000FF00 /
hudakz	0:a04710facbb6	6529	#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /!< Data byte 5 /
hudakz	0:a04710facbb6	6530	#define CAN_RDH1R_DATA6_Pos (16U)
hudakz	0:a04710facbb6	6531	#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /!< 0x00FF0000 /
hudakz	0:a04710facbb6	6532	#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /!< Data byte 6 /
hudakz	0:a04710facbb6	6533	#define CAN_RDH1R_DATA7_Pos (24U)
hudakz	0:a04710facbb6	6534	#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /!< 0xFF000000 /
hudakz	0:a04710facbb6	6535	#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /!< Data byte 7 /
hudakz	0:a04710facbb6	6536
hudakz	0:a04710facbb6	6537	/!< CAN filter registers /
hudakz	0:a04710facbb6	6538	/***************** Bit definition for CAN_FMR register ******************/
hudakz	0:a04710facbb6	6539	#define CAN_FMR_FINIT_Pos (0U)
hudakz	0:a04710facbb6	6540	#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	6541	#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /!< Filter Init Mode /
hudakz	0:a04710facbb6	6542	#define CAN_FMR_CAN2SB_Pos (8U)
hudakz	0:a04710facbb6	6543	#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /!< 0x00003F00 /
hudakz	0:a04710facbb6	6544	#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /!< CAN2 start bank /
hudakz	0:a04710facbb6	6545
hudakz	0:a04710facbb6	6546	/***************** Bit definition for CAN_FM1R register *****************/
hudakz	0:a04710facbb6	6547	#define CAN_FM1R_FBM_Pos (0U)
hudakz	0:a04710facbb6	6548	#define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /!< 0x00003FFF /
hudakz	0:a04710facbb6	6549	#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /!< Filter Mode /
hudakz	0:a04710facbb6	6550	#define CAN_FM1R_FBM0_Pos (0U)
hudakz	0:a04710facbb6	6551	#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	6552	#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /!< Filter Init Mode for filter 0 /
hudakz	0:a04710facbb6	6553	#define CAN_FM1R_FBM1_Pos (1U)
hudakz	0:a04710facbb6	6554	#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	6555	#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /!< Filter Init Mode for filter 1 /
hudakz	0:a04710facbb6	6556	#define CAN_FM1R_FBM2_Pos (2U)
hudakz	0:a04710facbb6	6557	#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	6558	#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /!< Filter Init Mode for filter 2 /
hudakz	0:a04710facbb6	6559	#define CAN_FM1R_FBM3_Pos (3U)
hudakz	0:a04710facbb6	6560	#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	6561	#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /!< Filter Init Mode for filter 3 /
hudakz	0:a04710facbb6	6562	#define CAN_FM1R_FBM4_Pos (4U)
hudakz	0:a04710facbb6	6563	#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	6564	#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /!< Filter Init Mode for filter 4 /
hudakz	0:a04710facbb6	6565	#define CAN_FM1R_FBM5_Pos (5U)
hudakz	0:a04710facbb6	6566	#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	6567	#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /!< Filter Init Mode for filter 5 /
hudakz	0:a04710facbb6	6568	#define CAN_FM1R_FBM6_Pos (6U)
hudakz	0:a04710facbb6	6569	#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	6570	#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /!< Filter Init Mode for filter 6 /
hudakz	0:a04710facbb6	6571	#define CAN_FM1R_FBM7_Pos (7U)
hudakz	0:a04710facbb6	6572	#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	6573	#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /!< Filter Init Mode for filter 7 /
hudakz	0:a04710facbb6	6574	#define CAN_FM1R_FBM8_Pos (8U)
hudakz	0:a04710facbb6	6575	#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	6576	#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /!< Filter Init Mode for filter 8 /
hudakz	0:a04710facbb6	6577	#define CAN_FM1R_FBM9_Pos (9U)
hudakz	0:a04710facbb6	6578	#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	6579	#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /!< Filter Init Mode for filter 9 /
hudakz	0:a04710facbb6	6580	#define CAN_FM1R_FBM10_Pos (10U)
hudakz	0:a04710facbb6	6581	#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	6582	#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /!< Filter Init Mode for filter 10 /
hudakz	0:a04710facbb6	6583	#define CAN_FM1R_FBM11_Pos (11U)
hudakz	0:a04710facbb6	6584	#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	6585	#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /!< Filter Init Mode for filter 11 /
hudakz	0:a04710facbb6	6586	#define CAN_FM1R_FBM12_Pos (12U)
hudakz	0:a04710facbb6	6587	#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	6588	#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /!< Filter Init Mode for filter 12 /
hudakz	0:a04710facbb6	6589	#define CAN_FM1R_FBM13_Pos (13U)
hudakz	0:a04710facbb6	6590	#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	6591	#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /!< Filter Init Mode for filter 13 /
hudakz	0:a04710facbb6	6592
hudakz	0:a04710facbb6	6593	/***************** Bit definition for CAN_FS1R register *****************/
hudakz	0:a04710facbb6	6594	#define CAN_FS1R_FSC_Pos (0U)
hudakz	0:a04710facbb6	6595	#define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /!< 0x00003FFF /
hudakz	0:a04710facbb6	6596	#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /!< Filter Scale Configuration /
hudakz	0:a04710facbb6	6597	#define CAN_FS1R_FSC0_Pos (0U)
hudakz	0:a04710facbb6	6598	#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	6599	#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /!< Filter Scale Configuration for filter 0 /
hudakz	0:a04710facbb6	6600	#define CAN_FS1R_FSC1_Pos (1U)
hudakz	0:a04710facbb6	6601	#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	6602	#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /!< Filter Scale Configuration for filter 1 /
hudakz	0:a04710facbb6	6603	#define CAN_FS1R_FSC2_Pos (2U)
hudakz	0:a04710facbb6	6604	#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	6605	#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /!< Filter Scale Configuration for filter 2 /
hudakz	0:a04710facbb6	6606	#define CAN_FS1R_FSC3_Pos (3U)
hudakz	0:a04710facbb6	6607	#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	6608	#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /!< Filter Scale Configuration for filter 3 /
hudakz	0:a04710facbb6	6609	#define CAN_FS1R_FSC4_Pos (4U)
hudakz	0:a04710facbb6	6610	#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	6611	#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /!< Filter Scale Configuration for filter 4 /
hudakz	0:a04710facbb6	6612	#define CAN_FS1R_FSC5_Pos (5U)
hudakz	0:a04710facbb6	6613	#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	6614	#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /!< Filter Scale Configuration for filter 5 /
hudakz	0:a04710facbb6	6615	#define CAN_FS1R_FSC6_Pos (6U)
hudakz	0:a04710facbb6	6616	#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	6617	#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /!< Filter Scale Configuration for filter 6 /
hudakz	0:a04710facbb6	6618	#define CAN_FS1R_FSC7_Pos (7U)
hudakz	0:a04710facbb6	6619	#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	6620	#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /!< Filter Scale Configuration for filter 7 /
hudakz	0:a04710facbb6	6621	#define CAN_FS1R_FSC8_Pos (8U)
hudakz	0:a04710facbb6	6622	#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	6623	#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /!< Filter Scale Configuration for filter 8 /
hudakz	0:a04710facbb6	6624	#define CAN_FS1R_FSC9_Pos (9U)
hudakz	0:a04710facbb6	6625	#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	6626	#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /!< Filter Scale Configuration for filter 9 /
hudakz	0:a04710facbb6	6627	#define CAN_FS1R_FSC10_Pos (10U)
hudakz	0:a04710facbb6	6628	#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	6629	#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /!< Filter Scale Configuration for filter 10 /
hudakz	0:a04710facbb6	6630	#define CAN_FS1R_FSC11_Pos (11U)
hudakz	0:a04710facbb6	6631	#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	6632	#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /!< Filter Scale Configuration for filter 11 /
hudakz	0:a04710facbb6	6633	#define CAN_FS1R_FSC12_Pos (12U)
hudakz	0:a04710facbb6	6634	#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	6635	#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /!< Filter Scale Configuration for filter 12 /
hudakz	0:a04710facbb6	6636	#define CAN_FS1R_FSC13_Pos (13U)
hudakz	0:a04710facbb6	6637	#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	6638	#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /!< Filter Scale Configuration for filter 13 /
hudakz	0:a04710facbb6	6639
hudakz	0:a04710facbb6	6640	/**************** Bit definition for CAN_FFA1R register *****************/
hudakz	0:a04710facbb6	6641	#define CAN_FFA1R_FFA_Pos (0U)
hudakz	0:a04710facbb6	6642	#define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /!< 0x00003FFF /
hudakz	0:a04710facbb6	6643	#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /!< Filter FIFO Assignment /
hudakz	0:a04710facbb6	6644	#define CAN_FFA1R_FFA0_Pos (0U)
hudakz	0:a04710facbb6	6645	#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	6646	#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /!< Filter FIFO Assignment for filter 0 /
hudakz	0:a04710facbb6	6647	#define CAN_FFA1R_FFA1_Pos (1U)
hudakz	0:a04710facbb6	6648	#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	6649	#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /!< Filter FIFO Assignment for filter 1 /
hudakz	0:a04710facbb6	6650	#define CAN_FFA1R_FFA2_Pos (2U)
hudakz	0:a04710facbb6	6651	#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	6652	#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /!< Filter FIFO Assignment for filter 2 /
hudakz	0:a04710facbb6	6653	#define CAN_FFA1R_FFA3_Pos (3U)
hudakz	0:a04710facbb6	6654	#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	6655	#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /!< Filter FIFO Assignment for filter 3 /
hudakz	0:a04710facbb6	6656	#define CAN_FFA1R_FFA4_Pos (4U)
hudakz	0:a04710facbb6	6657	#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	6658	#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /!< Filter FIFO Assignment for filter 4 /
hudakz	0:a04710facbb6	6659	#define CAN_FFA1R_FFA5_Pos (5U)
hudakz	0:a04710facbb6	6660	#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	6661	#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /!< Filter FIFO Assignment for filter 5 /
hudakz	0:a04710facbb6	6662	#define CAN_FFA1R_FFA6_Pos (6U)
hudakz	0:a04710facbb6	6663	#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	6664	#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /!< Filter FIFO Assignment for filter 6 /
hudakz	0:a04710facbb6	6665	#define CAN_FFA1R_FFA7_Pos (7U)
hudakz	0:a04710facbb6	6666	#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	6667	#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /!< Filter FIFO Assignment for filter 7 /
hudakz	0:a04710facbb6	6668	#define CAN_FFA1R_FFA8_Pos (8U)
hudakz	0:a04710facbb6	6669	#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	6670	#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /!< Filter FIFO Assignment for filter 8 /
hudakz	0:a04710facbb6	6671	#define CAN_FFA1R_FFA9_Pos (9U)
hudakz	0:a04710facbb6	6672	#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	6673	#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /!< Filter FIFO Assignment for filter 9 /
hudakz	0:a04710facbb6	6674	#define CAN_FFA1R_FFA10_Pos (10U)
hudakz	0:a04710facbb6	6675	#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	6676	#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /!< Filter FIFO Assignment for filter 10 /
hudakz	0:a04710facbb6	6677	#define CAN_FFA1R_FFA11_Pos (11U)
hudakz	0:a04710facbb6	6678	#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	6679	#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /!< Filter FIFO Assignment for filter 11 /
hudakz	0:a04710facbb6	6680	#define CAN_FFA1R_FFA12_Pos (12U)
hudakz	0:a04710facbb6	6681	#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	6682	#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /!< Filter FIFO Assignment for filter 12 /
hudakz	0:a04710facbb6	6683	#define CAN_FFA1R_FFA13_Pos (13U)
hudakz	0:a04710facbb6	6684	#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	6685	#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /!< Filter FIFO Assignment for filter 13 /
hudakz	0:a04710facbb6	6686
hudakz	0:a04710facbb6	6687	/***************** Bit definition for CAN_FA1R register *****************/
hudakz	0:a04710facbb6	6688	#define CAN_FA1R_FACT_Pos (0U)
hudakz	0:a04710facbb6	6689	#define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /!< 0x00003FFF /
hudakz	0:a04710facbb6	6690	#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /!< Filter Active /
hudakz	0:a04710facbb6	6691	#define CAN_FA1R_FACT0_Pos (0U)
hudakz	0:a04710facbb6	6692	#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	6693	#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /!< Filter 0 Active /
hudakz	0:a04710facbb6	6694	#define CAN_FA1R_FACT1_Pos (1U)
hudakz	0:a04710facbb6	6695	#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	6696	#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /!< Filter 1 Active /
hudakz	0:a04710facbb6	6697	#define CAN_FA1R_FACT2_Pos (2U)
hudakz	0:a04710facbb6	6698	#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	6699	#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /!< Filter 2 Active /
hudakz	0:a04710facbb6	6700	#define CAN_FA1R_FACT3_Pos (3U)
hudakz	0:a04710facbb6	6701	#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	6702	#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /!< Filter 3 Active /
hudakz	0:a04710facbb6	6703	#define CAN_FA1R_FACT4_Pos (4U)
hudakz	0:a04710facbb6	6704	#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	6705	#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /!< Filter 4 Active /
hudakz	0:a04710facbb6	6706	#define CAN_FA1R_FACT5_Pos (5U)
hudakz	0:a04710facbb6	6707	#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	6708	#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /!< Filter 5 Active /
hudakz	0:a04710facbb6	6709	#define CAN_FA1R_FACT6_Pos (6U)
hudakz	0:a04710facbb6	6710	#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	6711	#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /!< Filter 6 Active /
hudakz	0:a04710facbb6	6712	#define CAN_FA1R_FACT7_Pos (7U)
hudakz	0:a04710facbb6	6713	#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	6714	#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /!< Filter 7 Active /
hudakz	0:a04710facbb6	6715	#define CAN_FA1R_FACT8_Pos (8U)
hudakz	0:a04710facbb6	6716	#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	6717	#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /!< Filter 8 Active /
hudakz	0:a04710facbb6	6718	#define CAN_FA1R_FACT9_Pos (9U)
hudakz	0:a04710facbb6	6719	#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	6720	#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /!< Filter 9 Active /
hudakz	0:a04710facbb6	6721	#define CAN_FA1R_FACT10_Pos (10U)
hudakz	0:a04710facbb6	6722	#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	6723	#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /!< Filter 10 Active /
hudakz	0:a04710facbb6	6724	#define CAN_FA1R_FACT11_Pos (11U)
hudakz	0:a04710facbb6	6725	#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	6726	#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /!< Filter 11 Active /
hudakz	0:a04710facbb6	6727	#define CAN_FA1R_FACT12_Pos (12U)
hudakz	0:a04710facbb6	6728	#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	6729	#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /!< Filter 12 Active /
hudakz	0:a04710facbb6	6730	#define CAN_FA1R_FACT13_Pos (13U)
hudakz	0:a04710facbb6	6731	#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	6732	#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /!< Filter 13 Active /
hudakz	0:a04710facbb6	6733
hudakz	0:a04710facbb6	6734	/***************** Bit definition for CAN_F0R1 register *****************/
hudakz	0:a04710facbb6	6735	#define CAN_F0R1_FB0_Pos (0U)
hudakz	0:a04710facbb6	6736	#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	6737	#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	6738	#define CAN_F0R1_FB1_Pos (1U)
hudakz	0:a04710facbb6	6739	#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	6740	#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	6741	#define CAN_F0R1_FB2_Pos (2U)
hudakz	0:a04710facbb6	6742	#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	6743	#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	6744	#define CAN_F0R1_FB3_Pos (3U)
hudakz	0:a04710facbb6	6745	#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	6746	#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	6747	#define CAN_F0R1_FB4_Pos (4U)
hudakz	0:a04710facbb6	6748	#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	6749	#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	6750	#define CAN_F0R1_FB5_Pos (5U)
hudakz	0:a04710facbb6	6751	#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	6752	#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	6753	#define CAN_F0R1_FB6_Pos (6U)
hudakz	0:a04710facbb6	6754	#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	6755	#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	6756	#define CAN_F0R1_FB7_Pos (7U)
hudakz	0:a04710facbb6	6757	#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	6758	#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	6759	#define CAN_F0R1_FB8_Pos (8U)
hudakz	0:a04710facbb6	6760	#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	6761	#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	6762	#define CAN_F0R1_FB9_Pos (9U)
hudakz	0:a04710facbb6	6763	#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	6764	#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	6765	#define CAN_F0R1_FB10_Pos (10U)
hudakz	0:a04710facbb6	6766	#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	6767	#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	6768	#define CAN_F0R1_FB11_Pos (11U)
hudakz	0:a04710facbb6	6769	#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	6770	#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	6771	#define CAN_F0R1_FB12_Pos (12U)
hudakz	0:a04710facbb6	6772	#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	6773	#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	6774	#define CAN_F0R1_FB13_Pos (13U)
hudakz	0:a04710facbb6	6775	#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	6776	#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	6777	#define CAN_F0R1_FB14_Pos (14U)
hudakz	0:a04710facbb6	6778	#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	6779	#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	6780	#define CAN_F0R1_FB15_Pos (15U)
hudakz	0:a04710facbb6	6781	#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	6782	#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	6783	#define CAN_F0R1_FB16_Pos (16U)
hudakz	0:a04710facbb6	6784	#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	6785	#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	6786	#define CAN_F0R1_FB17_Pos (17U)
hudakz	0:a04710facbb6	6787	#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	6788	#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	6789	#define CAN_F0R1_FB18_Pos (18U)
hudakz	0:a04710facbb6	6790	#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	6791	#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	6792	#define CAN_F0R1_FB19_Pos (19U)
hudakz	0:a04710facbb6	6793	#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	6794	#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	6795	#define CAN_F0R1_FB20_Pos (20U)
hudakz	0:a04710facbb6	6796	#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	6797	#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	6798	#define CAN_F0R1_FB21_Pos (21U)
hudakz	0:a04710facbb6	6799	#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	6800	#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	6801	#define CAN_F0R1_FB22_Pos (22U)
hudakz	0:a04710facbb6	6802	#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	6803	#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	6804	#define CAN_F0R1_FB23_Pos (23U)
hudakz	0:a04710facbb6	6805	#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	6806	#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	6807	#define CAN_F0R1_FB24_Pos (24U)
hudakz	0:a04710facbb6	6808	#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	6809	#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	6810	#define CAN_F0R1_FB25_Pos (25U)
hudakz	0:a04710facbb6	6811	#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	6812	#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	6813	#define CAN_F0R1_FB26_Pos (26U)
hudakz	0:a04710facbb6	6814	#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	6815	#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	6816	#define CAN_F0R1_FB27_Pos (27U)
hudakz	0:a04710facbb6	6817	#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	6818	#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	6819	#define CAN_F0R1_FB28_Pos (28U)
hudakz	0:a04710facbb6	6820	#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	6821	#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	6822	#define CAN_F0R1_FB29_Pos (29U)
hudakz	0:a04710facbb6	6823	#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	6824	#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	6825	#define CAN_F0R1_FB30_Pos (30U)
hudakz	0:a04710facbb6	6826	#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	6827	#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	6828	#define CAN_F0R1_FB31_Pos (31U)
hudakz	0:a04710facbb6	6829	#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	6830	#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	6831
hudakz	0:a04710facbb6	6832	/***************** Bit definition for CAN_F1R1 register *****************/
hudakz	0:a04710facbb6	6833	#define CAN_F1R1_FB0_Pos (0U)
hudakz	0:a04710facbb6	6834	#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	6835	#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	6836	#define CAN_F1R1_FB1_Pos (1U)
hudakz	0:a04710facbb6	6837	#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	6838	#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	6839	#define CAN_F1R1_FB2_Pos (2U)
hudakz	0:a04710facbb6	6840	#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	6841	#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	6842	#define CAN_F1R1_FB3_Pos (3U)
hudakz	0:a04710facbb6	6843	#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	6844	#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	6845	#define CAN_F1R1_FB4_Pos (4U)
hudakz	0:a04710facbb6	6846	#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	6847	#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	6848	#define CAN_F1R1_FB5_Pos (5U)
hudakz	0:a04710facbb6	6849	#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	6850	#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	6851	#define CAN_F1R1_FB6_Pos (6U)
hudakz	0:a04710facbb6	6852	#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	6853	#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	6854	#define CAN_F1R1_FB7_Pos (7U)
hudakz	0:a04710facbb6	6855	#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	6856	#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	6857	#define CAN_F1R1_FB8_Pos (8U)
hudakz	0:a04710facbb6	6858	#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	6859	#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	6860	#define CAN_F1R1_FB9_Pos (9U)
hudakz	0:a04710facbb6	6861	#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	6862	#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	6863	#define CAN_F1R1_FB10_Pos (10U)
hudakz	0:a04710facbb6	6864	#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	6865	#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	6866	#define CAN_F1R1_FB11_Pos (11U)
hudakz	0:a04710facbb6	6867	#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	6868	#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	6869	#define CAN_F1R1_FB12_Pos (12U)
hudakz	0:a04710facbb6	6870	#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	6871	#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	6872	#define CAN_F1R1_FB13_Pos (13U)
hudakz	0:a04710facbb6	6873	#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	6874	#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	6875	#define CAN_F1R1_FB14_Pos (14U)
hudakz	0:a04710facbb6	6876	#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	6877	#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	6878	#define CAN_F1R1_FB15_Pos (15U)
hudakz	0:a04710facbb6	6879	#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	6880	#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	6881	#define CAN_F1R1_FB16_Pos (16U)
hudakz	0:a04710facbb6	6882	#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	6883	#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	6884	#define CAN_F1R1_FB17_Pos (17U)
hudakz	0:a04710facbb6	6885	#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	6886	#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	6887	#define CAN_F1R1_FB18_Pos (18U)
hudakz	0:a04710facbb6	6888	#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	6889	#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	6890	#define CAN_F1R1_FB19_Pos (19U)
hudakz	0:a04710facbb6	6891	#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	6892	#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	6893	#define CAN_F1R1_FB20_Pos (20U)
hudakz	0:a04710facbb6	6894	#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	6895	#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	6896	#define CAN_F1R1_FB21_Pos (21U)
hudakz	0:a04710facbb6	6897	#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	6898	#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	6899	#define CAN_F1R1_FB22_Pos (22U)
hudakz	0:a04710facbb6	6900	#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	6901	#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	6902	#define CAN_F1R1_FB23_Pos (23U)
hudakz	0:a04710facbb6	6903	#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	6904	#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	6905	#define CAN_F1R1_FB24_Pos (24U)
hudakz	0:a04710facbb6	6906	#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	6907	#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	6908	#define CAN_F1R1_FB25_Pos (25U)
hudakz	0:a04710facbb6	6909	#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	6910	#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	6911	#define CAN_F1R1_FB26_Pos (26U)
hudakz	0:a04710facbb6	6912	#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	6913	#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	6914	#define CAN_F1R1_FB27_Pos (27U)
hudakz	0:a04710facbb6	6915	#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	6916	#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	6917	#define CAN_F1R1_FB28_Pos (28U)
hudakz	0:a04710facbb6	6918	#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	6919	#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	6920	#define CAN_F1R1_FB29_Pos (29U)
hudakz	0:a04710facbb6	6921	#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	6922	#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	6923	#define CAN_F1R1_FB30_Pos (30U)
hudakz	0:a04710facbb6	6924	#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	6925	#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	6926	#define CAN_F1R1_FB31_Pos (31U)
hudakz	0:a04710facbb6	6927	#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	6928	#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	6929
hudakz	0:a04710facbb6	6930	/***************** Bit definition for CAN_F2R1 register *****************/
hudakz	0:a04710facbb6	6931	#define CAN_F2R1_FB0_Pos (0U)
hudakz	0:a04710facbb6	6932	#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	6933	#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	6934	#define CAN_F2R1_FB1_Pos (1U)
hudakz	0:a04710facbb6	6935	#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	6936	#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	6937	#define CAN_F2R1_FB2_Pos (2U)
hudakz	0:a04710facbb6	6938	#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	6939	#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	6940	#define CAN_F2R1_FB3_Pos (3U)
hudakz	0:a04710facbb6	6941	#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	6942	#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	6943	#define CAN_F2R1_FB4_Pos (4U)
hudakz	0:a04710facbb6	6944	#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	6945	#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	6946	#define CAN_F2R1_FB5_Pos (5U)
hudakz	0:a04710facbb6	6947	#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	6948	#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	6949	#define CAN_F2R1_FB6_Pos (6U)
hudakz	0:a04710facbb6	6950	#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	6951	#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	6952	#define CAN_F2R1_FB7_Pos (7U)
hudakz	0:a04710facbb6	6953	#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	6954	#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	6955	#define CAN_F2R1_FB8_Pos (8U)
hudakz	0:a04710facbb6	6956	#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	6957	#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	6958	#define CAN_F2R1_FB9_Pos (9U)
hudakz	0:a04710facbb6	6959	#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	6960	#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	6961	#define CAN_F2R1_FB10_Pos (10U)
hudakz	0:a04710facbb6	6962	#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	6963	#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	6964	#define CAN_F2R1_FB11_Pos (11U)
hudakz	0:a04710facbb6	6965	#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	6966	#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	6967	#define CAN_F2R1_FB12_Pos (12U)
hudakz	0:a04710facbb6	6968	#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	6969	#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	6970	#define CAN_F2R1_FB13_Pos (13U)
hudakz	0:a04710facbb6	6971	#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	6972	#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	6973	#define CAN_F2R1_FB14_Pos (14U)
hudakz	0:a04710facbb6	6974	#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	6975	#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	6976	#define CAN_F2R1_FB15_Pos (15U)
hudakz	0:a04710facbb6	6977	#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	6978	#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	6979	#define CAN_F2R1_FB16_Pos (16U)
hudakz	0:a04710facbb6	6980	#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	6981	#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	6982	#define CAN_F2R1_FB17_Pos (17U)
hudakz	0:a04710facbb6	6983	#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	6984	#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	6985	#define CAN_F2R1_FB18_Pos (18U)
hudakz	0:a04710facbb6	6986	#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	6987	#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	6988	#define CAN_F2R1_FB19_Pos (19U)
hudakz	0:a04710facbb6	6989	#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	6990	#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	6991	#define CAN_F2R1_FB20_Pos (20U)
hudakz	0:a04710facbb6	6992	#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	6993	#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	6994	#define CAN_F2R1_FB21_Pos (21U)
hudakz	0:a04710facbb6	6995	#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	6996	#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	6997	#define CAN_F2R1_FB22_Pos (22U)
hudakz	0:a04710facbb6	6998	#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	6999	#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	7000	#define CAN_F2R1_FB23_Pos (23U)
hudakz	0:a04710facbb6	7001	#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	7002	#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	7003	#define CAN_F2R1_FB24_Pos (24U)
hudakz	0:a04710facbb6	7004	#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	7005	#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	7006	#define CAN_F2R1_FB25_Pos (25U)
hudakz	0:a04710facbb6	7007	#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	7008	#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	7009	#define CAN_F2R1_FB26_Pos (26U)
hudakz	0:a04710facbb6	7010	#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	7011	#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	7012	#define CAN_F2R1_FB27_Pos (27U)
hudakz	0:a04710facbb6	7013	#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	7014	#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	7015	#define CAN_F2R1_FB28_Pos (28U)
hudakz	0:a04710facbb6	7016	#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	7017	#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	7018	#define CAN_F2R1_FB29_Pos (29U)
hudakz	0:a04710facbb6	7019	#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	7020	#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	7021	#define CAN_F2R1_FB30_Pos (30U)
hudakz	0:a04710facbb6	7022	#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	7023	#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	7024	#define CAN_F2R1_FB31_Pos (31U)
hudakz	0:a04710facbb6	7025	#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	7026	#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	7027
hudakz	0:a04710facbb6	7028	/***************** Bit definition for CAN_F3R1 register *****************/
hudakz	0:a04710facbb6	7029	#define CAN_F3R1_FB0_Pos (0U)
hudakz	0:a04710facbb6	7030	#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	7031	#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	7032	#define CAN_F3R1_FB1_Pos (1U)
hudakz	0:a04710facbb6	7033	#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	7034	#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	7035	#define CAN_F3R1_FB2_Pos (2U)
hudakz	0:a04710facbb6	7036	#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	7037	#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	7038	#define CAN_F3R1_FB3_Pos (3U)
hudakz	0:a04710facbb6	7039	#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	7040	#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	7041	#define CAN_F3R1_FB4_Pos (4U)
hudakz	0:a04710facbb6	7042	#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	7043	#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	7044	#define CAN_F3R1_FB5_Pos (5U)
hudakz	0:a04710facbb6	7045	#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	7046	#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	7047	#define CAN_F3R1_FB6_Pos (6U)
hudakz	0:a04710facbb6	7048	#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	7049	#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	7050	#define CAN_F3R1_FB7_Pos (7U)
hudakz	0:a04710facbb6	7051	#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	7052	#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	7053	#define CAN_F3R1_FB8_Pos (8U)
hudakz	0:a04710facbb6	7054	#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	7055	#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	7056	#define CAN_F3R1_FB9_Pos (9U)
hudakz	0:a04710facbb6	7057	#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	7058	#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	7059	#define CAN_F3R1_FB10_Pos (10U)
hudakz	0:a04710facbb6	7060	#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	7061	#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	7062	#define CAN_F3R1_FB11_Pos (11U)
hudakz	0:a04710facbb6	7063	#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	7064	#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	7065	#define CAN_F3R1_FB12_Pos (12U)
hudakz	0:a04710facbb6	7066	#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	7067	#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	7068	#define CAN_F3R1_FB13_Pos (13U)
hudakz	0:a04710facbb6	7069	#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	7070	#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	7071	#define CAN_F3R1_FB14_Pos (14U)
hudakz	0:a04710facbb6	7072	#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	7073	#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	7074	#define CAN_F3R1_FB15_Pos (15U)
hudakz	0:a04710facbb6	7075	#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	7076	#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	7077	#define CAN_F3R1_FB16_Pos (16U)
hudakz	0:a04710facbb6	7078	#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	7079	#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	7080	#define CAN_F3R1_FB17_Pos (17U)
hudakz	0:a04710facbb6	7081	#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	7082	#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	7083	#define CAN_F3R1_FB18_Pos (18U)
hudakz	0:a04710facbb6	7084	#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	7085	#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	7086	#define CAN_F3R1_FB19_Pos (19U)
hudakz	0:a04710facbb6	7087	#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	7088	#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	7089	#define CAN_F3R1_FB20_Pos (20U)
hudakz	0:a04710facbb6	7090	#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	7091	#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	7092	#define CAN_F3R1_FB21_Pos (21U)
hudakz	0:a04710facbb6	7093	#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	7094	#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	7095	#define CAN_F3R1_FB22_Pos (22U)
hudakz	0:a04710facbb6	7096	#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	7097	#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	7098	#define CAN_F3R1_FB23_Pos (23U)
hudakz	0:a04710facbb6	7099	#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	7100	#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	7101	#define CAN_F3R1_FB24_Pos (24U)
hudakz	0:a04710facbb6	7102	#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	7103	#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	7104	#define CAN_F3R1_FB25_Pos (25U)
hudakz	0:a04710facbb6	7105	#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	7106	#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	7107	#define CAN_F3R1_FB26_Pos (26U)
hudakz	0:a04710facbb6	7108	#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	7109	#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	7110	#define CAN_F3R1_FB27_Pos (27U)
hudakz	0:a04710facbb6	7111	#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	7112	#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	7113	#define CAN_F3R1_FB28_Pos (28U)
hudakz	0:a04710facbb6	7114	#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	7115	#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	7116	#define CAN_F3R1_FB29_Pos (29U)
hudakz	0:a04710facbb6	7117	#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	7118	#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	7119	#define CAN_F3R1_FB30_Pos (30U)
hudakz	0:a04710facbb6	7120	#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	7121	#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	7122	#define CAN_F3R1_FB31_Pos (31U)
hudakz	0:a04710facbb6	7123	#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	7124	#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	7125
hudakz	0:a04710facbb6	7126	/***************** Bit definition for CAN_F4R1 register *****************/
hudakz	0:a04710facbb6	7127	#define CAN_F4R1_FB0_Pos (0U)
hudakz	0:a04710facbb6	7128	#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	7129	#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	7130	#define CAN_F4R1_FB1_Pos (1U)
hudakz	0:a04710facbb6	7131	#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	7132	#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	7133	#define CAN_F4R1_FB2_Pos (2U)
hudakz	0:a04710facbb6	7134	#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	7135	#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	7136	#define CAN_F4R1_FB3_Pos (3U)
hudakz	0:a04710facbb6	7137	#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	7138	#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	7139	#define CAN_F4R1_FB4_Pos (4U)
hudakz	0:a04710facbb6	7140	#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	7141	#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	7142	#define CAN_F4R1_FB5_Pos (5U)
hudakz	0:a04710facbb6	7143	#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	7144	#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	7145	#define CAN_F4R1_FB6_Pos (6U)
hudakz	0:a04710facbb6	7146	#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	7147	#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	7148	#define CAN_F4R1_FB7_Pos (7U)
hudakz	0:a04710facbb6	7149	#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	7150	#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	7151	#define CAN_F4R1_FB8_Pos (8U)
hudakz	0:a04710facbb6	7152	#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	7153	#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	7154	#define CAN_F4R1_FB9_Pos (9U)
hudakz	0:a04710facbb6	7155	#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	7156	#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	7157	#define CAN_F4R1_FB10_Pos (10U)
hudakz	0:a04710facbb6	7158	#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	7159	#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	7160	#define CAN_F4R1_FB11_Pos (11U)
hudakz	0:a04710facbb6	7161	#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	7162	#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	7163	#define CAN_F4R1_FB12_Pos (12U)
hudakz	0:a04710facbb6	7164	#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	7165	#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	7166	#define CAN_F4R1_FB13_Pos (13U)
hudakz	0:a04710facbb6	7167	#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	7168	#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	7169	#define CAN_F4R1_FB14_Pos (14U)
hudakz	0:a04710facbb6	7170	#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	7171	#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	7172	#define CAN_F4R1_FB15_Pos (15U)
hudakz	0:a04710facbb6	7173	#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	7174	#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	7175	#define CAN_F4R1_FB16_Pos (16U)
hudakz	0:a04710facbb6	7176	#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	7177	#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	7178	#define CAN_F4R1_FB17_Pos (17U)
hudakz	0:a04710facbb6	7179	#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	7180	#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	7181	#define CAN_F4R1_FB18_Pos (18U)
hudakz	0:a04710facbb6	7182	#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	7183	#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	7184	#define CAN_F4R1_FB19_Pos (19U)
hudakz	0:a04710facbb6	7185	#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	7186	#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	7187	#define CAN_F4R1_FB20_Pos (20U)
hudakz	0:a04710facbb6	7188	#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	7189	#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	7190	#define CAN_F4R1_FB21_Pos (21U)
hudakz	0:a04710facbb6	7191	#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	7192	#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	7193	#define CAN_F4R1_FB22_Pos (22U)
hudakz	0:a04710facbb6	7194	#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	7195	#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	7196	#define CAN_F4R1_FB23_Pos (23U)
hudakz	0:a04710facbb6	7197	#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	7198	#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	7199	#define CAN_F4R1_FB24_Pos (24U)
hudakz	0:a04710facbb6	7200	#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	7201	#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	7202	#define CAN_F4R1_FB25_Pos (25U)
hudakz	0:a04710facbb6	7203	#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	7204	#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	7205	#define CAN_F4R1_FB26_Pos (26U)
hudakz	0:a04710facbb6	7206	#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	7207	#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	7208	#define CAN_F4R1_FB27_Pos (27U)
hudakz	0:a04710facbb6	7209	#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	7210	#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	7211	#define CAN_F4R1_FB28_Pos (28U)
hudakz	0:a04710facbb6	7212	#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	7213	#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	7214	#define CAN_F4R1_FB29_Pos (29U)
hudakz	0:a04710facbb6	7215	#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	7216	#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	7217	#define CAN_F4R1_FB30_Pos (30U)
hudakz	0:a04710facbb6	7218	#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	7219	#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	7220	#define CAN_F4R1_FB31_Pos (31U)
hudakz	0:a04710facbb6	7221	#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	7222	#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	7223
hudakz	0:a04710facbb6	7224	/***************** Bit definition for CAN_F5R1 register *****************/
hudakz	0:a04710facbb6	7225	#define CAN_F5R1_FB0_Pos (0U)
hudakz	0:a04710facbb6	7226	#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	7227	#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	7228	#define CAN_F5R1_FB1_Pos (1U)
hudakz	0:a04710facbb6	7229	#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	7230	#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	7231	#define CAN_F5R1_FB2_Pos (2U)
hudakz	0:a04710facbb6	7232	#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	7233	#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	7234	#define CAN_F5R1_FB3_Pos (3U)
hudakz	0:a04710facbb6	7235	#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	7236	#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	7237	#define CAN_F5R1_FB4_Pos (4U)
hudakz	0:a04710facbb6	7238	#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	7239	#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	7240	#define CAN_F5R1_FB5_Pos (5U)
hudakz	0:a04710facbb6	7241	#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	7242	#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	7243	#define CAN_F5R1_FB6_Pos (6U)
hudakz	0:a04710facbb6	7244	#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	7245	#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	7246	#define CAN_F5R1_FB7_Pos (7U)
hudakz	0:a04710facbb6	7247	#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	7248	#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	7249	#define CAN_F5R1_FB8_Pos (8U)
hudakz	0:a04710facbb6	7250	#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	7251	#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	7252	#define CAN_F5R1_FB9_Pos (9U)
hudakz	0:a04710facbb6	7253	#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	7254	#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	7255	#define CAN_F5R1_FB10_Pos (10U)
hudakz	0:a04710facbb6	7256	#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	7257	#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	7258	#define CAN_F5R1_FB11_Pos (11U)
hudakz	0:a04710facbb6	7259	#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	7260	#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	7261	#define CAN_F5R1_FB12_Pos (12U)
hudakz	0:a04710facbb6	7262	#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	7263	#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	7264	#define CAN_F5R1_FB13_Pos (13U)
hudakz	0:a04710facbb6	7265	#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	7266	#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	7267	#define CAN_F5R1_FB14_Pos (14U)
hudakz	0:a04710facbb6	7268	#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	7269	#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	7270	#define CAN_F5R1_FB15_Pos (15U)
hudakz	0:a04710facbb6	7271	#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	7272	#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	7273	#define CAN_F5R1_FB16_Pos (16U)
hudakz	0:a04710facbb6	7274	#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	7275	#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	7276	#define CAN_F5R1_FB17_Pos (17U)
hudakz	0:a04710facbb6	7277	#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	7278	#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	7279	#define CAN_F5R1_FB18_Pos (18U)
hudakz	0:a04710facbb6	7280	#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	7281	#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	7282	#define CAN_F5R1_FB19_Pos (19U)
hudakz	0:a04710facbb6	7283	#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	7284	#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	7285	#define CAN_F5R1_FB20_Pos (20U)
hudakz	0:a04710facbb6	7286	#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	7287	#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	7288	#define CAN_F5R1_FB21_Pos (21U)
hudakz	0:a04710facbb6	7289	#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	7290	#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	7291	#define CAN_F5R1_FB22_Pos (22U)
hudakz	0:a04710facbb6	7292	#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	7293	#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	7294	#define CAN_F5R1_FB23_Pos (23U)
hudakz	0:a04710facbb6	7295	#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	7296	#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	7297	#define CAN_F5R1_FB24_Pos (24U)
hudakz	0:a04710facbb6	7298	#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	7299	#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	7300	#define CAN_F5R1_FB25_Pos (25U)
hudakz	0:a04710facbb6	7301	#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	7302	#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	7303	#define CAN_F5R1_FB26_Pos (26U)
hudakz	0:a04710facbb6	7304	#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	7305	#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	7306	#define CAN_F5R1_FB27_Pos (27U)
hudakz	0:a04710facbb6	7307	#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	7308	#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	7309	#define CAN_F5R1_FB28_Pos (28U)
hudakz	0:a04710facbb6	7310	#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	7311	#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	7312	#define CAN_F5R1_FB29_Pos (29U)
hudakz	0:a04710facbb6	7313	#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	7314	#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	7315	#define CAN_F5R1_FB30_Pos (30U)
hudakz	0:a04710facbb6	7316	#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	7317	#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	7318	#define CAN_F5R1_FB31_Pos (31U)
hudakz	0:a04710facbb6	7319	#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	7320	#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	7321
hudakz	0:a04710facbb6	7322	/***************** Bit definition for CAN_F6R1 register *****************/
hudakz	0:a04710facbb6	7323	#define CAN_F6R1_FB0_Pos (0U)
hudakz	0:a04710facbb6	7324	#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	7325	#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	7326	#define CAN_F6R1_FB1_Pos (1U)
hudakz	0:a04710facbb6	7327	#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	7328	#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	7329	#define CAN_F6R1_FB2_Pos (2U)
hudakz	0:a04710facbb6	7330	#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	7331	#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	7332	#define CAN_F6R1_FB3_Pos (3U)
hudakz	0:a04710facbb6	7333	#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	7334	#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	7335	#define CAN_F6R1_FB4_Pos (4U)
hudakz	0:a04710facbb6	7336	#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	7337	#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	7338	#define CAN_F6R1_FB5_Pos (5U)
hudakz	0:a04710facbb6	7339	#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	7340	#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	7341	#define CAN_F6R1_FB6_Pos (6U)
hudakz	0:a04710facbb6	7342	#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	7343	#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	7344	#define CAN_F6R1_FB7_Pos (7U)
hudakz	0:a04710facbb6	7345	#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	7346	#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	7347	#define CAN_F6R1_FB8_Pos (8U)
hudakz	0:a04710facbb6	7348	#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	7349	#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	7350	#define CAN_F6R1_FB9_Pos (9U)
hudakz	0:a04710facbb6	7351	#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	7352	#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	7353	#define CAN_F6R1_FB10_Pos (10U)
hudakz	0:a04710facbb6	7354	#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	7355	#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	7356	#define CAN_F6R1_FB11_Pos (11U)
hudakz	0:a04710facbb6	7357	#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	7358	#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	7359	#define CAN_F6R1_FB12_Pos (12U)
hudakz	0:a04710facbb6	7360	#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	7361	#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	7362	#define CAN_F6R1_FB13_Pos (13U)
hudakz	0:a04710facbb6	7363	#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	7364	#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	7365	#define CAN_F6R1_FB14_Pos (14U)
hudakz	0:a04710facbb6	7366	#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	7367	#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	7368	#define CAN_F6R1_FB15_Pos (15U)
hudakz	0:a04710facbb6	7369	#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	7370	#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	7371	#define CAN_F6R1_FB16_Pos (16U)
hudakz	0:a04710facbb6	7372	#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	7373	#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	7374	#define CAN_F6R1_FB17_Pos (17U)
hudakz	0:a04710facbb6	7375	#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	7376	#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	7377	#define CAN_F6R1_FB18_Pos (18U)
hudakz	0:a04710facbb6	7378	#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	7379	#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	7380	#define CAN_F6R1_FB19_Pos (19U)
hudakz	0:a04710facbb6	7381	#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	7382	#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	7383	#define CAN_F6R1_FB20_Pos (20U)
hudakz	0:a04710facbb6	7384	#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	7385	#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	7386	#define CAN_F6R1_FB21_Pos (21U)
hudakz	0:a04710facbb6	7387	#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	7388	#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	7389	#define CAN_F6R1_FB22_Pos (22U)
hudakz	0:a04710facbb6	7390	#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	7391	#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	7392	#define CAN_F6R1_FB23_Pos (23U)
hudakz	0:a04710facbb6	7393	#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	7394	#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	7395	#define CAN_F6R1_FB24_Pos (24U)
hudakz	0:a04710facbb6	7396	#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	7397	#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	7398	#define CAN_F6R1_FB25_Pos (25U)
hudakz	0:a04710facbb6	7399	#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	7400	#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	7401	#define CAN_F6R1_FB26_Pos (26U)
hudakz	0:a04710facbb6	7402	#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	7403	#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	7404	#define CAN_F6R1_FB27_Pos (27U)
hudakz	0:a04710facbb6	7405	#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	7406	#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	7407	#define CAN_F6R1_FB28_Pos (28U)
hudakz	0:a04710facbb6	7408	#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	7409	#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	7410	#define CAN_F6R1_FB29_Pos (29U)
hudakz	0:a04710facbb6	7411	#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	7412	#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	7413	#define CAN_F6R1_FB30_Pos (30U)
hudakz	0:a04710facbb6	7414	#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	7415	#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	7416	#define CAN_F6R1_FB31_Pos (31U)
hudakz	0:a04710facbb6	7417	#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	7418	#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	7419
hudakz	0:a04710facbb6	7420	/***************** Bit definition for CAN_F7R1 register *****************/
hudakz	0:a04710facbb6	7421	#define CAN_F7R1_FB0_Pos (0U)
hudakz	0:a04710facbb6	7422	#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	7423	#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	7424	#define CAN_F7R1_FB1_Pos (1U)
hudakz	0:a04710facbb6	7425	#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	7426	#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	7427	#define CAN_F7R1_FB2_Pos (2U)
hudakz	0:a04710facbb6	7428	#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	7429	#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	7430	#define CAN_F7R1_FB3_Pos (3U)
hudakz	0:a04710facbb6	7431	#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	7432	#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	7433	#define CAN_F7R1_FB4_Pos (4U)
hudakz	0:a04710facbb6	7434	#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	7435	#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	7436	#define CAN_F7R1_FB5_Pos (5U)
hudakz	0:a04710facbb6	7437	#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	7438	#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	7439	#define CAN_F7R1_FB6_Pos (6U)
hudakz	0:a04710facbb6	7440	#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	7441	#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	7442	#define CAN_F7R1_FB7_Pos (7U)
hudakz	0:a04710facbb6	7443	#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	7444	#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	7445	#define CAN_F7R1_FB8_Pos (8U)
hudakz	0:a04710facbb6	7446	#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	7447	#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	7448	#define CAN_F7R1_FB9_Pos (9U)
hudakz	0:a04710facbb6	7449	#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	7450	#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	7451	#define CAN_F7R1_FB10_Pos (10U)
hudakz	0:a04710facbb6	7452	#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	7453	#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	7454	#define CAN_F7R1_FB11_Pos (11U)
hudakz	0:a04710facbb6	7455	#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	7456	#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	7457	#define CAN_F7R1_FB12_Pos (12U)
hudakz	0:a04710facbb6	7458	#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	7459	#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	7460	#define CAN_F7R1_FB13_Pos (13U)
hudakz	0:a04710facbb6	7461	#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	7462	#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	7463	#define CAN_F7R1_FB14_Pos (14U)
hudakz	0:a04710facbb6	7464	#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	7465	#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	7466	#define CAN_F7R1_FB15_Pos (15U)
hudakz	0:a04710facbb6	7467	#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	7468	#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	7469	#define CAN_F7R1_FB16_Pos (16U)
hudakz	0:a04710facbb6	7470	#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	7471	#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	7472	#define CAN_F7R1_FB17_Pos (17U)
hudakz	0:a04710facbb6	7473	#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	7474	#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	7475	#define CAN_F7R1_FB18_Pos (18U)
hudakz	0:a04710facbb6	7476	#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	7477	#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	7478	#define CAN_F7R1_FB19_Pos (19U)
hudakz	0:a04710facbb6	7479	#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	7480	#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	7481	#define CAN_F7R1_FB20_Pos (20U)
hudakz	0:a04710facbb6	7482	#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	7483	#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	7484	#define CAN_F7R1_FB21_Pos (21U)
hudakz	0:a04710facbb6	7485	#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	7486	#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	7487	#define CAN_F7R1_FB22_Pos (22U)
hudakz	0:a04710facbb6	7488	#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	7489	#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	7490	#define CAN_F7R1_FB23_Pos (23U)
hudakz	0:a04710facbb6	7491	#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	7492	#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	7493	#define CAN_F7R1_FB24_Pos (24U)
hudakz	0:a04710facbb6	7494	#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	7495	#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	7496	#define CAN_F7R1_FB25_Pos (25U)
hudakz	0:a04710facbb6	7497	#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	7498	#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	7499	#define CAN_F7R1_FB26_Pos (26U)
hudakz	0:a04710facbb6	7500	#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	7501	#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	7502	#define CAN_F7R1_FB27_Pos (27U)
hudakz	0:a04710facbb6	7503	#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	7504	#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	7505	#define CAN_F7R1_FB28_Pos (28U)
hudakz	0:a04710facbb6	7506	#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	7507	#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	7508	#define CAN_F7R1_FB29_Pos (29U)
hudakz	0:a04710facbb6	7509	#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	7510	#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	7511	#define CAN_F7R1_FB30_Pos (30U)
hudakz	0:a04710facbb6	7512	#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	7513	#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	7514	#define CAN_F7R1_FB31_Pos (31U)
hudakz	0:a04710facbb6	7515	#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	7516	#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	7517
hudakz	0:a04710facbb6	7518	/***************** Bit definition for CAN_F8R1 register *****************/
hudakz	0:a04710facbb6	7519	#define CAN_F8R1_FB0_Pos (0U)
hudakz	0:a04710facbb6	7520	#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	7521	#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	7522	#define CAN_F8R1_FB1_Pos (1U)
hudakz	0:a04710facbb6	7523	#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	7524	#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	7525	#define CAN_F8R1_FB2_Pos (2U)
hudakz	0:a04710facbb6	7526	#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	7527	#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	7528	#define CAN_F8R1_FB3_Pos (3U)
hudakz	0:a04710facbb6	7529	#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	7530	#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	7531	#define CAN_F8R1_FB4_Pos (4U)
hudakz	0:a04710facbb6	7532	#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	7533	#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	7534	#define CAN_F8R1_FB5_Pos (5U)
hudakz	0:a04710facbb6	7535	#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	7536	#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	7537	#define CAN_F8R1_FB6_Pos (6U)
hudakz	0:a04710facbb6	7538	#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	7539	#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	7540	#define CAN_F8R1_FB7_Pos (7U)
hudakz	0:a04710facbb6	7541	#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	7542	#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	7543	#define CAN_F8R1_FB8_Pos (8U)
hudakz	0:a04710facbb6	7544	#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	7545	#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	7546	#define CAN_F8R1_FB9_Pos (9U)
hudakz	0:a04710facbb6	7547	#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	7548	#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	7549	#define CAN_F8R1_FB10_Pos (10U)
hudakz	0:a04710facbb6	7550	#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	7551	#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	7552	#define CAN_F8R1_FB11_Pos (11U)
hudakz	0:a04710facbb6	7553	#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	7554	#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	7555	#define CAN_F8R1_FB12_Pos (12U)
hudakz	0:a04710facbb6	7556	#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	7557	#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	7558	#define CAN_F8R1_FB13_Pos (13U)
hudakz	0:a04710facbb6	7559	#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	7560	#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	7561	#define CAN_F8R1_FB14_Pos (14U)
hudakz	0:a04710facbb6	7562	#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	7563	#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	7564	#define CAN_F8R1_FB15_Pos (15U)
hudakz	0:a04710facbb6	7565	#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	7566	#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	7567	#define CAN_F8R1_FB16_Pos (16U)
hudakz	0:a04710facbb6	7568	#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	7569	#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	7570	#define CAN_F8R1_FB17_Pos (17U)
hudakz	0:a04710facbb6	7571	#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	7572	#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	7573	#define CAN_F8R1_FB18_Pos (18U)
hudakz	0:a04710facbb6	7574	#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	7575	#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	7576	#define CAN_F8R1_FB19_Pos (19U)
hudakz	0:a04710facbb6	7577	#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	7578	#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	7579	#define CAN_F8R1_FB20_Pos (20U)
hudakz	0:a04710facbb6	7580	#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	7581	#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	7582	#define CAN_F8R1_FB21_Pos (21U)
hudakz	0:a04710facbb6	7583	#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	7584	#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	7585	#define CAN_F8R1_FB22_Pos (22U)
hudakz	0:a04710facbb6	7586	#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	7587	#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	7588	#define CAN_F8R1_FB23_Pos (23U)
hudakz	0:a04710facbb6	7589	#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	7590	#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	7591	#define CAN_F8R1_FB24_Pos (24U)
hudakz	0:a04710facbb6	7592	#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	7593	#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	7594	#define CAN_F8R1_FB25_Pos (25U)
hudakz	0:a04710facbb6	7595	#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	7596	#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	7597	#define CAN_F8R1_FB26_Pos (26U)
hudakz	0:a04710facbb6	7598	#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	7599	#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	7600	#define CAN_F8R1_FB27_Pos (27U)
hudakz	0:a04710facbb6	7601	#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	7602	#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	7603	#define CAN_F8R1_FB28_Pos (28U)
hudakz	0:a04710facbb6	7604	#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	7605	#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	7606	#define CAN_F8R1_FB29_Pos (29U)
hudakz	0:a04710facbb6	7607	#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	7608	#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	7609	#define CAN_F8R1_FB30_Pos (30U)
hudakz	0:a04710facbb6	7610	#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	7611	#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	7612	#define CAN_F8R1_FB31_Pos (31U)
hudakz	0:a04710facbb6	7613	#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	7614	#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	7615
hudakz	0:a04710facbb6	7616	/***************** Bit definition for CAN_F9R1 register *****************/
hudakz	0:a04710facbb6	7617	#define CAN_F9R1_FB0_Pos (0U)
hudakz	0:a04710facbb6	7618	#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	7619	#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	7620	#define CAN_F9R1_FB1_Pos (1U)
hudakz	0:a04710facbb6	7621	#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	7622	#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	7623	#define CAN_F9R1_FB2_Pos (2U)
hudakz	0:a04710facbb6	7624	#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	7625	#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	7626	#define CAN_F9R1_FB3_Pos (3U)
hudakz	0:a04710facbb6	7627	#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	7628	#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	7629	#define CAN_F9R1_FB4_Pos (4U)
hudakz	0:a04710facbb6	7630	#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	7631	#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	7632	#define CAN_F9R1_FB5_Pos (5U)
hudakz	0:a04710facbb6	7633	#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	7634	#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	7635	#define CAN_F9R1_FB6_Pos (6U)
hudakz	0:a04710facbb6	7636	#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	7637	#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	7638	#define CAN_F9R1_FB7_Pos (7U)
hudakz	0:a04710facbb6	7639	#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	7640	#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	7641	#define CAN_F9R1_FB8_Pos (8U)
hudakz	0:a04710facbb6	7642	#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	7643	#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	7644	#define CAN_F9R1_FB9_Pos (9U)
hudakz	0:a04710facbb6	7645	#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	7646	#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	7647	#define CAN_F9R1_FB10_Pos (10U)
hudakz	0:a04710facbb6	7648	#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	7649	#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	7650	#define CAN_F9R1_FB11_Pos (11U)
hudakz	0:a04710facbb6	7651	#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	7652	#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	7653	#define CAN_F9R1_FB12_Pos (12U)
hudakz	0:a04710facbb6	7654	#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	7655	#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	7656	#define CAN_F9R1_FB13_Pos (13U)
hudakz	0:a04710facbb6	7657	#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	7658	#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	7659	#define CAN_F9R1_FB14_Pos (14U)
hudakz	0:a04710facbb6	7660	#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	7661	#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	7662	#define CAN_F9R1_FB15_Pos (15U)
hudakz	0:a04710facbb6	7663	#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	7664	#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	7665	#define CAN_F9R1_FB16_Pos (16U)
hudakz	0:a04710facbb6	7666	#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	7667	#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	7668	#define CAN_F9R1_FB17_Pos (17U)
hudakz	0:a04710facbb6	7669	#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	7670	#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	7671	#define CAN_F9R1_FB18_Pos (18U)
hudakz	0:a04710facbb6	7672	#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	7673	#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	7674	#define CAN_F9R1_FB19_Pos (19U)
hudakz	0:a04710facbb6	7675	#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	7676	#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	7677	#define CAN_F9R1_FB20_Pos (20U)
hudakz	0:a04710facbb6	7678	#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	7679	#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	7680	#define CAN_F9R1_FB21_Pos (21U)
hudakz	0:a04710facbb6	7681	#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	7682	#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	7683	#define CAN_F9R1_FB22_Pos (22U)
hudakz	0:a04710facbb6	7684	#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	7685	#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	7686	#define CAN_F9R1_FB23_Pos (23U)
hudakz	0:a04710facbb6	7687	#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	7688	#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	7689	#define CAN_F9R1_FB24_Pos (24U)
hudakz	0:a04710facbb6	7690	#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	7691	#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	7692	#define CAN_F9R1_FB25_Pos (25U)
hudakz	0:a04710facbb6	7693	#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	7694	#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	7695	#define CAN_F9R1_FB26_Pos (26U)
hudakz	0:a04710facbb6	7696	#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	7697	#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	7698	#define CAN_F9R1_FB27_Pos (27U)
hudakz	0:a04710facbb6	7699	#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	7700	#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	7701	#define CAN_F9R1_FB28_Pos (28U)
hudakz	0:a04710facbb6	7702	#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	7703	#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	7704	#define CAN_F9R1_FB29_Pos (29U)
hudakz	0:a04710facbb6	7705	#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	7706	#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	7707	#define CAN_F9R1_FB30_Pos (30U)
hudakz	0:a04710facbb6	7708	#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	7709	#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	7710	#define CAN_F9R1_FB31_Pos (31U)
hudakz	0:a04710facbb6	7711	#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	7712	#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	7713
hudakz	0:a04710facbb6	7714	/***************** Bit definition for CAN_F10R1 register ****************/
hudakz	0:a04710facbb6	7715	#define CAN_F10R1_FB0_Pos (0U)
hudakz	0:a04710facbb6	7716	#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	7717	#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	7718	#define CAN_F10R1_FB1_Pos (1U)
hudakz	0:a04710facbb6	7719	#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	7720	#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	7721	#define CAN_F10R1_FB2_Pos (2U)
hudakz	0:a04710facbb6	7722	#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	7723	#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	7724	#define CAN_F10R1_FB3_Pos (3U)
hudakz	0:a04710facbb6	7725	#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	7726	#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	7727	#define CAN_F10R1_FB4_Pos (4U)
hudakz	0:a04710facbb6	7728	#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	7729	#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	7730	#define CAN_F10R1_FB5_Pos (5U)
hudakz	0:a04710facbb6	7731	#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	7732	#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	7733	#define CAN_F10R1_FB6_Pos (6U)
hudakz	0:a04710facbb6	7734	#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	7735	#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	7736	#define CAN_F10R1_FB7_Pos (7U)
hudakz	0:a04710facbb6	7737	#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	7738	#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	7739	#define CAN_F10R1_FB8_Pos (8U)
hudakz	0:a04710facbb6	7740	#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	7741	#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	7742	#define CAN_F10R1_FB9_Pos (9U)
hudakz	0:a04710facbb6	7743	#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	7744	#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	7745	#define CAN_F10R1_FB10_Pos (10U)
hudakz	0:a04710facbb6	7746	#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	7747	#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	7748	#define CAN_F10R1_FB11_Pos (11U)
hudakz	0:a04710facbb6	7749	#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	7750	#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	7751	#define CAN_F10R1_FB12_Pos (12U)
hudakz	0:a04710facbb6	7752	#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	7753	#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	7754	#define CAN_F10R1_FB13_Pos (13U)
hudakz	0:a04710facbb6	7755	#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	7756	#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	7757	#define CAN_F10R1_FB14_Pos (14U)
hudakz	0:a04710facbb6	7758	#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	7759	#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	7760	#define CAN_F10R1_FB15_Pos (15U)
hudakz	0:a04710facbb6	7761	#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	7762	#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	7763	#define CAN_F10R1_FB16_Pos (16U)
hudakz	0:a04710facbb6	7764	#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	7765	#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	7766	#define CAN_F10R1_FB17_Pos (17U)
hudakz	0:a04710facbb6	7767	#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	7768	#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	7769	#define CAN_F10R1_FB18_Pos (18U)
hudakz	0:a04710facbb6	7770	#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	7771	#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	7772	#define CAN_F10R1_FB19_Pos (19U)
hudakz	0:a04710facbb6	7773	#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	7774	#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	7775	#define CAN_F10R1_FB20_Pos (20U)
hudakz	0:a04710facbb6	7776	#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	7777	#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	7778	#define CAN_F10R1_FB21_Pos (21U)
hudakz	0:a04710facbb6	7779	#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	7780	#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	7781	#define CAN_F10R1_FB22_Pos (22U)
hudakz	0:a04710facbb6	7782	#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	7783	#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	7784	#define CAN_F10R1_FB23_Pos (23U)
hudakz	0:a04710facbb6	7785	#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	7786	#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	7787	#define CAN_F10R1_FB24_Pos (24U)
hudakz	0:a04710facbb6	7788	#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	7789	#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	7790	#define CAN_F10R1_FB25_Pos (25U)
hudakz	0:a04710facbb6	7791	#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	7792	#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	7793	#define CAN_F10R1_FB26_Pos (26U)
hudakz	0:a04710facbb6	7794	#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	7795	#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	7796	#define CAN_F10R1_FB27_Pos (27U)
hudakz	0:a04710facbb6	7797	#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	7798	#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	7799	#define CAN_F10R1_FB28_Pos (28U)
hudakz	0:a04710facbb6	7800	#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	7801	#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	7802	#define CAN_F10R1_FB29_Pos (29U)
hudakz	0:a04710facbb6	7803	#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	7804	#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	7805	#define CAN_F10R1_FB30_Pos (30U)
hudakz	0:a04710facbb6	7806	#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	7807	#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	7808	#define CAN_F10R1_FB31_Pos (31U)
hudakz	0:a04710facbb6	7809	#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	7810	#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	7811
hudakz	0:a04710facbb6	7812	/***************** Bit definition for CAN_F11R1 register ****************/
hudakz	0:a04710facbb6	7813	#define CAN_F11R1_FB0_Pos (0U)
hudakz	0:a04710facbb6	7814	#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	7815	#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	7816	#define CAN_F11R1_FB1_Pos (1U)
hudakz	0:a04710facbb6	7817	#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	7818	#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	7819	#define CAN_F11R1_FB2_Pos (2U)
hudakz	0:a04710facbb6	7820	#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	7821	#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	7822	#define CAN_F11R1_FB3_Pos (3U)
hudakz	0:a04710facbb6	7823	#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	7824	#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	7825	#define CAN_F11R1_FB4_Pos (4U)
hudakz	0:a04710facbb6	7826	#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	7827	#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	7828	#define CAN_F11R1_FB5_Pos (5U)
hudakz	0:a04710facbb6	7829	#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	7830	#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	7831	#define CAN_F11R1_FB6_Pos (6U)
hudakz	0:a04710facbb6	7832	#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	7833	#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	7834	#define CAN_F11R1_FB7_Pos (7U)
hudakz	0:a04710facbb6	7835	#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	7836	#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	7837	#define CAN_F11R1_FB8_Pos (8U)
hudakz	0:a04710facbb6	7838	#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	7839	#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	7840	#define CAN_F11R1_FB9_Pos (9U)
hudakz	0:a04710facbb6	7841	#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	7842	#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	7843	#define CAN_F11R1_FB10_Pos (10U)
hudakz	0:a04710facbb6	7844	#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	7845	#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	7846	#define CAN_F11R1_FB11_Pos (11U)
hudakz	0:a04710facbb6	7847	#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	7848	#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	7849	#define CAN_F11R1_FB12_Pos (12U)
hudakz	0:a04710facbb6	7850	#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	7851	#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	7852	#define CAN_F11R1_FB13_Pos (13U)
hudakz	0:a04710facbb6	7853	#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	7854	#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	7855	#define CAN_F11R1_FB14_Pos (14U)
hudakz	0:a04710facbb6	7856	#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	7857	#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	7858	#define CAN_F11R1_FB15_Pos (15U)
hudakz	0:a04710facbb6	7859	#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	7860	#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	7861	#define CAN_F11R1_FB16_Pos (16U)
hudakz	0:a04710facbb6	7862	#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	7863	#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	7864	#define CAN_F11R1_FB17_Pos (17U)
hudakz	0:a04710facbb6	7865	#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	7866	#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	7867	#define CAN_F11R1_FB18_Pos (18U)
hudakz	0:a04710facbb6	7868	#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	7869	#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	7870	#define CAN_F11R1_FB19_Pos (19U)
hudakz	0:a04710facbb6	7871	#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	7872	#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	7873	#define CAN_F11R1_FB20_Pos (20U)
hudakz	0:a04710facbb6	7874	#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	7875	#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	7876	#define CAN_F11R1_FB21_Pos (21U)
hudakz	0:a04710facbb6	7877	#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	7878	#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	7879	#define CAN_F11R1_FB22_Pos (22U)
hudakz	0:a04710facbb6	7880	#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	7881	#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	7882	#define CAN_F11R1_FB23_Pos (23U)
hudakz	0:a04710facbb6	7883	#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	7884	#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	7885	#define CAN_F11R1_FB24_Pos (24U)
hudakz	0:a04710facbb6	7886	#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	7887	#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	7888	#define CAN_F11R1_FB25_Pos (25U)
hudakz	0:a04710facbb6	7889	#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	7890	#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	7891	#define CAN_F11R1_FB26_Pos (26U)
hudakz	0:a04710facbb6	7892	#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	7893	#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	7894	#define CAN_F11R1_FB27_Pos (27U)
hudakz	0:a04710facbb6	7895	#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	7896	#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	7897	#define CAN_F11R1_FB28_Pos (28U)
hudakz	0:a04710facbb6	7898	#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	7899	#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	7900	#define CAN_F11R1_FB29_Pos (29U)
hudakz	0:a04710facbb6	7901	#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	7902	#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	7903	#define CAN_F11R1_FB30_Pos (30U)
hudakz	0:a04710facbb6	7904	#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	7905	#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	7906	#define CAN_F11R1_FB31_Pos (31U)
hudakz	0:a04710facbb6	7907	#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	7908	#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	7909
hudakz	0:a04710facbb6	7910	/***************** Bit definition for CAN_F12R1 register ****************/
hudakz	0:a04710facbb6	7911	#define CAN_F12R1_FB0_Pos (0U)
hudakz	0:a04710facbb6	7912	#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	7913	#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	7914	#define CAN_F12R1_FB1_Pos (1U)
hudakz	0:a04710facbb6	7915	#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	7916	#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	7917	#define CAN_F12R1_FB2_Pos (2U)
hudakz	0:a04710facbb6	7918	#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	7919	#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	7920	#define CAN_F12R1_FB3_Pos (3U)
hudakz	0:a04710facbb6	7921	#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	7922	#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	7923	#define CAN_F12R1_FB4_Pos (4U)
hudakz	0:a04710facbb6	7924	#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	7925	#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	7926	#define CAN_F12R1_FB5_Pos (5U)
hudakz	0:a04710facbb6	7927	#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	7928	#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	7929	#define CAN_F12R1_FB6_Pos (6U)
hudakz	0:a04710facbb6	7930	#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	7931	#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	7932	#define CAN_F12R1_FB7_Pos (7U)
hudakz	0:a04710facbb6	7933	#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	7934	#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	7935	#define CAN_F12R1_FB8_Pos (8U)
hudakz	0:a04710facbb6	7936	#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	7937	#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	7938	#define CAN_F12R1_FB9_Pos (9U)
hudakz	0:a04710facbb6	7939	#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	7940	#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	7941	#define CAN_F12R1_FB10_Pos (10U)
hudakz	0:a04710facbb6	7942	#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	7943	#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	7944	#define CAN_F12R1_FB11_Pos (11U)
hudakz	0:a04710facbb6	7945	#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	7946	#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	7947	#define CAN_F12R1_FB12_Pos (12U)
hudakz	0:a04710facbb6	7948	#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	7949	#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	7950	#define CAN_F12R1_FB13_Pos (13U)
hudakz	0:a04710facbb6	7951	#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	7952	#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	7953	#define CAN_F12R1_FB14_Pos (14U)
hudakz	0:a04710facbb6	7954	#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	7955	#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	7956	#define CAN_F12R1_FB15_Pos (15U)
hudakz	0:a04710facbb6	7957	#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	7958	#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	7959	#define CAN_F12R1_FB16_Pos (16U)
hudakz	0:a04710facbb6	7960	#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	7961	#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	7962	#define CAN_F12R1_FB17_Pos (17U)
hudakz	0:a04710facbb6	7963	#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	7964	#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	7965	#define CAN_F12R1_FB18_Pos (18U)
hudakz	0:a04710facbb6	7966	#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	7967	#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	7968	#define CAN_F12R1_FB19_Pos (19U)
hudakz	0:a04710facbb6	7969	#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	7970	#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	7971	#define CAN_F12R1_FB20_Pos (20U)
hudakz	0:a04710facbb6	7972	#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	7973	#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	7974	#define CAN_F12R1_FB21_Pos (21U)
hudakz	0:a04710facbb6	7975	#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	7976	#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	7977	#define CAN_F12R1_FB22_Pos (22U)
hudakz	0:a04710facbb6	7978	#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	7979	#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	7980	#define CAN_F12R1_FB23_Pos (23U)
hudakz	0:a04710facbb6	7981	#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	7982	#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	7983	#define CAN_F12R1_FB24_Pos (24U)
hudakz	0:a04710facbb6	7984	#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	7985	#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	7986	#define CAN_F12R1_FB25_Pos (25U)
hudakz	0:a04710facbb6	7987	#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	7988	#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	7989	#define CAN_F12R1_FB26_Pos (26U)
hudakz	0:a04710facbb6	7990	#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	7991	#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	7992	#define CAN_F12R1_FB27_Pos (27U)
hudakz	0:a04710facbb6	7993	#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	7994	#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	7995	#define CAN_F12R1_FB28_Pos (28U)
hudakz	0:a04710facbb6	7996	#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	7997	#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	7998	#define CAN_F12R1_FB29_Pos (29U)
hudakz	0:a04710facbb6	7999	#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	8000	#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	8001	#define CAN_F12R1_FB30_Pos (30U)
hudakz	0:a04710facbb6	8002	#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	8003	#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	8004	#define CAN_F12R1_FB31_Pos (31U)
hudakz	0:a04710facbb6	8005	#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	8006	#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	8007
hudakz	0:a04710facbb6	8008	/***************** Bit definition for CAN_F13R1 register ****************/
hudakz	0:a04710facbb6	8009	#define CAN_F13R1_FB0_Pos (0U)
hudakz	0:a04710facbb6	8010	#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	8011	#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	8012	#define CAN_F13R1_FB1_Pos (1U)
hudakz	0:a04710facbb6	8013	#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	8014	#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	8015	#define CAN_F13R1_FB2_Pos (2U)
hudakz	0:a04710facbb6	8016	#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	8017	#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	8018	#define CAN_F13R1_FB3_Pos (3U)
hudakz	0:a04710facbb6	8019	#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	8020	#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	8021	#define CAN_F13R1_FB4_Pos (4U)
hudakz	0:a04710facbb6	8022	#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	8023	#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	8024	#define CAN_F13R1_FB5_Pos (5U)
hudakz	0:a04710facbb6	8025	#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	8026	#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	8027	#define CAN_F13R1_FB6_Pos (6U)
hudakz	0:a04710facbb6	8028	#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	8029	#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	8030	#define CAN_F13R1_FB7_Pos (7U)
hudakz	0:a04710facbb6	8031	#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	8032	#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	8033	#define CAN_F13R1_FB8_Pos (8U)
hudakz	0:a04710facbb6	8034	#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	8035	#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	8036	#define CAN_F13R1_FB9_Pos (9U)
hudakz	0:a04710facbb6	8037	#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	8038	#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	8039	#define CAN_F13R1_FB10_Pos (10U)
hudakz	0:a04710facbb6	8040	#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	8041	#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	8042	#define CAN_F13R1_FB11_Pos (11U)
hudakz	0:a04710facbb6	8043	#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	8044	#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	8045	#define CAN_F13R1_FB12_Pos (12U)
hudakz	0:a04710facbb6	8046	#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	8047	#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	8048	#define CAN_F13R1_FB13_Pos (13U)
hudakz	0:a04710facbb6	8049	#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	8050	#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	8051	#define CAN_F13R1_FB14_Pos (14U)
hudakz	0:a04710facbb6	8052	#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	8053	#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	8054	#define CAN_F13R1_FB15_Pos (15U)
hudakz	0:a04710facbb6	8055	#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	8056	#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	8057	#define CAN_F13R1_FB16_Pos (16U)
hudakz	0:a04710facbb6	8058	#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	8059	#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	8060	#define CAN_F13R1_FB17_Pos (17U)
hudakz	0:a04710facbb6	8061	#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	8062	#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	8063	#define CAN_F13R1_FB18_Pos (18U)
hudakz	0:a04710facbb6	8064	#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	8065	#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	8066	#define CAN_F13R1_FB19_Pos (19U)
hudakz	0:a04710facbb6	8067	#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	8068	#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	8069	#define CAN_F13R1_FB20_Pos (20U)
hudakz	0:a04710facbb6	8070	#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	8071	#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	8072	#define CAN_F13R1_FB21_Pos (21U)
hudakz	0:a04710facbb6	8073	#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	8074	#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	8075	#define CAN_F13R1_FB22_Pos (22U)
hudakz	0:a04710facbb6	8076	#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	8077	#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	8078	#define CAN_F13R1_FB23_Pos (23U)
hudakz	0:a04710facbb6	8079	#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	8080	#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	8081	#define CAN_F13R1_FB24_Pos (24U)
hudakz	0:a04710facbb6	8082	#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	8083	#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	8084	#define CAN_F13R1_FB25_Pos (25U)
hudakz	0:a04710facbb6	8085	#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	8086	#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	8087	#define CAN_F13R1_FB26_Pos (26U)
hudakz	0:a04710facbb6	8088	#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	8089	#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	8090	#define CAN_F13R1_FB27_Pos (27U)
hudakz	0:a04710facbb6	8091	#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	8092	#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	8093	#define CAN_F13R1_FB28_Pos (28U)
hudakz	0:a04710facbb6	8094	#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	8095	#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	8096	#define CAN_F13R1_FB29_Pos (29U)
hudakz	0:a04710facbb6	8097	#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	8098	#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	8099	#define CAN_F13R1_FB30_Pos (30U)
hudakz	0:a04710facbb6	8100	#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	8101	#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	8102	#define CAN_F13R1_FB31_Pos (31U)
hudakz	0:a04710facbb6	8103	#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	8104	#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	8105
hudakz	0:a04710facbb6	8106	/***************** Bit definition for CAN_F0R2 register *****************/
hudakz	0:a04710facbb6	8107	#define CAN_F0R2_FB0_Pos (0U)
hudakz	0:a04710facbb6	8108	#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	8109	#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	8110	#define CAN_F0R2_FB1_Pos (1U)
hudakz	0:a04710facbb6	8111	#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	8112	#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	8113	#define CAN_F0R2_FB2_Pos (2U)
hudakz	0:a04710facbb6	8114	#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	8115	#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	8116	#define CAN_F0R2_FB3_Pos (3U)
hudakz	0:a04710facbb6	8117	#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	8118	#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	8119	#define CAN_F0R2_FB4_Pos (4U)
hudakz	0:a04710facbb6	8120	#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	8121	#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	8122	#define CAN_F0R2_FB5_Pos (5U)
hudakz	0:a04710facbb6	8123	#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	8124	#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	8125	#define CAN_F0R2_FB6_Pos (6U)
hudakz	0:a04710facbb6	8126	#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	8127	#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	8128	#define CAN_F0R2_FB7_Pos (7U)
hudakz	0:a04710facbb6	8129	#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	8130	#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	8131	#define CAN_F0R2_FB8_Pos (8U)
hudakz	0:a04710facbb6	8132	#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	8133	#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	8134	#define CAN_F0R2_FB9_Pos (9U)
hudakz	0:a04710facbb6	8135	#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	8136	#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	8137	#define CAN_F0R2_FB10_Pos (10U)
hudakz	0:a04710facbb6	8138	#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	8139	#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	8140	#define CAN_F0R2_FB11_Pos (11U)
hudakz	0:a04710facbb6	8141	#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	8142	#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	8143	#define CAN_F0R2_FB12_Pos (12U)
hudakz	0:a04710facbb6	8144	#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	8145	#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	8146	#define CAN_F0R2_FB13_Pos (13U)
hudakz	0:a04710facbb6	8147	#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	8148	#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	8149	#define CAN_F0R2_FB14_Pos (14U)
hudakz	0:a04710facbb6	8150	#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	8151	#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	8152	#define CAN_F0R2_FB15_Pos (15U)
hudakz	0:a04710facbb6	8153	#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	8154	#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	8155	#define CAN_F0R2_FB16_Pos (16U)
hudakz	0:a04710facbb6	8156	#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	8157	#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	8158	#define CAN_F0R2_FB17_Pos (17U)
hudakz	0:a04710facbb6	8159	#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	8160	#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	8161	#define CAN_F0R2_FB18_Pos (18U)
hudakz	0:a04710facbb6	8162	#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	8163	#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	8164	#define CAN_F0R2_FB19_Pos (19U)
hudakz	0:a04710facbb6	8165	#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	8166	#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	8167	#define CAN_F0R2_FB20_Pos (20U)
hudakz	0:a04710facbb6	8168	#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	8169	#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	8170	#define CAN_F0R2_FB21_Pos (21U)
hudakz	0:a04710facbb6	8171	#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	8172	#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	8173	#define CAN_F0R2_FB22_Pos (22U)
hudakz	0:a04710facbb6	8174	#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	8175	#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	8176	#define CAN_F0R2_FB23_Pos (23U)
hudakz	0:a04710facbb6	8177	#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	8178	#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	8179	#define CAN_F0R2_FB24_Pos (24U)
hudakz	0:a04710facbb6	8180	#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	8181	#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	8182	#define CAN_F0R2_FB25_Pos (25U)
hudakz	0:a04710facbb6	8183	#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	8184	#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	8185	#define CAN_F0R2_FB26_Pos (26U)
hudakz	0:a04710facbb6	8186	#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	8187	#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	8188	#define CAN_F0R2_FB27_Pos (27U)
hudakz	0:a04710facbb6	8189	#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	8190	#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	8191	#define CAN_F0R2_FB28_Pos (28U)
hudakz	0:a04710facbb6	8192	#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	8193	#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	8194	#define CAN_F0R2_FB29_Pos (29U)
hudakz	0:a04710facbb6	8195	#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	8196	#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	8197	#define CAN_F0R2_FB30_Pos (30U)
hudakz	0:a04710facbb6	8198	#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	8199	#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	8200	#define CAN_F0R2_FB31_Pos (31U)
hudakz	0:a04710facbb6	8201	#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	8202	#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	8203
hudakz	0:a04710facbb6	8204	/***************** Bit definition for CAN_F1R2 register *****************/
hudakz	0:a04710facbb6	8205	#define CAN_F1R2_FB0_Pos (0U)
hudakz	0:a04710facbb6	8206	#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	8207	#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	8208	#define CAN_F1R2_FB1_Pos (1U)
hudakz	0:a04710facbb6	8209	#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	8210	#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	8211	#define CAN_F1R2_FB2_Pos (2U)
hudakz	0:a04710facbb6	8212	#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	8213	#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	8214	#define CAN_F1R2_FB3_Pos (3U)
hudakz	0:a04710facbb6	8215	#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	8216	#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	8217	#define CAN_F1R2_FB4_Pos (4U)
hudakz	0:a04710facbb6	8218	#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	8219	#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	8220	#define CAN_F1R2_FB5_Pos (5U)
hudakz	0:a04710facbb6	8221	#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	8222	#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	8223	#define CAN_F1R2_FB6_Pos (6U)
hudakz	0:a04710facbb6	8224	#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	8225	#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	8226	#define CAN_F1R2_FB7_Pos (7U)
hudakz	0:a04710facbb6	8227	#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	8228	#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	8229	#define CAN_F1R2_FB8_Pos (8U)
hudakz	0:a04710facbb6	8230	#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	8231	#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	8232	#define CAN_F1R2_FB9_Pos (9U)
hudakz	0:a04710facbb6	8233	#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	8234	#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	8235	#define CAN_F1R2_FB10_Pos (10U)
hudakz	0:a04710facbb6	8236	#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	8237	#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	8238	#define CAN_F1R2_FB11_Pos (11U)
hudakz	0:a04710facbb6	8239	#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	8240	#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	8241	#define CAN_F1R2_FB12_Pos (12U)
hudakz	0:a04710facbb6	8242	#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	8243	#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	8244	#define CAN_F1R2_FB13_Pos (13U)
hudakz	0:a04710facbb6	8245	#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	8246	#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	8247	#define CAN_F1R2_FB14_Pos (14U)
hudakz	0:a04710facbb6	8248	#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	8249	#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	8250	#define CAN_F1R2_FB15_Pos (15U)
hudakz	0:a04710facbb6	8251	#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	8252	#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	8253	#define CAN_F1R2_FB16_Pos (16U)
hudakz	0:a04710facbb6	8254	#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	8255	#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	8256	#define CAN_F1R2_FB17_Pos (17U)
hudakz	0:a04710facbb6	8257	#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	8258	#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	8259	#define CAN_F1R2_FB18_Pos (18U)
hudakz	0:a04710facbb6	8260	#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	8261	#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	8262	#define CAN_F1R2_FB19_Pos (19U)
hudakz	0:a04710facbb6	8263	#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	8264	#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	8265	#define CAN_F1R2_FB20_Pos (20U)
hudakz	0:a04710facbb6	8266	#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	8267	#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	8268	#define CAN_F1R2_FB21_Pos (21U)
hudakz	0:a04710facbb6	8269	#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	8270	#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	8271	#define CAN_F1R2_FB22_Pos (22U)
hudakz	0:a04710facbb6	8272	#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	8273	#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	8274	#define CAN_F1R2_FB23_Pos (23U)
hudakz	0:a04710facbb6	8275	#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	8276	#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	8277	#define CAN_F1R2_FB24_Pos (24U)
hudakz	0:a04710facbb6	8278	#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	8279	#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	8280	#define CAN_F1R2_FB25_Pos (25U)
hudakz	0:a04710facbb6	8281	#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	8282	#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	8283	#define CAN_F1R2_FB26_Pos (26U)
hudakz	0:a04710facbb6	8284	#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	8285	#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	8286	#define CAN_F1R2_FB27_Pos (27U)
hudakz	0:a04710facbb6	8287	#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	8288	#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	8289	#define CAN_F1R2_FB28_Pos (28U)
hudakz	0:a04710facbb6	8290	#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	8291	#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	8292	#define CAN_F1R2_FB29_Pos (29U)
hudakz	0:a04710facbb6	8293	#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	8294	#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	8295	#define CAN_F1R2_FB30_Pos (30U)
hudakz	0:a04710facbb6	8296	#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	8297	#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	8298	#define CAN_F1R2_FB31_Pos (31U)
hudakz	0:a04710facbb6	8299	#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	8300	#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	8301
hudakz	0:a04710facbb6	8302	/***************** Bit definition for CAN_F2R2 register *****************/
hudakz	0:a04710facbb6	8303	#define CAN_F2R2_FB0_Pos (0U)
hudakz	0:a04710facbb6	8304	#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	8305	#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	8306	#define CAN_F2R2_FB1_Pos (1U)
hudakz	0:a04710facbb6	8307	#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	8308	#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	8309	#define CAN_F2R2_FB2_Pos (2U)
hudakz	0:a04710facbb6	8310	#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	8311	#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	8312	#define CAN_F2R2_FB3_Pos (3U)
hudakz	0:a04710facbb6	8313	#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	8314	#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	8315	#define CAN_F2R2_FB4_Pos (4U)
hudakz	0:a04710facbb6	8316	#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	8317	#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	8318	#define CAN_F2R2_FB5_Pos (5U)
hudakz	0:a04710facbb6	8319	#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	8320	#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	8321	#define CAN_F2R2_FB6_Pos (6U)
hudakz	0:a04710facbb6	8322	#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	8323	#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	8324	#define CAN_F2R2_FB7_Pos (7U)
hudakz	0:a04710facbb6	8325	#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	8326	#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	8327	#define CAN_F2R2_FB8_Pos (8U)
hudakz	0:a04710facbb6	8328	#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	8329	#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	8330	#define CAN_F2R2_FB9_Pos (9U)
hudakz	0:a04710facbb6	8331	#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	8332	#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	8333	#define CAN_F2R2_FB10_Pos (10U)
hudakz	0:a04710facbb6	8334	#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	8335	#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	8336	#define CAN_F2R2_FB11_Pos (11U)
hudakz	0:a04710facbb6	8337	#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	8338	#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	8339	#define CAN_F2R2_FB12_Pos (12U)
hudakz	0:a04710facbb6	8340	#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	8341	#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	8342	#define CAN_F2R2_FB13_Pos (13U)
hudakz	0:a04710facbb6	8343	#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	8344	#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	8345	#define CAN_F2R2_FB14_Pos (14U)
hudakz	0:a04710facbb6	8346	#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	8347	#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	8348	#define CAN_F2R2_FB15_Pos (15U)
hudakz	0:a04710facbb6	8349	#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	8350	#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	8351	#define CAN_F2R2_FB16_Pos (16U)
hudakz	0:a04710facbb6	8352	#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	8353	#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	8354	#define CAN_F2R2_FB17_Pos (17U)
hudakz	0:a04710facbb6	8355	#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	8356	#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	8357	#define CAN_F2R2_FB18_Pos (18U)
hudakz	0:a04710facbb6	8358	#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	8359	#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	8360	#define CAN_F2R2_FB19_Pos (19U)
hudakz	0:a04710facbb6	8361	#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	8362	#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	8363	#define CAN_F2R2_FB20_Pos (20U)
hudakz	0:a04710facbb6	8364	#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	8365	#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	8366	#define CAN_F2R2_FB21_Pos (21U)
hudakz	0:a04710facbb6	8367	#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	8368	#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	8369	#define CAN_F2R2_FB22_Pos (22U)
hudakz	0:a04710facbb6	8370	#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	8371	#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	8372	#define CAN_F2R2_FB23_Pos (23U)
hudakz	0:a04710facbb6	8373	#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	8374	#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	8375	#define CAN_F2R2_FB24_Pos (24U)
hudakz	0:a04710facbb6	8376	#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	8377	#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	8378	#define CAN_F2R2_FB25_Pos (25U)
hudakz	0:a04710facbb6	8379	#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	8380	#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	8381	#define CAN_F2R2_FB26_Pos (26U)
hudakz	0:a04710facbb6	8382	#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	8383	#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	8384	#define CAN_F2R2_FB27_Pos (27U)
hudakz	0:a04710facbb6	8385	#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	8386	#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	8387	#define CAN_F2R2_FB28_Pos (28U)
hudakz	0:a04710facbb6	8388	#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	8389	#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	8390	#define CAN_F2R2_FB29_Pos (29U)
hudakz	0:a04710facbb6	8391	#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	8392	#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	8393	#define CAN_F2R2_FB30_Pos (30U)
hudakz	0:a04710facbb6	8394	#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	8395	#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	8396	#define CAN_F2R2_FB31_Pos (31U)
hudakz	0:a04710facbb6	8397	#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	8398	#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	8399
hudakz	0:a04710facbb6	8400	/***************** Bit definition for CAN_F3R2 register *****************/
hudakz	0:a04710facbb6	8401	#define CAN_F3R2_FB0_Pos (0U)
hudakz	0:a04710facbb6	8402	#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	8403	#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	8404	#define CAN_F3R2_FB1_Pos (1U)
hudakz	0:a04710facbb6	8405	#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	8406	#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	8407	#define CAN_F3R2_FB2_Pos (2U)
hudakz	0:a04710facbb6	8408	#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	8409	#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	8410	#define CAN_F3R2_FB3_Pos (3U)
hudakz	0:a04710facbb6	8411	#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	8412	#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	8413	#define CAN_F3R2_FB4_Pos (4U)
hudakz	0:a04710facbb6	8414	#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	8415	#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	8416	#define CAN_F3R2_FB5_Pos (5U)
hudakz	0:a04710facbb6	8417	#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	8418	#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	8419	#define CAN_F3R2_FB6_Pos (6U)
hudakz	0:a04710facbb6	8420	#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	8421	#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	8422	#define CAN_F3R2_FB7_Pos (7U)
hudakz	0:a04710facbb6	8423	#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	8424	#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	8425	#define CAN_F3R2_FB8_Pos (8U)
hudakz	0:a04710facbb6	8426	#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	8427	#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	8428	#define CAN_F3R2_FB9_Pos (9U)
hudakz	0:a04710facbb6	8429	#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	8430	#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	8431	#define CAN_F3R2_FB10_Pos (10U)
hudakz	0:a04710facbb6	8432	#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	8433	#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	8434	#define CAN_F3R2_FB11_Pos (11U)
hudakz	0:a04710facbb6	8435	#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	8436	#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	8437	#define CAN_F3R2_FB12_Pos (12U)
hudakz	0:a04710facbb6	8438	#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	8439	#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	8440	#define CAN_F3R2_FB13_Pos (13U)
hudakz	0:a04710facbb6	8441	#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	8442	#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	8443	#define CAN_F3R2_FB14_Pos (14U)
hudakz	0:a04710facbb6	8444	#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	8445	#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	8446	#define CAN_F3R2_FB15_Pos (15U)
hudakz	0:a04710facbb6	8447	#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	8448	#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	8449	#define CAN_F3R2_FB16_Pos (16U)
hudakz	0:a04710facbb6	8450	#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	8451	#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	8452	#define CAN_F3R2_FB17_Pos (17U)
hudakz	0:a04710facbb6	8453	#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	8454	#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	8455	#define CAN_F3R2_FB18_Pos (18U)
hudakz	0:a04710facbb6	8456	#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	8457	#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	8458	#define CAN_F3R2_FB19_Pos (19U)
hudakz	0:a04710facbb6	8459	#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	8460	#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	8461	#define CAN_F3R2_FB20_Pos (20U)
hudakz	0:a04710facbb6	8462	#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	8463	#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	8464	#define CAN_F3R2_FB21_Pos (21U)
hudakz	0:a04710facbb6	8465	#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	8466	#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	8467	#define CAN_F3R2_FB22_Pos (22U)
hudakz	0:a04710facbb6	8468	#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	8469	#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	8470	#define CAN_F3R2_FB23_Pos (23U)
hudakz	0:a04710facbb6	8471	#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	8472	#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	8473	#define CAN_F3R2_FB24_Pos (24U)
hudakz	0:a04710facbb6	8474	#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	8475	#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	8476	#define CAN_F3R2_FB25_Pos (25U)
hudakz	0:a04710facbb6	8477	#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	8478	#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	8479	#define CAN_F3R2_FB26_Pos (26U)
hudakz	0:a04710facbb6	8480	#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	8481	#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	8482	#define CAN_F3R2_FB27_Pos (27U)
hudakz	0:a04710facbb6	8483	#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	8484	#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	8485	#define CAN_F3R2_FB28_Pos (28U)
hudakz	0:a04710facbb6	8486	#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	8487	#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	8488	#define CAN_F3R2_FB29_Pos (29U)
hudakz	0:a04710facbb6	8489	#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	8490	#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	8491	#define CAN_F3R2_FB30_Pos (30U)
hudakz	0:a04710facbb6	8492	#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	8493	#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	8494	#define CAN_F3R2_FB31_Pos (31U)
hudakz	0:a04710facbb6	8495	#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	8496	#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	8497
hudakz	0:a04710facbb6	8498	/***************** Bit definition for CAN_F4R2 register *****************/
hudakz	0:a04710facbb6	8499	#define CAN_F4R2_FB0_Pos (0U)
hudakz	0:a04710facbb6	8500	#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	8501	#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	8502	#define CAN_F4R2_FB1_Pos (1U)
hudakz	0:a04710facbb6	8503	#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	8504	#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	8505	#define CAN_F4R2_FB2_Pos (2U)
hudakz	0:a04710facbb6	8506	#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	8507	#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	8508	#define CAN_F4R2_FB3_Pos (3U)
hudakz	0:a04710facbb6	8509	#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	8510	#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	8511	#define CAN_F4R2_FB4_Pos (4U)
hudakz	0:a04710facbb6	8512	#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	8513	#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	8514	#define CAN_F4R2_FB5_Pos (5U)
hudakz	0:a04710facbb6	8515	#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	8516	#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	8517	#define CAN_F4R2_FB6_Pos (6U)
hudakz	0:a04710facbb6	8518	#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	8519	#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	8520	#define CAN_F4R2_FB7_Pos (7U)
hudakz	0:a04710facbb6	8521	#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	8522	#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	8523	#define CAN_F4R2_FB8_Pos (8U)
hudakz	0:a04710facbb6	8524	#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	8525	#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	8526	#define CAN_F4R2_FB9_Pos (9U)
hudakz	0:a04710facbb6	8527	#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	8528	#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	8529	#define CAN_F4R2_FB10_Pos (10U)
hudakz	0:a04710facbb6	8530	#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	8531	#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	8532	#define CAN_F4R2_FB11_Pos (11U)
hudakz	0:a04710facbb6	8533	#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	8534	#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	8535	#define CAN_F4R2_FB12_Pos (12U)
hudakz	0:a04710facbb6	8536	#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	8537	#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	8538	#define CAN_F4R2_FB13_Pos (13U)
hudakz	0:a04710facbb6	8539	#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	8540	#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	8541	#define CAN_F4R2_FB14_Pos (14U)
hudakz	0:a04710facbb6	8542	#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	8543	#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	8544	#define CAN_F4R2_FB15_Pos (15U)
hudakz	0:a04710facbb6	8545	#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	8546	#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	8547	#define CAN_F4R2_FB16_Pos (16U)
hudakz	0:a04710facbb6	8548	#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	8549	#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	8550	#define CAN_F4R2_FB17_Pos (17U)
hudakz	0:a04710facbb6	8551	#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	8552	#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	8553	#define CAN_F4R2_FB18_Pos (18U)
hudakz	0:a04710facbb6	8554	#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	8555	#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	8556	#define CAN_F4R2_FB19_Pos (19U)
hudakz	0:a04710facbb6	8557	#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	8558	#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	8559	#define CAN_F4R2_FB20_Pos (20U)
hudakz	0:a04710facbb6	8560	#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	8561	#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	8562	#define CAN_F4R2_FB21_Pos (21U)
hudakz	0:a04710facbb6	8563	#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	8564	#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	8565	#define CAN_F4R2_FB22_Pos (22U)
hudakz	0:a04710facbb6	8566	#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	8567	#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	8568	#define CAN_F4R2_FB23_Pos (23U)
hudakz	0:a04710facbb6	8569	#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	8570	#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	8571	#define CAN_F4R2_FB24_Pos (24U)
hudakz	0:a04710facbb6	8572	#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	8573	#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	8574	#define CAN_F4R2_FB25_Pos (25U)
hudakz	0:a04710facbb6	8575	#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	8576	#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	8577	#define CAN_F4R2_FB26_Pos (26U)
hudakz	0:a04710facbb6	8578	#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	8579	#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	8580	#define CAN_F4R2_FB27_Pos (27U)
hudakz	0:a04710facbb6	8581	#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	8582	#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	8583	#define CAN_F4R2_FB28_Pos (28U)
hudakz	0:a04710facbb6	8584	#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	8585	#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	8586	#define CAN_F4R2_FB29_Pos (29U)
hudakz	0:a04710facbb6	8587	#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	8588	#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	8589	#define CAN_F4R2_FB30_Pos (30U)
hudakz	0:a04710facbb6	8590	#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	8591	#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	8592	#define CAN_F4R2_FB31_Pos (31U)
hudakz	0:a04710facbb6	8593	#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	8594	#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	8595
hudakz	0:a04710facbb6	8596	/***************** Bit definition for CAN_F5R2 register *****************/
hudakz	0:a04710facbb6	8597	#define CAN_F5R2_FB0_Pos (0U)
hudakz	0:a04710facbb6	8598	#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	8599	#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	8600	#define CAN_F5R2_FB1_Pos (1U)
hudakz	0:a04710facbb6	8601	#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	8602	#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	8603	#define CAN_F5R2_FB2_Pos (2U)
hudakz	0:a04710facbb6	8604	#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	8605	#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	8606	#define CAN_F5R2_FB3_Pos (3U)
hudakz	0:a04710facbb6	8607	#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	8608	#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	8609	#define CAN_F5R2_FB4_Pos (4U)
hudakz	0:a04710facbb6	8610	#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	8611	#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	8612	#define CAN_F5R2_FB5_Pos (5U)
hudakz	0:a04710facbb6	8613	#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	8614	#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	8615	#define CAN_F5R2_FB6_Pos (6U)
hudakz	0:a04710facbb6	8616	#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	8617	#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	8618	#define CAN_F5R2_FB7_Pos (7U)
hudakz	0:a04710facbb6	8619	#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	8620	#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	8621	#define CAN_F5R2_FB8_Pos (8U)
hudakz	0:a04710facbb6	8622	#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	8623	#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	8624	#define CAN_F5R2_FB9_Pos (9U)
hudakz	0:a04710facbb6	8625	#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	8626	#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	8627	#define CAN_F5R2_FB10_Pos (10U)
hudakz	0:a04710facbb6	8628	#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	8629	#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	8630	#define CAN_F5R2_FB11_Pos (11U)
hudakz	0:a04710facbb6	8631	#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	8632	#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	8633	#define CAN_F5R2_FB12_Pos (12U)
hudakz	0:a04710facbb6	8634	#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	8635	#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	8636	#define CAN_F5R2_FB13_Pos (13U)
hudakz	0:a04710facbb6	8637	#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	8638	#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	8639	#define CAN_F5R2_FB14_Pos (14U)
hudakz	0:a04710facbb6	8640	#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	8641	#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	8642	#define CAN_F5R2_FB15_Pos (15U)
hudakz	0:a04710facbb6	8643	#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	8644	#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	8645	#define CAN_F5R2_FB16_Pos (16U)
hudakz	0:a04710facbb6	8646	#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	8647	#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	8648	#define CAN_F5R2_FB17_Pos (17U)
hudakz	0:a04710facbb6	8649	#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	8650	#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	8651	#define CAN_F5R2_FB18_Pos (18U)
hudakz	0:a04710facbb6	8652	#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	8653	#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	8654	#define CAN_F5R2_FB19_Pos (19U)
hudakz	0:a04710facbb6	8655	#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	8656	#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	8657	#define CAN_F5R2_FB20_Pos (20U)
hudakz	0:a04710facbb6	8658	#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	8659	#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	8660	#define CAN_F5R2_FB21_Pos (21U)
hudakz	0:a04710facbb6	8661	#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	8662	#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	8663	#define CAN_F5R2_FB22_Pos (22U)
hudakz	0:a04710facbb6	8664	#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	8665	#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	8666	#define CAN_F5R2_FB23_Pos (23U)
hudakz	0:a04710facbb6	8667	#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	8668	#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	8669	#define CAN_F5R2_FB24_Pos (24U)
hudakz	0:a04710facbb6	8670	#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	8671	#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	8672	#define CAN_F5R2_FB25_Pos (25U)
hudakz	0:a04710facbb6	8673	#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	8674	#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	8675	#define CAN_F5R2_FB26_Pos (26U)
hudakz	0:a04710facbb6	8676	#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	8677	#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	8678	#define CAN_F5R2_FB27_Pos (27U)
hudakz	0:a04710facbb6	8679	#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	8680	#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	8681	#define CAN_F5R2_FB28_Pos (28U)
hudakz	0:a04710facbb6	8682	#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	8683	#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	8684	#define CAN_F5R2_FB29_Pos (29U)
hudakz	0:a04710facbb6	8685	#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	8686	#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	8687	#define CAN_F5R2_FB30_Pos (30U)
hudakz	0:a04710facbb6	8688	#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	8689	#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	8690	#define CAN_F5R2_FB31_Pos (31U)
hudakz	0:a04710facbb6	8691	#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	8692	#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	8693
hudakz	0:a04710facbb6	8694	/***************** Bit definition for CAN_F6R2 register *****************/
hudakz	0:a04710facbb6	8695	#define CAN_F6R2_FB0_Pos (0U)
hudakz	0:a04710facbb6	8696	#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	8697	#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	8698	#define CAN_F6R2_FB1_Pos (1U)
hudakz	0:a04710facbb6	8699	#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	8700	#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	8701	#define CAN_F6R2_FB2_Pos (2U)
hudakz	0:a04710facbb6	8702	#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	8703	#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	8704	#define CAN_F6R2_FB3_Pos (3U)
hudakz	0:a04710facbb6	8705	#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	8706	#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	8707	#define CAN_F6R2_FB4_Pos (4U)
hudakz	0:a04710facbb6	8708	#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	8709	#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	8710	#define CAN_F6R2_FB5_Pos (5U)
hudakz	0:a04710facbb6	8711	#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	8712	#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	8713	#define CAN_F6R2_FB6_Pos (6U)
hudakz	0:a04710facbb6	8714	#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	8715	#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	8716	#define CAN_F6R2_FB7_Pos (7U)
hudakz	0:a04710facbb6	8717	#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	8718	#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	8719	#define CAN_F6R2_FB8_Pos (8U)
hudakz	0:a04710facbb6	8720	#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	8721	#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	8722	#define CAN_F6R2_FB9_Pos (9U)
hudakz	0:a04710facbb6	8723	#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	8724	#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	8725	#define CAN_F6R2_FB10_Pos (10U)
hudakz	0:a04710facbb6	8726	#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	8727	#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	8728	#define CAN_F6R2_FB11_Pos (11U)
hudakz	0:a04710facbb6	8729	#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	8730	#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	8731	#define CAN_F6R2_FB12_Pos (12U)
hudakz	0:a04710facbb6	8732	#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	8733	#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	8734	#define CAN_F6R2_FB13_Pos (13U)
hudakz	0:a04710facbb6	8735	#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	8736	#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	8737	#define CAN_F6R2_FB14_Pos (14U)
hudakz	0:a04710facbb6	8738	#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	8739	#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	8740	#define CAN_F6R2_FB15_Pos (15U)
hudakz	0:a04710facbb6	8741	#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	8742	#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	8743	#define CAN_F6R2_FB16_Pos (16U)
hudakz	0:a04710facbb6	8744	#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	8745	#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	8746	#define CAN_F6R2_FB17_Pos (17U)
hudakz	0:a04710facbb6	8747	#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	8748	#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	8749	#define CAN_F6R2_FB18_Pos (18U)
hudakz	0:a04710facbb6	8750	#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	8751	#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	8752	#define CAN_F6R2_FB19_Pos (19U)
hudakz	0:a04710facbb6	8753	#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	8754	#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	8755	#define CAN_F6R2_FB20_Pos (20U)
hudakz	0:a04710facbb6	8756	#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	8757	#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	8758	#define CAN_F6R2_FB21_Pos (21U)
hudakz	0:a04710facbb6	8759	#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	8760	#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	8761	#define CAN_F6R2_FB22_Pos (22U)
hudakz	0:a04710facbb6	8762	#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	8763	#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	8764	#define CAN_F6R2_FB23_Pos (23U)
hudakz	0:a04710facbb6	8765	#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	8766	#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	8767	#define CAN_F6R2_FB24_Pos (24U)
hudakz	0:a04710facbb6	8768	#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	8769	#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	8770	#define CAN_F6R2_FB25_Pos (25U)
hudakz	0:a04710facbb6	8771	#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	8772	#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	8773	#define CAN_F6R2_FB26_Pos (26U)
hudakz	0:a04710facbb6	8774	#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	8775	#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	8776	#define CAN_F6R2_FB27_Pos (27U)
hudakz	0:a04710facbb6	8777	#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	8778	#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	8779	#define CAN_F6R2_FB28_Pos (28U)
hudakz	0:a04710facbb6	8780	#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	8781	#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	8782	#define CAN_F6R2_FB29_Pos (29U)
hudakz	0:a04710facbb6	8783	#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	8784	#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	8785	#define CAN_F6R2_FB30_Pos (30U)
hudakz	0:a04710facbb6	8786	#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	8787	#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	8788	#define CAN_F6R2_FB31_Pos (31U)
hudakz	0:a04710facbb6	8789	#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	8790	#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	8791
hudakz	0:a04710facbb6	8792	/***************** Bit definition for CAN_F7R2 register *****************/
hudakz	0:a04710facbb6	8793	#define CAN_F7R2_FB0_Pos (0U)
hudakz	0:a04710facbb6	8794	#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	8795	#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	8796	#define CAN_F7R2_FB1_Pos (1U)
hudakz	0:a04710facbb6	8797	#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	8798	#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	8799	#define CAN_F7R2_FB2_Pos (2U)
hudakz	0:a04710facbb6	8800	#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	8801	#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	8802	#define CAN_F7R2_FB3_Pos (3U)
hudakz	0:a04710facbb6	8803	#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	8804	#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	8805	#define CAN_F7R2_FB4_Pos (4U)
hudakz	0:a04710facbb6	8806	#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	8807	#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	8808	#define CAN_F7R2_FB5_Pos (5U)
hudakz	0:a04710facbb6	8809	#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	8810	#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	8811	#define CAN_F7R2_FB6_Pos (6U)
hudakz	0:a04710facbb6	8812	#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	8813	#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	8814	#define CAN_F7R2_FB7_Pos (7U)
hudakz	0:a04710facbb6	8815	#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	8816	#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	8817	#define CAN_F7R2_FB8_Pos (8U)
hudakz	0:a04710facbb6	8818	#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	8819	#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	8820	#define CAN_F7R2_FB9_Pos (9U)
hudakz	0:a04710facbb6	8821	#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	8822	#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	8823	#define CAN_F7R2_FB10_Pos (10U)
hudakz	0:a04710facbb6	8824	#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	8825	#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	8826	#define CAN_F7R2_FB11_Pos (11U)
hudakz	0:a04710facbb6	8827	#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	8828	#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	8829	#define CAN_F7R2_FB12_Pos (12U)
hudakz	0:a04710facbb6	8830	#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	8831	#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	8832	#define CAN_F7R2_FB13_Pos (13U)
hudakz	0:a04710facbb6	8833	#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	8834	#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	8835	#define CAN_F7R2_FB14_Pos (14U)
hudakz	0:a04710facbb6	8836	#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	8837	#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	8838	#define CAN_F7R2_FB15_Pos (15U)
hudakz	0:a04710facbb6	8839	#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	8840	#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	8841	#define CAN_F7R2_FB16_Pos (16U)
hudakz	0:a04710facbb6	8842	#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	8843	#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	8844	#define CAN_F7R2_FB17_Pos (17U)
hudakz	0:a04710facbb6	8845	#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	8846	#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	8847	#define CAN_F7R2_FB18_Pos (18U)
hudakz	0:a04710facbb6	8848	#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	8849	#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	8850	#define CAN_F7R2_FB19_Pos (19U)
hudakz	0:a04710facbb6	8851	#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	8852	#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	8853	#define CAN_F7R2_FB20_Pos (20U)
hudakz	0:a04710facbb6	8854	#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	8855	#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	8856	#define CAN_F7R2_FB21_Pos (21U)
hudakz	0:a04710facbb6	8857	#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	8858	#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	8859	#define CAN_F7R2_FB22_Pos (22U)
hudakz	0:a04710facbb6	8860	#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	8861	#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	8862	#define CAN_F7R2_FB23_Pos (23U)
hudakz	0:a04710facbb6	8863	#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	8864	#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	8865	#define CAN_F7R2_FB24_Pos (24U)
hudakz	0:a04710facbb6	8866	#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	8867	#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	8868	#define CAN_F7R2_FB25_Pos (25U)
hudakz	0:a04710facbb6	8869	#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	8870	#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	8871	#define CAN_F7R2_FB26_Pos (26U)
hudakz	0:a04710facbb6	8872	#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	8873	#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	8874	#define CAN_F7R2_FB27_Pos (27U)
hudakz	0:a04710facbb6	8875	#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	8876	#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	8877	#define CAN_F7R2_FB28_Pos (28U)
hudakz	0:a04710facbb6	8878	#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	8879	#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	8880	#define CAN_F7R2_FB29_Pos (29U)
hudakz	0:a04710facbb6	8881	#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	8882	#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	8883	#define CAN_F7R2_FB30_Pos (30U)
hudakz	0:a04710facbb6	8884	#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	8885	#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	8886	#define CAN_F7R2_FB31_Pos (31U)
hudakz	0:a04710facbb6	8887	#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	8888	#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	8889
hudakz	0:a04710facbb6	8890	/***************** Bit definition for CAN_F8R2 register *****************/
hudakz	0:a04710facbb6	8891	#define CAN_F8R2_FB0_Pos (0U)
hudakz	0:a04710facbb6	8892	#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	8893	#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	8894	#define CAN_F8R2_FB1_Pos (1U)
hudakz	0:a04710facbb6	8895	#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	8896	#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	8897	#define CAN_F8R2_FB2_Pos (2U)
hudakz	0:a04710facbb6	8898	#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	8899	#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	8900	#define CAN_F8R2_FB3_Pos (3U)
hudakz	0:a04710facbb6	8901	#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	8902	#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	8903	#define CAN_F8R2_FB4_Pos (4U)
hudakz	0:a04710facbb6	8904	#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	8905	#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	8906	#define CAN_F8R2_FB5_Pos (5U)
hudakz	0:a04710facbb6	8907	#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	8908	#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	8909	#define CAN_F8R2_FB6_Pos (6U)
hudakz	0:a04710facbb6	8910	#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	8911	#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	8912	#define CAN_F8R2_FB7_Pos (7U)
hudakz	0:a04710facbb6	8913	#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	8914	#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	8915	#define CAN_F8R2_FB8_Pos (8U)
hudakz	0:a04710facbb6	8916	#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	8917	#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	8918	#define CAN_F8R2_FB9_Pos (9U)
hudakz	0:a04710facbb6	8919	#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	8920	#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	8921	#define CAN_F8R2_FB10_Pos (10U)
hudakz	0:a04710facbb6	8922	#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	8923	#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	8924	#define CAN_F8R2_FB11_Pos (11U)
hudakz	0:a04710facbb6	8925	#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	8926	#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	8927	#define CAN_F8R2_FB12_Pos (12U)
hudakz	0:a04710facbb6	8928	#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	8929	#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	8930	#define CAN_F8R2_FB13_Pos (13U)
hudakz	0:a04710facbb6	8931	#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	8932	#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	8933	#define CAN_F8R2_FB14_Pos (14U)
hudakz	0:a04710facbb6	8934	#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	8935	#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	8936	#define CAN_F8R2_FB15_Pos (15U)
hudakz	0:a04710facbb6	8937	#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	8938	#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	8939	#define CAN_F8R2_FB16_Pos (16U)
hudakz	0:a04710facbb6	8940	#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	8941	#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	8942	#define CAN_F8R2_FB17_Pos (17U)
hudakz	0:a04710facbb6	8943	#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	8944	#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	8945	#define CAN_F8R2_FB18_Pos (18U)
hudakz	0:a04710facbb6	8946	#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	8947	#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	8948	#define CAN_F8R2_FB19_Pos (19U)
hudakz	0:a04710facbb6	8949	#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	8950	#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	8951	#define CAN_F8R2_FB20_Pos (20U)
hudakz	0:a04710facbb6	8952	#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	8953	#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	8954	#define CAN_F8R2_FB21_Pos (21U)
hudakz	0:a04710facbb6	8955	#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	8956	#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	8957	#define CAN_F8R2_FB22_Pos (22U)
hudakz	0:a04710facbb6	8958	#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	8959	#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	8960	#define CAN_F8R2_FB23_Pos (23U)
hudakz	0:a04710facbb6	8961	#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	8962	#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	8963	#define CAN_F8R2_FB24_Pos (24U)
hudakz	0:a04710facbb6	8964	#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	8965	#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	8966	#define CAN_F8R2_FB25_Pos (25U)
hudakz	0:a04710facbb6	8967	#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	8968	#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	8969	#define CAN_F8R2_FB26_Pos (26U)
hudakz	0:a04710facbb6	8970	#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	8971	#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	8972	#define CAN_F8R2_FB27_Pos (27U)
hudakz	0:a04710facbb6	8973	#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	8974	#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	8975	#define CAN_F8R2_FB28_Pos (28U)
hudakz	0:a04710facbb6	8976	#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	8977	#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	8978	#define CAN_F8R2_FB29_Pos (29U)
hudakz	0:a04710facbb6	8979	#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	8980	#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	8981	#define CAN_F8R2_FB30_Pos (30U)
hudakz	0:a04710facbb6	8982	#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	8983	#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	8984	#define CAN_F8R2_FB31_Pos (31U)
hudakz	0:a04710facbb6	8985	#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	8986	#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	8987
hudakz	0:a04710facbb6	8988	/***************** Bit definition for CAN_F9R2 register *****************/
hudakz	0:a04710facbb6	8989	#define CAN_F9R2_FB0_Pos (0U)
hudakz	0:a04710facbb6	8990	#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	8991	#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	8992	#define CAN_F9R2_FB1_Pos (1U)
hudakz	0:a04710facbb6	8993	#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	8994	#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	8995	#define CAN_F9R2_FB2_Pos (2U)
hudakz	0:a04710facbb6	8996	#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	8997	#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	8998	#define CAN_F9R2_FB3_Pos (3U)
hudakz	0:a04710facbb6	8999	#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	9000	#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	9001	#define CAN_F9R2_FB4_Pos (4U)
hudakz	0:a04710facbb6	9002	#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	9003	#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	9004	#define CAN_F9R2_FB5_Pos (5U)
hudakz	0:a04710facbb6	9005	#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	9006	#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	9007	#define CAN_F9R2_FB6_Pos (6U)
hudakz	0:a04710facbb6	9008	#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	9009	#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	9010	#define CAN_F9R2_FB7_Pos (7U)
hudakz	0:a04710facbb6	9011	#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	9012	#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	9013	#define CAN_F9R2_FB8_Pos (8U)
hudakz	0:a04710facbb6	9014	#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	9015	#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	9016	#define CAN_F9R2_FB9_Pos (9U)
hudakz	0:a04710facbb6	9017	#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	9018	#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	9019	#define CAN_F9R2_FB10_Pos (10U)
hudakz	0:a04710facbb6	9020	#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	9021	#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	9022	#define CAN_F9R2_FB11_Pos (11U)
hudakz	0:a04710facbb6	9023	#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	9024	#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	9025	#define CAN_F9R2_FB12_Pos (12U)
hudakz	0:a04710facbb6	9026	#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	9027	#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	9028	#define CAN_F9R2_FB13_Pos (13U)
hudakz	0:a04710facbb6	9029	#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	9030	#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	9031	#define CAN_F9R2_FB14_Pos (14U)
hudakz	0:a04710facbb6	9032	#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	9033	#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	9034	#define CAN_F9R2_FB15_Pos (15U)
hudakz	0:a04710facbb6	9035	#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	9036	#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	9037	#define CAN_F9R2_FB16_Pos (16U)
hudakz	0:a04710facbb6	9038	#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	9039	#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	9040	#define CAN_F9R2_FB17_Pos (17U)
hudakz	0:a04710facbb6	9041	#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	9042	#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	9043	#define CAN_F9R2_FB18_Pos (18U)
hudakz	0:a04710facbb6	9044	#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	9045	#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	9046	#define CAN_F9R2_FB19_Pos (19U)
hudakz	0:a04710facbb6	9047	#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	9048	#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	9049	#define CAN_F9R2_FB20_Pos (20U)
hudakz	0:a04710facbb6	9050	#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	9051	#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	9052	#define CAN_F9R2_FB21_Pos (21U)
hudakz	0:a04710facbb6	9053	#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	9054	#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	9055	#define CAN_F9R2_FB22_Pos (22U)
hudakz	0:a04710facbb6	9056	#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	9057	#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	9058	#define CAN_F9R2_FB23_Pos (23U)
hudakz	0:a04710facbb6	9059	#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	9060	#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	9061	#define CAN_F9R2_FB24_Pos (24U)
hudakz	0:a04710facbb6	9062	#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	9063	#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	9064	#define CAN_F9R2_FB25_Pos (25U)
hudakz	0:a04710facbb6	9065	#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	9066	#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	9067	#define CAN_F9R2_FB26_Pos (26U)
hudakz	0:a04710facbb6	9068	#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	9069	#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	9070	#define CAN_F9R2_FB27_Pos (27U)
hudakz	0:a04710facbb6	9071	#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	9072	#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	9073	#define CAN_F9R2_FB28_Pos (28U)
hudakz	0:a04710facbb6	9074	#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	9075	#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	9076	#define CAN_F9R2_FB29_Pos (29U)
hudakz	0:a04710facbb6	9077	#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	9078	#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	9079	#define CAN_F9R2_FB30_Pos (30U)
hudakz	0:a04710facbb6	9080	#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	9081	#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	9082	#define CAN_F9R2_FB31_Pos (31U)
hudakz	0:a04710facbb6	9083	#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	9084	#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	9085
hudakz	0:a04710facbb6	9086	/***************** Bit definition for CAN_F10R2 register ****************/
hudakz	0:a04710facbb6	9087	#define CAN_F10R2_FB0_Pos (0U)
hudakz	0:a04710facbb6	9088	#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	9089	#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	9090	#define CAN_F10R2_FB1_Pos (1U)
hudakz	0:a04710facbb6	9091	#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	9092	#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	9093	#define CAN_F10R2_FB2_Pos (2U)
hudakz	0:a04710facbb6	9094	#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	9095	#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	9096	#define CAN_F10R2_FB3_Pos (3U)
hudakz	0:a04710facbb6	9097	#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	9098	#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	9099	#define CAN_F10R2_FB4_Pos (4U)
hudakz	0:a04710facbb6	9100	#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	9101	#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	9102	#define CAN_F10R2_FB5_Pos (5U)
hudakz	0:a04710facbb6	9103	#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	9104	#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	9105	#define CAN_F10R2_FB6_Pos (6U)
hudakz	0:a04710facbb6	9106	#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	9107	#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	9108	#define CAN_F10R2_FB7_Pos (7U)
hudakz	0:a04710facbb6	9109	#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	9110	#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	9111	#define CAN_F10R2_FB8_Pos (8U)
hudakz	0:a04710facbb6	9112	#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	9113	#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	9114	#define CAN_F10R2_FB9_Pos (9U)
hudakz	0:a04710facbb6	9115	#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	9116	#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	9117	#define CAN_F10R2_FB10_Pos (10U)
hudakz	0:a04710facbb6	9118	#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	9119	#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	9120	#define CAN_F10R2_FB11_Pos (11U)
hudakz	0:a04710facbb6	9121	#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	9122	#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	9123	#define CAN_F10R2_FB12_Pos (12U)
hudakz	0:a04710facbb6	9124	#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	9125	#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	9126	#define CAN_F10R2_FB13_Pos (13U)
hudakz	0:a04710facbb6	9127	#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	9128	#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	9129	#define CAN_F10R2_FB14_Pos (14U)
hudakz	0:a04710facbb6	9130	#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	9131	#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	9132	#define CAN_F10R2_FB15_Pos (15U)
hudakz	0:a04710facbb6	9133	#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	9134	#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	9135	#define CAN_F10R2_FB16_Pos (16U)
hudakz	0:a04710facbb6	9136	#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	9137	#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	9138	#define CAN_F10R2_FB17_Pos (17U)
hudakz	0:a04710facbb6	9139	#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	9140	#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	9141	#define CAN_F10R2_FB18_Pos (18U)
hudakz	0:a04710facbb6	9142	#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	9143	#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	9144	#define CAN_F10R2_FB19_Pos (19U)
hudakz	0:a04710facbb6	9145	#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	9146	#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	9147	#define CAN_F10R2_FB20_Pos (20U)
hudakz	0:a04710facbb6	9148	#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	9149	#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	9150	#define CAN_F10R2_FB21_Pos (21U)
hudakz	0:a04710facbb6	9151	#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	9152	#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	9153	#define CAN_F10R2_FB22_Pos (22U)
hudakz	0:a04710facbb6	9154	#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	9155	#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	9156	#define CAN_F10R2_FB23_Pos (23U)
hudakz	0:a04710facbb6	9157	#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	9158	#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	9159	#define CAN_F10R2_FB24_Pos (24U)
hudakz	0:a04710facbb6	9160	#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	9161	#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	9162	#define CAN_F10R2_FB25_Pos (25U)
hudakz	0:a04710facbb6	9163	#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	9164	#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	9165	#define CAN_F10R2_FB26_Pos (26U)
hudakz	0:a04710facbb6	9166	#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	9167	#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	9168	#define CAN_F10R2_FB27_Pos (27U)
hudakz	0:a04710facbb6	9169	#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	9170	#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	9171	#define CAN_F10R2_FB28_Pos (28U)
hudakz	0:a04710facbb6	9172	#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	9173	#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	9174	#define CAN_F10R2_FB29_Pos (29U)
hudakz	0:a04710facbb6	9175	#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	9176	#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	9177	#define CAN_F10R2_FB30_Pos (30U)
hudakz	0:a04710facbb6	9178	#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	9179	#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	9180	#define CAN_F10R2_FB31_Pos (31U)
hudakz	0:a04710facbb6	9181	#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	9182	#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	9183
hudakz	0:a04710facbb6	9184	/***************** Bit definition for CAN_F11R2 register ****************/
hudakz	0:a04710facbb6	9185	#define CAN_F11R2_FB0_Pos (0U)
hudakz	0:a04710facbb6	9186	#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	9187	#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	9188	#define CAN_F11R2_FB1_Pos (1U)
hudakz	0:a04710facbb6	9189	#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	9190	#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	9191	#define CAN_F11R2_FB2_Pos (2U)
hudakz	0:a04710facbb6	9192	#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	9193	#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	9194	#define CAN_F11R2_FB3_Pos (3U)
hudakz	0:a04710facbb6	9195	#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	9196	#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	9197	#define CAN_F11R2_FB4_Pos (4U)
hudakz	0:a04710facbb6	9198	#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	9199	#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	9200	#define CAN_F11R2_FB5_Pos (5U)
hudakz	0:a04710facbb6	9201	#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	9202	#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	9203	#define CAN_F11R2_FB6_Pos (6U)
hudakz	0:a04710facbb6	9204	#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	9205	#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	9206	#define CAN_F11R2_FB7_Pos (7U)
hudakz	0:a04710facbb6	9207	#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	9208	#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	9209	#define CAN_F11R2_FB8_Pos (8U)
hudakz	0:a04710facbb6	9210	#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	9211	#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	9212	#define CAN_F11R2_FB9_Pos (9U)
hudakz	0:a04710facbb6	9213	#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	9214	#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	9215	#define CAN_F11R2_FB10_Pos (10U)
hudakz	0:a04710facbb6	9216	#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	9217	#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	9218	#define CAN_F11R2_FB11_Pos (11U)
hudakz	0:a04710facbb6	9219	#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	9220	#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	9221	#define CAN_F11R2_FB12_Pos (12U)
hudakz	0:a04710facbb6	9222	#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	9223	#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	9224	#define CAN_F11R2_FB13_Pos (13U)
hudakz	0:a04710facbb6	9225	#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	9226	#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	9227	#define CAN_F11R2_FB14_Pos (14U)
hudakz	0:a04710facbb6	9228	#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	9229	#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	9230	#define CAN_F11R2_FB15_Pos (15U)
hudakz	0:a04710facbb6	9231	#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	9232	#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	9233	#define CAN_F11R2_FB16_Pos (16U)
hudakz	0:a04710facbb6	9234	#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	9235	#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	9236	#define CAN_F11R2_FB17_Pos (17U)
hudakz	0:a04710facbb6	9237	#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	9238	#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	9239	#define CAN_F11R2_FB18_Pos (18U)
hudakz	0:a04710facbb6	9240	#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	9241	#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	9242	#define CAN_F11R2_FB19_Pos (19U)
hudakz	0:a04710facbb6	9243	#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	9244	#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	9245	#define CAN_F11R2_FB20_Pos (20U)
hudakz	0:a04710facbb6	9246	#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	9247	#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	9248	#define CAN_F11R2_FB21_Pos (21U)
hudakz	0:a04710facbb6	9249	#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	9250	#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	9251	#define CAN_F11R2_FB22_Pos (22U)
hudakz	0:a04710facbb6	9252	#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	9253	#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	9254	#define CAN_F11R2_FB23_Pos (23U)
hudakz	0:a04710facbb6	9255	#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	9256	#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	9257	#define CAN_F11R2_FB24_Pos (24U)
hudakz	0:a04710facbb6	9258	#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	9259	#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	9260	#define CAN_F11R2_FB25_Pos (25U)
hudakz	0:a04710facbb6	9261	#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	9262	#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	9263	#define CAN_F11R2_FB26_Pos (26U)
hudakz	0:a04710facbb6	9264	#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	9265	#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	9266	#define CAN_F11R2_FB27_Pos (27U)
hudakz	0:a04710facbb6	9267	#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	9268	#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	9269	#define CAN_F11R2_FB28_Pos (28U)
hudakz	0:a04710facbb6	9270	#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	9271	#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	9272	#define CAN_F11R2_FB29_Pos (29U)
hudakz	0:a04710facbb6	9273	#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	9274	#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	9275	#define CAN_F11R2_FB30_Pos (30U)
hudakz	0:a04710facbb6	9276	#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	9277	#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	9278	#define CAN_F11R2_FB31_Pos (31U)
hudakz	0:a04710facbb6	9279	#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	9280	#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	9281
hudakz	0:a04710facbb6	9282	/***************** Bit definition for CAN_F12R2 register ****************/
hudakz	0:a04710facbb6	9283	#define CAN_F12R2_FB0_Pos (0U)
hudakz	0:a04710facbb6	9284	#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	9285	#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	9286	#define CAN_F12R2_FB1_Pos (1U)
hudakz	0:a04710facbb6	9287	#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	9288	#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	9289	#define CAN_F12R2_FB2_Pos (2U)
hudakz	0:a04710facbb6	9290	#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	9291	#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	9292	#define CAN_F12R2_FB3_Pos (3U)
hudakz	0:a04710facbb6	9293	#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	9294	#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	9295	#define CAN_F12R2_FB4_Pos (4U)
hudakz	0:a04710facbb6	9296	#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	9297	#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	9298	#define CAN_F12R2_FB5_Pos (5U)
hudakz	0:a04710facbb6	9299	#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	9300	#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	9301	#define CAN_F12R2_FB6_Pos (6U)
hudakz	0:a04710facbb6	9302	#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	9303	#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	9304	#define CAN_F12R2_FB7_Pos (7U)
hudakz	0:a04710facbb6	9305	#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	9306	#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	9307	#define CAN_F12R2_FB8_Pos (8U)
hudakz	0:a04710facbb6	9308	#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	9309	#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	9310	#define CAN_F12R2_FB9_Pos (9U)
hudakz	0:a04710facbb6	9311	#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	9312	#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	9313	#define CAN_F12R2_FB10_Pos (10U)
hudakz	0:a04710facbb6	9314	#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	9315	#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	9316	#define CAN_F12R2_FB11_Pos (11U)
hudakz	0:a04710facbb6	9317	#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	9318	#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	9319	#define CAN_F12R2_FB12_Pos (12U)
hudakz	0:a04710facbb6	9320	#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	9321	#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	9322	#define CAN_F12R2_FB13_Pos (13U)
hudakz	0:a04710facbb6	9323	#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	9324	#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	9325	#define CAN_F12R2_FB14_Pos (14U)
hudakz	0:a04710facbb6	9326	#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	9327	#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	9328	#define CAN_F12R2_FB15_Pos (15U)
hudakz	0:a04710facbb6	9329	#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	9330	#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	9331	#define CAN_F12R2_FB16_Pos (16U)
hudakz	0:a04710facbb6	9332	#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	9333	#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	9334	#define CAN_F12R2_FB17_Pos (17U)
hudakz	0:a04710facbb6	9335	#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	9336	#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	9337	#define CAN_F12R2_FB18_Pos (18U)
hudakz	0:a04710facbb6	9338	#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	9339	#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	9340	#define CAN_F12R2_FB19_Pos (19U)
hudakz	0:a04710facbb6	9341	#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	9342	#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	9343	#define CAN_F12R2_FB20_Pos (20U)
hudakz	0:a04710facbb6	9344	#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	9345	#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	9346	#define CAN_F12R2_FB21_Pos (21U)
hudakz	0:a04710facbb6	9347	#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	9348	#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	9349	#define CAN_F12R2_FB22_Pos (22U)
hudakz	0:a04710facbb6	9350	#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	9351	#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	9352	#define CAN_F12R2_FB23_Pos (23U)
hudakz	0:a04710facbb6	9353	#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	9354	#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	9355	#define CAN_F12R2_FB24_Pos (24U)
hudakz	0:a04710facbb6	9356	#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	9357	#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	9358	#define CAN_F12R2_FB25_Pos (25U)
hudakz	0:a04710facbb6	9359	#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	9360	#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	9361	#define CAN_F12R2_FB26_Pos (26U)
hudakz	0:a04710facbb6	9362	#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	9363	#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	9364	#define CAN_F12R2_FB27_Pos (27U)
hudakz	0:a04710facbb6	9365	#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	9366	#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	9367	#define CAN_F12R2_FB28_Pos (28U)
hudakz	0:a04710facbb6	9368	#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	9369	#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	9370	#define CAN_F12R2_FB29_Pos (29U)
hudakz	0:a04710facbb6	9371	#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	9372	#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	9373	#define CAN_F12R2_FB30_Pos (30U)
hudakz	0:a04710facbb6	9374	#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	9375	#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	9376	#define CAN_F12R2_FB31_Pos (31U)
hudakz	0:a04710facbb6	9377	#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	9378	#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	9379
hudakz	0:a04710facbb6	9380	/***************** Bit definition for CAN_F13R2 register ****************/
hudakz	0:a04710facbb6	9381	#define CAN_F13R2_FB0_Pos (0U)
hudakz	0:a04710facbb6	9382	#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	9383	#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /!< Filter bit 0 /
hudakz	0:a04710facbb6	9384	#define CAN_F13R2_FB1_Pos (1U)
hudakz	0:a04710facbb6	9385	#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	9386	#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /!< Filter bit 1 /
hudakz	0:a04710facbb6	9387	#define CAN_F13R2_FB2_Pos (2U)
hudakz	0:a04710facbb6	9388	#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	9389	#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /!< Filter bit 2 /
hudakz	0:a04710facbb6	9390	#define CAN_F13R2_FB3_Pos (3U)
hudakz	0:a04710facbb6	9391	#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	9392	#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /!< Filter bit 3 /
hudakz	0:a04710facbb6	9393	#define CAN_F13R2_FB4_Pos (4U)
hudakz	0:a04710facbb6	9394	#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	9395	#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /!< Filter bit 4 /
hudakz	0:a04710facbb6	9396	#define CAN_F13R2_FB5_Pos (5U)
hudakz	0:a04710facbb6	9397	#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	9398	#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /!< Filter bit 5 /
hudakz	0:a04710facbb6	9399	#define CAN_F13R2_FB6_Pos (6U)
hudakz	0:a04710facbb6	9400	#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	9401	#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /!< Filter bit 6 /
hudakz	0:a04710facbb6	9402	#define CAN_F13R2_FB7_Pos (7U)
hudakz	0:a04710facbb6	9403	#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	9404	#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /!< Filter bit 7 /
hudakz	0:a04710facbb6	9405	#define CAN_F13R2_FB8_Pos (8U)
hudakz	0:a04710facbb6	9406	#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	9407	#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /!< Filter bit 8 /
hudakz	0:a04710facbb6	9408	#define CAN_F13R2_FB9_Pos (9U)
hudakz	0:a04710facbb6	9409	#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	9410	#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /!< Filter bit 9 /
hudakz	0:a04710facbb6	9411	#define CAN_F13R2_FB10_Pos (10U)
hudakz	0:a04710facbb6	9412	#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	9413	#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /!< Filter bit 10 /
hudakz	0:a04710facbb6	9414	#define CAN_F13R2_FB11_Pos (11U)
hudakz	0:a04710facbb6	9415	#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	9416	#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /!< Filter bit 11 /
hudakz	0:a04710facbb6	9417	#define CAN_F13R2_FB12_Pos (12U)
hudakz	0:a04710facbb6	9418	#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	9419	#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /!< Filter bit 12 /
hudakz	0:a04710facbb6	9420	#define CAN_F13R2_FB13_Pos (13U)
hudakz	0:a04710facbb6	9421	#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	9422	#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /!< Filter bit 13 /
hudakz	0:a04710facbb6	9423	#define CAN_F13R2_FB14_Pos (14U)
hudakz	0:a04710facbb6	9424	#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	9425	#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /!< Filter bit 14 /
hudakz	0:a04710facbb6	9426	#define CAN_F13R2_FB15_Pos (15U)
hudakz	0:a04710facbb6	9427	#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	9428	#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /!< Filter bit 15 /
hudakz	0:a04710facbb6	9429	#define CAN_F13R2_FB16_Pos (16U)
hudakz	0:a04710facbb6	9430	#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	9431	#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /!< Filter bit 16 /
hudakz	0:a04710facbb6	9432	#define CAN_F13R2_FB17_Pos (17U)
hudakz	0:a04710facbb6	9433	#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	9434	#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /!< Filter bit 17 /
hudakz	0:a04710facbb6	9435	#define CAN_F13R2_FB18_Pos (18U)
hudakz	0:a04710facbb6	9436	#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	9437	#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /!< Filter bit 18 /
hudakz	0:a04710facbb6	9438	#define CAN_F13R2_FB19_Pos (19U)
hudakz	0:a04710facbb6	9439	#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	9440	#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /!< Filter bit 19 /
hudakz	0:a04710facbb6	9441	#define CAN_F13R2_FB20_Pos (20U)
hudakz	0:a04710facbb6	9442	#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	9443	#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /!< Filter bit 20 /
hudakz	0:a04710facbb6	9444	#define CAN_F13R2_FB21_Pos (21U)
hudakz	0:a04710facbb6	9445	#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	9446	#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /!< Filter bit 21 /
hudakz	0:a04710facbb6	9447	#define CAN_F13R2_FB22_Pos (22U)
hudakz	0:a04710facbb6	9448	#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	9449	#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /!< Filter bit 22 /
hudakz	0:a04710facbb6	9450	#define CAN_F13R2_FB23_Pos (23U)
hudakz	0:a04710facbb6	9451	#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	9452	#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /!< Filter bit 23 /
hudakz	0:a04710facbb6	9453	#define CAN_F13R2_FB24_Pos (24U)
hudakz	0:a04710facbb6	9454	#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	9455	#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /!< Filter bit 24 /
hudakz	0:a04710facbb6	9456	#define CAN_F13R2_FB25_Pos (25U)
hudakz	0:a04710facbb6	9457	#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	9458	#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /!< Filter bit 25 /
hudakz	0:a04710facbb6	9459	#define CAN_F13R2_FB26_Pos (26U)
hudakz	0:a04710facbb6	9460	#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	9461	#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /!< Filter bit 26 /
hudakz	0:a04710facbb6	9462	#define CAN_F13R2_FB27_Pos (27U)
hudakz	0:a04710facbb6	9463	#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	9464	#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /!< Filter bit 27 /
hudakz	0:a04710facbb6	9465	#define CAN_F13R2_FB28_Pos (28U)
hudakz	0:a04710facbb6	9466	#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	9467	#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /!< Filter bit 28 /
hudakz	0:a04710facbb6	9468	#define CAN_F13R2_FB29_Pos (29U)
hudakz	0:a04710facbb6	9469	#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	9470	#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /!< Filter bit 29 /
hudakz	0:a04710facbb6	9471	#define CAN_F13R2_FB30_Pos (30U)
hudakz	0:a04710facbb6	9472	#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	9473	#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /!< Filter bit 30 /
hudakz	0:a04710facbb6	9474	#define CAN_F13R2_FB31_Pos (31U)
hudakz	0:a04710facbb6	9475	#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	9476	#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /!< Filter bit 31 /
hudakz	0:a04710facbb6	9477
hudakz	0:a04710facbb6	9478	/******************************************************************************/
hudakz	0:a04710facbb6	9479	/* */
hudakz	0:a04710facbb6	9480	/* Serial Peripheral Interface */
hudakz	0:a04710facbb6	9481	/* */
hudakz	0:a04710facbb6	9482	/******************************************************************************/
hudakz	0:a04710facbb6	9483
hudakz	0:a04710facbb6	9484	/***************** Bit definition for SPI_CR1 register ******************/
hudakz	0:a04710facbb6	9485	#define SPI_CR1_CPHA_Pos (0U)
hudakz	0:a04710facbb6	9486	#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	9487	#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /!< Clock Phase /
hudakz	0:a04710facbb6	9488	#define SPI_CR1_CPOL_Pos (1U)
hudakz	0:a04710facbb6	9489	#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	9490	#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /!< Clock Polarity /
hudakz	0:a04710facbb6	9491	#define SPI_CR1_MSTR_Pos (2U)
hudakz	0:a04710facbb6	9492	#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	9493	#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /!< Master Selection /
hudakz	0:a04710facbb6	9494
hudakz	0:a04710facbb6	9495	#define SPI_CR1_BR_Pos (3U)
hudakz	0:a04710facbb6	9496	#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /!< 0x00000038 /
hudakz	0:a04710facbb6	9497	#define SPI_CR1_BR SPI_CR1_BR_Msk /!< BR[2:0] bits (Baud Rate Control) /
hudakz	0:a04710facbb6	9498	#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	9499	#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	9500	#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	9501
hudakz	0:a04710facbb6	9502	#define SPI_CR1_SPE_Pos (6U)
hudakz	0:a04710facbb6	9503	#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	9504	#define SPI_CR1_SPE SPI_CR1_SPE_Msk /!< SPI Enable /
hudakz	0:a04710facbb6	9505	#define SPI_CR1_LSBFIRST_Pos (7U)
hudakz	0:a04710facbb6	9506	#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	9507	#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /!< Frame Format /
hudakz	0:a04710facbb6	9508	#define SPI_CR1_SSI_Pos (8U)
hudakz	0:a04710facbb6	9509	#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	9510	#define SPI_CR1_SSI SPI_CR1_SSI_Msk /!< Internal slave select /
hudakz	0:a04710facbb6	9511	#define SPI_CR1_SSM_Pos (9U)
hudakz	0:a04710facbb6	9512	#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	9513	#define SPI_CR1_SSM SPI_CR1_SSM_Msk /!< Software slave management /
hudakz	0:a04710facbb6	9514	#define SPI_CR1_RXONLY_Pos (10U)
hudakz	0:a04710facbb6	9515	#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	9516	#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /!< Receive only /
hudakz	0:a04710facbb6	9517	#define SPI_CR1_DFF_Pos (11U)
hudakz	0:a04710facbb6	9518	#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	9519	#define SPI_CR1_DFF SPI_CR1_DFF_Msk /!< Data Frame Format /
hudakz	0:a04710facbb6	9520	#define SPI_CR1_CRCNEXT_Pos (12U)
hudakz	0:a04710facbb6	9521	#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	9522	#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /!< Transmit CRC next /
hudakz	0:a04710facbb6	9523	#define SPI_CR1_CRCEN_Pos (13U)
hudakz	0:a04710facbb6	9524	#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	9525	#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /!< Hardware CRC calculation enable /
hudakz	0:a04710facbb6	9526	#define SPI_CR1_BIDIOE_Pos (14U)
hudakz	0:a04710facbb6	9527	#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	9528	#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /!< Output enable in bidirectional mode /
hudakz	0:a04710facbb6	9529	#define SPI_CR1_BIDIMODE_Pos (15U)
hudakz	0:a04710facbb6	9530	#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	9531	#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /!< Bidirectional data mode enable /
hudakz	0:a04710facbb6	9532
hudakz	0:a04710facbb6	9533	/***************** Bit definition for SPI_CR2 register ******************/
hudakz	0:a04710facbb6	9534	#define SPI_CR2_RXDMAEN_Pos (0U)
hudakz	0:a04710facbb6	9535	#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	9536	#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /!< Rx Buffer DMA Enable /
hudakz	0:a04710facbb6	9537	#define SPI_CR2_TXDMAEN_Pos (1U)
hudakz	0:a04710facbb6	9538	#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	9539	#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /!< Tx Buffer DMA Enable /
hudakz	0:a04710facbb6	9540	#define SPI_CR2_SSOE_Pos (2U)
hudakz	0:a04710facbb6	9541	#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	9542	#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /!< SS Output Enable /
hudakz	0:a04710facbb6	9543	#define SPI_CR2_ERRIE_Pos (5U)
hudakz	0:a04710facbb6	9544	#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	9545	#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /!< Error Interrupt Enable /
hudakz	0:a04710facbb6	9546	#define SPI_CR2_RXNEIE_Pos (6U)
hudakz	0:a04710facbb6	9547	#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	9548	#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /!< RX buffer Not Empty Interrupt Enable /
hudakz	0:a04710facbb6	9549	#define SPI_CR2_TXEIE_Pos (7U)
hudakz	0:a04710facbb6	9550	#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	9551	#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /!< Tx buffer Empty Interrupt Enable /
hudakz	0:a04710facbb6	9552
hudakz	0:a04710facbb6	9553	/****************** Bit definition for SPI_SR register ******************/
hudakz	0:a04710facbb6	9554	#define SPI_SR_RXNE_Pos (0U)
hudakz	0:a04710facbb6	9555	#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	9556	#define SPI_SR_RXNE SPI_SR_RXNE_Msk /!< Receive buffer Not Empty /
hudakz	0:a04710facbb6	9557	#define SPI_SR_TXE_Pos (1U)
hudakz	0:a04710facbb6	9558	#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	9559	#define SPI_SR_TXE SPI_SR_TXE_Msk /!< Transmit buffer Empty /
hudakz	0:a04710facbb6	9560	#define SPI_SR_CHSIDE_Pos (2U)
hudakz	0:a04710facbb6	9561	#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	9562	#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /!< Channel side /
hudakz	0:a04710facbb6	9563	#define SPI_SR_UDR_Pos (3U)
hudakz	0:a04710facbb6	9564	#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	9565	#define SPI_SR_UDR SPI_SR_UDR_Msk /!< Underrun flag /
hudakz	0:a04710facbb6	9566	#define SPI_SR_CRCERR_Pos (4U)
hudakz	0:a04710facbb6	9567	#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	9568	#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /!< CRC Error flag /
hudakz	0:a04710facbb6	9569	#define SPI_SR_MODF_Pos (5U)
hudakz	0:a04710facbb6	9570	#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	9571	#define SPI_SR_MODF SPI_SR_MODF_Msk /!< Mode fault /
hudakz	0:a04710facbb6	9572	#define SPI_SR_OVR_Pos (6U)
hudakz	0:a04710facbb6	9573	#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	9574	#define SPI_SR_OVR SPI_SR_OVR_Msk /!< Overrun flag /
hudakz	0:a04710facbb6	9575	#define SPI_SR_BSY_Pos (7U)
hudakz	0:a04710facbb6	9576	#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	9577	#define SPI_SR_BSY SPI_SR_BSY_Msk /!< Busy flag /
hudakz	0:a04710facbb6	9578
hudakz	0:a04710facbb6	9579	/****************** Bit definition for SPI_DR register ******************/
hudakz	0:a04710facbb6	9580	#define SPI_DR_DR_Pos (0U)
hudakz	0:a04710facbb6	9581	#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	9582	#define SPI_DR_DR SPI_DR_DR_Msk /!< Data Register /
hudakz	0:a04710facbb6	9583
hudakz	0:a04710facbb6	9584	/***************** Bit definition for SPI_CRCPR register ****************/
hudakz	0:a04710facbb6	9585	#define SPI_CRCPR_CRCPOLY_Pos (0U)
hudakz	0:a04710facbb6	9586	#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	9587	#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /!< CRC polynomial register /
hudakz	0:a04710facbb6	9588
hudakz	0:a04710facbb6	9589	/**************** Bit definition for SPI_RXCRCR register ****************/
hudakz	0:a04710facbb6	9590	#define SPI_RXCRCR_RXCRC_Pos (0U)
hudakz	0:a04710facbb6	9591	#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	9592	#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /!< Rx CRC Register /
hudakz	0:a04710facbb6	9593
hudakz	0:a04710facbb6	9594	/**************** Bit definition for SPI_TXCRCR register ****************/
hudakz	0:a04710facbb6	9595	#define SPI_TXCRCR_TXCRC_Pos (0U)
hudakz	0:a04710facbb6	9596	#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /!< 0x0000FFFF /
hudakz	0:a04710facbb6	9597	#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /!< Tx CRC Register /
hudakz	0:a04710facbb6	9598
hudakz	0:a04710facbb6	9599	/**************** Bit definition for SPI_I2SCFGR register ***************/
hudakz	0:a04710facbb6	9600	#define SPI_I2SCFGR_I2SMOD_Pos (11U)
hudakz	0:a04710facbb6	9601	#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	9602	#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /!< I2S mode selection /
hudakz	0:a04710facbb6	9603
hudakz	0:a04710facbb6	9604
hudakz	0:a04710facbb6	9605	/******************************************************************************/
hudakz	0:a04710facbb6	9606	/* */
hudakz	0:a04710facbb6	9607	/* Inter-integrated Circuit Interface */
hudakz	0:a04710facbb6	9608	/* */
hudakz	0:a04710facbb6	9609	/******************************************************************************/
hudakz	0:a04710facbb6	9610
hudakz	0:a04710facbb6	9611	/***************** Bit definition for I2C_CR1 register ******************/
hudakz	0:a04710facbb6	9612	#define I2C_CR1_PE_Pos (0U)
hudakz	0:a04710facbb6	9613	#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	9614	#define I2C_CR1_PE I2C_CR1_PE_Msk /!< Peripheral Enable /
hudakz	0:a04710facbb6	9615	#define I2C_CR1_SMBUS_Pos (1U)
hudakz	0:a04710facbb6	9616	#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	9617	#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /!< SMBus Mode /
hudakz	0:a04710facbb6	9618	#define I2C_CR1_SMBTYPE_Pos (3U)
hudakz	0:a04710facbb6	9619	#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	9620	#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /!< SMBus Type /
hudakz	0:a04710facbb6	9621	#define I2C_CR1_ENARP_Pos (4U)
hudakz	0:a04710facbb6	9622	#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	9623	#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /!< ARP Enable /
hudakz	0:a04710facbb6	9624	#define I2C_CR1_ENPEC_Pos (5U)
hudakz	0:a04710facbb6	9625	#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	9626	#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /!< PEC Enable /
hudakz	0:a04710facbb6	9627	#define I2C_CR1_ENGC_Pos (6U)
hudakz	0:a04710facbb6	9628	#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	9629	#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /!< General Call Enable /
hudakz	0:a04710facbb6	9630	#define I2C_CR1_NOSTRETCH_Pos (7U)
hudakz	0:a04710facbb6	9631	#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	9632	#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /!< Clock Stretching Disable (Slave mode) /
hudakz	0:a04710facbb6	9633	#define I2C_CR1_START_Pos (8U)
hudakz	0:a04710facbb6	9634	#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	9635	#define I2C_CR1_START I2C_CR1_START_Msk /!< Start Generation /
hudakz	0:a04710facbb6	9636	#define I2C_CR1_STOP_Pos (9U)
hudakz	0:a04710facbb6	9637	#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	9638	#define I2C_CR1_STOP I2C_CR1_STOP_Msk /!< Stop Generation /
hudakz	0:a04710facbb6	9639	#define I2C_CR1_ACK_Pos (10U)
hudakz	0:a04710facbb6	9640	#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	9641	#define I2C_CR1_ACK I2C_CR1_ACK_Msk /!< Acknowledge Enable /
hudakz	0:a04710facbb6	9642	#define I2C_CR1_POS_Pos (11U)
hudakz	0:a04710facbb6	9643	#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	9644	#define I2C_CR1_POS I2C_CR1_POS_Msk /!< Acknowledge/PEC Position (for data reception) /
hudakz	0:a04710facbb6	9645	#define I2C_CR1_PEC_Pos (12U)
hudakz	0:a04710facbb6	9646	#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	9647	#define I2C_CR1_PEC I2C_CR1_PEC_Msk /!< Packet Error Checking /
hudakz	0:a04710facbb6	9648	#define I2C_CR1_ALERT_Pos (13U)
hudakz	0:a04710facbb6	9649	#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	9650	#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /!< SMBus Alert /
hudakz	0:a04710facbb6	9651	#define I2C_CR1_SWRST_Pos (15U)
hudakz	0:a04710facbb6	9652	#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	9653	#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /!< Software Reset /
hudakz	0:a04710facbb6	9654
hudakz	0:a04710facbb6	9655	/***************** Bit definition for I2C_CR2 register ******************/
hudakz	0:a04710facbb6	9656	#define I2C_CR2_FREQ_Pos (0U)
hudakz	0:a04710facbb6	9657	#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /!< 0x0000003F /
hudakz	0:a04710facbb6	9658	#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /!< FREQ[5:0] bits (Peripheral Clock Frequency) /
hudakz	0:a04710facbb6	9659	#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	9660	#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	9661	#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	9662	#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	9663	#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	9664	#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	9665
hudakz	0:a04710facbb6	9666	#define I2C_CR2_ITERREN_Pos (8U)
hudakz	0:a04710facbb6	9667	#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	9668	#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /!< Error Interrupt Enable /
hudakz	0:a04710facbb6	9669	#define I2C_CR2_ITEVTEN_Pos (9U)
hudakz	0:a04710facbb6	9670	#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	9671	#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /!< Event Interrupt Enable /
hudakz	0:a04710facbb6	9672	#define I2C_CR2_ITBUFEN_Pos (10U)
hudakz	0:a04710facbb6	9673	#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	9674	#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /!< Buffer Interrupt Enable /
hudakz	0:a04710facbb6	9675	#define I2C_CR2_DMAEN_Pos (11U)
hudakz	0:a04710facbb6	9676	#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	9677	#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /!< DMA Requests Enable /
hudakz	0:a04710facbb6	9678	#define I2C_CR2_LAST_Pos (12U)
hudakz	0:a04710facbb6	9679	#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	9680	#define I2C_CR2_LAST I2C_CR2_LAST_Msk /!< DMA Last Transfer /
hudakz	0:a04710facbb6	9681
hudakz	0:a04710facbb6	9682	/***************** Bit definition for I2C_OAR1 register *****************/
hudakz	0:a04710facbb6	9683	#define I2C_OAR1_ADD1_7 0x000000FEU /!< Interface Address /
hudakz	0:a04710facbb6	9684	#define I2C_OAR1_ADD8_9 0x00000300U /!< Interface Address /
hudakz	0:a04710facbb6	9685
hudakz	0:a04710facbb6	9686	#define I2C_OAR1_ADD0_Pos (0U)
hudakz	0:a04710facbb6	9687	#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	9688	#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /!< Bit 0 /
hudakz	0:a04710facbb6	9689	#define I2C_OAR1_ADD1_Pos (1U)
hudakz	0:a04710facbb6	9690	#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	9691	#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /!< Bit 1 /
hudakz	0:a04710facbb6	9692	#define I2C_OAR1_ADD2_Pos (2U)
hudakz	0:a04710facbb6	9693	#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	9694	#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /!< Bit 2 /
hudakz	0:a04710facbb6	9695	#define I2C_OAR1_ADD3_Pos (3U)
hudakz	0:a04710facbb6	9696	#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	9697	#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /!< Bit 3 /
hudakz	0:a04710facbb6	9698	#define I2C_OAR1_ADD4_Pos (4U)
hudakz	0:a04710facbb6	9699	#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	9700	#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /!< Bit 4 /
hudakz	0:a04710facbb6	9701	#define I2C_OAR1_ADD5_Pos (5U)
hudakz	0:a04710facbb6	9702	#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	9703	#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /!< Bit 5 /
hudakz	0:a04710facbb6	9704	#define I2C_OAR1_ADD6_Pos (6U)
hudakz	0:a04710facbb6	9705	#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	9706	#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /!< Bit 6 /
hudakz	0:a04710facbb6	9707	#define I2C_OAR1_ADD7_Pos (7U)
hudakz	0:a04710facbb6	9708	#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	9709	#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /!< Bit 7 /
hudakz	0:a04710facbb6	9710	#define I2C_OAR1_ADD8_Pos (8U)
hudakz	0:a04710facbb6	9711	#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	9712	#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /!< Bit 8 /
hudakz	0:a04710facbb6	9713	#define I2C_OAR1_ADD9_Pos (9U)
hudakz	0:a04710facbb6	9714	#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	9715	#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /!< Bit 9 /
hudakz	0:a04710facbb6	9716
hudakz	0:a04710facbb6	9717	#define I2C_OAR1_ADDMODE_Pos (15U)
hudakz	0:a04710facbb6	9718	#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	9719	#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /!< Addressing Mode (Slave mode) /
hudakz	0:a04710facbb6	9720
hudakz	0:a04710facbb6	9721	/***************** Bit definition for I2C_OAR2 register *****************/
hudakz	0:a04710facbb6	9722	#define I2C_OAR2_ENDUAL_Pos (0U)
hudakz	0:a04710facbb6	9723	#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	9724	#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /!< Dual addressing mode enable /
hudakz	0:a04710facbb6	9725	#define I2C_OAR2_ADD2_Pos (1U)
hudakz	0:a04710facbb6	9726	#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /!< 0x000000FE /
hudakz	0:a04710facbb6	9727	#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /!< Interface address /
hudakz	0:a04710facbb6	9728
hudakz	0:a04710facbb6	9729	/****************** Bit definition for I2C_DR register ******************/
hudakz	0:a04710facbb6	9730	#define I2C_DR_DR_Pos (0U)
hudakz	0:a04710facbb6	9731	#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /!< 0x000000FF /
hudakz	0:a04710facbb6	9732	#define I2C_DR_DR I2C_DR_DR_Msk /!< 8-bit Data Register /
hudakz	0:a04710facbb6	9733
hudakz	0:a04710facbb6	9734	/***************** Bit definition for I2C_SR1 register ******************/
hudakz	0:a04710facbb6	9735	#define I2C_SR1_SB_Pos (0U)
hudakz	0:a04710facbb6	9736	#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	9737	#define I2C_SR1_SB I2C_SR1_SB_Msk /!< Start Bit (Master mode) /
hudakz	0:a04710facbb6	9738	#define I2C_SR1_ADDR_Pos (1U)
hudakz	0:a04710facbb6	9739	#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	9740	#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /!< Address sent (master mode)/matched (slave mode) /
hudakz	0:a04710facbb6	9741	#define I2C_SR1_BTF_Pos (2U)
hudakz	0:a04710facbb6	9742	#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	9743	#define I2C_SR1_BTF I2C_SR1_BTF_Msk /!< Byte Transfer Finished /
hudakz	0:a04710facbb6	9744	#define I2C_SR1_ADD10_Pos (3U)
hudakz	0:a04710facbb6	9745	#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	9746	#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /!< 10-bit header sent (Master mode) /
hudakz	0:a04710facbb6	9747	#define I2C_SR1_STOPF_Pos (4U)
hudakz	0:a04710facbb6	9748	#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	9749	#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /!< Stop detection (Slave mode) /
hudakz	0:a04710facbb6	9750	#define I2C_SR1_RXNE_Pos (6U)
hudakz	0:a04710facbb6	9751	#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	9752	#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /!< Data Register not Empty (receivers) /
hudakz	0:a04710facbb6	9753	#define I2C_SR1_TXE_Pos (7U)
hudakz	0:a04710facbb6	9754	#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	9755	#define I2C_SR1_TXE I2C_SR1_TXE_Msk /!< Data Register Empty (transmitters) /
hudakz	0:a04710facbb6	9756	#define I2C_SR1_BERR_Pos (8U)
hudakz	0:a04710facbb6	9757	#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	9758	#define I2C_SR1_BERR I2C_SR1_BERR_Msk /!< Bus Error /
hudakz	0:a04710facbb6	9759	#define I2C_SR1_ARLO_Pos (9U)
hudakz	0:a04710facbb6	9760	#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	9761	#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /!< Arbitration Lost (master mode) /
hudakz	0:a04710facbb6	9762	#define I2C_SR1_AF_Pos (10U)
hudakz	0:a04710facbb6	9763	#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	9764	#define I2C_SR1_AF I2C_SR1_AF_Msk /!< Acknowledge Failure /
hudakz	0:a04710facbb6	9765	#define I2C_SR1_OVR_Pos (11U)
hudakz	0:a04710facbb6	9766	#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	9767	#define I2C_SR1_OVR I2C_SR1_OVR_Msk /!< Overrun/Underrun /
hudakz	0:a04710facbb6	9768	#define I2C_SR1_PECERR_Pos (12U)
hudakz	0:a04710facbb6	9769	#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	9770	#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /!< PEC Error in reception /
hudakz	0:a04710facbb6	9771	#define I2C_SR1_TIMEOUT_Pos (14U)
hudakz	0:a04710facbb6	9772	#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	9773	#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /!< Timeout or Tlow Error /
hudakz	0:a04710facbb6	9774	#define I2C_SR1_SMBALERT_Pos (15U)
hudakz	0:a04710facbb6	9775	#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	9776	#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /!< SMBus Alert /
hudakz	0:a04710facbb6	9777
hudakz	0:a04710facbb6	9778	/***************** Bit definition for I2C_SR2 register ******************/
hudakz	0:a04710facbb6	9779	#define I2C_SR2_MSL_Pos (0U)
hudakz	0:a04710facbb6	9780	#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	9781	#define I2C_SR2_MSL I2C_SR2_MSL_Msk /!< Master/Slave /
hudakz	0:a04710facbb6	9782	#define I2C_SR2_BUSY_Pos (1U)
hudakz	0:a04710facbb6	9783	#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	9784	#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /!< Bus Busy /
hudakz	0:a04710facbb6	9785	#define I2C_SR2_TRA_Pos (2U)
hudakz	0:a04710facbb6	9786	#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	9787	#define I2C_SR2_TRA I2C_SR2_TRA_Msk /!< Transmitter/Receiver /
hudakz	0:a04710facbb6	9788	#define I2C_SR2_GENCALL_Pos (4U)
hudakz	0:a04710facbb6	9789	#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	9790	#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /!< General Call Address (Slave mode) /
hudakz	0:a04710facbb6	9791	#define I2C_SR2_SMBDEFAULT_Pos (5U)
hudakz	0:a04710facbb6	9792	#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	9793	#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /!< SMBus Device Default Address (Slave mode) /
hudakz	0:a04710facbb6	9794	#define I2C_SR2_SMBHOST_Pos (6U)
hudakz	0:a04710facbb6	9795	#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	9796	#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /!< SMBus Host Header (Slave mode) /
hudakz	0:a04710facbb6	9797	#define I2C_SR2_DUALF_Pos (7U)
hudakz	0:a04710facbb6	9798	#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	9799	#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /!< Dual Flag (Slave mode) /
hudakz	0:a04710facbb6	9800	#define I2C_SR2_PEC_Pos (8U)
hudakz	0:a04710facbb6	9801	#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /!< 0x0000FF00 /
hudakz	0:a04710facbb6	9802	#define I2C_SR2_PEC I2C_SR2_PEC_Msk /!< Packet Error Checking Register /
hudakz	0:a04710facbb6	9803
hudakz	0:a04710facbb6	9804	/***************** Bit definition for I2C_CCR register ******************/
hudakz	0:a04710facbb6	9805	#define I2C_CCR_CCR_Pos (0U)
hudakz	0:a04710facbb6	9806	#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /!< 0x00000FFF /
hudakz	0:a04710facbb6	9807	#define I2C_CCR_CCR I2C_CCR_CCR_Msk /!< Clock Control Register in Fast/Standard mode (Master mode) /
hudakz	0:a04710facbb6	9808	#define I2C_CCR_DUTY_Pos (14U)
hudakz	0:a04710facbb6	9809	#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	9810	#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /!< Fast Mode Duty Cycle /
hudakz	0:a04710facbb6	9811	#define I2C_CCR_FS_Pos (15U)
hudakz	0:a04710facbb6	9812	#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	9813	#define I2C_CCR_FS I2C_CCR_FS_Msk /!< I2C Master Mode Selection /
hudakz	0:a04710facbb6	9814
hudakz	0:a04710facbb6	9815	/**************** Bit definition for I2C_TRISE register *****************/
hudakz	0:a04710facbb6	9816	#define I2C_TRISE_TRISE_Pos (0U)
hudakz	0:a04710facbb6	9817	#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /!< 0x0000003F /
hudakz	0:a04710facbb6	9818	#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /!< Maximum Rise Time in Fast/Standard mode (Master mode) /
hudakz	0:a04710facbb6	9819
hudakz	0:a04710facbb6	9820	/******************************************************************************/
hudakz	0:a04710facbb6	9821	/* */
hudakz	0:a04710facbb6	9822	/* Universal Synchronous Asynchronous Receiver Transmitter */
hudakz	0:a04710facbb6	9823	/* */
hudakz	0:a04710facbb6	9824	/******************************************************************************/
hudakz	0:a04710facbb6	9825
hudakz	0:a04710facbb6	9826	/***************** Bit definition for USART_SR register *****************/
hudakz	0:a04710facbb6	9827	#define USART_SR_PE_Pos (0U)
hudakz	0:a04710facbb6	9828	#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	9829	#define USART_SR_PE USART_SR_PE_Msk /!< Parity Error /
hudakz	0:a04710facbb6	9830	#define USART_SR_FE_Pos (1U)
hudakz	0:a04710facbb6	9831	#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	9832	#define USART_SR_FE USART_SR_FE_Msk /!< Framing Error /
hudakz	0:a04710facbb6	9833	#define USART_SR_NE_Pos (2U)
hudakz	0:a04710facbb6	9834	#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	9835	#define USART_SR_NE USART_SR_NE_Msk /!< Noise Error Flag /
hudakz	0:a04710facbb6	9836	#define USART_SR_ORE_Pos (3U)
hudakz	0:a04710facbb6	9837	#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	9838	#define USART_SR_ORE USART_SR_ORE_Msk /!< OverRun Error /
hudakz	0:a04710facbb6	9839	#define USART_SR_IDLE_Pos (4U)
hudakz	0:a04710facbb6	9840	#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	9841	#define USART_SR_IDLE USART_SR_IDLE_Msk /!< IDLE line detected /
hudakz	0:a04710facbb6	9842	#define USART_SR_RXNE_Pos (5U)
hudakz	0:a04710facbb6	9843	#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	9844	#define USART_SR_RXNE USART_SR_RXNE_Msk /!< Read Data Register Not Empty /
hudakz	0:a04710facbb6	9845	#define USART_SR_TC_Pos (6U)
hudakz	0:a04710facbb6	9846	#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	9847	#define USART_SR_TC USART_SR_TC_Msk /!< Transmission Complete /
hudakz	0:a04710facbb6	9848	#define USART_SR_TXE_Pos (7U)
hudakz	0:a04710facbb6	9849	#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	9850	#define USART_SR_TXE USART_SR_TXE_Msk /!< Transmit Data Register Empty /
hudakz	0:a04710facbb6	9851	#define USART_SR_LBD_Pos (8U)
hudakz	0:a04710facbb6	9852	#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	9853	#define USART_SR_LBD USART_SR_LBD_Msk /!< LIN Break Detection Flag /
hudakz	0:a04710facbb6	9854	#define USART_SR_CTS_Pos (9U)
hudakz	0:a04710facbb6	9855	#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	9856	#define USART_SR_CTS USART_SR_CTS_Msk /!< CTS Flag /
hudakz	0:a04710facbb6	9857
hudakz	0:a04710facbb6	9858	/***************** Bit definition for USART_DR register *****************/
hudakz	0:a04710facbb6	9859	#define USART_DR_DR_Pos (0U)
hudakz	0:a04710facbb6	9860	#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /!< 0x000001FF /
hudakz	0:a04710facbb6	9861	#define USART_DR_DR USART_DR_DR_Msk /!< Data value /
hudakz	0:a04710facbb6	9862
hudakz	0:a04710facbb6	9863	/**************** Bit definition for USART_BRR register *****************/
hudakz	0:a04710facbb6	9864	#define USART_BRR_DIV_Fraction_Pos (0U)
hudakz	0:a04710facbb6	9865	#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	9866	#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /!< Fraction of USARTDIV /
hudakz	0:a04710facbb6	9867	#define USART_BRR_DIV_Mantissa_Pos (4U)
hudakz	0:a04710facbb6	9868	#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /!< 0x0000FFF0 /
hudakz	0:a04710facbb6	9869	#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /!< Mantissa of USARTDIV /
hudakz	0:a04710facbb6	9870
hudakz	0:a04710facbb6	9871	/**************** Bit definition for USART_CR1 register *****************/
hudakz	0:a04710facbb6	9872	#define USART_CR1_SBK_Pos (0U)
hudakz	0:a04710facbb6	9873	#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	9874	#define USART_CR1_SBK USART_CR1_SBK_Msk /!< Send Break /
hudakz	0:a04710facbb6	9875	#define USART_CR1_RWU_Pos (1U)
hudakz	0:a04710facbb6	9876	#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	9877	#define USART_CR1_RWU USART_CR1_RWU_Msk /!< Receiver wakeup /
hudakz	0:a04710facbb6	9878	#define USART_CR1_RE_Pos (2U)
hudakz	0:a04710facbb6	9879	#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	9880	#define USART_CR1_RE USART_CR1_RE_Msk /!< Receiver Enable /
hudakz	0:a04710facbb6	9881	#define USART_CR1_TE_Pos (3U)
hudakz	0:a04710facbb6	9882	#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	9883	#define USART_CR1_TE USART_CR1_TE_Msk /!< Transmitter Enable /
hudakz	0:a04710facbb6	9884	#define USART_CR1_IDLEIE_Pos (4U)
hudakz	0:a04710facbb6	9885	#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	9886	#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /!< IDLE Interrupt Enable /
hudakz	0:a04710facbb6	9887	#define USART_CR1_RXNEIE_Pos (5U)
hudakz	0:a04710facbb6	9888	#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	9889	#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /!< RXNE Interrupt Enable /
hudakz	0:a04710facbb6	9890	#define USART_CR1_TCIE_Pos (6U)
hudakz	0:a04710facbb6	9891	#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	9892	#define USART_CR1_TCIE USART_CR1_TCIE_Msk /!< Transmission Complete Interrupt Enable /
hudakz	0:a04710facbb6	9893	#define USART_CR1_TXEIE_Pos (7U)
hudakz	0:a04710facbb6	9894	#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	9895	#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /!< PE Interrupt Enable /
hudakz	0:a04710facbb6	9896	#define USART_CR1_PEIE_Pos (8U)
hudakz	0:a04710facbb6	9897	#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	9898	#define USART_CR1_PEIE USART_CR1_PEIE_Msk /!< PE Interrupt Enable /
hudakz	0:a04710facbb6	9899	#define USART_CR1_PS_Pos (9U)
hudakz	0:a04710facbb6	9900	#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	9901	#define USART_CR1_PS USART_CR1_PS_Msk /!< Parity Selection /
hudakz	0:a04710facbb6	9902	#define USART_CR1_PCE_Pos (10U)
hudakz	0:a04710facbb6	9903	#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	9904	#define USART_CR1_PCE USART_CR1_PCE_Msk /!< Parity Control Enable /
hudakz	0:a04710facbb6	9905	#define USART_CR1_WAKE_Pos (11U)
hudakz	0:a04710facbb6	9906	#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	9907	#define USART_CR1_WAKE USART_CR1_WAKE_Msk /!< Wakeup method /
hudakz	0:a04710facbb6	9908	#define USART_CR1_M_Pos (12U)
hudakz	0:a04710facbb6	9909	#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	9910	#define USART_CR1_M USART_CR1_M_Msk /!< Word length /
hudakz	0:a04710facbb6	9911	#define USART_CR1_UE_Pos (13U)
hudakz	0:a04710facbb6	9912	#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	9913	#define USART_CR1_UE USART_CR1_UE_Msk /!< USART Enable /
hudakz	0:a04710facbb6	9914
hudakz	0:a04710facbb6	9915	/**************** Bit definition for USART_CR2 register *****************/
hudakz	0:a04710facbb6	9916	#define USART_CR2_ADD_Pos (0U)
hudakz	0:a04710facbb6	9917	#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /!< 0x0000000F /
hudakz	0:a04710facbb6	9918	#define USART_CR2_ADD USART_CR2_ADD_Msk /!< Address of the USART node /
hudakz	0:a04710facbb6	9919	#define USART_CR2_LBDL_Pos (5U)
hudakz	0:a04710facbb6	9920	#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	9921	#define USART_CR2_LBDL USART_CR2_LBDL_Msk /!< LIN Break Detection Length /
hudakz	0:a04710facbb6	9922	#define USART_CR2_LBDIE_Pos (6U)
hudakz	0:a04710facbb6	9923	#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	9924	#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /!< LIN Break Detection Interrupt Enable /
hudakz	0:a04710facbb6	9925	#define USART_CR2_LBCL_Pos (8U)
hudakz	0:a04710facbb6	9926	#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	9927	#define USART_CR2_LBCL USART_CR2_LBCL_Msk /!< Last Bit Clock pulse /
hudakz	0:a04710facbb6	9928	#define USART_CR2_CPHA_Pos (9U)
hudakz	0:a04710facbb6	9929	#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	9930	#define USART_CR2_CPHA USART_CR2_CPHA_Msk /!< Clock Phase /
hudakz	0:a04710facbb6	9931	#define USART_CR2_CPOL_Pos (10U)
hudakz	0:a04710facbb6	9932	#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	9933	#define USART_CR2_CPOL USART_CR2_CPOL_Msk /!< Clock Polarity /
hudakz	0:a04710facbb6	9934	#define USART_CR2_CLKEN_Pos (11U)
hudakz	0:a04710facbb6	9935	#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	9936	#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /!< Clock Enable /
hudakz	0:a04710facbb6	9937
hudakz	0:a04710facbb6	9938	#define USART_CR2_STOP_Pos (12U)
hudakz	0:a04710facbb6	9939	#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /!< 0x00003000 /
hudakz	0:a04710facbb6	9940	#define USART_CR2_STOP USART_CR2_STOP_Msk /!< STOP[1:0] bits (STOP bits) /
hudakz	0:a04710facbb6	9941	#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	9942	#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	9943
hudakz	0:a04710facbb6	9944	#define USART_CR2_LINEN_Pos (14U)
hudakz	0:a04710facbb6	9945	#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	9946	#define USART_CR2_LINEN USART_CR2_LINEN_Msk /!< LIN mode enable /
hudakz	0:a04710facbb6	9947
hudakz	0:a04710facbb6	9948	/**************** Bit definition for USART_CR3 register *****************/
hudakz	0:a04710facbb6	9949	#define USART_CR3_EIE_Pos (0U)
hudakz	0:a04710facbb6	9950	#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	9951	#define USART_CR3_EIE USART_CR3_EIE_Msk /!< Error Interrupt Enable /
hudakz	0:a04710facbb6	9952	#define USART_CR3_IREN_Pos (1U)
hudakz	0:a04710facbb6	9953	#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	9954	#define USART_CR3_IREN USART_CR3_IREN_Msk /!< IrDA mode Enable /
hudakz	0:a04710facbb6	9955	#define USART_CR3_IRLP_Pos (2U)
hudakz	0:a04710facbb6	9956	#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	9957	#define USART_CR3_IRLP USART_CR3_IRLP_Msk /!< IrDA Low-Power /
hudakz	0:a04710facbb6	9958	#define USART_CR3_HDSEL_Pos (3U)
hudakz	0:a04710facbb6	9959	#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	9960	#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /!< Half-Duplex Selection /
hudakz	0:a04710facbb6	9961	#define USART_CR3_NACK_Pos (4U)
hudakz	0:a04710facbb6	9962	#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	9963	#define USART_CR3_NACK USART_CR3_NACK_Msk /!< Smartcard NACK enable /
hudakz	0:a04710facbb6	9964	#define USART_CR3_SCEN_Pos (5U)
hudakz	0:a04710facbb6	9965	#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	9966	#define USART_CR3_SCEN USART_CR3_SCEN_Msk /!< Smartcard mode enable /
hudakz	0:a04710facbb6	9967	#define USART_CR3_DMAR_Pos (6U)
hudakz	0:a04710facbb6	9968	#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	9969	#define USART_CR3_DMAR USART_CR3_DMAR_Msk /!< DMA Enable Receiver /
hudakz	0:a04710facbb6	9970	#define USART_CR3_DMAT_Pos (7U)
hudakz	0:a04710facbb6	9971	#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	9972	#define USART_CR3_DMAT USART_CR3_DMAT_Msk /!< DMA Enable Transmitter /
hudakz	0:a04710facbb6	9973	#define USART_CR3_RTSE_Pos (8U)
hudakz	0:a04710facbb6	9974	#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	9975	#define USART_CR3_RTSE USART_CR3_RTSE_Msk /!< RTS Enable /
hudakz	0:a04710facbb6	9976	#define USART_CR3_CTSE_Pos (9U)
hudakz	0:a04710facbb6	9977	#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	9978	#define USART_CR3_CTSE USART_CR3_CTSE_Msk /!< CTS Enable /
hudakz	0:a04710facbb6	9979	#define USART_CR3_CTSIE_Pos (10U)
hudakz	0:a04710facbb6	9980	#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	9981	#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /!< CTS Interrupt Enable /
hudakz	0:a04710facbb6	9982
hudakz	0:a04710facbb6	9983	/**************** Bit definition for USART_GTPR register ****************/
hudakz	0:a04710facbb6	9984	#define USART_GTPR_PSC_Pos (0U)
hudakz	0:a04710facbb6	9985	#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /!< 0x000000FF /
hudakz	0:a04710facbb6	9986	#define USART_GTPR_PSC USART_GTPR_PSC_Msk /!< PSC[7:0] bits (Prescaler value) /
hudakz	0:a04710facbb6	9987	#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	9988	#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	9989	#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	9990	#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	9991	#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	9992	#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	9993	#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	9994	#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	9995
hudakz	0:a04710facbb6	9996	#define USART_GTPR_GT_Pos (8U)
hudakz	0:a04710facbb6	9997	#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /!< 0x0000FF00 /
hudakz	0:a04710facbb6	9998	#define USART_GTPR_GT USART_GTPR_GT_Msk /!< Guard time value /
hudakz	0:a04710facbb6	9999
hudakz	0:a04710facbb6	10000	/******************************************************************************/
hudakz	0:a04710facbb6	10001	/* */
hudakz	0:a04710facbb6	10002	/* Debug MCU */
hudakz	0:a04710facbb6	10003	/* */
hudakz	0:a04710facbb6	10004	/******************************************************************************/
hudakz	0:a04710facbb6	10005
hudakz	0:a04710facbb6	10006	/************** Bit definition for DBGMCU_IDCODE register ***************/
hudakz	0:a04710facbb6	10007	#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
hudakz	0:a04710facbb6	10008	#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /!< 0x00000FFF /
hudakz	0:a04710facbb6	10009	#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /!< Device Identifier /
hudakz	0:a04710facbb6	10010
hudakz	0:a04710facbb6	10011	#define DBGMCU_IDCODE_REV_ID_Pos (16U)
hudakz	0:a04710facbb6	10012	#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /!< 0xFFFF0000 /
hudakz	0:a04710facbb6	10013	#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /!< REV_ID[15:0] bits (Revision Identifier) /
hudakz	0:a04710facbb6	10014	#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	10015	#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00020000 /
hudakz	0:a04710facbb6	10016	#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00040000 /
hudakz	0:a04710facbb6	10017	#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00080000 /
hudakz	0:a04710facbb6	10018	#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00100000 /
hudakz	0:a04710facbb6	10019	#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00200000 /
hudakz	0:a04710facbb6	10020	#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00400000 /
hudakz	0:a04710facbb6	10021	#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00800000 /
hudakz	0:a04710facbb6	10022	#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x01000000 /
hudakz	0:a04710facbb6	10023	#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x02000000 /
hudakz	0:a04710facbb6	10024	#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x04000000 /
hudakz	0:a04710facbb6	10025	#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x08000000 /
hudakz	0:a04710facbb6	10026	#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x10000000 /
hudakz	0:a04710facbb6	10027	#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x20000000 /
hudakz	0:a04710facbb6	10028	#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x40000000 /
hudakz	0:a04710facbb6	10029	#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x80000000 /
hudakz	0:a04710facbb6	10030
hudakz	0:a04710facbb6	10031	/**************** Bit definition for DBGMCU_CR register *****************/
hudakz	0:a04710facbb6	10032	#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
hudakz	0:a04710facbb6	10033	#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	10034	#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /!< Debug Sleep Mode /
hudakz	0:a04710facbb6	10035	#define DBGMCU_CR_DBG_STOP_Pos (1U)
hudakz	0:a04710facbb6	10036	#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	10037	#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /!< Debug Stop Mode /
hudakz	0:a04710facbb6	10038	#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
hudakz	0:a04710facbb6	10039	#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	10040	#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /!< Debug Standby mode /
hudakz	0:a04710facbb6	10041	#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
hudakz	0:a04710facbb6	10042	#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	10043	#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /!< Trace Pin Assignment Control /
hudakz	0:a04710facbb6	10044
hudakz	0:a04710facbb6	10045	#define DBGMCU_CR_TRACE_MODE_Pos (6U)
hudakz	0:a04710facbb6	10046	#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /!< 0x000000C0 /
hudakz	0:a04710facbb6	10047	#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) /
hudakz	0:a04710facbb6	10048	#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	10049	#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	10050
hudakz	0:a04710facbb6	10051	#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
hudakz	0:a04710facbb6	10052	#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /!< 0x00000100 /
hudakz	0:a04710facbb6	10053	#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /!< Debug Independent Watchdog stopped when Core is halted /
hudakz	0:a04710facbb6	10054	#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
hudakz	0:a04710facbb6	10055	#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	10056	#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /!< Debug Window Watchdog stopped when Core is halted /
hudakz	0:a04710facbb6	10057	#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
hudakz	0:a04710facbb6	10058	#define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	10059	#define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /!< TIM1 counter stopped when core is halted /
hudakz	0:a04710facbb6	10060	#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
hudakz	0:a04710facbb6	10061	#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /!< 0x00000800 /
hudakz	0:a04710facbb6	10062	#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /!< TIM2 counter stopped when core is halted /
hudakz	0:a04710facbb6	10063	#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
hudakz	0:a04710facbb6	10064	#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	10065	#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /!< TIM3 counter stopped when core is halted /
hudakz	0:a04710facbb6	10066	#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
hudakz	0:a04710facbb6	10067	#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /!< 0x00002000 /
hudakz	0:a04710facbb6	10068	#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /!< TIM4 counter stopped when core is halted /
hudakz	0:a04710facbb6	10069	#define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U)
hudakz	0:a04710facbb6	10070	#define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN1_STOP_Pos) /!< 0x00004000 /
hudakz	0:a04710facbb6	10071	#define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /!< Debug CAN1 stopped when Core is halted /
hudakz	0:a04710facbb6	10072	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
hudakz	0:a04710facbb6	10073	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /!< 0x00008000 /
hudakz	0:a04710facbb6	10074	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /!< SMBUS timeout mode stopped when Core is halted /
hudakz	0:a04710facbb6	10075	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
hudakz	0:a04710facbb6	10076	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /!< 0x00010000 /
hudakz	0:a04710facbb6	10077	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /!< SMBUS timeout mode stopped when Core is halted /
hudakz	0:a04710facbb6	10078
hudakz	0:a04710facbb6	10079	/******************************************************************************/
hudakz	0:a04710facbb6	10080	/* */
hudakz	0:a04710facbb6	10081	/* FLASH and Option Bytes Registers */
hudakz	0:a04710facbb6	10082	/* */
hudakz	0:a04710facbb6	10083	/******************************************************************************/
hudakz	0:a04710facbb6	10084	/***************** Bit definition for FLASH_ACR register ****************/
hudakz	0:a04710facbb6	10085	#define FLASH_ACR_LATENCY_Pos (0U)
hudakz	0:a04710facbb6	10086	#define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /!< 0x00000007 /
hudakz	0:a04710facbb6	10087	#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /!< LATENCY[2:0] bits (Latency) /
hudakz	0:a04710facbb6	10088	#define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	10089	#define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	10090	#define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	10091
hudakz	0:a04710facbb6	10092	#define FLASH_ACR_HLFCYA_Pos (3U)
hudakz	0:a04710facbb6	10093	#define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	10094	#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /!< Flash Half Cycle Access Enable /
hudakz	0:a04710facbb6	10095	#define FLASH_ACR_PRFTBE_Pos (4U)
hudakz	0:a04710facbb6	10096	#define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	10097	#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /!< Prefetch Buffer Enable /
hudakz	0:a04710facbb6	10098	#define FLASH_ACR_PRFTBS_Pos (5U)
hudakz	0:a04710facbb6	10099	#define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	10100	#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /!< Prefetch Buffer Status /
hudakz	0:a04710facbb6	10101
hudakz	0:a04710facbb6	10102	/**************** Bit definition for FLASH_KEYR register ****************/
hudakz	0:a04710facbb6	10103	#define FLASH_KEYR_FKEYR_Pos (0U)
hudakz	0:a04710facbb6	10104	#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /!< 0xFFFFFFFF /
hudakz	0:a04710facbb6	10105	#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /!< FPEC Key /
hudakz	0:a04710facbb6	10106
hudakz	0:a04710facbb6	10107	#define RDP_KEY_Pos (0U)
hudakz	0:a04710facbb6	10108	#define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /!< 0x000000A5 /
hudakz	0:a04710facbb6	10109	#define RDP_KEY RDP_KEY_Msk /!< RDP Key /
hudakz	0:a04710facbb6	10110	#define FLASH_KEY1_Pos (0U)
hudakz	0:a04710facbb6	10111	#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /!< 0x45670123 /
hudakz	0:a04710facbb6	10112	#define FLASH_KEY1 FLASH_KEY1_Msk /!< FPEC Key1 /
hudakz	0:a04710facbb6	10113	#define FLASH_KEY2_Pos (0U)
hudakz	0:a04710facbb6	10114	#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /!< 0xCDEF89AB /
hudakz	0:a04710facbb6	10115	#define FLASH_KEY2 FLASH_KEY2_Msk /!< FPEC Key2 /
hudakz	0:a04710facbb6	10116
hudakz	0:a04710facbb6	10117	/*************** Bit definition for FLASH_OPTKEYR register **************/
hudakz	0:a04710facbb6	10118	#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
hudakz	0:a04710facbb6	10119	#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /!< 0xFFFFFFFF /
hudakz	0:a04710facbb6	10120	#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /!< Option Byte Key /
hudakz	0:a04710facbb6	10121
hudakz	0:a04710facbb6	10122	#define FLASH_OPTKEY1 FLASH_KEY1 /!< Option Byte Key1 /
hudakz	0:a04710facbb6	10123	#define FLASH_OPTKEY2 FLASH_KEY2 /!< Option Byte Key2 /
hudakz	0:a04710facbb6	10124
hudakz	0:a04710facbb6	10125	/**************** Bit definition for FLASH_SR register ******************/
hudakz	0:a04710facbb6	10126	#define FLASH_SR_BSY_Pos (0U)
hudakz	0:a04710facbb6	10127	#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	10128	#define FLASH_SR_BSY FLASH_SR_BSY_Msk /!< Busy /
hudakz	0:a04710facbb6	10129	#define FLASH_SR_PGERR_Pos (2U)
hudakz	0:a04710facbb6	10130	#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	10131	#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /!< Programming Error /
hudakz	0:a04710facbb6	10132	#define FLASH_SR_WRPRTERR_Pos (4U)
hudakz	0:a04710facbb6	10133	#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	10134	#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /!< Write Protection Error /
hudakz	0:a04710facbb6	10135	#define FLASH_SR_EOP_Pos (5U)
hudakz	0:a04710facbb6	10136	#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	10137	#define FLASH_SR_EOP FLASH_SR_EOP_Msk /!< End of operation /
hudakz	0:a04710facbb6	10138
hudakz	0:a04710facbb6	10139	/***************** Bit definition for FLASH_CR register *****************/
hudakz	0:a04710facbb6	10140	#define FLASH_CR_PG_Pos (0U)
hudakz	0:a04710facbb6	10141	#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	10142	#define FLASH_CR_PG FLASH_CR_PG_Msk /!< Programming /
hudakz	0:a04710facbb6	10143	#define FLASH_CR_PER_Pos (1U)
hudakz	0:a04710facbb6	10144	#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	10145	#define FLASH_CR_PER FLASH_CR_PER_Msk /!< Page Erase /
hudakz	0:a04710facbb6	10146	#define FLASH_CR_MER_Pos (2U)
hudakz	0:a04710facbb6	10147	#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	10148	#define FLASH_CR_MER FLASH_CR_MER_Msk /!< Mass Erase /
hudakz	0:a04710facbb6	10149	#define FLASH_CR_OPTPG_Pos (4U)
hudakz	0:a04710facbb6	10150	#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	10151	#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /!< Option Byte Programming /
hudakz	0:a04710facbb6	10152	#define FLASH_CR_OPTER_Pos (5U)
hudakz	0:a04710facbb6	10153	#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /!< 0x00000020 /
hudakz	0:a04710facbb6	10154	#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /!< Option Byte Erase /
hudakz	0:a04710facbb6	10155	#define FLASH_CR_STRT_Pos (6U)
hudakz	0:a04710facbb6	10156	#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /!< 0x00000040 /
hudakz	0:a04710facbb6	10157	#define FLASH_CR_STRT FLASH_CR_STRT_Msk /!< Start /
hudakz	0:a04710facbb6	10158	#define FLASH_CR_LOCK_Pos (7U)
hudakz	0:a04710facbb6	10159	#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /!< 0x00000080 /
hudakz	0:a04710facbb6	10160	#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /!< Lock /
hudakz	0:a04710facbb6	10161	#define FLASH_CR_OPTWRE_Pos (9U)
hudakz	0:a04710facbb6	10162	#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /!< 0x00000200 /
hudakz	0:a04710facbb6	10163	#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /!< Option Bytes Write Enable /
hudakz	0:a04710facbb6	10164	#define FLASH_CR_ERRIE_Pos (10U)
hudakz	0:a04710facbb6	10165	#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /!< 0x00000400 /
hudakz	0:a04710facbb6	10166	#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /!< Error Interrupt Enable /
hudakz	0:a04710facbb6	10167	#define FLASH_CR_EOPIE_Pos (12U)
hudakz	0:a04710facbb6	10168	#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /!< 0x00001000 /
hudakz	0:a04710facbb6	10169	#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /!< End of operation interrupt enable /
hudakz	0:a04710facbb6	10170
hudakz	0:a04710facbb6	10171	/***************** Bit definition for FLASH_AR register *****************/
hudakz	0:a04710facbb6	10172	#define FLASH_AR_FAR_Pos (0U)
hudakz	0:a04710facbb6	10173	#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /!< 0xFFFFFFFF /
hudakz	0:a04710facbb6	10174	#define FLASH_AR_FAR FLASH_AR_FAR_Msk /!< Flash Address /
hudakz	0:a04710facbb6	10175
hudakz	0:a04710facbb6	10176	/**************** Bit definition for FLASH_OBR register *****************/
hudakz	0:a04710facbb6	10177	#define FLASH_OBR_OPTERR_Pos (0U)
hudakz	0:a04710facbb6	10178	#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /!< 0x00000001 /
hudakz	0:a04710facbb6	10179	#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /!< Option Byte Error /
hudakz	0:a04710facbb6	10180	#define FLASH_OBR_RDPRT_Pos (1U)
hudakz	0:a04710facbb6	10181	#define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /!< 0x00000002 /
hudakz	0:a04710facbb6	10182	#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /!< Read protection /
hudakz	0:a04710facbb6	10183
hudakz	0:a04710facbb6	10184	#define FLASH_OBR_IWDG_SW_Pos (2U)
hudakz	0:a04710facbb6	10185	#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /!< 0x00000004 /
hudakz	0:a04710facbb6	10186	#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /!< IWDG SW /
hudakz	0:a04710facbb6	10187	#define FLASH_OBR_nRST_STOP_Pos (3U)
hudakz	0:a04710facbb6	10188	#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /!< 0x00000008 /
hudakz	0:a04710facbb6	10189	#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /!< nRST_STOP /
hudakz	0:a04710facbb6	10190	#define FLASH_OBR_nRST_STDBY_Pos (4U)
hudakz	0:a04710facbb6	10191	#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /!< 0x00000010 /
hudakz	0:a04710facbb6	10192	#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /!< nRST_STDBY /
hudakz	0:a04710facbb6	10193	#define FLASH_OBR_USER_Pos (2U)
hudakz	0:a04710facbb6	10194	#define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /!< 0x0000001C /
hudakz	0:a04710facbb6	10195	#define FLASH_OBR_USER FLASH_OBR_USER_Msk /!< User Option Bytes /
hudakz	0:a04710facbb6	10196	#define FLASH_OBR_DATA0_Pos (10U)
hudakz	0:a04710facbb6	10197	#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /!< 0x0003FC00 /
hudakz	0:a04710facbb6	10198	#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /!< Data0 /
hudakz	0:a04710facbb6	10199	#define FLASH_OBR_DATA1_Pos (18U)
hudakz	0:a04710facbb6	10200	#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /!< 0x03FC0000 /
hudakz	0:a04710facbb6	10201	#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /!< Data1 /
hudakz	0:a04710facbb6	10202
hudakz	0:a04710facbb6	10203	/**************** Bit definition for FLASH_WRPR register ****************/
hudakz	0:a04710facbb6	10204	#define FLASH_WRPR_WRP_Pos (0U)
hudakz	0:a04710facbb6	10205	#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /!< 0xFFFFFFFF /
hudakz	0:a04710facbb6	10206	#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /!< Write Protect /
hudakz	0:a04710facbb6	10207
hudakz	0:a04710facbb6	10208	/----------------------------------------------------------------------------/
hudakz	0:a04710facbb6	10209
hudakz	0:a04710facbb6	10210	/**************** Bit definition for FLASH_RDP register *****************/
hudakz	0:a04710facbb6	10211	#define FLASH_RDP_RDP_Pos (0U)
hudakz	0:a04710facbb6	10212	#define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /!< 0x000000FF /
hudakz	0:a04710facbb6	10213	#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /!< Read protection option byte /
hudakz	0:a04710facbb6	10214	#define FLASH_RDP_nRDP_Pos (8U)
hudakz	0:a04710facbb6	10215	#define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /!< 0x0000FF00 /
hudakz	0:a04710facbb6	10216	#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /!< Read protection complemented option byte /
hudakz	0:a04710facbb6	10217
hudakz	0:a04710facbb6	10218	/**************** Bit definition for FLASH_USER register ****************/
hudakz	0:a04710facbb6	10219	#define FLASH_USER_USER_Pos (16U)
hudakz	0:a04710facbb6	10220	#define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /!< 0x00FF0000 /
hudakz	0:a04710facbb6	10221	#define FLASH_USER_USER FLASH_USER_USER_Msk /!< User option byte /
hudakz	0:a04710facbb6	10222	#define FLASH_USER_nUSER_Pos (24U)
hudakz	0:a04710facbb6	10223	#define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /!< 0xFF000000 /
hudakz	0:a04710facbb6	10224	#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /!< User complemented option byte /
hudakz	0:a04710facbb6	10225
hudakz	0:a04710facbb6	10226	/**************** Bit definition for FLASH_Data0 register ***************/
hudakz	0:a04710facbb6	10227	#define FLASH_DATA0_DATA0_Pos (0U)
hudakz	0:a04710facbb6	10228	#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /!< 0x000000FF /
hudakz	0:a04710facbb6	10229	#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /!< User data storage option byte /
hudakz	0:a04710facbb6	10230	#define FLASH_DATA0_nDATA0_Pos (8U)
hudakz	0:a04710facbb6	10231	#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /!< 0x0000FF00 /
hudakz	0:a04710facbb6	10232	#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /!< User data storage complemented option byte /
hudakz	0:a04710facbb6	10233
hudakz	0:a04710facbb6	10234	/**************** Bit definition for FLASH_Data1 register ***************/
hudakz	0:a04710facbb6	10235	#define FLASH_DATA1_DATA1_Pos (16U)
hudakz	0:a04710facbb6	10236	#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /!< 0x00FF0000 /
hudakz	0:a04710facbb6	10237	#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /!< User data storage option byte /
hudakz	0:a04710facbb6	10238	#define FLASH_DATA1_nDATA1_Pos (24U)
hudakz	0:a04710facbb6	10239	#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /!< 0xFF000000 /
hudakz	0:a04710facbb6	10240	#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /!< User data storage complemented option byte /
hudakz	0:a04710facbb6	10241
hudakz	0:a04710facbb6	10242	/**************** Bit definition for FLASH_WRP0 register ****************/
hudakz	0:a04710facbb6	10243	#define FLASH_WRP0_WRP0_Pos (0U)
hudakz	0:a04710facbb6	10244	#define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /!< 0x000000FF /
hudakz	0:a04710facbb6	10245	#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /!< Flash memory write protection option bytes /
hudakz	0:a04710facbb6	10246	#define FLASH_WRP0_nWRP0_Pos (8U)
hudakz	0:a04710facbb6	10247	#define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /!< 0x0000FF00 /
hudakz	0:a04710facbb6	10248	#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /!< Flash memory write protection complemented option bytes /
hudakz	0:a04710facbb6	10249
hudakz	0:a04710facbb6	10250	/**************** Bit definition for FLASH_WRP1 register ****************/
hudakz	0:a04710facbb6	10251	#define FLASH_WRP1_WRP1_Pos (16U)
hudakz	0:a04710facbb6	10252	#define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /!< 0x00FF0000 /
hudakz	0:a04710facbb6	10253	#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /!< Flash memory write protection option bytes /
hudakz	0:a04710facbb6	10254	#define FLASH_WRP1_nWRP1_Pos (24U)
hudakz	0:a04710facbb6	10255	#define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /!< 0xFF000000 /
hudakz	0:a04710facbb6	10256	#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /!< Flash memory write protection complemented option bytes /
hudakz	0:a04710facbb6	10257
hudakz	0:a04710facbb6	10258	/**************** Bit definition for FLASH_WRP2 register ****************/
hudakz	0:a04710facbb6	10259	#define FLASH_WRP2_WRP2_Pos (0U)
hudakz	0:a04710facbb6	10260	#define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /!< 0x000000FF /
hudakz	0:a04710facbb6	10261	#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /!< Flash memory write protection option bytes /
hudakz	0:a04710facbb6	10262	#define FLASH_WRP2_nWRP2_Pos (8U)
hudakz	0:a04710facbb6	10263	#define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /!< 0x0000FF00 /
hudakz	0:a04710facbb6	10264	#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /!< Flash memory write protection complemented option bytes /
hudakz	0:a04710facbb6	10265
hudakz	0:a04710facbb6	10266	/**************** Bit definition for FLASH_WRP3 register ****************/
hudakz	0:a04710facbb6	10267	#define FLASH_WRP3_WRP3_Pos (16U)
hudakz	0:a04710facbb6	10268	#define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /!< 0x00FF0000 /
hudakz	0:a04710facbb6	10269	#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /!< Flash memory write protection option bytes /
hudakz	0:a04710facbb6	10270	#define FLASH_WRP3_nWRP3_Pos (24U)
hudakz	0:a04710facbb6	10271	#define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /!< 0xFF000000 /
hudakz	0:a04710facbb6	10272	#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /!< Flash memory write protection complemented option bytes /
hudakz	0:a04710facbb6	10273
hudakz	0:a04710facbb6	10274
hudakz	0:a04710facbb6	10275
hudakz	0:a04710facbb6	10276	/**
hudakz	0:a04710facbb6	10277	* @}
hudakz	0:a04710facbb6	10278	*/
hudakz	0:a04710facbb6	10279
hudakz	0:a04710facbb6	10280	/**
hudakz	0:a04710facbb6	10281	* @}
hudakz	0:a04710facbb6	10282	*/
hudakz	0:a04710facbb6	10283
hudakz	0:a04710facbb6	10284	/** @addtogroup Exported_macro
hudakz	0:a04710facbb6	10285	* @{
hudakz	0:a04710facbb6	10286	*/
hudakz	0:a04710facbb6	10287
hudakz	0:a04710facbb6	10288	/**************************** ADC Instances *******************************/
hudakz	0:a04710facbb6	10289	#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) \|\| \
hudakz	0:a04710facbb6	10290	((INSTANCE) == ADC2))
hudakz	0:a04710facbb6	10291
hudakz	0:a04710facbb6	10292	#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
hudakz	0:a04710facbb6	10293
hudakz	0:a04710facbb6	10294	#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
hudakz	0:a04710facbb6	10295
hudakz	0:a04710facbb6	10296	#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
hudakz	0:a04710facbb6	10297
hudakz	0:a04710facbb6	10298	/**************************** CAN Instances *******************************/
hudakz	0:a04710facbb6	10299	#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
hudakz	0:a04710facbb6	10300
hudakz	0:a04710facbb6	10301	/**************************** CRC Instances *******************************/
hudakz	0:a04710facbb6	10302	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
hudakz	0:a04710facbb6	10303
hudakz	0:a04710facbb6	10304	/**************************** DAC Instances *******************************/
hudakz	0:a04710facbb6	10305
hudakz	0:a04710facbb6	10306	/**************************** DMA Instances *******************************/
hudakz	0:a04710facbb6	10307	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
hudakz	0:a04710facbb6	10308	((INSTANCE) == DMA1_Channel2) \|\| \
hudakz	0:a04710facbb6	10309	((INSTANCE) == DMA1_Channel3) \|\| \
hudakz	0:a04710facbb6	10310	((INSTANCE) == DMA1_Channel4) \|\| \
hudakz	0:a04710facbb6	10311	((INSTANCE) == DMA1_Channel5) \|\| \
hudakz	0:a04710facbb6	10312	((INSTANCE) == DMA1_Channel6) \|\| \
hudakz	0:a04710facbb6	10313	((INSTANCE) == DMA1_Channel7))
hudakz	0:a04710facbb6	10314
hudakz	0:a04710facbb6	10315	/***************************** GPIO Instances *****************************/
hudakz	0:a04710facbb6	10316	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
hudakz	0:a04710facbb6	10317	((INSTANCE) == GPIOB) \|\| \
hudakz	0:a04710facbb6	10318	((INSTANCE) == GPIOC) \|\| \
hudakz	0:a04710facbb6	10319	((INSTANCE) == GPIOD) \|\| \
hudakz	0:a04710facbb6	10320	((INSTANCE) == GPIOE))
hudakz	0:a04710facbb6	10321
hudakz	0:a04710facbb6	10322	/************************** GPIO Alternate Function Instances *************/
hudakz	0:a04710facbb6	10323	#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
hudakz	0:a04710facbb6	10324
hudakz	0:a04710facbb6	10325	/************************** GPIO Lock Instances ***************************/
hudakz	0:a04710facbb6	10326	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
hudakz	0:a04710facbb6	10327
hudakz	0:a04710facbb6	10328	/****************************** I2C Instances *****************************/
hudakz	0:a04710facbb6	10329	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
hudakz	0:a04710facbb6	10330	((INSTANCE) == I2C2))
hudakz	0:a04710facbb6	10331
hudakz	0:a04710facbb6	10332	/***************************** SMBUS Instances ****************************/
hudakz	0:a04710facbb6	10333	#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
hudakz	0:a04710facbb6	10334
hudakz	0:a04710facbb6	10335	/**************************** IWDG Instances ******************************/
hudakz	0:a04710facbb6	10336	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
hudakz	0:a04710facbb6	10337
hudakz	0:a04710facbb6	10338	/****************************** SPI Instances *****************************/
hudakz	0:a04710facbb6	10339	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
hudakz	0:a04710facbb6	10340	((INSTANCE) == SPI2))
hudakz	0:a04710facbb6	10341
hudakz	0:a04710facbb6	10342	/**************************** START TIM Instances *************************/
hudakz	0:a04710facbb6	10343	/**************************** TIM Instances *******************************/
hudakz	0:a04710facbb6	10344	#define IS_TIM_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10345	(((INSTANCE) == TIM1) \|\| \
hudakz	0:a04710facbb6	10346	((INSTANCE) == TIM2) \|\| \
hudakz	0:a04710facbb6	10347	((INSTANCE) == TIM3) \|\| \
hudakz	0:a04710facbb6	10348	((INSTANCE) == TIM4))
hudakz	0:a04710facbb6	10349
hudakz	0:a04710facbb6	10350	#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
hudakz	0:a04710facbb6	10351
hudakz	0:a04710facbb6	10352	#define IS_TIM_CC1_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10353	(((INSTANCE) == TIM1) \|\| \
hudakz	0:a04710facbb6	10354	((INSTANCE) == TIM2) \|\| \
hudakz	0:a04710facbb6	10355	((INSTANCE) == TIM3) \|\| \
hudakz	0:a04710facbb6	10356	((INSTANCE) == TIM4))
hudakz	0:a04710facbb6	10357
hudakz	0:a04710facbb6	10358	#define IS_TIM_CC2_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10359	(((INSTANCE) == TIM1) \|\| \
hudakz	0:a04710facbb6	10360	((INSTANCE) == TIM2) \|\| \
hudakz	0:a04710facbb6	10361	((INSTANCE) == TIM3) \|\| \
hudakz	0:a04710facbb6	10362	((INSTANCE) == TIM4))
hudakz	0:a04710facbb6	10363
hudakz	0:a04710facbb6	10364	#define IS_TIM_CC3_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10365	(((INSTANCE) == TIM1) \|\| \
hudakz	0:a04710facbb6	10366	((INSTANCE) == TIM2) \|\| \
hudakz	0:a04710facbb6	10367	((INSTANCE) == TIM3) \|\| \
hudakz	0:a04710facbb6	10368	((INSTANCE) == TIM4))
hudakz	0:a04710facbb6	10369
hudakz	0:a04710facbb6	10370	#define IS_TIM_CC4_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10371	(((INSTANCE) == TIM1) \|\| \
hudakz	0:a04710facbb6	10372	((INSTANCE) == TIM2) \|\| \
hudakz	0:a04710facbb6	10373	((INSTANCE) == TIM3) \|\| \
hudakz	0:a04710facbb6	10374	((INSTANCE) == TIM4))
hudakz	0:a04710facbb6	10375
hudakz	0:a04710facbb6	10376	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10377	(((INSTANCE) == TIM1) \|\| \
hudakz	0:a04710facbb6	10378	((INSTANCE) == TIM2) \|\| \
hudakz	0:a04710facbb6	10379	((INSTANCE) == TIM3) \|\| \
hudakz	0:a04710facbb6	10380	((INSTANCE) == TIM4))
hudakz	0:a04710facbb6	10381
hudakz	0:a04710facbb6	10382	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10383	(((INSTANCE) == TIM1) \|\| \
hudakz	0:a04710facbb6	10384	((INSTANCE) == TIM2) \|\| \
hudakz	0:a04710facbb6	10385	((INSTANCE) == TIM3) \|\| \
hudakz	0:a04710facbb6	10386	((INSTANCE) == TIM4))
hudakz	0:a04710facbb6	10387
hudakz	0:a04710facbb6	10388	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10389	(((INSTANCE) == TIM1) \|\| \
hudakz	0:a04710facbb6	10390	((INSTANCE) == TIM2) \|\| \
hudakz	0:a04710facbb6	10391	((INSTANCE) == TIM3) \|\| \
hudakz	0:a04710facbb6	10392	((INSTANCE) == TIM4))
hudakz	0:a04710facbb6	10393
hudakz	0:a04710facbb6	10394	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10395	(((INSTANCE) == TIM1) \|\| \
hudakz	0:a04710facbb6	10396	((INSTANCE) == TIM2) \|\| \
hudakz	0:a04710facbb6	10397	((INSTANCE) == TIM3) \|\| \
hudakz	0:a04710facbb6	10398	((INSTANCE) == TIM4))
hudakz	0:a04710facbb6	10399
hudakz	0:a04710facbb6	10400	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10401	(((INSTANCE) == TIM1) \|\| \
hudakz	0:a04710facbb6	10402	((INSTANCE) == TIM2) \|\| \
hudakz	0:a04710facbb6	10403	((INSTANCE) == TIM3) \|\| \
hudakz	0:a04710facbb6	10404	((INSTANCE) == TIM4))
hudakz	0:a04710facbb6	10405
hudakz	0:a04710facbb6	10406	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10407	(((INSTANCE) == TIM1) \|\| \
hudakz	0:a04710facbb6	10408	((INSTANCE) == TIM2) \|\| \
hudakz	0:a04710facbb6	10409	((INSTANCE) == TIM3) \|\| \
hudakz	0:a04710facbb6	10410	((INSTANCE) == TIM4))
hudakz	0:a04710facbb6	10411
hudakz	0:a04710facbb6	10412	#define IS_TIM_XOR_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10413	(((INSTANCE) == TIM1) \|\| \
hudakz	0:a04710facbb6	10414	((INSTANCE) == TIM2) \|\| \
hudakz	0:a04710facbb6	10415	((INSTANCE) == TIM3) \|\| \
hudakz	0:a04710facbb6	10416	((INSTANCE) == TIM4))
hudakz	0:a04710facbb6	10417
hudakz	0:a04710facbb6	10418	#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10419	(((INSTANCE) == TIM1) \|\| \
hudakz	0:a04710facbb6	10420	((INSTANCE) == TIM2) \|\| \
hudakz	0:a04710facbb6	10421	((INSTANCE) == TIM3) \|\| \
hudakz	0:a04710facbb6	10422	((INSTANCE) == TIM4))
hudakz	0:a04710facbb6	10423
hudakz	0:a04710facbb6	10424	#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10425	(((INSTANCE) == TIM1) \|\| \
hudakz	0:a04710facbb6	10426	((INSTANCE) == TIM2) \|\| \
hudakz	0:a04710facbb6	10427	((INSTANCE) == TIM3) \|\| \
hudakz	0:a04710facbb6	10428	((INSTANCE) == TIM4))
hudakz	0:a04710facbb6	10429
hudakz	0:a04710facbb6	10430	#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10431	(((INSTANCE) == TIM1) \|\| \
hudakz	0:a04710facbb6	10432	((INSTANCE) == TIM2) \|\| \
hudakz	0:a04710facbb6	10433	((INSTANCE) == TIM3) \|\| \
hudakz	0:a04710facbb6	10434	((INSTANCE) == TIM4))
hudakz	0:a04710facbb6	10435
hudakz	0:a04710facbb6	10436	#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10437	((INSTANCE) == TIM1)
hudakz	0:a04710facbb6	10438
hudakz	0:a04710facbb6	10439	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
hudakz	0:a04710facbb6	10440	((((INSTANCE) == TIM1) && \
hudakz	0:a04710facbb6	10441	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
hudakz	0:a04710facbb6	10442	((CHANNEL) == TIM_CHANNEL_2) \|\| \
hudakz	0:a04710facbb6	10443	((CHANNEL) == TIM_CHANNEL_3) \|\| \
hudakz	0:a04710facbb6	10444	((CHANNEL) == TIM_CHANNEL_4))) \
hudakz	0:a04710facbb6	10445	\|\| \
hudakz	0:a04710facbb6	10446	(((INSTANCE) == TIM2) && \
hudakz	0:a04710facbb6	10447	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
hudakz	0:a04710facbb6	10448	((CHANNEL) == TIM_CHANNEL_2) \|\| \
hudakz	0:a04710facbb6	10449	((CHANNEL) == TIM_CHANNEL_3) \|\| \
hudakz	0:a04710facbb6	10450	((CHANNEL) == TIM_CHANNEL_4))) \
hudakz	0:a04710facbb6	10451	\|\| \
hudakz	0:a04710facbb6	10452	(((INSTANCE) == TIM3) && \
hudakz	0:a04710facbb6	10453	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
hudakz	0:a04710facbb6	10454	((CHANNEL) == TIM_CHANNEL_2) \|\| \
hudakz	0:a04710facbb6	10455	((CHANNEL) == TIM_CHANNEL_3) \|\| \
hudakz	0:a04710facbb6	10456	((CHANNEL) == TIM_CHANNEL_4))) \
hudakz	0:a04710facbb6	10457	\|\| \
hudakz	0:a04710facbb6	10458	(((INSTANCE) == TIM4) && \
hudakz	0:a04710facbb6	10459	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
hudakz	0:a04710facbb6	10460	((CHANNEL) == TIM_CHANNEL_2) \|\| \
hudakz	0:a04710facbb6	10461	((CHANNEL) == TIM_CHANNEL_3) \|\| \
hudakz	0:a04710facbb6	10462	((CHANNEL) == TIM_CHANNEL_4))))
hudakz	0:a04710facbb6	10463
hudakz	0:a04710facbb6	10464	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
hudakz	0:a04710facbb6	10465	(((INSTANCE) == TIM1) && \
hudakz	0:a04710facbb6	10466	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
hudakz	0:a04710facbb6	10467	((CHANNEL) == TIM_CHANNEL_2) \|\| \
hudakz	0:a04710facbb6	10468	((CHANNEL) == TIM_CHANNEL_3)))
hudakz	0:a04710facbb6	10469
hudakz	0:a04710facbb6	10470	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10471	(((INSTANCE) == TIM1) \|\| \
hudakz	0:a04710facbb6	10472	((INSTANCE) == TIM2) \|\| \
hudakz	0:a04710facbb6	10473	((INSTANCE) == TIM3) \|\| \
hudakz	0:a04710facbb6	10474	((INSTANCE) == TIM4))
hudakz	0:a04710facbb6	10475
hudakz	0:a04710facbb6	10476	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10477	((INSTANCE) == TIM1)
hudakz	0:a04710facbb6	10478
hudakz	0:a04710facbb6	10479	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10480	(((INSTANCE) == TIM1) \|\| \
hudakz	0:a04710facbb6	10481	((INSTANCE) == TIM2) \|\| \
hudakz	0:a04710facbb6	10482	((INSTANCE) == TIM3) \|\| \
hudakz	0:a04710facbb6	10483	((INSTANCE) == TIM4))
hudakz	0:a04710facbb6	10484
hudakz	0:a04710facbb6	10485	#define IS_TIM_DMA_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10486	(((INSTANCE) == TIM1) \|\| \
hudakz	0:a04710facbb6	10487	((INSTANCE) == TIM2) \|\| \
hudakz	0:a04710facbb6	10488	((INSTANCE) == TIM3) \|\| \
hudakz	0:a04710facbb6	10489	((INSTANCE) == TIM4))
hudakz	0:a04710facbb6	10490
hudakz	0:a04710facbb6	10491	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10492	(((INSTANCE) == TIM1) \|\| \
hudakz	0:a04710facbb6	10493	((INSTANCE) == TIM2) \|\| \
hudakz	0:a04710facbb6	10494	((INSTANCE) == TIM3) \|\| \
hudakz	0:a04710facbb6	10495	((INSTANCE) == TIM4))
hudakz	0:a04710facbb6	10496
hudakz	0:a04710facbb6	10497	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
hudakz	0:a04710facbb6	10498	((INSTANCE) == TIM1)
hudakz	0:a04710facbb6	10499
hudakz	0:a04710facbb6	10500	#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
hudakz	0:a04710facbb6	10501	((INSTANCE) == TIM2) \|\| \
hudakz	0:a04710facbb6	10502	((INSTANCE) == TIM3) \|\| \
hudakz	0:a04710facbb6	10503	((INSTANCE) == TIM4))
hudakz	0:a04710facbb6	10504
hudakz	0:a04710facbb6	10505	#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
hudakz	0:a04710facbb6	10506	((INSTANCE) == TIM2) \|\| \
hudakz	0:a04710facbb6	10507	((INSTANCE) == TIM3) \|\| \
hudakz	0:a04710facbb6	10508	((INSTANCE) == TIM4))
hudakz	0:a04710facbb6	10509
hudakz	0:a04710facbb6	10510	#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
hudakz	0:a04710facbb6	10511
hudakz	0:a04710facbb6	10512	/**************************** END TIM Instances ***************************/
hudakz	0:a04710facbb6	10513
hudakz	0:a04710facbb6	10514
hudakz	0:a04710facbb6	10515	/****************** USART Instances : Synchronous mode ********************/
hudakz	0:a04710facbb6	10516	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
hudakz	0:a04710facbb6	10517	((INSTANCE) == USART2) \|\| \
hudakz	0:a04710facbb6	10518	((INSTANCE) == USART3))
hudakz	0:a04710facbb6	10519
hudakz	0:a04710facbb6	10520	/****************** UART Instances : Asynchronous mode ********************/
hudakz	0:a04710facbb6	10521	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
hudakz	0:a04710facbb6	10522	((INSTANCE) == USART2) \|\| \
hudakz	0:a04710facbb6	10523	((INSTANCE) == USART3))
hudakz	0:a04710facbb6	10524
hudakz	0:a04710facbb6	10525	/****************** UART Instances : Half-Duplex mode ********************/
hudakz	0:a04710facbb6	10526	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
hudakz	0:a04710facbb6	10527	((INSTANCE) == USART2) \|\| \
hudakz	0:a04710facbb6	10528	((INSTANCE) == USART3))
hudakz	0:a04710facbb6	10529
hudakz	0:a04710facbb6	10530	/****************** UART Instances : LIN mode ********************/
hudakz	0:a04710facbb6	10531	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
hudakz	0:a04710facbb6	10532	((INSTANCE) == USART2) \|\| \
hudakz	0:a04710facbb6	10533	((INSTANCE) == USART3))
hudakz	0:a04710facbb6	10534
hudakz	0:a04710facbb6	10535	/**************** UART Instances : Hardware Flow control ******************/
hudakz	0:a04710facbb6	10536	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
hudakz	0:a04710facbb6	10537	((INSTANCE) == USART2) \|\| \
hudakz	0:a04710facbb6	10538	((INSTANCE) == USART3))
hudakz	0:a04710facbb6	10539
hudakz	0:a04710facbb6	10540	/******************* UART Instances : Smard card mode *********************/
hudakz	0:a04710facbb6	10541	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
hudakz	0:a04710facbb6	10542	((INSTANCE) == USART2) \|\| \
hudakz	0:a04710facbb6	10543	((INSTANCE) == USART3))
hudakz	0:a04710facbb6	10544
hudakz	0:a04710facbb6	10545	/********************* UART Instances : IRDA mode *************************/
hudakz	0:a04710facbb6	10546	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
hudakz	0:a04710facbb6	10547	((INSTANCE) == USART2) \|\| \
hudakz	0:a04710facbb6	10548	((INSTANCE) == USART3))
hudakz	0:a04710facbb6	10549
hudakz	0:a04710facbb6	10550	/*************** UART Instances : Multi-Processor mode ********************/
hudakz	0:a04710facbb6	10551	#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
hudakz	0:a04710facbb6	10552	((INSTANCE) == USART2) \|\| \
hudakz	0:a04710facbb6	10553	((INSTANCE) == USART3))
hudakz	0:a04710facbb6	10554
hudakz	0:a04710facbb6	10555	/*************** UART Instances : DMA mode available ********************/
hudakz	0:a04710facbb6	10556	#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
hudakz	0:a04710facbb6	10557	((INSTANCE) == USART2) \|\| \
hudakz	0:a04710facbb6	10558	((INSTANCE) == USART3))
hudakz	0:a04710facbb6	10559
hudakz	0:a04710facbb6	10560	/**************************** RTC Instances *******************************/
hudakz	0:a04710facbb6	10561	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
hudakz	0:a04710facbb6	10562
hudakz	0:a04710facbb6	10563	/************************** WWDG Instances ***************************/
hudakz	0:a04710facbb6	10564	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
hudakz	0:a04710facbb6	10565
hudakz	0:a04710facbb6	10566	/**************************** USB Instances ******************************/
hudakz	0:a04710facbb6	10567	#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
hudakz	0:a04710facbb6	10568
hudakz	0:a04710facbb6	10569
hudakz	0:a04710facbb6	10570
hudakz	0:a04710facbb6	10571	#define RCC_HSE_MIN 4000000U
hudakz	0:a04710facbb6	10572	#define RCC_HSE_MAX 16000000U
hudakz	0:a04710facbb6	10573
hudakz	0:a04710facbb6	10574	#define RCC_MAX_FREQUENCY 72000000U
hudakz	0:a04710facbb6	10575
hudakz	0:a04710facbb6	10576	/**
hudakz	0:a04710facbb6	10577	* @}
hudakz	0:a04710facbb6	10578	*/
hudakz	0:a04710facbb6	10579	/******************************************************************************/
hudakz	0:a04710facbb6	10580	/* For a painless codes migration between the STM32F1xx device product */
hudakz	0:a04710facbb6	10581	/* lines, the aliases defined below are put in place to overcome the */
hudakz	0:a04710facbb6	10582	/* differences in the interrupt handlers and IRQn definitions. */
hudakz	0:a04710facbb6	10583	/* No need to update developed interrupt code when moving across */
hudakz	0:a04710facbb6	10584	/* product lines within the same STM32F1 Family */
hudakz	0:a04710facbb6	10585	/******************************************************************************/
hudakz	0:a04710facbb6	10586
hudakz	0:a04710facbb6	10587	/* Aliases for __IRQn */
hudakz	0:a04710facbb6	10588	#define ADC1_IRQn ADC1_2_IRQn
hudakz	0:a04710facbb6	10589	#define TIM9_IRQn TIM1_BRK_IRQn
hudakz	0:a04710facbb6	10590	#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
hudakz	0:a04710facbb6	10591	#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
hudakz	0:a04710facbb6	10592	#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
hudakz	0:a04710facbb6	10593	#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
hudakz	0:a04710facbb6	10594	#define TIM11_IRQn TIM1_TRG_COM_IRQn
hudakz	0:a04710facbb6	10595	#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
hudakz	0:a04710facbb6	10596	#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
hudakz	0:a04710facbb6	10597	#define TIM10_IRQn TIM1_UP_IRQn
hudakz	0:a04710facbb6	10598	#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
hudakz	0:a04710facbb6	10599	#define CEC_IRQn USBWakeUp_IRQn
hudakz	0:a04710facbb6	10600	#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
hudakz	0:a04710facbb6	10601	#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
hudakz	0:a04710facbb6	10602	#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
hudakz	0:a04710facbb6	10603	#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
hudakz	0:a04710facbb6	10604
hudakz	0:a04710facbb6	10605
hudakz	0:a04710facbb6	10606	/* Aliases for __IRQHandler */
hudakz	0:a04710facbb6	10607	#define ADC1_IRQHandler ADC1_2_IRQHandler
hudakz	0:a04710facbb6	10608	#define TIM9_IRQHandler TIM1_BRK_IRQHandler
hudakz	0:a04710facbb6	10609	#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
hudakz	0:a04710facbb6	10610	#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
hudakz	0:a04710facbb6	10611	#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
hudakz	0:a04710facbb6	10612	#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
hudakz	0:a04710facbb6	10613	#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
hudakz	0:a04710facbb6	10614	#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
hudakz	0:a04710facbb6	10615	#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
hudakz	0:a04710facbb6	10616	#define TIM10_IRQHandler TIM1_UP_IRQHandler
hudakz	0:a04710facbb6	10617	#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
hudakz	0:a04710facbb6	10618	#define CEC_IRQHandler USBWakeUp_IRQHandler
hudakz	0:a04710facbb6	10619	#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
hudakz	0:a04710facbb6	10620	#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
hudakz	0:a04710facbb6	10621	#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
hudakz	0:a04710facbb6	10622	#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
hudakz	0:a04710facbb6	10623
hudakz	0:a04710facbb6	10624
hudakz	0:a04710facbb6	10625	/**
hudakz	0:a04710facbb6	10626	* @}
hudakz	0:a04710facbb6	10627	*/
hudakz	0:a04710facbb6	10628
hudakz	0:a04710facbb6	10629	/**
hudakz	0:a04710facbb6	10630	* @}
hudakz	0:a04710facbb6	10631	*/
hudakz	0:a04710facbb6	10632
hudakz	0:a04710facbb6	10633
hudakz	0:a04710facbb6	10634	#ifdef __cplusplus
hudakz	0:a04710facbb6	10635	}
hudakz	0:a04710facbb6	10636	#endif /* __cplusplus */
hudakz	0:a04710facbb6	10637
hudakz	0:a04710facbb6	10638	#endif /* __STM32F103xB_H */
hudakz	0:a04710facbb6	10639
hudakz	0:a04710facbb6	10640
hudakz	0:a04710facbb6	10641
hudakz	0:a04710facbb6	10642	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Mbed OS support:	Mbed OS
Created:	14 May 2020
Imports:	18
Forks:	0
Commits:	4
Dependents:	0
Dependencies:	0
Followers:	3

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TARGET_BLUEPILL/device/stm32f103xb.h@3:90a9ecd02b47, 2020-06-04 (annotated)

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