Takuya Urakawa / F401RE-USBHost

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Dependencies:   FATFileSystem

Dependents:   F401RE-USBHostMIDI_RecieveExample

Fork of F401RE-USBHost by Norimasa Okamoto

USBHostMIDI/CircBuffer.h@23:9c1d09c6a2b6, 2014-09-17 (annotated)

Committer:
hsgw
Date:
Wed Sep 17 14:29:11 2014 +0000
Revision:
23:9c1d09c6a2b6
Parent:
18:bac56d0365e1 
revert rev20

Who changed what in which revision?

UserRevisionLine numberNew contents of line
hsgw 18:bac56d0365e1 1 /* USBHostMidi library
hsgw 18:bac56d0365e1 2 * Originaled by k.shoji
hsgw 18:bac56d0365e1 3 * porting by Takuya Urakawa
hsgw 18:bac56d0365e1 4 */
hsgw 18:bac56d0365e1 5
hsgw 18:bac56d0365e1 6 /* mbed USBHost Library
hsgw 18:bac56d0365e1 7 * Copyright (c) 2006-2013 ARM Limited
hsgw 18:bac56d0365e1 8 *
hsgw 18:bac56d0365e1 9 * Licensed under the Apache License, Version 2.0 (the "License");
hsgw 18:bac56d0365e1 10 * you may not use this file except in compliance with the License.
hsgw 18:bac56d0365e1 11 * You may obtain a copy of the License at
hsgw 18:bac56d0365e1 12 *
hsgw 18:bac56d0365e1 13 * http://www.apache.org/licenses/LICENSE-2.0
hsgw 18:bac56d0365e1 14 *
hsgw 18:bac56d0365e1 15 * Unless required by applicable law or agreed to in writing, software
hsgw 18:bac56d0365e1 16 * distributed under the License is distributed on an "AS IS" BASIS,
hsgw 18:bac56d0365e1 17 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
hsgw 18:bac56d0365e1 18 * See the License for the specific language governing permissions and
hsgw 18:bac56d0365e1 19 * limitations under the License.
hsgw 18:bac56d0365e1 20 */
hsgw 18:bac56d0365e1 21
hsgw 18:bac56d0365e1 22 #ifndef CIRCBUFFER_H
hsgw 18:bac56d0365e1 23 #define CIRCBUFFER_H
hsgw 18:bac56d0365e1 24
hsgw 18:bac56d0365e1 25 #include "stdint.h"
hsgw 18:bac56d0365e1 26
hsgw 18:bac56d0365e1 27 //circular buffer
hsgw 18:bac56d0365e1 28 template<typename T, int size>
hsgw 18:bac56d0365e1 29 class CircBuffer {
hsgw 18:bac56d0365e1 30 public:
hsgw 18:bac56d0365e1 31
hsgw 18:bac56d0365e1 32 CircBuffer() {
hsgw 18:bac56d0365e1 33 write = 0;
hsgw 18:bac56d0365e1 34 read = 0;
hsgw 18:bac56d0365e1 35 }
hsgw 18:bac56d0365e1 36
hsgw 18:bac56d0365e1 37 bool isFull() {
hsgw 18:bac56d0365e1 38 bool r = (((write + 1) % size) == read);
hsgw 18:bac56d0365e1 39 return r;
hsgw 18:bac56d0365e1 40 }
hsgw 18:bac56d0365e1 41
hsgw 18:bac56d0365e1 42 bool isEmpty() {
hsgw 18:bac56d0365e1 43 bool r = (read == write);
hsgw 18:bac56d0365e1 44 return r;
hsgw 18:bac56d0365e1 45 }
hsgw 18:bac56d0365e1 46
hsgw 18:bac56d0365e1 47 void flush() {
hsgw 18:bac56d0365e1 48 write = 0;
hsgw 18:bac56d0365e1 49 read = 0;
hsgw 18:bac56d0365e1 50 }
hsgw 18:bac56d0365e1 51
hsgw 18:bac56d0365e1 52 void queue(T k) {
hsgw 18:bac56d0365e1 53 while (((write + 1) % size) == read) {
hsgw 18:bac56d0365e1 54 wait_ms(10);
hsgw 18:bac56d0365e1 55 }
hsgw 18:bac56d0365e1 56 buf[write++] = k;
hsgw 18:bac56d0365e1 57 write %= size;
hsgw 18:bac56d0365e1 58 }
hsgw 18:bac56d0365e1 59
hsgw 18:bac56d0365e1 60 uint16_t available() {
hsgw 18:bac56d0365e1 61 uint16_t a = (write >= read) ? (write - read) : (size - read + write);
hsgw 18:bac56d0365e1 62 return a;
hsgw 18:bac56d0365e1 63 }
hsgw 18:bac56d0365e1 64
hsgw 18:bac56d0365e1 65 bool dequeue(T * c) {
hsgw 18:bac56d0365e1 66 bool empty = (read == write);
hsgw 18:bac56d0365e1 67 if (!empty) {
hsgw 18:bac56d0365e1 68 *c = buf[read++];
hsgw 18:bac56d0365e1 69 read %= size;
hsgw 18:bac56d0365e1 70 }
hsgw 18:bac56d0365e1 71 return (!empty);
hsgw 18:bac56d0365e1 72 }
hsgw 18:bac56d0365e1 73
hsgw 18:bac56d0365e1 74 private:
hsgw 18:bac56d0365e1 75 volatile uint16_t write;
hsgw 18:bac56d0365e1 76 volatile uint16_t read;
hsgw 18:bac56d0365e1 77 volatile T buf[size];
hsgw 18:bac56d0365e1 78 };
hsgw 18:bac56d0365e1 79
hsgw 18:bac56d0365e1 80 #endif