Ian Kilburn / VL53L0X

Simple library for VL53L0X ToF Sensor

Dependents:   4012Code PWM

VL53L0X.cpp@0:aae0c331fe7e, 2017-02-26 (annotated)

Committer:
highroads
Date:
Sun Feb 26 12:45:46 2017 +0000
Revision:
0:aae0c331fe7e
Library for VL53L0X

Who changed what in which revision?

UserRevisionLine numberNew contents of line
highroads 0:aae0c331fe7e 1 /// Most of the functionality of this library is based on the VL53L0X API
highroads 0:aae0c331fe7e 2 // provided by ST (STSW-IMG005), and some of the explanatory comments are quoted
highroads 0:aae0c331fe7e 3 // or paraphrased from the API source code, API user manual (UM2039), and the
highroads 0:aae0c331fe7e 4 // VL53L0X datasheet.
highroads 0:aae0c331fe7e 5
highroads 0:aae0c331fe7e 6 #include "VL53L0X.h"
highroads 0:aae0c331fe7e 7 #include "mbed.h"
highroads 0:aae0c331fe7e 8 // Defines /////////////////////////////////////////////////////////////////////
highroads 0:aae0c331fe7e 9
highroads 0:aae0c331fe7e 10 // The Arduino two-wire interface uses a 7-bit number for the address,
highroads 0:aae0c331fe7e 11 // and sets the last bit correctly based on reads and writes
highroads 0:aae0c331fe7e 12 #define ADDRESS_DEFAULT 0b0101001 << 1
highroads 0:aae0c331fe7e 13
highroads 0:aae0c331fe7e 14 // Record the current time to check an upcoming timeout against
highroads 0:aae0c331fe7e 15 #define startTimeout() (timeout_start_ms = 0)
highroads 0:aae0c331fe7e 16
highroads 0:aae0c331fe7e 17 // Check if timeout is enabled (set to nonzero value) and has expired
highroads 0:aae0c331fe7e 18 #define checkTimeoutExpired() (io_timeout > 0 && ((uint16_t)10 - timeout_start_ms) > io_timeout)
highroads 0:aae0c331fe7e 19
highroads 0:aae0c331fe7e 20 // Decode VCSEL (vertical cavity surface emitting laser) pulse period in PCLKs
highroads 0:aae0c331fe7e 21 // from register value
highroads 0:aae0c331fe7e 22 // based on VL53L0X_decode_vcsel_period()
highroads 0:aae0c331fe7e 23 #define decodeVcselPeriod(reg_val) (((reg_val) + 1) << 1)
highroads 0:aae0c331fe7e 24
highroads 0:aae0c331fe7e 25 // Encode VCSEL pulse period register value from period in PCLKs
highroads 0:aae0c331fe7e 26 // based on VL53L0X_encode_vcsel_period()
highroads 0:aae0c331fe7e 27 #define encodeVcselPeriod(period_pclks) (((period_pclks) >> 1) - 1)
highroads 0:aae0c331fe7e 28
highroads 0:aae0c331fe7e 29 // Calculate macro period in *nanoseconds* from VCSEL period in PCLKs
highroads 0:aae0c331fe7e 30 // based on VL53L0X_calc_macro_period_ps()
highroads 0:aae0c331fe7e 31 // PLL_period_ps = 1655; macro_period_vclks = 2304
highroads 0:aae0c331fe7e 32 #define calcMacroPeriod(vcsel_period_pclks) ((((uint32_t)2304 * (vcsel_period_pclks) * 1655) + 500) / 1000)
highroads 0:aae0c331fe7e 33
highroads 0:aae0c331fe7e 34 // Constructors ////////////////////////////////////////////////////////////////
highroads 0:aae0c331fe7e 35
highroads 0:aae0c331fe7e 36 VL53L0X::VL53L0X(PinName sda, PinName scl) : m_i2c(sda,scl),m_addr(ADDRESS_DEFAULT), io_timeout(0) // no timeout
highroads 0:aae0c331fe7e 37 , did_timeout(false)
highroads 0:aae0c331fe7e 38 {
highroads 0:aae0c331fe7e 39 }
highroads 0:aae0c331fe7e 40
highroads 0:aae0c331fe7e 41 // Public Methods //////////////////////////////////////////////////////////////
highroads 0:aae0c331fe7e 42
highroads 0:aae0c331fe7e 43 void VL53L0X::setAddress(uint8_t new_addr)
highroads 0:aae0c331fe7e 44 {
highroads 0:aae0c331fe7e 45 writeReg(I2C_SLAVE_DEVICE_ADDRESS, new_addr & 0x7F);
highroads 0:aae0c331fe7e 46 address = new_addr;
highroads 0:aae0c331fe7e 47 }
highroads 0:aae0c331fe7e 48
highroads 0:aae0c331fe7e 49 // Initialize sensor using sequence based on VL53L0X_DataInit(),
highroads 0:aae0c331fe7e 50 // VL53L0X_StaticInit(), and VL53L0X_PerformRefCalibration().
highroads 0:aae0c331fe7e 51 // This function does not perform reference SPAD calibration
highroads 0:aae0c331fe7e 52 // (VL53L0X_PerformRefSpadManagement()), since the API user manual says that it
highroads 0:aae0c331fe7e 53 // is performed by ST on the bare modules; it seems like that should work well
highroads 0:aae0c331fe7e 54 // enough unless a cover glass is added.
highroads 0:aae0c331fe7e 55 // If io_2v8 (optional) is true or not given, the sensor is configured for 2V8
highroads 0:aae0c331fe7e 56 // mode.
highroads 0:aae0c331fe7e 57 bool VL53L0X::init(bool io_2v8)
highroads 0:aae0c331fe7e 58 {
highroads 0:aae0c331fe7e 59 // VL53L0X_DataInit() begin
highroads 0:aae0c331fe7e 60
highroads 0:aae0c331fe7e 61 // sensor uses 1V8 mode for I/O by default; switch to 2V8 mode if necessary
highroads 0:aae0c331fe7e 62 if (io_2v8)
highroads 0:aae0c331fe7e 63 {
highroads 0:aae0c331fe7e 64 writeReg(VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV,
highroads 0:aae0c331fe7e 65 readReg(VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV) | 0x01); // set bit 0
highroads 0:aae0c331fe7e 66 }
highroads 0:aae0c331fe7e 67
highroads 0:aae0c331fe7e 68 // "Set I2C standard mode"
highroads 0:aae0c331fe7e 69 writeReg(0x88, 0x00);
highroads 0:aae0c331fe7e 70
highroads 0:aae0c331fe7e 71 writeReg(0x80, 0x01);
highroads 0:aae0c331fe7e 72 writeReg(0xFF, 0x01);
highroads 0:aae0c331fe7e 73 writeReg(0x00, 0x00);
highroads 0:aae0c331fe7e 74 stop_variable = readReg(0x91);
highroads 0:aae0c331fe7e 75 writeReg(0x00, 0x01);
highroads 0:aae0c331fe7e 76 writeReg(0xFF, 0x00);
highroads 0:aae0c331fe7e 77 writeReg(0x80, 0x00);
highroads 0:aae0c331fe7e 78
highroads 0:aae0c331fe7e 79 // disable SIGNAL_RATE_MSRC (bit 1) and SIGNAL_RATE_PRE_RANGE (bit 4) limit checks
highroads 0:aae0c331fe7e 80 writeReg(MSRC_CONFIG_CONTROL, readReg(MSRC_CONFIG_CONTROL) | 0x12);
highroads 0:aae0c331fe7e 81
highroads 0:aae0c331fe7e 82 // set final range signal rate limit to 0.25 MCPS (million counts per second)
highroads 0:aae0c331fe7e 83 setSignalRateLimit(0.25);
highroads 0:aae0c331fe7e 84
highroads 0:aae0c331fe7e 85 writeReg(SYSTEM_SEQUENCE_CONFIG, 0xFF);
highroads 0:aae0c331fe7e 86
highroads 0:aae0c331fe7e 87 // VL53L0X_DataInit() end
highroads 0:aae0c331fe7e 88
highroads 0:aae0c331fe7e 89 // VL53L0X_StaticInit() begin
highroads 0:aae0c331fe7e 90
highroads 0:aae0c331fe7e 91 uint8_t spad_count;
highroads 0:aae0c331fe7e 92 bool spad_type_is_aperture;
highroads 0:aae0c331fe7e 93 if (!getSpadInfo(&spad_count, &spad_type_is_aperture)) { return false; }
highroads 0:aae0c331fe7e 94
highroads 0:aae0c331fe7e 95 // The SPAD map (RefGoodSpadMap) is read by VL53L0X_get_info_from_device() in
highroads 0:aae0c331fe7e 96 // the API, but the same data seems to be more easily readable from
highroads 0:aae0c331fe7e 97 // GLOBAL_CONFIG_SPAD_ENABLES_REF_0 through _6, so read it from there
highroads 0:aae0c331fe7e 98 char ref_spad_map[6];
highroads 0:aae0c331fe7e 99 readMulti(GLOBAL_CONFIG_SPAD_ENABLES_REF_0, ref_spad_map, 6);
highroads 0:aae0c331fe7e 100
highroads 0:aae0c331fe7e 101 // -- VL53L0X_set_reference_spads() begin (assume NVM values are valid)
highroads 0:aae0c331fe7e 102
highroads 0:aae0c331fe7e 103 writeReg(0xFF, 0x01);
highroads 0:aae0c331fe7e 104 writeReg(DYNAMIC_SPAD_REF_EN_START_OFFSET, 0x00);
highroads 0:aae0c331fe7e 105 writeReg(DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD, 0x2C);
highroads 0:aae0c331fe7e 106 writeReg(0xFF, 0x00);
highroads 0:aae0c331fe7e 107 writeReg(GLOBAL_CONFIG_REF_EN_START_SELECT, 0xB4);
highroads 0:aae0c331fe7e 108
highroads 0:aae0c331fe7e 109 uint8_t first_spad_to_enable = spad_type_is_aperture ? 12 : 0; // 12 is the first aperture spad
highroads 0:aae0c331fe7e 110 uint8_t spads_enabled = 0;
highroads 0:aae0c331fe7e 111
highroads 0:aae0c331fe7e 112 for (uint8_t i = 0; i < 48; i++)
highroads 0:aae0c331fe7e 113 {
highroads 0:aae0c331fe7e 114 if (i < first_spad_to_enable || spads_enabled == spad_count)
highroads 0:aae0c331fe7e 115 {
highroads 0:aae0c331fe7e 116 // This bit is lower than the first one that should be enabled, or
highroads 0:aae0c331fe7e 117 // (reference_spad_count) bits have already been enabled, so zero this bit
highroads 0:aae0c331fe7e 118 ref_spad_map[i / 8] &= ~(1 << (i % 8));
highroads 0:aae0c331fe7e 119 }
highroads 0:aae0c331fe7e 120 else if ((ref_spad_map[i / 8] >> (i % 8)) & 0x1)
highroads 0:aae0c331fe7e 121 {
highroads 0:aae0c331fe7e 122 spads_enabled++;
highroads 0:aae0c331fe7e 123 }
highroads 0:aae0c331fe7e 124 }
highroads 0:aae0c331fe7e 125
highroads 0:aae0c331fe7e 126 writeMulti(GLOBAL_CONFIG_SPAD_ENABLES_REF_0, ref_spad_map, 6);
highroads 0:aae0c331fe7e 127
highroads 0:aae0c331fe7e 128 // -- VL53L0X_set_reference_spads() end
highroads 0:aae0c331fe7e 129
highroads 0:aae0c331fe7e 130 // -- VL53L0X_load_tuning_settings() begin
highroads 0:aae0c331fe7e 131 // DefaultTuningSettings from vl53l0x_tuning.h
highroads 0:aae0c331fe7e 132
highroads 0:aae0c331fe7e 133 writeReg(0xFF, 0x01);
highroads 0:aae0c331fe7e 134 writeReg(0x00, 0x00);
highroads 0:aae0c331fe7e 135
highroads 0:aae0c331fe7e 136 writeReg(0xFF, 0x00);
highroads 0:aae0c331fe7e 137 writeReg(0x09, 0x00);
highroads 0:aae0c331fe7e 138 writeReg(0x10, 0x00);
highroads 0:aae0c331fe7e 139 writeReg(0x11, 0x00);
highroads 0:aae0c331fe7e 140
highroads 0:aae0c331fe7e 141 writeReg(0x24, 0x01);
highroads 0:aae0c331fe7e 142 writeReg(0x25, 0xFF);
highroads 0:aae0c331fe7e 143 writeReg(0x75, 0x00);
highroads 0:aae0c331fe7e 144
highroads 0:aae0c331fe7e 145 writeReg(0xFF, 0x01);
highroads 0:aae0c331fe7e 146 writeReg(0x4E, 0x2C);
highroads 0:aae0c331fe7e 147 writeReg(0x48, 0x00);
highroads 0:aae0c331fe7e 148 writeReg(0x30, 0x20);
highroads 0:aae0c331fe7e 149
highroads 0:aae0c331fe7e 150 writeReg(0xFF, 0x00);
highroads 0:aae0c331fe7e 151 writeReg(0x30, 0x09);
highroads 0:aae0c331fe7e 152 writeReg(0x54, 0x00);
highroads 0:aae0c331fe7e 153 writeReg(0x31, 0x04);
highroads 0:aae0c331fe7e 154 writeReg(0x32, 0x03);
highroads 0:aae0c331fe7e 155 writeReg(0x40, 0x83);
highroads 0:aae0c331fe7e 156 writeReg(0x46, 0x25);
highroads 0:aae0c331fe7e 157 writeReg(0x60, 0x00);
highroads 0:aae0c331fe7e 158 writeReg(0x27, 0x00);
highroads 0:aae0c331fe7e 159 writeReg(0x50, 0x06);
highroads 0:aae0c331fe7e 160 writeReg(0x51, 0x00);
highroads 0:aae0c331fe7e 161 writeReg(0x52, 0x96);
highroads 0:aae0c331fe7e 162 writeReg(0x56, 0x08);
highroads 0:aae0c331fe7e 163 writeReg(0x57, 0x30);
highroads 0:aae0c331fe7e 164 writeReg(0x61, 0x00);
highroads 0:aae0c331fe7e 165 writeReg(0x62, 0x00);
highroads 0:aae0c331fe7e 166 writeReg(0x64, 0x00);
highroads 0:aae0c331fe7e 167 writeReg(0x65, 0x00);
highroads 0:aae0c331fe7e 168 writeReg(0x66, 0xA0);
highroads 0:aae0c331fe7e 169
highroads 0:aae0c331fe7e 170 writeReg(0xFF, 0x01);
highroads 0:aae0c331fe7e 171 writeReg(0x22, 0x32);
highroads 0:aae0c331fe7e 172 writeReg(0x47, 0x14);
highroads 0:aae0c331fe7e 173 writeReg(0x49, 0xFF);
highroads 0:aae0c331fe7e 174 writeReg(0x4A, 0x00);
highroads 0:aae0c331fe7e 175
highroads 0:aae0c331fe7e 176 writeReg(0xFF, 0x00);
highroads 0:aae0c331fe7e 177 writeReg(0x7A, 0x0A);
highroads 0:aae0c331fe7e 178 writeReg(0x7B, 0x00);
highroads 0:aae0c331fe7e 179 writeReg(0x78, 0x21);
highroads 0:aae0c331fe7e 180
highroads 0:aae0c331fe7e 181 writeReg(0xFF, 0x01);
highroads 0:aae0c331fe7e 182 writeReg(0x23, 0x34);
highroads 0:aae0c331fe7e 183 writeReg(0x42, 0x00);
highroads 0:aae0c331fe7e 184 writeReg(0x44, 0xFF);
highroads 0:aae0c331fe7e 185 writeReg(0x45, 0x26);
highroads 0:aae0c331fe7e 186 writeReg(0x46, 0x05);
highroads 0:aae0c331fe7e 187 writeReg(0x40, 0x40);
highroads 0:aae0c331fe7e 188 writeReg(0x0E, 0x06);
highroads 0:aae0c331fe7e 189 writeReg(0x20, 0x1A);
highroads 0:aae0c331fe7e 190 writeReg(0x43, 0x40);
highroads 0:aae0c331fe7e 191
highroads 0:aae0c331fe7e 192 writeReg(0xFF, 0x00);
highroads 0:aae0c331fe7e 193 writeReg(0x34, 0x03);
highroads 0:aae0c331fe7e 194 writeReg(0x35, 0x44);
highroads 0:aae0c331fe7e 195
highroads 0:aae0c331fe7e 196 writeReg(0xFF, 0x01);
highroads 0:aae0c331fe7e 197 writeReg(0x31, 0x04);
highroads 0:aae0c331fe7e 198 writeReg(0x4B, 0x09);
highroads 0:aae0c331fe7e 199 writeReg(0x4C, 0x05);
highroads 0:aae0c331fe7e 200 writeReg(0x4D, 0x04);
highroads 0:aae0c331fe7e 201
highroads 0:aae0c331fe7e 202 writeReg(0xFF, 0x00);
highroads 0:aae0c331fe7e 203 writeReg(0x44, 0x00);
highroads 0:aae0c331fe7e 204 writeReg(0x45, 0x20);
highroads 0:aae0c331fe7e 205 writeReg(0x47, 0x08);
highroads 0:aae0c331fe7e 206 writeReg(0x48, 0x28);
highroads 0:aae0c331fe7e 207 writeReg(0x67, 0x00);
highroads 0:aae0c331fe7e 208 writeReg(0x70, 0x04);
highroads 0:aae0c331fe7e 209 writeReg(0x71, 0x01);
highroads 0:aae0c331fe7e 210 writeReg(0x72, 0xFE);
highroads 0:aae0c331fe7e 211 writeReg(0x76, 0x00);
highroads 0:aae0c331fe7e 212 writeReg(0x77, 0x00);
highroads 0:aae0c331fe7e 213
highroads 0:aae0c331fe7e 214 writeReg(0xFF, 0x01);
highroads 0:aae0c331fe7e 215 writeReg(0x0D, 0x01);
highroads 0:aae0c331fe7e 216
highroads 0:aae0c331fe7e 217 writeReg(0xFF, 0x00);
highroads 0:aae0c331fe7e 218 writeReg(0x80, 0x01);
highroads 0:aae0c331fe7e 219 writeReg(0x01, 0xF8);
highroads 0:aae0c331fe7e 220
highroads 0:aae0c331fe7e 221 writeReg(0xFF, 0x01);
highroads 0:aae0c331fe7e 222 writeReg(0x8E, 0x01);
highroads 0:aae0c331fe7e 223 writeReg(0x00, 0x01);
highroads 0:aae0c331fe7e 224 writeReg(0xFF, 0x00);
highroads 0:aae0c331fe7e 225 writeReg(0x80, 0x00);
highroads 0:aae0c331fe7e 226
highroads 0:aae0c331fe7e 227 // -- VL53L0X_load_tuning_settings() end
highroads 0:aae0c331fe7e 228
highroads 0:aae0c331fe7e 229 // "Set interrupt config to new sample ready"
highroads 0:aae0c331fe7e 230 // -- VL53L0X_SetGpioConfig() begin
highroads 0:aae0c331fe7e 231
highroads 0:aae0c331fe7e 232 writeReg(SYSTEM_INTERRUPT_CONFIG_GPIO, 0x04);
highroads 0:aae0c331fe7e 233 writeReg(GPIO_HV_MUX_ACTIVE_HIGH, readReg(GPIO_HV_MUX_ACTIVE_HIGH) & ~0x10); // active low
highroads 0:aae0c331fe7e 234 writeReg(SYSTEM_INTERRUPT_CLEAR, 0x01);
highroads 0:aae0c331fe7e 235
highroads 0:aae0c331fe7e 236 // -- VL53L0X_SetGpioConfig() end
highroads 0:aae0c331fe7e 237
highroads 0:aae0c331fe7e 238 measurement_timing_budget_us = getMeasurementTimingBudget();
highroads 0:aae0c331fe7e 239
highroads 0:aae0c331fe7e 240 // "Disable MSRC and TCC by default"
highroads 0:aae0c331fe7e 241 // MSRC = Minimum Signal Rate Check
highroads 0:aae0c331fe7e 242 // TCC = Target CentreCheck
highroads 0:aae0c331fe7e 243 // -- VL53L0X_SetSequenceStepEnable() begin
highroads 0:aae0c331fe7e 244
highroads 0:aae0c331fe7e 245 writeReg(SYSTEM_SEQUENCE_CONFIG, 0xE8);
highroads 0:aae0c331fe7e 246
highroads 0:aae0c331fe7e 247 // -- VL53L0X_SetSequenceStepEnable() end
highroads 0:aae0c331fe7e 248
highroads 0:aae0c331fe7e 249 // "Recalculate timing budget"
highroads 0:aae0c331fe7e 250 setMeasurementTimingBudget(measurement_timing_budget_us);
highroads 0:aae0c331fe7e 251
highroads 0:aae0c331fe7e 252 // VL53L0X_StaticInit() end
highroads 0:aae0c331fe7e 253
highroads 0:aae0c331fe7e 254 // VL53L0X_PerformRefCalibration() begin (VL53L0X_perform_ref_calibration())
highroads 0:aae0c331fe7e 255
highroads 0:aae0c331fe7e 256 // -- VL53L0X_perform_vhv_calibration() begin
highroads 0:aae0c331fe7e 257
highroads 0:aae0c331fe7e 258 writeReg(SYSTEM_SEQUENCE_CONFIG, 0x01);
highroads 0:aae0c331fe7e 259 if (!performSingleRefCalibration(0x40)) { return false; }
highroads 0:aae0c331fe7e 260
highroads 0:aae0c331fe7e 261 // -- VL53L0X_perform_vhv_calibration() end
highroads 0:aae0c331fe7e 262
highroads 0:aae0c331fe7e 263 // -- VL53L0X_perform_phase_calibration() begin
highroads 0:aae0c331fe7e 264
highroads 0:aae0c331fe7e 265 writeReg(SYSTEM_SEQUENCE_CONFIG, 0x02);
highroads 0:aae0c331fe7e 266 if (!performSingleRefCalibration(0x00)) { return false; }
highroads 0:aae0c331fe7e 267
highroads 0:aae0c331fe7e 268 // -- VL53L0X_perform_phase_calibration() end
highroads 0:aae0c331fe7e 269
highroads 0:aae0c331fe7e 270 // "restore the previous Sequence Config"
highroads 0:aae0c331fe7e 271 writeReg(SYSTEM_SEQUENCE_CONFIG, 0xE8);
highroads 0:aae0c331fe7e 272
highroads 0:aae0c331fe7e 273 // VL53L0X_PerformRefCalibration() end
highroads 0:aae0c331fe7e 274
highroads 0:aae0c331fe7e 275 return true;
highroads 0:aae0c331fe7e 276 }
highroads 0:aae0c331fe7e 277
highroads 0:aae0c331fe7e 278 // Set the return signal rate limit check value in units of MCPS (mega counts
highroads 0:aae0c331fe7e 279 // per second). "This represents the amplitude of the signal reflected from the
highroads 0:aae0c331fe7e 280 // target and detected by the device"; setting this limit presumably determines
highroads 0:aae0c331fe7e 281 // the minimum measurement necessary for the sensor to report a valid reading.
highroads 0:aae0c331fe7e 282 // Setting a lower limit increases the potential range of the sensor but also
highroads 0:aae0c331fe7e 283 // seems to increase the likelihood of getting an inaccurate reading because of
highroads 0:aae0c331fe7e 284 // unwanted reflections from objects other than the intended target.
highroads 0:aae0c331fe7e 285 // Defaults to 0.25 MCPS as initialized by the ST API and this library.
highroads 0:aae0c331fe7e 286 bool VL53L0X::setSignalRateLimit(float limit_Mcps)
highroads 0:aae0c331fe7e 287 {
highroads 0:aae0c331fe7e 288 if (limit_Mcps < 0 || limit_Mcps > 511.99) { return false; }
highroads 0:aae0c331fe7e 289
highroads 0:aae0c331fe7e 290 // Q9.7 fixed point format (9 integer bits, 7 fractional bits)
highroads 0:aae0c331fe7e 291 writeReg16Bit(FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT, limit_Mcps * (1 << 7));
highroads 0:aae0c331fe7e 292 return true;
highroads 0:aae0c331fe7e 293 }
highroads 0:aae0c331fe7e 294
highroads 0:aae0c331fe7e 295 // Get the return signal rate limit check value in MCPS
highroads 0:aae0c331fe7e 296 float VL53L0X::getSignalRateLimit(void)
highroads 0:aae0c331fe7e 297 {
highroads 0:aae0c331fe7e 298 return (float)readReg16Bit(FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT) / (1 << 7);
highroads 0:aae0c331fe7e 299 }
highroads 0:aae0c331fe7e 300
highroads 0:aae0c331fe7e 301 // Set the measurement timing budget in microseconds, which is the time allowed
highroads 0:aae0c331fe7e 302 // for one measurement; the ST API and this library take care of splitting the
highroads 0:aae0c331fe7e 303 // timing budget among the sub-steps in the ranging sequence. A longer timing
highroads 0:aae0c331fe7e 304 // budget allows for more accurate measurements. Increasing the budget by a
highroads 0:aae0c331fe7e 305 // factor of N decreases the range measurement standard deviation by a factor of
highroads 0:aae0c331fe7e 306 // sqrt(N). Defaults to about 33 milliseconds; the minimum is 20 ms.
highroads 0:aae0c331fe7e 307 // based on VL53L0X_set_measurement_timing_budget_micro_seconds()
highroads 0:aae0c331fe7e 308 bool VL53L0X::setMeasurementTimingBudget(uint32_t budget_us)
highroads 0:aae0c331fe7e 309 {
highroads 0:aae0c331fe7e 310 SequenceStepEnables enables;
highroads 0:aae0c331fe7e 311 SequenceStepTimeouts timeouts;
highroads 0:aae0c331fe7e 312
highroads 0:aae0c331fe7e 313 uint16_t const StartOverhead = 1320; // note that this is different than the value in get_
highroads 0:aae0c331fe7e 314 uint16_t const EndOverhead = 960;
highroads 0:aae0c331fe7e 315 uint16_t const MsrcOverhead = 660;
highroads 0:aae0c331fe7e 316 uint16_t const TccOverhead = 590;
highroads 0:aae0c331fe7e 317 uint16_t const DssOverhead = 690;
highroads 0:aae0c331fe7e 318 uint16_t const PreRangeOverhead = 660;
highroads 0:aae0c331fe7e 319 uint16_t const FinalRangeOverhead = 550;
highroads 0:aae0c331fe7e 320
highroads 0:aae0c331fe7e 321 uint32_t const MinTimingBudget = 20000;
highroads 0:aae0c331fe7e 322
highroads 0:aae0c331fe7e 323 if (budget_us < MinTimingBudget) { return false; }
highroads 0:aae0c331fe7e 324
highroads 0:aae0c331fe7e 325 uint32_t used_budget_us = StartOverhead + EndOverhead;
highroads 0:aae0c331fe7e 326
highroads 0:aae0c331fe7e 327 getSequenceStepEnables(&enables);
highroads 0:aae0c331fe7e 328 getSequenceStepTimeouts(&enables, &timeouts);
highroads 0:aae0c331fe7e 329
highroads 0:aae0c331fe7e 330 if (enables.tcc)
highroads 0:aae0c331fe7e 331 {
highroads 0:aae0c331fe7e 332 used_budget_us += (timeouts.msrc_dss_tcc_us + TccOverhead);
highroads 0:aae0c331fe7e 333 }
highroads 0:aae0c331fe7e 334
highroads 0:aae0c331fe7e 335 if (enables.dss)
highroads 0:aae0c331fe7e 336 {
highroads 0:aae0c331fe7e 337 used_budget_us += 2 * (timeouts.msrc_dss_tcc_us + DssOverhead);
highroads 0:aae0c331fe7e 338 }
highroads 0:aae0c331fe7e 339 else if (enables.msrc)
highroads 0:aae0c331fe7e 340 {
highroads 0:aae0c331fe7e 341 used_budget_us += (timeouts.msrc_dss_tcc_us + MsrcOverhead);
highroads 0:aae0c331fe7e 342 }
highroads 0:aae0c331fe7e 343
highroads 0:aae0c331fe7e 344 if (enables.pre_range)
highroads 0:aae0c331fe7e 345 {
highroads 0:aae0c331fe7e 346 used_budget_us += (timeouts.pre_range_us + PreRangeOverhead);
highroads 0:aae0c331fe7e 347 }
highroads 0:aae0c331fe7e 348
highroads 0:aae0c331fe7e 349 if (enables.final_range)
highroads 0:aae0c331fe7e 350 {
highroads 0:aae0c331fe7e 351 used_budget_us += FinalRangeOverhead;
highroads 0:aae0c331fe7e 352
highroads 0:aae0c331fe7e 353 // "Note that the final range timeout is determined by the timing
highroads 0:aae0c331fe7e 354 // budget and the sum of all other timeouts within the sequence.
highroads 0:aae0c331fe7e 355 // If there is no room for the final range timeout, then an error
highroads 0:aae0c331fe7e 356 // will be set. Otherwise the remaining time will be applied to
highroads 0:aae0c331fe7e 357 // the final range."
highroads 0:aae0c331fe7e 358
highroads 0:aae0c331fe7e 359 if (used_budget_us > budget_us)
highroads 0:aae0c331fe7e 360 {
highroads 0:aae0c331fe7e 361 // "Requested timeout too big."
highroads 0:aae0c331fe7e 362 return false;
highroads 0:aae0c331fe7e 363 }
highroads 0:aae0c331fe7e 364
highroads 0:aae0c331fe7e 365 uint32_t final_range_timeout_us = budget_us - used_budget_us;
highroads 0:aae0c331fe7e 366
highroads 0:aae0c331fe7e 367 // set_sequence_step_timeout() begin
highroads 0:aae0c331fe7e 368 // (SequenceStepId == VL53L0X_SEQUENCESTEP_FINAL_RANGE)
highroads 0:aae0c331fe7e 369
highroads 0:aae0c331fe7e 370 // "For the final range timeout, the pre-range timeout
highroads 0:aae0c331fe7e 371 // must be added. To do this both final and pre-range
highroads 0:aae0c331fe7e 372 // timeouts must be expressed in macro periods MClks
highroads 0:aae0c331fe7e 373 // because they have different vcsel periods."
highroads 0:aae0c331fe7e 374
highroads 0:aae0c331fe7e 375 uint16_t final_range_timeout_mclks =
highroads 0:aae0c331fe7e 376 timeoutMicrosecondsToMclks(final_range_timeout_us,
highroads 0:aae0c331fe7e 377 timeouts.final_range_vcsel_period_pclks);
highroads 0:aae0c331fe7e 378
highroads 0:aae0c331fe7e 379 if (enables.pre_range)
highroads 0:aae0c331fe7e 380 {
highroads 0:aae0c331fe7e 381 final_range_timeout_mclks += timeouts.pre_range_mclks;
highroads 0:aae0c331fe7e 382 }
highroads 0:aae0c331fe7e 383
highroads 0:aae0c331fe7e 384 writeReg16Bit(FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI,
highroads 0:aae0c331fe7e 385 encodeTimeout(final_range_timeout_mclks));
highroads 0:aae0c331fe7e 386
highroads 0:aae0c331fe7e 387 // set_sequence_step_timeout() end
highroads 0:aae0c331fe7e 388
highroads 0:aae0c331fe7e 389 measurement_timing_budget_us = budget_us; // store for internal reuse
highroads 0:aae0c331fe7e 390 }
highroads 0:aae0c331fe7e 391 return true;
highroads 0:aae0c331fe7e 392 }
highroads 0:aae0c331fe7e 393
highroads 0:aae0c331fe7e 394 // Get the measurement timing budget in microseconds
highroads 0:aae0c331fe7e 395 // based on VL53L0X_get_measurement_timing_budget_micro_seconds()
highroads 0:aae0c331fe7e 396 // in us
highroads 0:aae0c331fe7e 397 uint32_t VL53L0X::getMeasurementTimingBudget(void)
highroads 0:aae0c331fe7e 398 {
highroads 0:aae0c331fe7e 399 SequenceStepEnables enables;
highroads 0:aae0c331fe7e 400 SequenceStepTimeouts timeouts;
highroads 0:aae0c331fe7e 401
highroads 0:aae0c331fe7e 402 uint16_t const StartOverhead = 1910; // note that this is different than the value in set_
highroads 0:aae0c331fe7e 403 uint16_t const EndOverhead = 960;
highroads 0:aae0c331fe7e 404 uint16_t const MsrcOverhead = 660;
highroads 0:aae0c331fe7e 405 uint16_t const TccOverhead = 590;
highroads 0:aae0c331fe7e 406 uint16_t const DssOverhead = 690;
highroads 0:aae0c331fe7e 407 uint16_t const PreRangeOverhead = 660;
highroads 0:aae0c331fe7e 408 uint16_t const FinalRangeOverhead = 550;
highroads 0:aae0c331fe7e 409
highroads 0:aae0c331fe7e 410 // "Start and end overhead times always present"
highroads 0:aae0c331fe7e 411 uint32_t budget_us = StartOverhead + EndOverhead;
highroads 0:aae0c331fe7e 412
highroads 0:aae0c331fe7e 413 getSequenceStepEnables(&enables);
highroads 0:aae0c331fe7e 414 getSequenceStepTimeouts(&enables, &timeouts);
highroads 0:aae0c331fe7e 415
highroads 0:aae0c331fe7e 416 if (enables.tcc)
highroads 0:aae0c331fe7e 417 {
highroads 0:aae0c331fe7e 418 budget_us += (timeouts.msrc_dss_tcc_us + TccOverhead);
highroads 0:aae0c331fe7e 419 }
highroads 0:aae0c331fe7e 420
highroads 0:aae0c331fe7e 421 if (enables.dss)
highroads 0:aae0c331fe7e 422 {
highroads 0:aae0c331fe7e 423 budget_us += 2 * (timeouts.msrc_dss_tcc_us + DssOverhead);
highroads 0:aae0c331fe7e 424 }
highroads 0:aae0c331fe7e 425 else if (enables.msrc)
highroads 0:aae0c331fe7e 426 {
highroads 0:aae0c331fe7e 427 budget_us += (timeouts.msrc_dss_tcc_us + MsrcOverhead);
highroads 0:aae0c331fe7e 428 }
highroads 0:aae0c331fe7e 429
highroads 0:aae0c331fe7e 430 if (enables.pre_range)
highroads 0:aae0c331fe7e 431 {
highroads 0:aae0c331fe7e 432 budget_us += (timeouts.pre_range_us + PreRangeOverhead);
highroads 0:aae0c331fe7e 433 }
highroads 0:aae0c331fe7e 434
highroads 0:aae0c331fe7e 435 if (enables.final_range)
highroads 0:aae0c331fe7e 436 {
highroads 0:aae0c331fe7e 437 budget_us += (timeouts.final_range_us + FinalRangeOverhead);
highroads 0:aae0c331fe7e 438 }
highroads 0:aae0c331fe7e 439
highroads 0:aae0c331fe7e 440 measurement_timing_budget_us = budget_us; // store for internal reuse
highroads 0:aae0c331fe7e 441 return budget_us;
highroads 0:aae0c331fe7e 442 }
highroads 0:aae0c331fe7e 443
highroads 0:aae0c331fe7e 444 // Set the VCSEL (vertical cavity surface emitting laser) pulse period for the
highroads 0:aae0c331fe7e 445 // given period type (pre-range or final range) to the given value in PCLKs.
highroads 0:aae0c331fe7e 446 // Longer periods seem to increase the potential range of the sensor.
highroads 0:aae0c331fe7e 447 // Valid values are (even numbers only):
highroads 0:aae0c331fe7e 448 // pre: 12 to 18 (initialized default: 14)
highroads 0:aae0c331fe7e 449 // final: 8 to 14 (initialized default: 10)
highroads 0:aae0c331fe7e 450 // based on VL53L0X_set_vcsel_pulse_period()
highroads 0:aae0c331fe7e 451 bool VL53L0X::setVcselPulsePeriod(vcselPeriodType type, uint8_t period_pclks)
highroads 0:aae0c331fe7e 452 {
highroads 0:aae0c331fe7e 453 uint8_t vcsel_period_reg = encodeVcselPeriod(period_pclks);
highroads 0:aae0c331fe7e 454
highroads 0:aae0c331fe7e 455 SequenceStepEnables enables;
highroads 0:aae0c331fe7e 456 SequenceStepTimeouts timeouts;
highroads 0:aae0c331fe7e 457
highroads 0:aae0c331fe7e 458 getSequenceStepEnables(&enables);
highroads 0:aae0c331fe7e 459 getSequenceStepTimeouts(&enables, &timeouts);
highroads 0:aae0c331fe7e 460
highroads 0:aae0c331fe7e 461 // "Apply specific settings for the requested clock period"
highroads 0:aae0c331fe7e 462 // "Re-calculate and apply timeouts, in macro periods"
highroads 0:aae0c331fe7e 463
highroads 0:aae0c331fe7e 464 // "When the VCSEL period for the pre or final range is changed,
highroads 0:aae0c331fe7e 465 // the corresponding timeout must be read from the device using
highroads 0:aae0c331fe7e 466 // the current VCSEL period, then the new VCSEL period can be
highroads 0:aae0c331fe7e 467 // applied. The timeout then must be written back to the device
highroads 0:aae0c331fe7e 468 // using the new VCSEL period.
highroads 0:aae0c331fe7e 469 //
highroads 0:aae0c331fe7e 470 // For the MSRC timeout, the same applies - this timeout being
highroads 0:aae0c331fe7e 471 // dependant on the pre-range vcsel period."
highroads 0:aae0c331fe7e 472
highroads 0:aae0c331fe7e 473
highroads 0:aae0c331fe7e 474 if (type == VcselPeriodPreRange)
highroads 0:aae0c331fe7e 475 {
highroads 0:aae0c331fe7e 476 // "Set phase check limits"
highroads 0:aae0c331fe7e 477 switch (period_pclks)
highroads 0:aae0c331fe7e 478 {
highroads 0:aae0c331fe7e 479 case 12:
highroads 0:aae0c331fe7e 480 writeReg(PRE_RANGE_CONFIG_VALID_PHASE_HIGH, 0x18);
highroads 0:aae0c331fe7e 481 break;
highroads 0:aae0c331fe7e 482
highroads 0:aae0c331fe7e 483 case 14:
highroads 0:aae0c331fe7e 484 writeReg(PRE_RANGE_CONFIG_VALID_PHASE_HIGH, 0x30);
highroads 0:aae0c331fe7e 485 break;
highroads 0:aae0c331fe7e 486
highroads 0:aae0c331fe7e 487 case 16:
highroads 0:aae0c331fe7e 488 writeReg(PRE_RANGE_CONFIG_VALID_PHASE_HIGH, 0x40);
highroads 0:aae0c331fe7e 489 break;
highroads 0:aae0c331fe7e 490
highroads 0:aae0c331fe7e 491 case 18:
highroads 0:aae0c331fe7e 492 writeReg(PRE_RANGE_CONFIG_VALID_PHASE_HIGH, 0x50);
highroads 0:aae0c331fe7e 493 break;
highroads 0:aae0c331fe7e 494
highroads 0:aae0c331fe7e 495 default:
highroads 0:aae0c331fe7e 496 // invalid period
highroads 0:aae0c331fe7e 497 return false;
highroads 0:aae0c331fe7e 498 }
highroads 0:aae0c331fe7e 499 writeReg(PRE_RANGE_CONFIG_VALID_PHASE_LOW, 0x08);
highroads 0:aae0c331fe7e 500
highroads 0:aae0c331fe7e 501 // apply new VCSEL period
highroads 0:aae0c331fe7e 502 writeReg(PRE_RANGE_CONFIG_VCSEL_PERIOD, vcsel_period_reg);
highroads 0:aae0c331fe7e 503
highroads 0:aae0c331fe7e 504 // update timeouts
highroads 0:aae0c331fe7e 505
highroads 0:aae0c331fe7e 506 // set_sequence_step_timeout() begin
highroads 0:aae0c331fe7e 507 // (SequenceStepId == VL53L0X_SEQUENCESTEP_PRE_RANGE)
highroads 0:aae0c331fe7e 508
highroads 0:aae0c331fe7e 509 uint16_t new_pre_range_timeout_mclks =
highroads 0:aae0c331fe7e 510 timeoutMicrosecondsToMclks(timeouts.pre_range_us, period_pclks);
highroads 0:aae0c331fe7e 511
highroads 0:aae0c331fe7e 512 writeReg16Bit(PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI,
highroads 0:aae0c331fe7e 513 encodeTimeout(new_pre_range_timeout_mclks));
highroads 0:aae0c331fe7e 514
highroads 0:aae0c331fe7e 515 // set_sequence_step_timeout() end
highroads 0:aae0c331fe7e 516
highroads 0:aae0c331fe7e 517 // set_sequence_step_timeout() begin
highroads 0:aae0c331fe7e 518 // (SequenceStepId == VL53L0X_SEQUENCESTEP_MSRC)
highroads 0:aae0c331fe7e 519
highroads 0:aae0c331fe7e 520 uint16_t new_msrc_timeout_mclks =
highroads 0:aae0c331fe7e 521 timeoutMicrosecondsToMclks(timeouts.msrc_dss_tcc_us, period_pclks);
highroads 0:aae0c331fe7e 522
highroads 0:aae0c331fe7e 523 writeReg(MSRC_CONFIG_TIMEOUT_MACROP,
highroads 0:aae0c331fe7e 524 (new_msrc_timeout_mclks > 256) ? 255 : (new_msrc_timeout_mclks - 1));
highroads 0:aae0c331fe7e 525
highroads 0:aae0c331fe7e 526 // set_sequence_step_timeout() end
highroads 0:aae0c331fe7e 527 }
highroads 0:aae0c331fe7e 528 else if (type == VcselPeriodFinalRange)
highroads 0:aae0c331fe7e 529 {
highroads 0:aae0c331fe7e 530 switch (period_pclks)
highroads 0:aae0c331fe7e 531 {
highroads 0:aae0c331fe7e 532 case 8:
highroads 0:aae0c331fe7e 533 writeReg(FINAL_RANGE_CONFIG_VALID_PHASE_HIGH, 0x10);
highroads 0:aae0c331fe7e 534 writeReg(FINAL_RANGE_CONFIG_VALID_PHASE_LOW, 0x08);
highroads 0:aae0c331fe7e 535 writeReg(GLOBAL_CONFIG_VCSEL_WIDTH, 0x02);
highroads 0:aae0c331fe7e 536 writeReg(ALGO_PHASECAL_CONFIG_TIMEOUT, 0x0C);
highroads 0:aae0c331fe7e 537 writeReg(0xFF, 0x01);
highroads 0:aae0c331fe7e 538 writeReg(ALGO_PHASECAL_LIM, 0x30);
highroads 0:aae0c331fe7e 539 writeReg(0xFF, 0x00);
highroads 0:aae0c331fe7e 540 break;
highroads 0:aae0c331fe7e 541
highroads 0:aae0c331fe7e 542 case 10:
highroads 0:aae0c331fe7e 543 writeReg(FINAL_RANGE_CONFIG_VALID_PHASE_HIGH, 0x28);
highroads 0:aae0c331fe7e 544 writeReg(FINAL_RANGE_CONFIG_VALID_PHASE_LOW, 0x08);
highroads 0:aae0c331fe7e 545 writeReg(GLOBAL_CONFIG_VCSEL_WIDTH, 0x03);
highroads 0:aae0c331fe7e 546 writeReg(ALGO_PHASECAL_CONFIG_TIMEOUT, 0x09);
highroads 0:aae0c331fe7e 547 writeReg(0xFF, 0x01);
highroads 0:aae0c331fe7e 548 writeReg(ALGO_PHASECAL_LIM, 0x20);
highroads 0:aae0c331fe7e 549 writeReg(0xFF, 0x00);
highroads 0:aae0c331fe7e 550 break;
highroads 0:aae0c331fe7e 551
highroads 0:aae0c331fe7e 552 case 12:
highroads 0:aae0c331fe7e 553 writeReg(FINAL_RANGE_CONFIG_VALID_PHASE_HIGH, 0x38);
highroads 0:aae0c331fe7e 554 writeReg(FINAL_RANGE_CONFIG_VALID_PHASE_LOW, 0x08);
highroads 0:aae0c331fe7e 555 writeReg(GLOBAL_CONFIG_VCSEL_WIDTH, 0x03);
highroads 0:aae0c331fe7e 556 writeReg(ALGO_PHASECAL_CONFIG_TIMEOUT, 0x08);
highroads 0:aae0c331fe7e 557 writeReg(0xFF, 0x01);
highroads 0:aae0c331fe7e 558 writeReg(ALGO_PHASECAL_LIM, 0x20);
highroads 0:aae0c331fe7e 559 writeReg(0xFF, 0x00);
highroads 0:aae0c331fe7e 560 break;
highroads 0:aae0c331fe7e 561
highroads 0:aae0c331fe7e 562 case 14:
highroads 0:aae0c331fe7e 563 writeReg(FINAL_RANGE_CONFIG_VALID_PHASE_HIGH, 0x48);
highroads 0:aae0c331fe7e 564 writeReg(FINAL_RANGE_CONFIG_VALID_PHASE_LOW, 0x08);
highroads 0:aae0c331fe7e 565 writeReg(GLOBAL_CONFIG_VCSEL_WIDTH, 0x03);
highroads 0:aae0c331fe7e 566 writeReg(ALGO_PHASECAL_CONFIG_TIMEOUT, 0x07);
highroads 0:aae0c331fe7e 567 writeReg(0xFF, 0x01);
highroads 0:aae0c331fe7e 568 writeReg(ALGO_PHASECAL_LIM, 0x20);
highroads 0:aae0c331fe7e 569 writeReg(0xFF, 0x00);
highroads 0:aae0c331fe7e 570 break;
highroads 0:aae0c331fe7e 571
highroads 0:aae0c331fe7e 572 default:
highroads 0:aae0c331fe7e 573 // invalid period
highroads 0:aae0c331fe7e 574 return false;
highroads 0:aae0c331fe7e 575 }
highroads 0:aae0c331fe7e 576
highroads 0:aae0c331fe7e 577 // apply new VCSEL period
highroads 0:aae0c331fe7e 578 writeReg(FINAL_RANGE_CONFIG_VCSEL_PERIOD, vcsel_period_reg);
highroads 0:aae0c331fe7e 579
highroads 0:aae0c331fe7e 580 // update timeouts
highroads 0:aae0c331fe7e 581
highroads 0:aae0c331fe7e 582 // set_sequence_step_timeout() begin
highroads 0:aae0c331fe7e 583 // (SequenceStepId == VL53L0X_SEQUENCESTEP_FINAL_RANGE)
highroads 0:aae0c331fe7e 584
highroads 0:aae0c331fe7e 585 // "For the final range timeout, the pre-range timeout
highroads 0:aae0c331fe7e 586 // must be added. To do this both final and pre-range
highroads 0:aae0c331fe7e 587 // timeouts must be expressed in macro periods MClks
highroads 0:aae0c331fe7e 588 // because they have different vcsel periods."
highroads 0:aae0c331fe7e 589
highroads 0:aae0c331fe7e 590 uint16_t new_final_range_timeout_mclks =
highroads 0:aae0c331fe7e 591 timeoutMicrosecondsToMclks(timeouts.final_range_us, period_pclks);
highroads 0:aae0c331fe7e 592
highroads 0:aae0c331fe7e 593 if (enables.pre_range)
highroads 0:aae0c331fe7e 594 {
highroads 0:aae0c331fe7e 595 new_final_range_timeout_mclks += timeouts.pre_range_mclks;
highroads 0:aae0c331fe7e 596 }
highroads 0:aae0c331fe7e 597
highroads 0:aae0c331fe7e 598 writeReg16Bit(FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI,
highroads 0:aae0c331fe7e 599 encodeTimeout(new_final_range_timeout_mclks));
highroads 0:aae0c331fe7e 600
highroads 0:aae0c331fe7e 601 // set_sequence_step_timeout end
highroads 0:aae0c331fe7e 602 }
highroads 0:aae0c331fe7e 603 else
highroads 0:aae0c331fe7e 604 {
highroads 0:aae0c331fe7e 605 // invalid type
highroads 0:aae0c331fe7e 606 return false;
highroads 0:aae0c331fe7e 607 }
highroads 0:aae0c331fe7e 608
highroads 0:aae0c331fe7e 609 // "Finally, the timing budget must be re-applied"
highroads 0:aae0c331fe7e 610
highroads 0:aae0c331fe7e 611 setMeasurementTimingBudget(measurement_timing_budget_us);
highroads 0:aae0c331fe7e 612
highroads 0:aae0c331fe7e 613 // "Perform the phase calibration. This is needed after changing on vcsel period."
highroads 0:aae0c331fe7e 614 // VL53L0X_perform_phase_calibration() begin
highroads 0:aae0c331fe7e 615
highroads 0:aae0c331fe7e 616 uint8_t sequence_config = readReg(SYSTEM_SEQUENCE_CONFIG);
highroads 0:aae0c331fe7e 617 writeReg(SYSTEM_SEQUENCE_CONFIG, 0x02);
highroads 0:aae0c331fe7e 618 performSingleRefCalibration(0x0);
highroads 0:aae0c331fe7e 619 writeReg(SYSTEM_SEQUENCE_CONFIG, sequence_config);
highroads 0:aae0c331fe7e 620
highroads 0:aae0c331fe7e 621 // VL53L0X_perform_phase_calibration() end
highroads 0:aae0c331fe7e 622
highroads 0:aae0c331fe7e 623 return true;
highroads 0:aae0c331fe7e 624 }
highroads 0:aae0c331fe7e 625
highroads 0:aae0c331fe7e 626 // Get the VCSEL pulse period in PCLKs for the given period type.
highroads 0:aae0c331fe7e 627 // based on VL53L0X_get_vcsel_pulse_period()
highroads 0:aae0c331fe7e 628 uint8_t VL53L0X::getVcselPulsePeriod(vcselPeriodType type)
highroads 0:aae0c331fe7e 629 {
highroads 0:aae0c331fe7e 630 if (type == VcselPeriodPreRange)
highroads 0:aae0c331fe7e 631 {
highroads 0:aae0c331fe7e 632 return decodeVcselPeriod(readReg(PRE_RANGE_CONFIG_VCSEL_PERIOD));
highroads 0:aae0c331fe7e 633 }
highroads 0:aae0c331fe7e 634 else if (type == VcselPeriodFinalRange)
highroads 0:aae0c331fe7e 635 {
highroads 0:aae0c331fe7e 636 return decodeVcselPeriod(readReg(FINAL_RANGE_CONFIG_VCSEL_PERIOD));
highroads 0:aae0c331fe7e 637 }
highroads 0:aae0c331fe7e 638 else { return 255; }
highroads 0:aae0c331fe7e 639 }
highroads 0:aae0c331fe7e 640
highroads 0:aae0c331fe7e 641 // Start continuous ranging measurements. If period_ms (optional) is 0 or not
highroads 0:aae0c331fe7e 642 // given, continuous back-to-back mode is used (the sensor takes measurements as
highroads 0:aae0c331fe7e 643 // often as possible); otherwise, continuous timed mode is used, with the given
highroads 0:aae0c331fe7e 644 // inter-measurement period in milliseconds determining how often the sensor
highroads 0:aae0c331fe7e 645 // takes a measurement.
highroads 0:aae0c331fe7e 646 // based on VL53L0X_StartMeasurement()
highroads 0:aae0c331fe7e 647 void VL53L0X::startContinuous(uint32_t period_ms)
highroads 0:aae0c331fe7e 648 {
highroads 0:aae0c331fe7e 649 writeReg(0x80, 0x01);
highroads 0:aae0c331fe7e 650 writeReg(0xFF, 0x01);
highroads 0:aae0c331fe7e 651 writeReg(0x00, 0x00);
highroads 0:aae0c331fe7e 652 writeReg(0x91, stop_variable);
highroads 0:aae0c331fe7e 653 writeReg(0x00, 0x01);
highroads 0:aae0c331fe7e 654 writeReg(0xFF, 0x00);
highroads 0:aae0c331fe7e 655 writeReg(0x80, 0x00);
highroads 0:aae0c331fe7e 656
highroads 0:aae0c331fe7e 657 if (period_ms != 0)
highroads 0:aae0c331fe7e 658 {
highroads 0:aae0c331fe7e 659 // continuous timed mode
highroads 0:aae0c331fe7e 660
highroads 0:aae0c331fe7e 661 // VL53L0X_SetInterMeasurementPeriodMilliSeconds() begin
highroads 0:aae0c331fe7e 662
highroads 0:aae0c331fe7e 663 uint16_t osc_calibrate_val = readReg16Bit(OSC_CALIBRATE_VAL);
highroads 0:aae0c331fe7e 664
highroads 0:aae0c331fe7e 665 if (osc_calibrate_val != 0)
highroads 0:aae0c331fe7e 666 {
highroads 0:aae0c331fe7e 667 period_ms *= osc_calibrate_val;
highroads 0:aae0c331fe7e 668 }
highroads 0:aae0c331fe7e 669
highroads 0:aae0c331fe7e 670 writeReg32Bit(SYSTEM_INTERMEASUREMENT_PERIOD, period_ms);
highroads 0:aae0c331fe7e 671
highroads 0:aae0c331fe7e 672 // VL53L0X_SetInterMeasurementPeriodMilliSeconds() end
highroads 0:aae0c331fe7e 673
highroads 0:aae0c331fe7e 674 writeReg(SYSRANGE_START, 0x04); // VL53L0X_REG_SYSRANGE_MODE_TIMED
highroads 0:aae0c331fe7e 675 }
highroads 0:aae0c331fe7e 676 else
highroads 0:aae0c331fe7e 677 {
highroads 0:aae0c331fe7e 678 // continuous back-to-back mode
highroads 0:aae0c331fe7e 679 writeReg(SYSRANGE_START, 0x02); // VL53L0X_REG_SYSRANGE_MODE_BACKTOBACK
highroads 0:aae0c331fe7e 680 }
highroads 0:aae0c331fe7e 681 }
highroads 0:aae0c331fe7e 682
highroads 0:aae0c331fe7e 683 // Stop continuous measurements
highroads 0:aae0c331fe7e 684 // based on VL53L0X_StopMeasurement()
highroads 0:aae0c331fe7e 685 void VL53L0X::stopContinuous(void)
highroads 0:aae0c331fe7e 686 {
highroads 0:aae0c331fe7e 687 writeReg(SYSRANGE_START, 0x01); // VL53L0X_REG_SYSRANGE_MODE_SINGLESHOT
highroads 0:aae0c331fe7e 688
highroads 0:aae0c331fe7e 689 writeReg(0xFF, 0x01);
highroads 0:aae0c331fe7e 690 writeReg(0x00, 0x00);
highroads 0:aae0c331fe7e 691 writeReg(0x91, 0x00);
highroads 0:aae0c331fe7e 692 writeReg(0x00, 0x01);
highroads 0:aae0c331fe7e 693 writeReg(0xFF, 0x00);
highroads 0:aae0c331fe7e 694 }
highroads 0:aae0c331fe7e 695
highroads 0:aae0c331fe7e 696 // Returns a range reading in millimeters when continuous mode is active
highroads 0:aae0c331fe7e 697 // (readRangeSingleMillimeters() also calls this function after starting a
highroads 0:aae0c331fe7e 698 // single-shot range measurement)
highroads 0:aae0c331fe7e 699 uint16_t VL53L0X::readRangeContinuousMillimeters(void)
highroads 0:aae0c331fe7e 700 {
highroads 0:aae0c331fe7e 701 startTimeout();
highroads 0:aae0c331fe7e 702 while ((readReg(RESULT_INTERRUPT_STATUS) & 0x07) == 0)
highroads 0:aae0c331fe7e 703 {
highroads 0:aae0c331fe7e 704 if (checkTimeoutExpired())
highroads 0:aae0c331fe7e 705 {
highroads 0:aae0c331fe7e 706 did_timeout = true;
highroads 0:aae0c331fe7e 707 return 65535;
highroads 0:aae0c331fe7e 708 }
highroads 0:aae0c331fe7e 709 }
highroads 0:aae0c331fe7e 710
highroads 0:aae0c331fe7e 711 // assumptions: Linearity Corrective Gain is 1000 (default);
highroads 0:aae0c331fe7e 712 // fractional ranging is not enabled
highroads 0:aae0c331fe7e 713 uint16_t range = readReg16Bit(RESULT_RANGE_STATUS + 10);
highroads 0:aae0c331fe7e 714
highroads 0:aae0c331fe7e 715 writeReg(SYSTEM_INTERRUPT_CLEAR, 0x01);
highroads 0:aae0c331fe7e 716
highroads 0:aae0c331fe7e 717 return range;
highroads 0:aae0c331fe7e 718 }
highroads 0:aae0c331fe7e 719
highroads 0:aae0c331fe7e 720 // Performs a single-shot range measurement and returns the reading in
highroads 0:aae0c331fe7e 721 // millimeters
highroads 0:aae0c331fe7e 722 // based on VL53L0X_PerformSingleRangingMeasurement()
highroads 0:aae0c331fe7e 723 uint16_t VL53L0X::readRangeSingleMillimeters(void)
highroads 0:aae0c331fe7e 724 {
highroads 0:aae0c331fe7e 725 writeReg(0x80, 0x01);
highroads 0:aae0c331fe7e 726 writeReg(0xFF, 0x01);
highroads 0:aae0c331fe7e 727 writeReg(0x00, 0x00);
highroads 0:aae0c331fe7e 728 writeReg(0x91, stop_variable);
highroads 0:aae0c331fe7e 729 writeReg(0x00, 0x01);
highroads 0:aae0c331fe7e 730 writeReg(0xFF, 0x00);
highroads 0:aae0c331fe7e 731 writeReg(0x80, 0x00);
highroads 0:aae0c331fe7e 732
highroads 0:aae0c331fe7e 733 writeReg(SYSRANGE_START, 0x01);
highroads 0:aae0c331fe7e 734
highroads 0:aae0c331fe7e 735 // "Wait until start bit has been cleared"
highroads 0:aae0c331fe7e 736 startTimeout();
highroads 0:aae0c331fe7e 737 while (readReg(SYSRANGE_START) & 0x01)
highroads 0:aae0c331fe7e 738 {
highroads 0:aae0c331fe7e 739 if (checkTimeoutExpired())
highroads 0:aae0c331fe7e 740 {
highroads 0:aae0c331fe7e 741 did_timeout = true;
highroads 0:aae0c331fe7e 742 return 65535;
highroads 0:aae0c331fe7e 743 }
highroads 0:aae0c331fe7e 744 }
highroads 0:aae0c331fe7e 745
highroads 0:aae0c331fe7e 746 return readRangeContinuousMillimeters();
highroads 0:aae0c331fe7e 747 }
highroads 0:aae0c331fe7e 748
highroads 0:aae0c331fe7e 749 // Did a timeout occur in one of the read functions since the last call to
highroads 0:aae0c331fe7e 750 // timeoutOccurred()?
highroads 0:aae0c331fe7e 751 bool VL53L0X::timeoutOccurred()
highroads 0:aae0c331fe7e 752 {
highroads 0:aae0c331fe7e 753 bool tmp = did_timeout;
highroads 0:aae0c331fe7e 754 did_timeout = false;
highroads 0:aae0c331fe7e 755 return tmp;
highroads 0:aae0c331fe7e 756 }
highroads 0:aae0c331fe7e 757
highroads 0:aae0c331fe7e 758 // Private Methods /////////////////////////////////////////////////////////////
highroads 0:aae0c331fe7e 759
highroads 0:aae0c331fe7e 760 // Get reference SPAD (single photon avalanche diode) count and type
highroads 0:aae0c331fe7e 761 // based on VL53L0X_get_info_from_device(),
highroads 0:aae0c331fe7e 762 // but only gets reference SPAD count and type
highroads 0:aae0c331fe7e 763 bool VL53L0X::getSpadInfo(uint8_t * count, bool * type_is_aperture)
highroads 0:aae0c331fe7e 764 {
highroads 0:aae0c331fe7e 765 uint8_t tmp;
highroads 0:aae0c331fe7e 766
highroads 0:aae0c331fe7e 767 writeReg(0x80, 0x01);
highroads 0:aae0c331fe7e 768 writeReg(0xFF, 0x01);
highroads 0:aae0c331fe7e 769 writeReg(0x00, 0x00);
highroads 0:aae0c331fe7e 770
highroads 0:aae0c331fe7e 771 writeReg(0xFF, 0x06);
highroads 0:aae0c331fe7e 772 writeReg(0x83, readReg(0x83) | 0x04);
highroads 0:aae0c331fe7e 773 writeReg(0xFF, 0x07);
highroads 0:aae0c331fe7e 774 writeReg(0x81, 0x01);
highroads 0:aae0c331fe7e 775
highroads 0:aae0c331fe7e 776 writeReg(0x80, 0x01);
highroads 0:aae0c331fe7e 777
highroads 0:aae0c331fe7e 778 writeReg(0x94, 0x6b);
highroads 0:aae0c331fe7e 779 writeReg(0x83, 0x00);
highroads 0:aae0c331fe7e 780 startTimeout();
highroads 0:aae0c331fe7e 781 while (readReg(0x83) == 0x00)
highroads 0:aae0c331fe7e 782 {
highroads 0:aae0c331fe7e 783 if (checkTimeoutExpired()) { return false; }
highroads 0:aae0c331fe7e 784 }
highroads 0:aae0c331fe7e 785 writeReg(0x83, 0x01);
highroads 0:aae0c331fe7e 786 tmp = readReg(0x92);
highroads 0:aae0c331fe7e 787
highroads 0:aae0c331fe7e 788 *count = tmp & 0x7f;
highroads 0:aae0c331fe7e 789 *type_is_aperture = (tmp >> 7) & 0x01;
highroads 0:aae0c331fe7e 790
highroads 0:aae0c331fe7e 791 writeReg(0x81, 0x00);
highroads 0:aae0c331fe7e 792 writeReg(0xFF, 0x06);
highroads 0:aae0c331fe7e 793 writeReg(0x83, readReg( 0x83 & ~0x04));
highroads 0:aae0c331fe7e 794 writeReg(0xFF, 0x01);
highroads 0:aae0c331fe7e 795 writeReg(0x00, 0x01);
highroads 0:aae0c331fe7e 796
highroads 0:aae0c331fe7e 797 writeReg(0xFF, 0x00);
highroads 0:aae0c331fe7e 798 writeReg(0x80, 0x00);
highroads 0:aae0c331fe7e 799
highroads 0:aae0c331fe7e 800 return true;
highroads 0:aae0c331fe7e 801 }
highroads 0:aae0c331fe7e 802
highroads 0:aae0c331fe7e 803 // Get sequence step enables
highroads 0:aae0c331fe7e 804 // based on VL53L0X_GetSequenceStepEnables()
highroads 0:aae0c331fe7e 805 void VL53L0X::getSequenceStepEnables(SequenceStepEnables * enables)
highroads 0:aae0c331fe7e 806 {
highroads 0:aae0c331fe7e 807 uint8_t sequence_config = readReg(SYSTEM_SEQUENCE_CONFIG);
highroads 0:aae0c331fe7e 808
highroads 0:aae0c331fe7e 809 enables->tcc = (sequence_config >> 4) & 0x1;
highroads 0:aae0c331fe7e 810 enables->dss = (sequence_config >> 3) & 0x1;
highroads 0:aae0c331fe7e 811 enables->msrc = (sequence_config >> 2) & 0x1;
highroads 0:aae0c331fe7e 812 enables->pre_range = (sequence_config >> 6) & 0x1;
highroads 0:aae0c331fe7e 813 enables->final_range = (sequence_config >> 7) & 0x1;
highroads 0:aae0c331fe7e 814 }
highroads 0:aae0c331fe7e 815
highroads 0:aae0c331fe7e 816 // Get sequence step timeouts
highroads 0:aae0c331fe7e 817 // based on get_sequence_step_timeout(),
highroads 0:aae0c331fe7e 818 // but gets all timeouts instead of just the requested one, and also stores
highroads 0:aae0c331fe7e 819 // intermediate values
highroads 0:aae0c331fe7e 820 void VL53L0X::getSequenceStepTimeouts(SequenceStepEnables const * enables, SequenceStepTimeouts * timeouts)
highroads 0:aae0c331fe7e 821 {
highroads 0:aae0c331fe7e 822 timeouts->pre_range_vcsel_period_pclks = getVcselPulsePeriod(VcselPeriodPreRange);
highroads 0:aae0c331fe7e 823
highroads 0:aae0c331fe7e 824 timeouts->msrc_dss_tcc_mclks = readReg(MSRC_CONFIG_TIMEOUT_MACROP) + 1;
highroads 0:aae0c331fe7e 825 timeouts->msrc_dss_tcc_us =
highroads 0:aae0c331fe7e 826 timeoutMclksToMicroseconds(timeouts->msrc_dss_tcc_mclks,
highroads 0:aae0c331fe7e 827 timeouts->pre_range_vcsel_period_pclks);
highroads 0:aae0c331fe7e 828
highroads 0:aae0c331fe7e 829 timeouts->pre_range_mclks =
highroads 0:aae0c331fe7e 830 decodeTimeout(readReg16Bit(PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI));
highroads 0:aae0c331fe7e 831 timeouts->pre_range_us =
highroads 0:aae0c331fe7e 832 timeoutMclksToMicroseconds(timeouts->pre_range_mclks,
highroads 0:aae0c331fe7e 833 timeouts->pre_range_vcsel_period_pclks);
highroads 0:aae0c331fe7e 834
highroads 0:aae0c331fe7e 835 timeouts->final_range_vcsel_period_pclks = getVcselPulsePeriod(VcselPeriodFinalRange);
highroads 0:aae0c331fe7e 836
highroads 0:aae0c331fe7e 837 timeouts->final_range_mclks =
highroads 0:aae0c331fe7e 838 decodeTimeout(readReg16Bit(FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI));
highroads 0:aae0c331fe7e 839
highroads 0:aae0c331fe7e 840 if (enables->pre_range)
highroads 0:aae0c331fe7e 841 {
highroads 0:aae0c331fe7e 842 timeouts->final_range_mclks -= timeouts->pre_range_mclks;
highroads 0:aae0c331fe7e 843 }
highroads 0:aae0c331fe7e 844
highroads 0:aae0c331fe7e 845 timeouts->final_range_us =
highroads 0:aae0c331fe7e 846 timeoutMclksToMicroseconds(timeouts->final_range_mclks,
highroads 0:aae0c331fe7e 847 timeouts->final_range_vcsel_period_pclks);
highroads 0:aae0c331fe7e 848 }
highroads 0:aae0c331fe7e 849
highroads 0:aae0c331fe7e 850 // Decode sequence step timeout in MCLKs from register value
highroads 0:aae0c331fe7e 851 // based on VL53L0X_decode_timeout()
highroads 0:aae0c331fe7e 852 // Note: the original function returned a uint32_t, but the return value is
highroads 0:aae0c331fe7e 853 // always stored in a uint16_t.
highroads 0:aae0c331fe7e 854 uint16_t VL53L0X::decodeTimeout(uint16_t reg_val)
highroads 0:aae0c331fe7e 855 {
highroads 0:aae0c331fe7e 856 // format: "(LSByte * 2^MSByte) + 1"
highroads 0:aae0c331fe7e 857 return (uint16_t)((reg_val & 0x00FF) <<
highroads 0:aae0c331fe7e 858 (uint16_t)((reg_val & 0xFF00) >> 8)) + 1;
highroads 0:aae0c331fe7e 859 }
highroads 0:aae0c331fe7e 860
highroads 0:aae0c331fe7e 861 // Encode sequence step timeout register value from timeout in MCLKs
highroads 0:aae0c331fe7e 862 // based on VL53L0X_encode_timeout()
highroads 0:aae0c331fe7e 863 // Note: the original function took a uint16_t, but the argument passed to it
highroads 0:aae0c331fe7e 864 // is always a uint16_t.
highroads 0:aae0c331fe7e 865 uint16_t VL53L0X::encodeTimeout(uint16_t timeout_mclks)
highroads 0:aae0c331fe7e 866 {
highroads 0:aae0c331fe7e 867 // format: "(LSByte * 2^MSByte) + 1"
highroads 0:aae0c331fe7e 868
highroads 0:aae0c331fe7e 869 uint32_t ls_byte = 0;
highroads 0:aae0c331fe7e 870 uint16_t ms_byte = 0;
highroads 0:aae0c331fe7e 871
highroads 0:aae0c331fe7e 872 if (timeout_mclks > 0)
highroads 0:aae0c331fe7e 873 {
highroads 0:aae0c331fe7e 874 ls_byte = timeout_mclks - 1;
highroads 0:aae0c331fe7e 875
highroads 0:aae0c331fe7e 876 while ((ls_byte & 0xFFFFFF00) > 0)
highroads 0:aae0c331fe7e 877 {
highroads 0:aae0c331fe7e 878 ls_byte >>= 1;
highroads 0:aae0c331fe7e 879 ms_byte++;
highroads 0:aae0c331fe7e 880 }
highroads 0:aae0c331fe7e 881
highroads 0:aae0c331fe7e 882 return (ms_byte << 8) | (ls_byte & 0xFF);
highroads 0:aae0c331fe7e 883 }
highroads 0:aae0c331fe7e 884 else { return 0; }
highroads 0:aae0c331fe7e 885 }
highroads 0:aae0c331fe7e 886
highroads 0:aae0c331fe7e 887 // Convert sequence step timeout from MCLKs to microseconds with given VCSEL period in PCLKs
highroads 0:aae0c331fe7e 888 // based on VL53L0X_calc_timeout_us()
highroads 0:aae0c331fe7e 889 uint32_t VL53L0X::timeoutMclksToMicroseconds(uint16_t timeout_period_mclks, uint8_t vcsel_period_pclks)
highroads 0:aae0c331fe7e 890 {
highroads 0:aae0c331fe7e 891 uint32_t macro_period_ns = calcMacroPeriod(vcsel_period_pclks);
highroads 0:aae0c331fe7e 892
highroads 0:aae0c331fe7e 893 return ((timeout_period_mclks * macro_period_ns) + (macro_period_ns / 2)) / 1000;
highroads 0:aae0c331fe7e 894 }
highroads 0:aae0c331fe7e 895
highroads 0:aae0c331fe7e 896 // Convert sequence step timeout from microseconds to MCLKs with given VCSEL period in PCLKs
highroads 0:aae0c331fe7e 897 // based on VL53L0X_calc_timeout_mclks()
highroads 0:aae0c331fe7e 898 uint32_t VL53L0X::timeoutMicrosecondsToMclks(uint32_t timeout_period_us, uint8_t vcsel_period_pclks)
highroads 0:aae0c331fe7e 899 {
highroads 0:aae0c331fe7e 900 uint32_t macro_period_ns = calcMacroPeriod(vcsel_period_pclks);
highroads 0:aae0c331fe7e 901
highroads 0:aae0c331fe7e 902 return (((timeout_period_us * 1000) + (macro_period_ns / 2)) / macro_period_ns);
highroads 0:aae0c331fe7e 903 }
highroads 0:aae0c331fe7e 904
highroads 0:aae0c331fe7e 905
highroads 0:aae0c331fe7e 906 // based on VL53L0X_perform_single_ref_calibration()
highroads 0:aae0c331fe7e 907 bool VL53L0X::performSingleRefCalibration(uint8_t vhv_init_byte)
highroads 0:aae0c331fe7e 908 {
highroads 0:aae0c331fe7e 909 writeReg(SYSRANGE_START, 0x01 | vhv_init_byte); // VL53L0X_REG_SYSRANGE_MODE_START_STOP
highroads 0:aae0c331fe7e 910
highroads 0:aae0c331fe7e 911 startTimeout();
highroads 0:aae0c331fe7e 912 while ((readReg(RESULT_INTERRUPT_STATUS) & 0x07) == 0)
highroads 0:aae0c331fe7e 913 {
highroads 0:aae0c331fe7e 914 if (checkTimeoutExpired()) { return false; }
highroads 0:aae0c331fe7e 915 }
highroads 0:aae0c331fe7e 916
highroads 0:aae0c331fe7e 917 writeReg(SYSTEM_INTERRUPT_CLEAR, 0x01);
highroads 0:aae0c331fe7e 918
highroads 0:aae0c331fe7e 919 writeReg(SYSRANGE_START, 0x00);
highroads 0:aae0c331fe7e 920
highroads 0:aae0c331fe7e 921 return true;
highroads 0:aae0c331fe7e 922 }
highroads 0:aae0c331fe7e 923
highroads 0:aae0c331fe7e 924 // Write an 8-bit register
highroads 0:aae0c331fe7e 925 void VL53L0X::writeReg(uint8_t reg, uint8_t value)
highroads 0:aae0c331fe7e 926 {
highroads 0:aae0c331fe7e 927 char data_write[2];
highroads 0:aae0c331fe7e 928 data_write[0]=reg;
highroads 0:aae0c331fe7e 929 data_write[1]=value;
highroads 0:aae0c331fe7e 930 m_i2c.write(m_addr,data_write,2);
highroads 0:aae0c331fe7e 931 }
highroads 0:aae0c331fe7e 932
highroads 0:aae0c331fe7e 933 // Write a 16-bit register
highroads 0:aae0c331fe7e 934 void VL53L0X::writeReg16Bit(uint8_t reg, uint16_t value)
highroads 0:aae0c331fe7e 935 {
highroads 0:aae0c331fe7e 936 char data_write[3];
highroads 0:aae0c331fe7e 937 data_write[0]=reg;
highroads 0:aae0c331fe7e 938 data_write[1]=(value >> 8) & 0xFF; // value high byte
highroads 0:aae0c331fe7e 939 data_write[2]=value & 0xFF; // value low byte
highroads 0:aae0c331fe7e 940 m_i2c.write(m_addr,data_write,3);
highroads 0:aae0c331fe7e 941 }
highroads 0:aae0c331fe7e 942
highroads 0:aae0c331fe7e 943 // Write a 32-bit register
highroads 0:aae0c331fe7e 944 void VL53L0X::writeReg32Bit(uint8_t reg, uint32_t value)
highroads 0:aae0c331fe7e 945 {
highroads 0:aae0c331fe7e 946 char data_write[5];
highroads 0:aae0c331fe7e 947 data_write[0]=reg;
highroads 0:aae0c331fe7e 948 data_write[1]=(value >> 24) & 0xFF; // value highest byte
highroads 0:aae0c331fe7e 949 data_write[2]=(value >> 16) & 0xFF;
highroads 0:aae0c331fe7e 950 data_write[3]=(value >> 8) & 0xFF;
highroads 0:aae0c331fe7e 951 data_write[4]= value & 0xFF; // value lowest byte
highroads 0:aae0c331fe7e 952 m_i2c.write(m_addr,data_write,5);
highroads 0:aae0c331fe7e 953 }
highroads 0:aae0c331fe7e 954
highroads 0:aae0c331fe7e 955 // Read an 8-bit register
highroads 0:aae0c331fe7e 956 uint8_t VL53L0X::readReg(uint8_t reg)
highroads 0:aae0c331fe7e 957 {
highroads 0:aae0c331fe7e 958 uint8_t value;
highroads 0:aae0c331fe7e 959 char data_write[1];
highroads 0:aae0c331fe7e 960 char data_read[1];
highroads 0:aae0c331fe7e 961
highroads 0:aae0c331fe7e 962 data_write[0]=reg;
highroads 0:aae0c331fe7e 963 m_i2c.write(m_addr,data_write,1);
highroads 0:aae0c331fe7e 964 m_i2c.read(m_addr,data_read,1);
highroads 0:aae0c331fe7e 965 value=data_read[0];
highroads 0:aae0c331fe7e 966 return value;
highroads 0:aae0c331fe7e 967 }
highroads 0:aae0c331fe7e 968
highroads 0:aae0c331fe7e 969 // Read a 16-bit register
highroads 0:aae0c331fe7e 970 uint16_t VL53L0X::readReg16Bit(uint8_t reg)
highroads 0:aae0c331fe7e 971 {
highroads 0:aae0c331fe7e 972 uint16_t value;
highroads 0:aae0c331fe7e 973 uint8_t data_high;
highroads 0:aae0c331fe7e 974 uint8_t data_low;
highroads 0:aae0c331fe7e 975 char data_write[1];
highroads 0:aae0c331fe7e 976 char data_read[2];
highroads 0:aae0c331fe7e 977
highroads 0:aae0c331fe7e 978 data_write[0]=reg;
highroads 0:aae0c331fe7e 979 m_i2c.write(m_addr,data_write,1);
highroads 0:aae0c331fe7e 980 m_i2c.read(m_addr,data_read,2);
highroads 0:aae0c331fe7e 981 data_high=data_read[0]; // value high byte
highroads 0:aae0c331fe7e 982 data_low=data_read[1]; // value low byte
highroads 0:aae0c331fe7e 983 value = (data_high << 8)| data_low;
highroads 0:aae0c331fe7e 984
highroads 0:aae0c331fe7e 985 return value;
highroads 0:aae0c331fe7e 986 }
highroads 0:aae0c331fe7e 987
highroads 0:aae0c331fe7e 988 // Read a 32-bit register
highroads 0:aae0c331fe7e 989 uint32_t VL53L0X::readReg32Bit(uint8_t reg)
highroads 0:aae0c331fe7e 990 {
highroads 0:aae0c331fe7e 991 uint32_t value;
highroads 0:aae0c331fe7e 992 uint8_t data_high;
highroads 0:aae0c331fe7e 993 uint8_t data_2;
highroads 0:aae0c331fe7e 994 uint8_t data_1;
highroads 0:aae0c331fe7e 995 uint8_t data_low;
highroads 0:aae0c331fe7e 996 char data_write[1];
highroads 0:aae0c331fe7e 997 char data_read[4];
highroads 0:aae0c331fe7e 998
highroads 0:aae0c331fe7e 999 data_write[0]=reg;
highroads 0:aae0c331fe7e 1000 m_i2c.write(m_addr,data_write,1);
highroads 0:aae0c331fe7e 1001 m_i2c.read(m_addr,data_read,4);
highroads 0:aae0c331fe7e 1002
highroads 0:aae0c331fe7e 1003 data_high=data_read[0];
highroads 0:aae0c331fe7e 1004 data_2=data_read[1];
highroads 0:aae0c331fe7e 1005 data_1=data_read[2];
highroads 0:aae0c331fe7e 1006 data_low=data_read[3];
highroads 0:aae0c331fe7e 1007
highroads 0:aae0c331fe7e 1008 value = (data_high << 24)|(data_2 << 16)|(data_1 << 8)|(data_low); // value highest byte
highroads 0:aae0c331fe7e 1009
highroads 0:aae0c331fe7e 1010 return value;
highroads 0:aae0c331fe7e 1011 }
highroads 0:aae0c331fe7e 1012
highroads 0:aae0c331fe7e 1013 // Write an arbitrary number of bytes from the given array to the sensor,
highroads 0:aae0c331fe7e 1014 // starting at the given register
highroads 0:aae0c331fe7e 1015 void VL53L0X::writeMulti(uint8_t reg, char src[], uint8_t count)
highroads 0:aae0c331fe7e 1016 {
highroads 0:aae0c331fe7e 1017 char data_write[1];
highroads 0:aae0c331fe7e 1018 data_write[0]=reg;
highroads 0:aae0c331fe7e 1019 m_i2c.write(m_addr,data_write,1);
highroads 0:aae0c331fe7e 1020 m_i2c.write(m_addr,src,count);
highroads 0:aae0c331fe7e 1021 }
highroads 0:aae0c331fe7e 1022
highroads 0:aae0c331fe7e 1023 // Read an arbitrary number of bytes from the sensor, starting at the given
highroads 0:aae0c331fe7e 1024 // register, into the given array
highroads 0:aae0c331fe7e 1025 void VL53L0X::readMulti(uint8_t reg, char dst[], uint8_t count)
highroads 0:aae0c331fe7e 1026 {
highroads 0:aae0c331fe7e 1027 char data_write[1];
highroads 0:aae0c331fe7e 1028 data_write[0]=reg;
highroads 0:aae0c331fe7e 1029 m_i2c.write(m_addr,data_write,1);
highroads 0:aae0c331fe7e 1030 m_i2c.read(m_addr,dst,count);
highroads 0:aae0c331fe7e 1031 }