Henrique Rosa
/
ILI9341_01_PAR8_Teste_V3
Testanto funções Display
MCUFRIEND_kbv/utility/mcufriend_shield.h@1:a5ccd53612ea, 2021-04-21 (annotated)
- Committer:
- silviosz
- Date:
- Wed Apr 21 14:54:37 2021 +0000
- Revision:
- 1:a5ccd53612ea
ILI9341 display controller; parallel connection (Arduino Shield); NUCLEO-F103RB tested (2021-04-21) = success!
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
silviosz | 1:a5ccd53612ea | 1 | //#define USE_SPECIAL //check for custom drivers |
silviosz | 1:a5ccd53612ea | 2 | |
silviosz | 1:a5ccd53612ea | 3 | #define WR_ACTIVE2 {WR_ACTIVE; WR_ACTIVE;} |
silviosz | 1:a5ccd53612ea | 4 | #define WR_ACTIVE4 {WR_ACTIVE2; WR_ACTIVE2;} |
silviosz | 1:a5ccd53612ea | 5 | #define WR_ACTIVE8 {WR_ACTIVE4; WR_ACTIVE4;} |
silviosz | 1:a5ccd53612ea | 6 | #define RD_ACTIVE2 {RD_ACTIVE; RD_ACTIVE;} |
silviosz | 1:a5ccd53612ea | 7 | #define RD_ACTIVE4 {RD_ACTIVE2; RD_ACTIVE2;} |
silviosz | 1:a5ccd53612ea | 8 | #define RD_ACTIVE8 {RD_ACTIVE4; RD_ACTIVE4;} |
silviosz | 1:a5ccd53612ea | 9 | #define RD_ACTIVE16 {RD_ACTIVE8; RD_ACTIVE8;} |
silviosz | 1:a5ccd53612ea | 10 | #define WR_IDLE2 {WR_IDLE; WR_IDLE;} |
silviosz | 1:a5ccd53612ea | 11 | #define WR_IDLE4 {WR_IDLE2; WR_IDLE2;} |
silviosz | 1:a5ccd53612ea | 12 | #define RD_IDLE2 {RD_IDLE; RD_IDLE;} |
silviosz | 1:a5ccd53612ea | 13 | #define RD_IDLE4 {RD_IDLE2; RD_IDLE2;} |
silviosz | 1:a5ccd53612ea | 14 | |
silviosz | 1:a5ccd53612ea | 15 | #if defined(USE_SPECIAL) |
silviosz | 1:a5ccd53612ea | 16 | #include "mcufriend_special.h" |
silviosz | 1:a5ccd53612ea | 17 | #if !defined(USE_SPECIAL_FAIL) |
silviosz | 1:a5ccd53612ea | 18 | #warning WE ARE USING A SPECIAL CUSTOM DRIVER |
silviosz | 1:a5ccd53612ea | 19 | #endif |
silviosz | 1:a5ccd53612ea | 20 | #endif |
silviosz | 1:a5ccd53612ea | 21 | #if !defined(USE_SPECIAL) || defined (USE_SPECIAL_FAIL) |
silviosz | 1:a5ccd53612ea | 22 | |
silviosz | 1:a5ccd53612ea | 23 | #if 0 |
silviosz | 1:a5ccd53612ea | 24 | //################################### UNO ############################## |
silviosz | 1:a5ccd53612ea | 25 | #elif defined(__AVR_ATmega328P__) || defined(__AVR_ATmega328PB__) //regular UNO shield on UNO |
silviosz | 1:a5ccd53612ea | 26 | #define RD_PORT PORTC |
silviosz | 1:a5ccd53612ea | 27 | #define RD_PIN 0 |
silviosz | 1:a5ccd53612ea | 28 | #define WR_PORT PORTC |
silviosz | 1:a5ccd53612ea | 29 | #define WR_PIN 1 |
silviosz | 1:a5ccd53612ea | 30 | #define CD_PORT PORTC |
silviosz | 1:a5ccd53612ea | 31 | #define CD_PIN 2 |
silviosz | 1:a5ccd53612ea | 32 | #define CS_PORT PORTC |
silviosz | 1:a5ccd53612ea | 33 | #define CS_PIN 3 |
silviosz | 1:a5ccd53612ea | 34 | #define RESET_PORT PORTC |
silviosz | 1:a5ccd53612ea | 35 | #define RESET_PIN 4 |
silviosz | 1:a5ccd53612ea | 36 | |
silviosz | 1:a5ccd53612ea | 37 | #define BMASK 0x03 //more intuitive style for mixed Ports |
silviosz | 1:a5ccd53612ea | 38 | #define DMASK 0xFC //does exactly the same as previous |
silviosz | 1:a5ccd53612ea | 39 | #define write_8(x) { PORTB = (PORTB & ~BMASK) | ((x) & BMASK); PORTD = (PORTD & ~DMASK) | ((x) & DMASK); } |
silviosz | 1:a5ccd53612ea | 40 | #define read_8() ( (PINB & BMASK) | (PIND & DMASK) ) |
silviosz | 1:a5ccd53612ea | 41 | #define setWriteDir() { DDRB |= BMASK; DDRD |= DMASK; } |
silviosz | 1:a5ccd53612ea | 42 | #define setReadDir() { DDRB &= ~BMASK; DDRD &= ~DMASK; } |
silviosz | 1:a5ccd53612ea | 43 | #define write8(x) { write_8(x); WR_STROBE; } |
silviosz | 1:a5ccd53612ea | 44 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
silviosz | 1:a5ccd53612ea | 45 | #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; } |
silviosz | 1:a5ccd53612ea | 46 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
silviosz | 1:a5ccd53612ea | 47 | |
silviosz | 1:a5ccd53612ea | 48 | #define PIN_LOW(p, b) (p) &= ~(1<<(b)) |
silviosz | 1:a5ccd53612ea | 49 | #define PIN_HIGH(p, b) (p) |= (1<<(b)) |
silviosz | 1:a5ccd53612ea | 50 | #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b)) |
silviosz | 1:a5ccd53612ea | 51 | |
silviosz | 1:a5ccd53612ea | 52 | //################################### MEGA2560 ############################## |
silviosz | 1:a5ccd53612ea | 53 | #elif defined(__AVR_ATmega2560__) || defined(__AVR_ATmega1280__) //regular UNO shield on MEGA2560 |
silviosz | 1:a5ccd53612ea | 54 | #define RD_PORT PORTF |
silviosz | 1:a5ccd53612ea | 55 | #define RD_PIN 0 |
silviosz | 1:a5ccd53612ea | 56 | #define WR_PORT PORTF |
silviosz | 1:a5ccd53612ea | 57 | #define WR_PIN 1 |
silviosz | 1:a5ccd53612ea | 58 | #define CD_PORT PORTF |
silviosz | 1:a5ccd53612ea | 59 | #define CD_PIN 2 |
silviosz | 1:a5ccd53612ea | 60 | #define CS_PORT PORTF |
silviosz | 1:a5ccd53612ea | 61 | #define CS_PIN 3 |
silviosz | 1:a5ccd53612ea | 62 | #define RESET_PORT PORTF |
silviosz | 1:a5ccd53612ea | 63 | #define RESET_PIN 4 |
silviosz | 1:a5ccd53612ea | 64 | |
silviosz | 1:a5ccd53612ea | 65 | #define EMASK 0x38 |
silviosz | 1:a5ccd53612ea | 66 | #define GMASK 0x20 |
silviosz | 1:a5ccd53612ea | 67 | #define HMASK 0x78 |
silviosz | 1:a5ccd53612ea | 68 | #define write_8(x) { PORTH &= ~HMASK; PORTG &= ~GMASK; PORTE &= ~EMASK; \ |
silviosz | 1:a5ccd53612ea | 69 | PORTH |= (((x) & (3<<0)) << 5); \ |
silviosz | 1:a5ccd53612ea | 70 | PORTE |= (((x) & (3<<2)) << 2); \ |
silviosz | 1:a5ccd53612ea | 71 | PORTG |= (((x) & (1<<4)) << 1); \ |
silviosz | 1:a5ccd53612ea | 72 | PORTE |= (((x) & (1<<5)) >> 2); \ |
silviosz | 1:a5ccd53612ea | 73 | PORTH |= (((x) & (3<<6)) >> 3); \ |
silviosz | 1:a5ccd53612ea | 74 | } |
silviosz | 1:a5ccd53612ea | 75 | |
silviosz | 1:a5ccd53612ea | 76 | #define read_8() ( ((PINH & (3<<5)) >> 5)\ |
silviosz | 1:a5ccd53612ea | 77 | | ((PINE & (3<<4)) >> 2)\ |
silviosz | 1:a5ccd53612ea | 78 | | ((PING & (1<<5)) >> 1)\ |
silviosz | 1:a5ccd53612ea | 79 | | ((PINE & (1<<3)) << 2)\ |
silviosz | 1:a5ccd53612ea | 80 | | ((PINH & (3<<3)) << 3)\ |
silviosz | 1:a5ccd53612ea | 81 | ) |
silviosz | 1:a5ccd53612ea | 82 | #define setWriteDir() { DDRH |= HMASK; DDRG |= GMASK; DDRE |= EMASK; } |
silviosz | 1:a5ccd53612ea | 83 | #define setReadDir() { DDRH &= ~HMASK; DDRG &= ~GMASK; DDRE &= ~EMASK; } |
silviosz | 1:a5ccd53612ea | 84 | #define write8(x) { write_8(x); WR_STROBE; } |
silviosz | 1:a5ccd53612ea | 85 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
silviosz | 1:a5ccd53612ea | 86 | #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; } |
silviosz | 1:a5ccd53612ea | 87 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
silviosz | 1:a5ccd53612ea | 88 | |
silviosz | 1:a5ccd53612ea | 89 | #define PIN_LOW(p, b) (p) &= ~(1<<(b)) |
silviosz | 1:a5ccd53612ea | 90 | #define PIN_HIGH(p, b) (p) |= (1<<(b)) |
silviosz | 1:a5ccd53612ea | 91 | #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b)) |
silviosz | 1:a5ccd53612ea | 92 | |
silviosz | 1:a5ccd53612ea | 93 | //################################### MEGA4809 NANO_EVERY 4808 ############################## |
silviosz | 1:a5ccd53612ea | 94 | #elif defined(__AVR_ATmega4808__) // Thinary EVERY-4808 with Nano-Shield_Adapter |
silviosz | 1:a5ccd53612ea | 95 | #warning EVERY-4808 with Nano-Shield_Adapter |
silviosz | 1:a5ccd53612ea | 96 | #define RD_PORT VPORTD // |
silviosz | 1:a5ccd53612ea | 97 | #define RD_PIN 0 |
silviosz | 1:a5ccd53612ea | 98 | #define WR_PORT VPORTD |
silviosz | 1:a5ccd53612ea | 99 | #define WR_PIN 1 |
silviosz | 1:a5ccd53612ea | 100 | #define CD_PORT VPORTD |
silviosz | 1:a5ccd53612ea | 101 | #define CD_PIN 2 |
silviosz | 1:a5ccd53612ea | 102 | #define CS_PORT VPORTD |
silviosz | 1:a5ccd53612ea | 103 | #define CS_PIN 3 |
silviosz | 1:a5ccd53612ea | 104 | #define RESET_PORT VPORTF |
silviosz | 1:a5ccd53612ea | 105 | #define RESET_PIN 2 |
silviosz | 1:a5ccd53612ea | 106 | |
silviosz | 1:a5ccd53612ea | 107 | #define AMASK 0xFF |
silviosz | 1:a5ccd53612ea | 108 | #define write_8(x) { VPORTA.OUT = ((x) << 6) | ((x) >> 2); } |
silviosz | 1:a5ccd53612ea | 109 | #define read_8() ( (VPORTA.IN >> 6) | (VPORTA.IN << 2) ) |
silviosz | 1:a5ccd53612ea | 110 | #define setWriteDir() { VPORTA_DIR |= AMASK; } |
silviosz | 1:a5ccd53612ea | 111 | #define setReadDir() { VPORTA_DIR &= ~AMASK; } |
silviosz | 1:a5ccd53612ea | 112 | |
silviosz | 1:a5ccd53612ea | 113 | //#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; } //6.47s no_inline |
silviosz | 1:a5ccd53612ea | 114 | #define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //-Os=5.43s @20MHz always_inline. (-O1=5.41s, -O3=5.25s) |
silviosz | 1:a5ccd53612ea | 115 | #define READ_DELAY { RD_ACTIVE4; } //ID=0x7789 |
silviosz | 1:a5ccd53612ea | 116 | #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; } |
silviosz | 1:a5ccd53612ea | 117 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
silviosz | 1:a5ccd53612ea | 118 | #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } |
silviosz | 1:a5ccd53612ea | 119 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
silviosz | 1:a5ccd53612ea | 120 | |
silviosz | 1:a5ccd53612ea | 121 | #define PIN_LOW(p, b) (p).OUT &= ~(1<<(b)) |
silviosz | 1:a5ccd53612ea | 122 | #define PIN_HIGH(p, b) (p).OUT |= (1<<(b)) |
silviosz | 1:a5ccd53612ea | 123 | #define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b)) |
silviosz | 1:a5ccd53612ea | 124 | |
silviosz | 1:a5ccd53612ea | 125 | //################################### MEGA4809 NANO_EVERY ############################## |
silviosz | 1:a5ccd53612ea | 126 | #elif defined(__AVR_ATmega4809__) && defined(ARDUINO_AVR_NANO_EVERY) // EVERY-4809 with Nano-Shield_Adapter |
silviosz | 1:a5ccd53612ea | 127 | #warning EVERY-4809 with Nano-Shield_Adapter using VPORT.OUT and BLD/BST |
silviosz | 1:a5ccd53612ea | 128 | #define RD_PORT VPORTD // |
silviosz | 1:a5ccd53612ea | 129 | #define RD_PIN 3 |
silviosz | 1:a5ccd53612ea | 130 | #define WR_PORT VPORTD |
silviosz | 1:a5ccd53612ea | 131 | #define WR_PIN 2 |
silviosz | 1:a5ccd53612ea | 132 | #define CD_PORT VPORTD |
silviosz | 1:a5ccd53612ea | 133 | #define CD_PIN 1 |
silviosz | 1:a5ccd53612ea | 134 | #define CS_PORT VPORTD |
silviosz | 1:a5ccd53612ea | 135 | #define CS_PIN 0 |
silviosz | 1:a5ccd53612ea | 136 | #define RESET_PORT VPORTF |
silviosz | 1:a5ccd53612ea | 137 | #define RESET_PIN 2 |
silviosz | 1:a5ccd53612ea | 138 | |
silviosz | 1:a5ccd53612ea | 139 | #define AMASK (3<<0) |
silviosz | 1:a5ccd53612ea | 140 | #define BMASK (5<<0) |
silviosz | 1:a5ccd53612ea | 141 | #define CMASK (1<<6) |
silviosz | 1:a5ccd53612ea | 142 | #define EMASK (1<<3) |
silviosz | 1:a5ccd53612ea | 143 | #define FMASK (3<<4) |
silviosz | 1:a5ccd53612ea | 144 | static __attribute((always_inline)) |
silviosz | 1:a5ccd53612ea | 145 | void write_8(uint8_t val) |
silviosz | 1:a5ccd53612ea | 146 | { |
silviosz | 1:a5ccd53612ea | 147 | asm volatile("in __tmp_reg__,0x01" "\n\t" //VPORTA.OUT |
silviosz | 1:a5ccd53612ea | 148 | "BST %0,2" "\n\t" "BLD __tmp_reg__,0" "\n\t" |
silviosz | 1:a5ccd53612ea | 149 | "BST %0,7" "\n\t" "BLD __tmp_reg__,1" "\n\t" |
silviosz | 1:a5ccd53612ea | 150 | "out 0x01,__tmp_reg__" : : "a" (val)); |
silviosz | 1:a5ccd53612ea | 151 | asm volatile("in __tmp_reg__,0x05" "\n\t" //VPORTB.OUT |
silviosz | 1:a5ccd53612ea | 152 | "BST %0,1" "\n\t" "BLD __tmp_reg__,0" "\n\t" |
silviosz | 1:a5ccd53612ea | 153 | "BST %0,5" "\n\t" "BLD __tmp_reg__,2" "\n\t" |
silviosz | 1:a5ccd53612ea | 154 | "out 0x05,__tmp_reg__" : : "a" (val)); |
silviosz | 1:a5ccd53612ea | 155 | asm volatile("in __tmp_reg__,0x09" "\n\t" //VPORTC.OUT |
silviosz | 1:a5ccd53612ea | 156 | "BST %0,4" "\n\t" "BLD __tmp_reg__,6" "\n\t" |
silviosz | 1:a5ccd53612ea | 157 | "out 0x09,__tmp_reg__" : : "a" (val)); |
silviosz | 1:a5ccd53612ea | 158 | asm volatile("in __tmp_reg__,0x11" "\n\t" //VPORTE.OUT |
silviosz | 1:a5ccd53612ea | 159 | "BST %0,0" "\n\t" "BLD __tmp_reg__,3" "\n\t" |
silviosz | 1:a5ccd53612ea | 160 | "out 0x11,__tmp_reg__" : : "a" (val)); |
silviosz | 1:a5ccd53612ea | 161 | asm volatile("in __tmp_reg__,0x15" "\n\t" //VPORTF.OUT |
silviosz | 1:a5ccd53612ea | 162 | "BST %0,3" "\n\t" "BLD __tmp_reg__,5" "\n\t" |
silviosz | 1:a5ccd53612ea | 163 | "BST %0,6" "\n\t" "BLD __tmp_reg__,4" "\n\t" |
silviosz | 1:a5ccd53612ea | 164 | "out 0x15,__tmp_reg__" : : "a" (val)); |
silviosz | 1:a5ccd53612ea | 165 | } |
silviosz | 1:a5ccd53612ea | 166 | |
silviosz | 1:a5ccd53612ea | 167 | #define read_8() ( 0 \ |
silviosz | 1:a5ccd53612ea | 168 | | ((VPORTA_IN & (1<<0)) << 2)\ |
silviosz | 1:a5ccd53612ea | 169 | | ((VPORTA_IN & (1<<1)) << 6)\ |
silviosz | 1:a5ccd53612ea | 170 | | ((VPORTB_IN & (1<<0)) << 1)\ |
silviosz | 1:a5ccd53612ea | 171 | | ((VPORTB_IN & (1<<2)) << 3)\ |
silviosz | 1:a5ccd53612ea | 172 | | ((VPORTC_IN & CMASK) >> 2)\ |
silviosz | 1:a5ccd53612ea | 173 | | ((VPORTE_IN & EMASK) >> 3)\ |
silviosz | 1:a5ccd53612ea | 174 | | ((VPORTF_IN & (1<<5)) >> 2)\ |
silviosz | 1:a5ccd53612ea | 175 | | ((VPORTF_IN & (1<<4)) << 2)\ |
silviosz | 1:a5ccd53612ea | 176 | ) |
silviosz | 1:a5ccd53612ea | 177 | #define setWriteDir() { VPORTA_DIR |= AMASK; VPORTB_DIR |= BMASK; VPORTC_DIR |= CMASK; VPORTE_DIR |= EMASK; VPORTF_DIR |= FMASK; } |
silviosz | 1:a5ccd53612ea | 178 | #define setReadDir() { VPORTA_DIR &= ~AMASK; VPORTB_DIR &= ~BMASK; VPORTC_DIR &= ~CMASK; VPORTE_DIR &= ~EMASK; VPORTF_DIR &= ~FMASK; } |
silviosz | 1:a5ccd53612ea | 179 | |
silviosz | 1:a5ccd53612ea | 180 | //#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; } //6.47s no_inline |
silviosz | 1:a5ccd53612ea | 181 | #define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //-Os=5.43s @20MHz always_inline. (-O1=5.41s, -O3=5.25s) |
silviosz | 1:a5ccd53612ea | 182 | #define READ_DELAY { RD_ACTIVE4; } //ID=0x7789 |
silviosz | 1:a5ccd53612ea | 183 | #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; } |
silviosz | 1:a5ccd53612ea | 184 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
silviosz | 1:a5ccd53612ea | 185 | #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } |
silviosz | 1:a5ccd53612ea | 186 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
silviosz | 1:a5ccd53612ea | 187 | |
silviosz | 1:a5ccd53612ea | 188 | #define PIN_LOW(p, b) (p).OUT &= ~(1<<(b)) |
silviosz | 1:a5ccd53612ea | 189 | #define PIN_HIGH(p, b) (p).OUT |= (1<<(b)) |
silviosz | 1:a5ccd53612ea | 190 | #define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b)) |
silviosz | 1:a5ccd53612ea | 191 | |
silviosz | 1:a5ccd53612ea | 192 | //################################### TEENSY++2.0 ############################## |
silviosz | 1:a5ccd53612ea | 193 | #elif defined(__AVR_AT90USB1286__) //regular UNO shield on TEENSY++ 2.0 thanks tysonlt |
silviosz | 1:a5ccd53612ea | 194 | |
silviosz | 1:a5ccd53612ea | 195 | //LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST| |
silviosz | 1:a5ccd53612ea | 196 | //AVR pin |PD7|PD6|PD5|PD4|PD3|PD2|PE1|PE0| |PF0|PF1|PF2|PF3|PF4| |
silviosz | 1:a5ccd53612ea | 197 | |
silviosz | 1:a5ccd53612ea | 198 | #define RD_PORT PORTF |
silviosz | 1:a5ccd53612ea | 199 | #define RD_PIN 0 |
silviosz | 1:a5ccd53612ea | 200 | #define WR_PORT PORTF |
silviosz | 1:a5ccd53612ea | 201 | #define WR_PIN 1 |
silviosz | 1:a5ccd53612ea | 202 | #define CD_PORT PORTF |
silviosz | 1:a5ccd53612ea | 203 | #define CD_PIN 2 |
silviosz | 1:a5ccd53612ea | 204 | #define CS_PORT PORTF |
silviosz | 1:a5ccd53612ea | 205 | #define CS_PIN 3 |
silviosz | 1:a5ccd53612ea | 206 | #define RESET_PORT PORTF |
silviosz | 1:a5ccd53612ea | 207 | #define RESET_PIN 4 |
silviosz | 1:a5ccd53612ea | 208 | |
silviosz | 1:a5ccd53612ea | 209 | #define EMASK 0x03 //more intuitive style for mixed Ports |
silviosz | 1:a5ccd53612ea | 210 | #define DMASK 0xFC //does exactly the same as previous |
silviosz | 1:a5ccd53612ea | 211 | #define write_8(x) { PORTE = (PORTE & ~EMASK) | ((x) & EMASK); PORTD = (PORTD & ~DMASK) | ((x) & DMASK); } |
silviosz | 1:a5ccd53612ea | 212 | #define read_8() ( (PINE & EMASK) | (PIND & DMASK) ) |
silviosz | 1:a5ccd53612ea | 213 | #define setWriteDir() { DDRE |= EMASK; DDRD |= DMASK; } |
silviosz | 1:a5ccd53612ea | 214 | #define setReadDir() { DDRE &= ~EMASK; DDRD &= ~DMASK; } |
silviosz | 1:a5ccd53612ea | 215 | #define write8(x) { write_8(x); WR_STROBE; } |
silviosz | 1:a5ccd53612ea | 216 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
silviosz | 1:a5ccd53612ea | 217 | #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; } |
silviosz | 1:a5ccd53612ea | 218 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
silviosz | 1:a5ccd53612ea | 219 | |
silviosz | 1:a5ccd53612ea | 220 | #define PIN_LOW(p, b) (p) &= ~(1<<(b)) |
silviosz | 1:a5ccd53612ea | 221 | #define PIN_HIGH(p, b) (p) |= (1<<(b)) |
silviosz | 1:a5ccd53612ea | 222 | #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b)) |
silviosz | 1:a5ccd53612ea | 223 | |
silviosz | 1:a5ccd53612ea | 224 | //################################# ZERO and M0_PRO ############################ |
silviosz | 1:a5ccd53612ea | 225 | #elif defined(__SAMD21G18A__) //regular UNO shield on ZERO or M0_PRO |
silviosz | 1:a5ccd53612ea | 226 | #include "sam.h" |
silviosz | 1:a5ccd53612ea | 227 | // configure macros for the control pins |
silviosz | 1:a5ccd53612ea | 228 | #define RD_PORT PORT->Group[0] |
silviosz | 1:a5ccd53612ea | 229 | #define RD_PIN 2 |
silviosz | 1:a5ccd53612ea | 230 | #define WR_PORT PORT->Group[1] |
silviosz | 1:a5ccd53612ea | 231 | #define WR_PIN 8 |
silviosz | 1:a5ccd53612ea | 232 | #define CD_PORT PORT->Group[1] |
silviosz | 1:a5ccd53612ea | 233 | #define CD_PIN 9 |
silviosz | 1:a5ccd53612ea | 234 | #define CS_PORT PORT->Group[0] |
silviosz | 1:a5ccd53612ea | 235 | #define CS_PIN 4 |
silviosz | 1:a5ccd53612ea | 236 | #define RESET_PORT PORT->Group[0] |
silviosz | 1:a5ccd53612ea | 237 | #define RESET_PIN 5 |
silviosz | 1:a5ccd53612ea | 238 | // configure macros for data bus |
silviosz | 1:a5ccd53612ea | 239 | #define DMASK 0x0030C3C0 |
silviosz | 1:a5ccd53612ea | 240 | // #define write_8(x) PORT->Group[0].OUT.reg = (PORT->Group[0].OUT.reg & ~DMASK)|(((x) & 0x0F) << 6)|(((x) & 0x30) << 10)|(((x) & 0xC0)<<14) |
silviosz | 1:a5ccd53612ea | 241 | #if defined(ARDUINO_SAMD_ZERO) || defined(ARDUINO_SAMD_ZERO) // American ZERO |
silviosz | 1:a5ccd53612ea | 242 | #define write_8(x) {\ |
silviosz | 1:a5ccd53612ea | 243 | PORT->Group[0].OUTCLR.reg = DMASK;\ |
silviosz | 1:a5ccd53612ea | 244 | PORT->Group[0].OUTSET.reg = (((x) & 0x0B) << 6)\ |
silviosz | 1:a5ccd53612ea | 245 | |(((x) & (1<<2)) << 12)\ |
silviosz | 1:a5ccd53612ea | 246 | |(((x) & (1<<4)) << 4)\ |
silviosz | 1:a5ccd53612ea | 247 | |(((x) & (1<<5)) << 10)\ |
silviosz | 1:a5ccd53612ea | 248 | |(((x) & 0xC0) << 14);\ |
silviosz | 1:a5ccd53612ea | 249 | } |
silviosz | 1:a5ccd53612ea | 250 | #define read_8() (((PORT->Group[0].IN.reg >> 6) & 0x0B)\ |
silviosz | 1:a5ccd53612ea | 251 | |((PORT->Group[0].IN.reg >> 12) & (1<<2))\ |
silviosz | 1:a5ccd53612ea | 252 | |((PORT->Group[0].IN.reg >> 4) & (1<<4))\ |
silviosz | 1:a5ccd53612ea | 253 | |((PORT->Group[0].IN.reg >> 10) & (1<<5))\ |
silviosz | 1:a5ccd53612ea | 254 | |((PORT->Group[0].IN.reg >> 14) & 0xC0)) |
silviosz | 1:a5ccd53612ea | 255 | #else //default to an M0_PRO on v1.6.5 or 1.7.6 |
silviosz | 1:a5ccd53612ea | 256 | #define write_8(x) {\ |
silviosz | 1:a5ccd53612ea | 257 | PORT->Group[0].OUTCLR.reg = DMASK;\ |
silviosz | 1:a5ccd53612ea | 258 | PORT->Group[0].OUTSET.reg = (((x) & 0x0F) << 6)\ |
silviosz | 1:a5ccd53612ea | 259 | |(((x) & 0x30) << 10)\ |
silviosz | 1:a5ccd53612ea | 260 | |(((x) & 0xC0) << 14);\ |
silviosz | 1:a5ccd53612ea | 261 | } |
silviosz | 1:a5ccd53612ea | 262 | #define read_8() (((PORT->Group[0].IN.reg >> 6) & 0x0F)|((PORT->Group[0].IN.reg >> 10) & 0x30)|((PORT->Group[0].IN.reg >> 14) & 0xC0)) |
silviosz | 1:a5ccd53612ea | 263 | #endif |
silviosz | 1:a5ccd53612ea | 264 | #define setWriteDir() { PORT->Group[0].DIRSET.reg = DMASK; \ |
silviosz | 1:a5ccd53612ea | 265 | PORT->Group[0].WRCONFIG.reg = (DMASK & 0xFFFF) | (0<<22) | (1<<28) | (1<<30); \ |
silviosz | 1:a5ccd53612ea | 266 | PORT->Group[0].WRCONFIG.reg = (DMASK>>16) | (0<<22) | (1<<28) | (1<<30) | (1<<31); \ |
silviosz | 1:a5ccd53612ea | 267 | } |
silviosz | 1:a5ccd53612ea | 268 | #define setReadDir() { PORT->Group[0].DIRCLR.reg = DMASK; \ |
silviosz | 1:a5ccd53612ea | 269 | PORT->Group[0].WRCONFIG.reg = (DMASK & 0xFFFF) | (1<<17) | (1<<28) | (1<<30); \ |
silviosz | 1:a5ccd53612ea | 270 | PORT->Group[0].WRCONFIG.reg = (DMASK>>16) | (1<<17) | (1<<28) | (1<<30) | (1<<31); \ |
silviosz | 1:a5ccd53612ea | 271 | } |
silviosz | 1:a5ccd53612ea | 272 | #define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; } |
silviosz | 1:a5ccd53612ea | 273 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
silviosz | 1:a5ccd53612ea | 274 | #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; } |
silviosz | 1:a5ccd53612ea | 275 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
silviosz | 1:a5ccd53612ea | 276 | // Shield Control macros. |
silviosz | 1:a5ccd53612ea | 277 | #define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin)) |
silviosz | 1:a5ccd53612ea | 278 | #define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin)) |
silviosz | 1:a5ccd53612ea | 279 | #define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin)) |
silviosz | 1:a5ccd53612ea | 280 | |
silviosz | 1:a5ccd53612ea | 281 | //####################################### DUE ############################ |
silviosz | 1:a5ccd53612ea | 282 | #elif defined(__SAM3X8E__) //regular UNO shield on DUE |
silviosz | 1:a5ccd53612ea | 283 | #define WRITE_DELAY { WR_ACTIVE; } |
silviosz | 1:a5ccd53612ea | 284 | #define IDLE_DELAY { WR_IDLE; } |
silviosz | 1:a5ccd53612ea | 285 | #define READ_DELAY { RD_ACTIVE;} |
silviosz | 1:a5ccd53612ea | 286 | // configure macros for the control pins |
silviosz | 1:a5ccd53612ea | 287 | #define RD_PORT PIOA |
silviosz | 1:a5ccd53612ea | 288 | #define RD_PIN 16 |
silviosz | 1:a5ccd53612ea | 289 | #define WR_PORT PIOA |
silviosz | 1:a5ccd53612ea | 290 | #define WR_PIN 24 |
silviosz | 1:a5ccd53612ea | 291 | #define CD_PORT PIOA |
silviosz | 1:a5ccd53612ea | 292 | #define CD_PIN 23 |
silviosz | 1:a5ccd53612ea | 293 | #define CS_PORT PIOA |
silviosz | 1:a5ccd53612ea | 294 | #define CS_PIN 22 |
silviosz | 1:a5ccd53612ea | 295 | #define RESET_PORT PIOA |
silviosz | 1:a5ccd53612ea | 296 | #define RESET_PIN 6 |
silviosz | 1:a5ccd53612ea | 297 | // configure macros for data bus |
silviosz | 1:a5ccd53612ea | 298 | #define BMASK (1<<25) |
silviosz | 1:a5ccd53612ea | 299 | #define CMASK (0xBF << 21) |
silviosz | 1:a5ccd53612ea | 300 | #define write_8(x) { PIOB->PIO_CODR = BMASK; PIOC->PIO_CODR = CMASK; \ |
silviosz | 1:a5ccd53612ea | 301 | PIOB->PIO_SODR = (((x) & (1<<2)) << 23); \ |
silviosz | 1:a5ccd53612ea | 302 | PIOC->PIO_SODR = (((x) & (1<<0)) << 22) \ |
silviosz | 1:a5ccd53612ea | 303 | | (((x) & (1<<1)) << 20) \ |
silviosz | 1:a5ccd53612ea | 304 | | (((x) & (1<<3)) << 25) \ |
silviosz | 1:a5ccd53612ea | 305 | | (((x) & (1<<4)) << 22) \ |
silviosz | 1:a5ccd53612ea | 306 | | (((x) & (1<<5)) << 20) \ |
silviosz | 1:a5ccd53612ea | 307 | | (((x) & (1<<6)) << 18) \ |
silviosz | 1:a5ccd53612ea | 308 | | (((x) & (1<<7)) << 16); \ |
silviosz | 1:a5ccd53612ea | 309 | } |
silviosz | 1:a5ccd53612ea | 310 | |
silviosz | 1:a5ccd53612ea | 311 | #define read_8() ( ((PIOC->PIO_PDSR & (1<<22)) >> 22)\ |
silviosz | 1:a5ccd53612ea | 312 | | ((PIOC->PIO_PDSR & (1<<21)) >> 20)\ |
silviosz | 1:a5ccd53612ea | 313 | | ((PIOB->PIO_PDSR & (1<<25)) >> 23)\ |
silviosz | 1:a5ccd53612ea | 314 | | ((PIOC->PIO_PDSR & (1<<28)) >> 25)\ |
silviosz | 1:a5ccd53612ea | 315 | | ((PIOC->PIO_PDSR & (1<<26)) >> 22)\ |
silviosz | 1:a5ccd53612ea | 316 | | ((PIOC->PIO_PDSR & (1<<25)) >> 20)\ |
silviosz | 1:a5ccd53612ea | 317 | | ((PIOC->PIO_PDSR & (1<<24)) >> 18)\ |
silviosz | 1:a5ccd53612ea | 318 | | ((PIOC->PIO_PDSR & (1<<23)) >> 16)\ |
silviosz | 1:a5ccd53612ea | 319 | ) |
silviosz | 1:a5ccd53612ea | 320 | #define setWriteDir() { PIOB->PIO_OER = BMASK; PIOC->PIO_OER = CMASK; } |
silviosz | 1:a5ccd53612ea | 321 | #define setReadDir() { \ |
silviosz | 1:a5ccd53612ea | 322 | PMC->PMC_PCER0 = (1 << ID_PIOB)|(1 << ID_PIOC);\ |
silviosz | 1:a5ccd53612ea | 323 | PIOB->PIO_ODR = BMASK; PIOC->PIO_ODR = CMASK;\ |
silviosz | 1:a5ccd53612ea | 324 | } |
silviosz | 1:a5ccd53612ea | 325 | #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; IDLE_DELAY; } |
silviosz | 1:a5ccd53612ea | 326 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
silviosz | 1:a5ccd53612ea | 327 | #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; RD_IDLE; } |
silviosz | 1:a5ccd53612ea | 328 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
silviosz | 1:a5ccd53612ea | 329 | |
silviosz | 1:a5ccd53612ea | 330 | // Shield Control macros. |
silviosz | 1:a5ccd53612ea | 331 | #define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin)) |
silviosz | 1:a5ccd53612ea | 332 | #define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin)) |
silviosz | 1:a5ccd53612ea | 333 | #define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin)) |
silviosz | 1:a5ccd53612ea | 334 | |
silviosz | 1:a5ccd53612ea | 335 | //################################### LEONARDO ############################## |
silviosz | 1:a5ccd53612ea | 336 | #elif defined(__AVR_ATmega32U4__) //regular UNO shield on Leonardo |
silviosz | 1:a5ccd53612ea | 337 | #define RD_PORT PORTF |
silviosz | 1:a5ccd53612ea | 338 | #define RD_PIN 7 |
silviosz | 1:a5ccd53612ea | 339 | #define WR_PORT PORTF |
silviosz | 1:a5ccd53612ea | 340 | #define WR_PIN 6 |
silviosz | 1:a5ccd53612ea | 341 | #define CD_PORT PORTF |
silviosz | 1:a5ccd53612ea | 342 | #define CD_PIN 5 |
silviosz | 1:a5ccd53612ea | 343 | #define CS_PORT PORTF |
silviosz | 1:a5ccd53612ea | 344 | #define CS_PIN 4 |
silviosz | 1:a5ccd53612ea | 345 | #define RESET_PORT PORTF |
silviosz | 1:a5ccd53612ea | 346 | #define RESET_PIN 1 |
silviosz | 1:a5ccd53612ea | 347 | |
silviosz | 1:a5ccd53612ea | 348 | #define BMASK (3<<4) |
silviosz | 1:a5ccd53612ea | 349 | #define CMASK (1<<6) |
silviosz | 1:a5ccd53612ea | 350 | #define DMASK ((1<<7)|(1<<4)|(3<<0)) |
silviosz | 1:a5ccd53612ea | 351 | #define EMASK (1<<6) |
silviosz | 1:a5ccd53612ea | 352 | static inline //hope we use r24 |
silviosz | 1:a5ccd53612ea | 353 | void write_8(uint8_t x) |
silviosz | 1:a5ccd53612ea | 354 | { |
silviosz | 1:a5ccd53612ea | 355 | PORTB &= ~BMASK; |
silviosz | 1:a5ccd53612ea | 356 | PORTC &= ~CMASK; |
silviosz | 1:a5ccd53612ea | 357 | PORTD &= ~DMASK; |
silviosz | 1:a5ccd53612ea | 358 | PORTE &= ~EMASK; |
silviosz | 1:a5ccd53612ea | 359 | PORTB |= (((x) & (3 << 0)) << 4); |
silviosz | 1:a5ccd53612ea | 360 | PORTD |= (((x) & (1 << 2)) >> 1); |
silviosz | 1:a5ccd53612ea | 361 | PORTD |= (((x) & (1 << 3)) >> 3); |
silviosz | 1:a5ccd53612ea | 362 | PORTD |= (((x) & (1 << 4)) << 0); |
silviosz | 1:a5ccd53612ea | 363 | PORTC |= (((x) & (1 << 5)) << 1); |
silviosz | 1:a5ccd53612ea | 364 | PORTD |= (((x) & (1 << 6)) << 1); |
silviosz | 1:a5ccd53612ea | 365 | PORTE |= (((x) & (1 << 7)) >> 1); |
silviosz | 1:a5ccd53612ea | 366 | } |
silviosz | 1:a5ccd53612ea | 367 | |
silviosz | 1:a5ccd53612ea | 368 | #define read_8() ( ((PINB & (3<<4)) >> 4)\ |
silviosz | 1:a5ccd53612ea | 369 | | ((PIND & (1<<1)) << 1)\ |
silviosz | 1:a5ccd53612ea | 370 | | ((PIND & (1<<0)) << 3)\ |
silviosz | 1:a5ccd53612ea | 371 | | ((PIND & (1<<4)) >> 0)\ |
silviosz | 1:a5ccd53612ea | 372 | | ((PINC & (1<<6)) >> 1)\ |
silviosz | 1:a5ccd53612ea | 373 | | ((PIND & (1<<7)) >> 1)\ |
silviosz | 1:a5ccd53612ea | 374 | | ((PINE & (1<<6)) << 1)\ |
silviosz | 1:a5ccd53612ea | 375 | ) |
silviosz | 1:a5ccd53612ea | 376 | #define setWriteDir() { DDRB |= BMASK; DDRC |= CMASK; DDRD |= DMASK; DDRE |= EMASK; } |
silviosz | 1:a5ccd53612ea | 377 | #define setReadDir() { DDRB &= ~BMASK; DDRC &= ~CMASK; DDRD &= ~DMASK; DDRE &= ~EMASK; } |
silviosz | 1:a5ccd53612ea | 378 | #define write8(x) { write_8(x); WR_STROBE; } |
silviosz | 1:a5ccd53612ea | 379 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
silviosz | 1:a5ccd53612ea | 380 | #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; } |
silviosz | 1:a5ccd53612ea | 381 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
silviosz | 1:a5ccd53612ea | 382 | |
silviosz | 1:a5ccd53612ea | 383 | #define PIN_LOW(p, b) (p) &= ~(1<<(b)) |
silviosz | 1:a5ccd53612ea | 384 | #define PIN_HIGH(p, b) (p) |= (1<<(b)) |
silviosz | 1:a5ccd53612ea | 385 | #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b)) |
silviosz | 1:a5ccd53612ea | 386 | |
silviosz | 1:a5ccd53612ea | 387 | //################################### UNO SHIELD on BOBUINO ############################## |
silviosz | 1:a5ccd53612ea | 388 | #elif defined(__AVR_ATmega1284P__) || defined(__AVR_ATmega644P__) //UNO shield on BOBUINO |
silviosz | 1:a5ccd53612ea | 389 | #warning regular UNO shield on BOBUINO |
silviosz | 1:a5ccd53612ea | 390 | |
silviosz | 1:a5ccd53612ea | 391 | //LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST| |
silviosz | 1:a5ccd53612ea | 392 | //AVR pin |PB3|PB2|PB1|PB0|PD3|PD2|PD6|PD5| |PA7|PA6|PA5|PA4|PA3| |
silviosz | 1:a5ccd53612ea | 393 | |
silviosz | 1:a5ccd53612ea | 394 | #define RD_PORT PORTA |
silviosz | 1:a5ccd53612ea | 395 | #define RD_PIN 7 |
silviosz | 1:a5ccd53612ea | 396 | #define WR_PORT PORTA |
silviosz | 1:a5ccd53612ea | 397 | #define WR_PIN 6 |
silviosz | 1:a5ccd53612ea | 398 | #define CD_PORT PORTA |
silviosz | 1:a5ccd53612ea | 399 | #define CD_PIN 5 |
silviosz | 1:a5ccd53612ea | 400 | #define CS_PORT PORTA |
silviosz | 1:a5ccd53612ea | 401 | #define CS_PIN 4 |
silviosz | 1:a5ccd53612ea | 402 | #define RESET_PORT PORTA |
silviosz | 1:a5ccd53612ea | 403 | #define RESET_PIN 3 |
silviosz | 1:a5ccd53612ea | 404 | |
silviosz | 1:a5ccd53612ea | 405 | #define BMASK 0x0F // |
silviosz | 1:a5ccd53612ea | 406 | #define DMASK 0x6C // |
silviosz | 1:a5ccd53612ea | 407 | #define write_8(x) { PORTB = (PORTB & ~BMASK) | ((x) >> 4); \ |
silviosz | 1:a5ccd53612ea | 408 | PORTD = (PORTD & ~DMASK) | ((x) & 0x0C) | (((x) & 0x03) << 5); } |
silviosz | 1:a5ccd53612ea | 409 | #define read_8() ( (PINB << 4) | (PIND & 0x0C) | ((PIND & 0x60) >> 5) ) |
silviosz | 1:a5ccd53612ea | 410 | #define setWriteDir() { DDRB |= BMASK; DDRD |= DMASK; } |
silviosz | 1:a5ccd53612ea | 411 | #define setReadDir() { DDRB &= ~BMASK; DDRD &= ~DMASK; } |
silviosz | 1:a5ccd53612ea | 412 | #define write8(x) { write_8(x); WR_STROBE; } |
silviosz | 1:a5ccd53612ea | 413 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
silviosz | 1:a5ccd53612ea | 414 | #define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; } |
silviosz | 1:a5ccd53612ea | 415 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
silviosz | 1:a5ccd53612ea | 416 | |
silviosz | 1:a5ccd53612ea | 417 | #define PIN_LOW(p, b) (p) &= ~(1<<(b)) |
silviosz | 1:a5ccd53612ea | 418 | #define PIN_HIGH(p, b) (p) |= (1<<(b)) |
silviosz | 1:a5ccd53612ea | 419 | #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b)) |
silviosz | 1:a5ccd53612ea | 420 | |
silviosz | 1:a5ccd53612ea | 421 | //####################################### TEENSY ############################ |
silviosz | 1:a5ccd53612ea | 422 | #elif defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__) // regular UNO shield on a Teensy 3.x |
silviosz | 1:a5ccd53612ea | 423 | #warning regular UNO shield on a Teensy 3.x |
silviosz | 1:a5ccd53612ea | 424 | |
silviosz | 1:a5ccd53612ea | 425 | //LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST| |
silviosz | 1:a5ccd53612ea | 426 | //MK20 pin |PD2|PD4|PD7|PA13|PA12|PD2|PC3|PD3| |PD1|PC0|PB0|PB1|PB3| |
silviosz | 1:a5ccd53612ea | 427 | |
silviosz | 1:a5ccd53612ea | 428 | #if defined(__MK20DX128__) || defined(__MK20DX256__) // Teensy3.0 || 3.2 96MHz |
silviosz | 1:a5ccd53612ea | 429 | #define WRITE_DELAY { WR_ACTIVE2; } |
silviosz | 1:a5ccd53612ea | 430 | #define READ_DELAY { RD_ACTIVE8; RD_ACTIVE; } |
silviosz | 1:a5ccd53612ea | 431 | #elif defined(__MK64FX512__) // Teensy3.5 120MHz thanks to PeteJohno |
silviosz | 1:a5ccd53612ea | 432 | #define WRITE_DELAY { WR_ACTIVE4; } |
silviosz | 1:a5ccd53612ea | 433 | #define READ_DELAY { RD_ACTIVE8; } |
silviosz | 1:a5ccd53612ea | 434 | #elif defined(__MK66FX1M0__) // Teensy3.6 180MHz untested. delays can possibly be reduced. |
silviosz | 1:a5ccd53612ea | 435 | #define WRITE_DELAY { WR_ACTIVE8; } |
silviosz | 1:a5ccd53612ea | 436 | #define READ_DELAY { RD_ACTIVE16; } |
silviosz | 1:a5ccd53612ea | 437 | #else |
silviosz | 1:a5ccd53612ea | 438 | #error unspecified delays |
silviosz | 1:a5ccd53612ea | 439 | #endif |
silviosz | 1:a5ccd53612ea | 440 | |
silviosz | 1:a5ccd53612ea | 441 | #define RD_PORT GPIOD |
silviosz | 1:a5ccd53612ea | 442 | #define RD_PIN 1 |
silviosz | 1:a5ccd53612ea | 443 | #define WR_PORT GPIOC |
silviosz | 1:a5ccd53612ea | 444 | #define WR_PIN 0 |
silviosz | 1:a5ccd53612ea | 445 | #define CD_PORT GPIOB |
silviosz | 1:a5ccd53612ea | 446 | #define CD_PIN 0 |
silviosz | 1:a5ccd53612ea | 447 | #define CS_PORT GPIOB |
silviosz | 1:a5ccd53612ea | 448 | #define CS_PIN 1 |
silviosz | 1:a5ccd53612ea | 449 | #define RESET_PORT GPIOB |
silviosz | 1:a5ccd53612ea | 450 | #define RESET_PIN 3 |
silviosz | 1:a5ccd53612ea | 451 | |
silviosz | 1:a5ccd53612ea | 452 | // configure macros for the data pins |
silviosz | 1:a5ccd53612ea | 453 | #define AMASK ((1<<12)|(1<<13)) |
silviosz | 1:a5ccd53612ea | 454 | #define CMASK ((1<<3)) |
silviosz | 1:a5ccd53612ea | 455 | #define DMASK ((1<<0)|(1<<2)|(1<<3)|(1<<4)|(1<<7)) |
silviosz | 1:a5ccd53612ea | 456 | |
silviosz | 1:a5ccd53612ea | 457 | #define write_8(d) { \ |
silviosz | 1:a5ccd53612ea | 458 | GPIOA_PCOR = AMASK; GPIOC_PCOR = CMASK; GPIOD_PCOR = DMASK; \ |
silviosz | 1:a5ccd53612ea | 459 | GPIOA_PSOR = (((d) & (1 << 3)) << 9) \ |
silviosz | 1:a5ccd53612ea | 460 | | (((d) & (1 << 4)) << 9); \ |
silviosz | 1:a5ccd53612ea | 461 | GPIOC_PSOR = (((d) & (1 << 1)) << 2); \ |
silviosz | 1:a5ccd53612ea | 462 | GPIOD_PSOR = (((d) & (1 << 0)) << 3) \ |
silviosz | 1:a5ccd53612ea | 463 | | (((d) & (1 << 2)) >> 2) \ |
silviosz | 1:a5ccd53612ea | 464 | | (((d) & (1 << 5)) << 2) \ |
silviosz | 1:a5ccd53612ea | 465 | | (((d) & (1 << 6)) >> 2) \ |
silviosz | 1:a5ccd53612ea | 466 | | (((d) & (1 << 7)) >> 5); \ |
silviosz | 1:a5ccd53612ea | 467 | } |
silviosz | 1:a5ccd53612ea | 468 | #define read_8() ((((GPIOD_PDIR & (1<<3)) >> 3) \ |
silviosz | 1:a5ccd53612ea | 469 | | ((GPIOC_PDIR & (1 << 3)) >> 2) \ |
silviosz | 1:a5ccd53612ea | 470 | | ((GPIOD_PDIR & (1 << 0)) << 2) \ |
silviosz | 1:a5ccd53612ea | 471 | | ((GPIOA_PDIR & (1 << 12)) >> 9) \ |
silviosz | 1:a5ccd53612ea | 472 | | ((GPIOA_PDIR & (1 << 13)) >> 9) \ |
silviosz | 1:a5ccd53612ea | 473 | | ((GPIOD_PDIR & (1 << 7)) >> 2) \ |
silviosz | 1:a5ccd53612ea | 474 | | ((GPIOD_PDIR & (1 << 4)) << 2) \ |
silviosz | 1:a5ccd53612ea | 475 | | ((GPIOD_PDIR & (1 << 2)) << 5))) |
silviosz | 1:a5ccd53612ea | 476 | #define setWriteDir() {GPIOA_PDDR |= AMASK;GPIOC_PDDR |= CMASK;GPIOD_PDDR |= DMASK; } |
silviosz | 1:a5ccd53612ea | 477 | #define setReadDir() {GPIOA_PDDR &= ~AMASK;GPIOC_PDDR &= ~CMASK;GPIOD_PDDR &= ~DMASK; } |
silviosz | 1:a5ccd53612ea | 478 | #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; } //PJ adjusted |
silviosz | 1:a5ccd53612ea | 479 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
silviosz | 1:a5ccd53612ea | 480 | #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } //PJ adjusted |
silviosz | 1:a5ccd53612ea | 481 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
silviosz | 1:a5ccd53612ea | 482 | //#define GPIO_INIT() {SIM_SCGC5 |= 0x3E00;} //PORTA-PORTE |
silviosz | 1:a5ccd53612ea | 483 | #define GPIO_INIT() {for (int i = 2; i <= 9; i++) pinMode(i, OUTPUT); for (int i = A0; i <= A4; i++) pinMode(i, OUTPUT);} |
silviosz | 1:a5ccd53612ea | 484 | |
silviosz | 1:a5ccd53612ea | 485 | #define PASTE(x, y) x ## y |
silviosz | 1:a5ccd53612ea | 486 | |
silviosz | 1:a5ccd53612ea | 487 | #define PIN_LOW(port, pin) PASTE(port, _PCOR) = (1<<(pin)) |
silviosz | 1:a5ccd53612ea | 488 | #define PIN_HIGH(port, pin) PASTE(port, _PSOR) = (1<<(pin)) |
silviosz | 1:a5ccd53612ea | 489 | #define PIN_OUTPUT(port, pin) PASTE(port, _PDDR) |= (1<<(pin)) |
silviosz | 1:a5ccd53612ea | 490 | |
silviosz | 1:a5ccd53612ea | 491 | //####################################### STM32 ############################ |
silviosz | 1:a5ccd53612ea | 492 | // NUCLEO: ARDUINO_NUCLEO_xxxx from ST Core or ARDUINO_STM_NUCLEO_F103RB from MapleCore |
silviosz | 1:a5ccd53612ea | 493 | // BLUEPILL: ARDUINO_NUCLEO_F103C8 / ARDUINO_BLUEPILL_F103C8 from ST Core or ARDUINO_GENERIC_STM32F103C from MapleCore |
silviosz | 1:a5ccd53612ea | 494 | // MAPLE_REV3: n/a from ST Core or ARDUINO_MAPLE_REV3 from MapleCore |
silviosz | 1:a5ccd53612ea | 495 | // ST Core: ARDUINO_ARCH_STM32 |
silviosz | 1:a5ccd53612ea | 496 | // MapleCore: __STM32F1__ |
silviosz | 1:a5ccd53612ea | 497 | #elif defined(__STM32F1__) || defined(ARDUINO_ARCH_STM32) //MapleCore or ST Core |
silviosz | 1:a5ccd53612ea | 498 | #define IS_NUCLEO64 ( defined(ARDUINO_STM_NUCLEO_F103RB) \ |
silviosz | 1:a5ccd53612ea | 499 | || defined(ARDUINO_NUCLEO_F030R8) || defined(ARDUINO_NUCLEO_F091RC) \ |
silviosz | 1:a5ccd53612ea | 500 | || defined(ARDUINO_NUCLEO_F103RB) || defined(ARDUINO_NUCLEO_F303RE) \ |
silviosz | 1:a5ccd53612ea | 501 | || defined(ARDUINO_NUCLEO_F401RE) || defined(ARDUINO_NUCLEO_F411RE) \ |
silviosz | 1:a5ccd53612ea | 502 | || defined(ARDUINO_NUCLEO_F446RE) || defined(ARDUINO_NUCLEO_L053R8) \ |
silviosz | 1:a5ccd53612ea | 503 | || defined(ARDUINO_NUCLEO_L152RE) || defined(ARDUINO_NUCLEO_L476RG) \ |
silviosz | 1:a5ccd53612ea | 504 | || defined(ARDUINO_NUCLEO_F072RB) \ |
silviosz | 1:a5ccd53612ea | 505 | ) |
silviosz | 1:a5ccd53612ea | 506 | #define IS_NUCLEO144 ( defined(ARDUINO_NUCLEO_F207ZG) \ |
silviosz | 1:a5ccd53612ea | 507 | || defined(ARDUINO_NUCLEO_F429ZI) || defined(ARDUINO_NUCLEO_F767ZI) \ |
silviosz | 1:a5ccd53612ea | 508 | || defined(ARDUINO_NUCLEO_L496ZG) || defined(ARDUINO_NUCLEO_L496ZG_P) \ |
silviosz | 1:a5ccd53612ea | 509 | || defined(ARDUINO_NUCLEO_H743ZI) \ |
silviosz | 1:a5ccd53612ea | 510 | ) |
silviosz | 1:a5ccd53612ea | 511 | // F1xx, F4xx, L4xx have different registers and styles. General Macros |
silviosz | 1:a5ccd53612ea | 512 | #if defined(__STM32F1__) //weird Maple Core |
silviosz | 1:a5ccd53612ea | 513 | #define REGS(x) regs->x |
silviosz | 1:a5ccd53612ea | 514 | #else //regular ST Core |
silviosz | 1:a5ccd53612ea | 515 | #define REGS(x) x |
silviosz | 1:a5ccd53612ea | 516 | #endif |
silviosz | 1:a5ccd53612ea | 517 | #define PIN_HIGH(port, pin) (port)-> REGS(BSRR) = (1<<(pin)) |
silviosz | 1:a5ccd53612ea | 518 | #define PIN_LOW(port, pin) (port)-> REGS(BSRR) = (1<<((pin)+16)) |
silviosz | 1:a5ccd53612ea | 519 | #define PIN_MODE2(reg, pin, mode) reg=(reg&~(0x3<<((pin)<<1)))|(mode<<((pin)<<1)) |
silviosz | 1:a5ccd53612ea | 520 | #define GROUP_MODE(port, reg, mask, val) {port->REGS(reg) = (port->REGS(reg) & ~(mask)) | ((mask)&(val)); } |
silviosz | 1:a5ccd53612ea | 521 | |
silviosz | 1:a5ccd53612ea | 522 | // Family specific Macros. F103 needs ST and Maple compatibility |
silviosz | 1:a5ccd53612ea | 523 | // note that ILI9320 class of controller has much slower Read cycles |
silviosz | 1:a5ccd53612ea | 524 | #if 0 |
silviosz | 1:a5ccd53612ea | 525 | #elif defined(__STM32F1__) || defined(ARDUINO_NUCLEO_F103C8) || defined(ARDUINO_BLUEPILL_F103C8) || defined(ARDUINO_NUCLEO_F103RB) |
silviosz | 1:a5ccd53612ea | 526 | #define WRITE_DELAY { } |
silviosz | 1:a5ccd53612ea | 527 | #define READ_DELAY { RD_ACTIVE; } |
silviosz | 1:a5ccd53612ea | 528 | #if defined(__STM32F1__) //MapleCore crts.o does RCC. not understand regular syntax anyway |
silviosz | 1:a5ccd53612ea | 529 | #define GPIO_INIT() |
silviosz | 1:a5ccd53612ea | 530 | #else |
silviosz | 1:a5ccd53612ea | 531 | #define GPIO_INIT() { RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | RCC_APB2ENR_AFIOEN; \ |
silviosz | 1:a5ccd53612ea | 532 | AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_1;} |
silviosz | 1:a5ccd53612ea | 533 | #endif |
silviosz | 1:a5ccd53612ea | 534 | #define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333) |
silviosz | 1:a5ccd53612ea | 535 | #define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444) |
silviosz | 1:a5ccd53612ea | 536 | #define PIN_OUTPUT(port, pin) {\ |
silviosz | 1:a5ccd53612ea | 537 | if (pin < 8) {GP_OUT(port, CRL, 0xF<<((pin)<<2));} \ |
silviosz | 1:a5ccd53612ea | 538 | else {GP_OUT(port, CRH, 0xF<<((pin&7)<<2));} \ |
silviosz | 1:a5ccd53612ea | 539 | } |
silviosz | 1:a5ccd53612ea | 540 | #define PIN_INPUT(port, pin) { \ |
silviosz | 1:a5ccd53612ea | 541 | if (pin < 8) { GP_INP(port, CRL, 0xF<<((pin)<<2)); } \ |
silviosz | 1:a5ccd53612ea | 542 | else { GP_INP(port, CRH, 0xF<<((pin&7)<<2)); } \ |
silviosz | 1:a5ccd53612ea | 543 | } |
silviosz | 1:a5ccd53612ea | 544 | |
silviosz | 1:a5ccd53612ea | 545 | // should be easy to add F030, F091, F303, L053, ... |
silviosz | 1:a5ccd53612ea | 546 | #elif defined(STM32F030x8) |
silviosz | 1:a5ccd53612ea | 547 | #define WRITE_DELAY { } |
silviosz | 1:a5ccd53612ea | 548 | #define READ_DELAY { RD_ACTIVE; } |
silviosz | 1:a5ccd53612ea | 549 | #define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; } |
silviosz | 1:a5ccd53612ea | 550 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
silviosz | 1:a5ccd53612ea | 551 | |
silviosz | 1:a5ccd53612ea | 552 | #elif defined(STM32F072xB) |
silviosz | 1:a5ccd53612ea | 553 | #define WRITE_DELAY { } |
silviosz | 1:a5ccd53612ea | 554 | #define READ_DELAY { RD_ACTIVE; } |
silviosz | 1:a5ccd53612ea | 555 | #define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; } |
silviosz | 1:a5ccd53612ea | 556 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
silviosz | 1:a5ccd53612ea | 557 | |
silviosz | 1:a5ccd53612ea | 558 | #elif defined(STM32F091xC) |
silviosz | 1:a5ccd53612ea | 559 | #define WRITE_DELAY { } |
silviosz | 1:a5ccd53612ea | 560 | #define READ_DELAY { RD_ACTIVE; } |
silviosz | 1:a5ccd53612ea | 561 | #define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; } |
silviosz | 1:a5ccd53612ea | 562 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
silviosz | 1:a5ccd53612ea | 563 | |
silviosz | 1:a5ccd53612ea | 564 | #elif defined(STM32F207xx) |
silviosz | 1:a5ccd53612ea | 565 | #warning DELAY macros untested yet |
silviosz | 1:a5ccd53612ea | 566 | #define WRITE_DELAY { WR_ACTIVE8; } //120MHz |
silviosz | 1:a5ccd53612ea | 567 | #define IDLE_DELAY { WR_IDLE2;WR_IDLE; } |
silviosz | 1:a5ccd53612ea | 568 | #define READ_DELAY { RD_ACTIVE16;} |
silviosz | 1:a5ccd53612ea | 569 | #define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN; } |
silviosz | 1:a5ccd53612ea | 570 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
silviosz | 1:a5ccd53612ea | 571 | |
silviosz | 1:a5ccd53612ea | 572 | #elif defined(STM32F303xE) |
silviosz | 1:a5ccd53612ea | 573 | #define WRITE_DELAY { } |
silviosz | 1:a5ccd53612ea | 574 | #define READ_DELAY { RD_ACTIVE8; } //thanks MasterT |
silviosz | 1:a5ccd53612ea | 575 | #define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; \ |
silviosz | 1:a5ccd53612ea | 576 | /* AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_1; */ } |
silviosz | 1:a5ccd53612ea | 577 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) //thanks fpiSTM |
silviosz | 1:a5ccd53612ea | 578 | |
silviosz | 1:a5ccd53612ea | 579 | #elif defined(STM32F401xE) |
silviosz | 1:a5ccd53612ea | 580 | #define WRITE_DELAY { WR_ACTIVE2; } //84MHz |
silviosz | 1:a5ccd53612ea | 581 | #define READ_DELAY { RD_ACTIVE4; } |
silviosz | 1:a5ccd53612ea | 582 | #define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN; } |
silviosz | 1:a5ccd53612ea | 583 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
silviosz | 1:a5ccd53612ea | 584 | |
silviosz | 1:a5ccd53612ea | 585 | #elif defined(STM32F411xE) |
silviosz | 1:a5ccd53612ea | 586 | #define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //100MHz |
silviosz | 1:a5ccd53612ea | 587 | #define READ_DELAY { RD_ACTIVE4; RD_ACTIVE2; } |
silviosz | 1:a5ccd53612ea | 588 | #define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN; } |
silviosz | 1:a5ccd53612ea | 589 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
silviosz | 1:a5ccd53612ea | 590 | |
silviosz | 1:a5ccd53612ea | 591 | #elif defined(STM32F429xx) |
silviosz | 1:a5ccd53612ea | 592 | #warning DELAY macros untested yet |
silviosz | 1:a5ccd53612ea | 593 | #define WRITE_DELAY { WR_ACTIVE8; } //180MHz |
silviosz | 1:a5ccd53612ea | 594 | #define IDLE_DELAY { WR_IDLE2;WR_IDLE; } |
silviosz | 1:a5ccd53612ea | 595 | #define READ_DELAY { RD_ACTIVE16;} |
silviosz | 1:a5ccd53612ea | 596 | #define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN; } |
silviosz | 1:a5ccd53612ea | 597 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
silviosz | 1:a5ccd53612ea | 598 | |
silviosz | 1:a5ccd53612ea | 599 | #elif defined(STM32F446xx) |
silviosz | 1:a5ccd53612ea | 600 | #define WRITE_DELAY { WR_ACTIVE8; } //180MHz |
silviosz | 1:a5ccd53612ea | 601 | #define IDLE_DELAY { WR_IDLE2;WR_IDLE; } |
silviosz | 1:a5ccd53612ea | 602 | #define READ_DELAY { RD_ACTIVE16;} |
silviosz | 1:a5ccd53612ea | 603 | #define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN; } |
silviosz | 1:a5ccd53612ea | 604 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
silviosz | 1:a5ccd53612ea | 605 | |
silviosz | 1:a5ccd53612ea | 606 | #elif defined(STM32F767xx) |
silviosz | 1:a5ccd53612ea | 607 | #warning DELAY macros untested yet |
silviosz | 1:a5ccd53612ea | 608 | #define WRITE_DELAY { WR_ACTIVE8;WR_ACTIVE2; } //216MHz |
silviosz | 1:a5ccd53612ea | 609 | #define IDLE_DELAY { WR_IDLE2;WR_IDLE; } |
silviosz | 1:a5ccd53612ea | 610 | #define READ_DELAY { RD_ACTIVE16;RD_ACTIVE16;RD_ACTIVE4;} |
silviosz | 1:a5ccd53612ea | 611 | #define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN; } |
silviosz | 1:a5ccd53612ea | 612 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
silviosz | 1:a5ccd53612ea | 613 | |
silviosz | 1:a5ccd53612ea | 614 | #elif defined(STM32H743xx) // thanks MagicianT |
silviosz | 1:a5ccd53612ea | 615 | #warning STM32H743xx< DELAY macros untested yet |
silviosz | 1:a5ccd53612ea | 616 | #define WRITE_DELAY { WR_ACTIVE8;WR_ACTIVE2; } //F_CPU=400MHz |
silviosz | 1:a5ccd53612ea | 617 | #define IDLE_DELAY { WR_IDLE2;WR_IDLE; } |
silviosz | 1:a5ccd53612ea | 618 | #define READ_DELAY { RD_ACTIVE16;RD_ACTIVE16;RD_ACTIVE4;} |
silviosz | 1:a5ccd53612ea | 619 | #define GPIO_INIT() { RCC->AHB4ENR |= RCC_AHB4ENR_GPIOAEN | RCC_AHB4ENR_GPIOCEN | RCC_AHB4ENR_GPIODEN | RCC_AHB4ENR_GPIOEEN | RCC_AHB4ENR_GPIOFEN; } |
silviosz | 1:a5ccd53612ea | 620 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
silviosz | 1:a5ccd53612ea | 621 | |
silviosz | 1:a5ccd53612ea | 622 | #elif defined(STM32L053xx) |
silviosz | 1:a5ccd53612ea | 623 | #define WRITE_DELAY { } //32MHz M0+ |
silviosz | 1:a5ccd53612ea | 624 | #define READ_DELAY { RD_ACTIVE; } |
silviosz | 1:a5ccd53612ea | 625 | #define GPIO_INIT() { RCC->IOPENR |= RCC_IOPENR_GPIOAEN | RCC_IOPENR_GPIOBEN | RCC_IOPENR_GPIOCEN; } |
silviosz | 1:a5ccd53612ea | 626 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
silviosz | 1:a5ccd53612ea | 627 | |
silviosz | 1:a5ccd53612ea | 628 | #elif defined(STM32L152xE) |
silviosz | 1:a5ccd53612ea | 629 | #define WRITE_DELAY { } //32MHz M3 |
silviosz | 1:a5ccd53612ea | 630 | #define READ_DELAY { RD_ACTIVE; } |
silviosz | 1:a5ccd53612ea | 631 | #define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; } |
silviosz | 1:a5ccd53612ea | 632 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
silviosz | 1:a5ccd53612ea | 633 | |
silviosz | 1:a5ccd53612ea | 634 | #elif defined(STM32L476xx) |
silviosz | 1:a5ccd53612ea | 635 | #define WRITE_DELAY { WR_ACTIVE2; } //80MHz |
silviosz | 1:a5ccd53612ea | 636 | #define READ_DELAY { RD_ACTIVE4; RD_ACTIVE; } |
silviosz | 1:a5ccd53612ea | 637 | #define GPIO_INIT() { RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | RCC_AHB2ENR_GPIOCEN; } |
silviosz | 1:a5ccd53612ea | 638 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
silviosz | 1:a5ccd53612ea | 639 | |
silviosz | 1:a5ccd53612ea | 640 | #elif defined(STM32L496xx) |
silviosz | 1:a5ccd53612ea | 641 | #warning DELAY macros untested yet |
silviosz | 1:a5ccd53612ea | 642 | #define WRITE_DELAY { WR_ACTIVE2; } //80MHz |
silviosz | 1:a5ccd53612ea | 643 | #define READ_DELAY { RD_ACTIVE4; RD_ACTIVE; } |
silviosz | 1:a5ccd53612ea | 644 | #define GPIO_INIT() { RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOCEN | RCC_AHB2ENR_GPIODEN | RCC_AHB2ENR_GPIOEEN | RCC_AHB2ENR_GPIOFEN; } |
silviosz | 1:a5ccd53612ea | 645 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
silviosz | 1:a5ccd53612ea | 646 | |
silviosz | 1:a5ccd53612ea | 647 | #else |
silviosz | 1:a5ccd53612ea | 648 | #error unsupported STM32 |
silviosz | 1:a5ccd53612ea | 649 | #endif |
silviosz | 1:a5ccd53612ea | 650 | |
silviosz | 1:a5ccd53612ea | 651 | #if 0 |
silviosz | 1:a5ccd53612ea | 652 | #elif defined(ARDUINO_GENERIC_STM32F103C) || defined(ARDUINO_NUCLEO_F103C8) || defined(ARDUINO_BLUEPILL_F103C8) |
silviosz | 1:a5ccd53612ea | 653 | #warning Uno Shield on BLUEPILL |
silviosz | 1:a5ccd53612ea | 654 | |
silviosz | 1:a5ccd53612ea | 655 | //LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST| |SD_SS|SD_DI|SD_DO|SD_SCK| |
silviosz | 1:a5ccd53612ea | 656 | //STM32 pin |PA7|PA6|PA5|PA4|PA3|PA2|PA1|PA0| |PB0|PB6|PB7|PB8|PB9| |PA15 |PB5 |PB4 |PB3 | **ALT-SPI1** |
silviosz | 1:a5ccd53612ea | 657 | |
silviosz | 1:a5ccd53612ea | 658 | #define RD_PORT GPIOB |
silviosz | 1:a5ccd53612ea | 659 | //#define RD_PIN 5 |
silviosz | 1:a5ccd53612ea | 660 | #define RD_PIN 0 //hardware mod to Adapter. Allows use of PB5 for SD Card |
silviosz | 1:a5ccd53612ea | 661 | #define WR_PORT GPIOB |
silviosz | 1:a5ccd53612ea | 662 | #define WR_PIN 6 |
silviosz | 1:a5ccd53612ea | 663 | #define CD_PORT GPIOB |
silviosz | 1:a5ccd53612ea | 664 | #define CD_PIN 7 |
silviosz | 1:a5ccd53612ea | 665 | #define CS_PORT GPIOB |
silviosz | 1:a5ccd53612ea | 666 | #define CS_PIN 8 |
silviosz | 1:a5ccd53612ea | 667 | #define RESET_PORT GPIOB |
silviosz | 1:a5ccd53612ea | 668 | #define RESET_PIN 9 |
silviosz | 1:a5ccd53612ea | 669 | |
silviosz | 1:a5ccd53612ea | 670 | // configure macros for the data pins |
silviosz | 1:a5ccd53612ea | 671 | #define write_8(d) { GPIOA->REGS(BSRR) = 0x00FF << 16; GPIOA->REGS(BSRR) = (d) & 0xFF; } |
silviosz | 1:a5ccd53612ea | 672 | #define read_8() (GPIOA->REGS(IDR) & 0xFF) |
silviosz | 1:a5ccd53612ea | 673 | // PA7 ..PA0 |
silviosz | 1:a5ccd53612ea | 674 | #define setWriteDir() {GP_OUT(GPIOA, CRL, 0xFFFFFFFF); } |
silviosz | 1:a5ccd53612ea | 675 | #define setReadDir() {GP_INP(GPIOA, CRL, 0xFFFFFFFF); } |
silviosz | 1:a5ccd53612ea | 676 | |
silviosz | 1:a5ccd53612ea | 677 | #elif IS_NUCLEO64 // Uno Shield on NUCLEO-64 |
silviosz | 1:a5ccd53612ea | 678 | #warning Uno Shield on NUCLEO-64 |
silviosz | 1:a5ccd53612ea | 679 | #define RD_PORT GPIOA //PA0 |
silviosz | 1:a5ccd53612ea | 680 | #define RD_PIN 0 |
silviosz | 1:a5ccd53612ea | 681 | #define WR_PORT GPIOA //PA1 |
silviosz | 1:a5ccd53612ea | 682 | #define WR_PIN 1 |
silviosz | 1:a5ccd53612ea | 683 | #define CD_PORT GPIOA //PA4 |
silviosz | 1:a5ccd53612ea | 684 | #define CD_PIN 4 |
silviosz | 1:a5ccd53612ea | 685 | #define CS_PORT GPIOB //PB0 |
silviosz | 1:a5ccd53612ea | 686 | #define CS_PIN 0 |
silviosz | 1:a5ccd53612ea | 687 | #define RESET_PORT GPIOC //PC1 |
silviosz | 1:a5ccd53612ea | 688 | #define RESET_PIN 1 |
silviosz | 1:a5ccd53612ea | 689 | |
silviosz | 1:a5ccd53612ea | 690 | // configure macros for the data pins |
silviosz | 1:a5ccd53612ea | 691 | #define AMASK ((1<<9)|(1<<10)|(1<<8)) //#0, #2, #7 |
silviosz | 1:a5ccd53612ea | 692 | #define BMASK ((1<<3)|(1<<5)|(1<<4)|(1<<10)) //#3, #4, #5, #6 |
silviosz | 1:a5ccd53612ea | 693 | #define CMASK ((1<<7)) //#1 |
silviosz | 1:a5ccd53612ea | 694 | |
silviosz | 1:a5ccd53612ea | 695 | #define write_8(d) { \ |
silviosz | 1:a5ccd53612ea | 696 | GPIOA->REGS(BSRR) = AMASK << 16; \ |
silviosz | 1:a5ccd53612ea | 697 | GPIOB->REGS(BSRR) = BMASK << 16; \ |
silviosz | 1:a5ccd53612ea | 698 | GPIOC->REGS(BSRR) = CMASK << 16; \ |
silviosz | 1:a5ccd53612ea | 699 | GPIOA->REGS(BSRR) = ( ((d) & (1<<0)) << 9) \ |
silviosz | 1:a5ccd53612ea | 700 | | (((d) & (1<<2)) << 8) \ |
silviosz | 1:a5ccd53612ea | 701 | | (((d) & (1<<7)) << 1); \ |
silviosz | 1:a5ccd53612ea | 702 | GPIOB->REGS(BSRR) = ( ((d) & (1<<3)) << 0) \ |
silviosz | 1:a5ccd53612ea | 703 | | (((d) & (1<<4)) << 1) \ |
silviosz | 1:a5ccd53612ea | 704 | | (((d) & (1<<5)) >> 1) \ |
silviosz | 1:a5ccd53612ea | 705 | | (((d) & (1<<6)) << 4); \ |
silviosz | 1:a5ccd53612ea | 706 | GPIOC->REGS(BSRR) = ( ((d) & (1<<1)) << 6); \ |
silviosz | 1:a5ccd53612ea | 707 | } |
silviosz | 1:a5ccd53612ea | 708 | |
silviosz | 1:a5ccd53612ea | 709 | #define read_8() ( ( ( (GPIOA->REGS(IDR) & (1<<9)) >> 9) \ |
silviosz | 1:a5ccd53612ea | 710 | | ((GPIOC->REGS(IDR) & (1<<7)) >> 6) \ |
silviosz | 1:a5ccd53612ea | 711 | | ((GPIOA->REGS(IDR) & (1<<10)) >> 8) \ |
silviosz | 1:a5ccd53612ea | 712 | | ((GPIOB->REGS(IDR) & (1<<3)) >> 0) \ |
silviosz | 1:a5ccd53612ea | 713 | | ((GPIOB->REGS(IDR) & (1<<5)) >> 1) \ |
silviosz | 1:a5ccd53612ea | 714 | | ((GPIOB->REGS(IDR) & (1<<4)) << 1) \ |
silviosz | 1:a5ccd53612ea | 715 | | ((GPIOB->REGS(IDR) & (1<<10)) >> 4) \ |
silviosz | 1:a5ccd53612ea | 716 | | ((GPIOA->REGS(IDR) & (1<<8)) >> 1))) |
silviosz | 1:a5ccd53612ea | 717 | |
silviosz | 1:a5ccd53612ea | 718 | |
silviosz | 1:a5ccd53612ea | 719 | #if defined(ARDUINO_NUCLEO_F103RB) || defined(ARDUINO_STM_NUCLEO_F103RB) //F103 has unusual GPIO modes |
silviosz | 1:a5ccd53612ea | 720 | // PA10,PA9,PA8 PB10 PB5,PB4,PB3 PC7 |
silviosz | 1:a5ccd53612ea | 721 | #define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFFF); GP_OUT(GPIOB, CRH, 0xF00); GP_OUT(GPIOB, CRL, 0xFFF000); GP_OUT(GPIOC, CRL, 0xF0000000); } |
silviosz | 1:a5ccd53612ea | 722 | #define setReadDir() {GP_INP(GPIOA, CRH, 0xFFF); GP_INP(GPIOB, CRH, 0xF00); GP_INP(GPIOB, CRL, 0xFFF000); GP_INP(GPIOC, CRL, 0xF0000000); } |
silviosz | 1:a5ccd53612ea | 723 | #else //F0xx, F3xx, F4xx, L0xx, L1xx, L4xx use MODER |
silviosz | 1:a5ccd53612ea | 724 | // PA10,PA9,PA8 PB10,PB5,PB4,PB3 PC7 |
silviosz | 1:a5ccd53612ea | 725 | #define setWriteDir() { setReadDir(); \ |
silviosz | 1:a5ccd53612ea | 726 | GPIOA->MODER |= 0x150000; GPIOB->MODER |= 0x100540; GPIOC->MODER |= 0x4000; } |
silviosz | 1:a5ccd53612ea | 727 | #define setReadDir() { GPIOA->MODER &= ~0x3F0000; GPIOB->MODER &= ~0x300FC0; GPIOC->MODER &= ~0xC000; } |
silviosz | 1:a5ccd53612ea | 728 | #endif |
silviosz | 1:a5ccd53612ea | 729 | |
silviosz | 1:a5ccd53612ea | 730 | #elif IS_NUCLEO144 // Uno Shield on NUCLEO-144 |
silviosz | 1:a5ccd53612ea | 731 | #warning Uno Shield on NUCLEO-144 |
silviosz | 1:a5ccd53612ea | 732 | #define RD_PORT GPIOA //PA3 |
silviosz | 1:a5ccd53612ea | 733 | #define RD_PIN 3 |
silviosz | 1:a5ccd53612ea | 734 | #define WR_PORT GPIOC //PC0 |
silviosz | 1:a5ccd53612ea | 735 | #define WR_PIN 0 |
silviosz | 1:a5ccd53612ea | 736 | #define CD_PORT GPIOC //PC3 |
silviosz | 1:a5ccd53612ea | 737 | #define CD_PIN 3 |
silviosz | 1:a5ccd53612ea | 738 | #define CS_PORT GPIOF //PF3 |
silviosz | 1:a5ccd53612ea | 739 | #define CS_PIN 3 |
silviosz | 1:a5ccd53612ea | 740 | #define RESET_PORT GPIOF //PF5 |
silviosz | 1:a5ccd53612ea | 741 | #define RESET_PIN 5 |
silviosz | 1:a5ccd53612ea | 742 | |
silviosz | 1:a5ccd53612ea | 743 | // configure macros for the data pins |
silviosz | 1:a5ccd53612ea | 744 | #define DMASK ((1<<15)) //#1 |
silviosz | 1:a5ccd53612ea | 745 | #define EMASK ((1<<13)|(1<<11)|(1<<9)) //#3, #5, #6 |
silviosz | 1:a5ccd53612ea | 746 | #define FMASK ((1<<12)|(1<<15)|(1<<14)|(1<<13)) //#0, #2, #4, #7 |
silviosz | 1:a5ccd53612ea | 747 | |
silviosz | 1:a5ccd53612ea | 748 | #define write_8(d) { \ |
silviosz | 1:a5ccd53612ea | 749 | GPIOD->REGS(BSRR) = DMASK << 16; \ |
silviosz | 1:a5ccd53612ea | 750 | GPIOE->REGS(BSRR) = EMASK << 16; \ |
silviosz | 1:a5ccd53612ea | 751 | GPIOF->REGS(BSRR) = FMASK << 16; \ |
silviosz | 1:a5ccd53612ea | 752 | GPIOD->REGS(BSRR) = ( ((d) & (1<<1)) << 14); \ |
silviosz | 1:a5ccd53612ea | 753 | GPIOE->REGS(BSRR) = ( ((d) & (1<<3)) << 10) \ |
silviosz | 1:a5ccd53612ea | 754 | | (((d) & (1<<5)) << 6) \ |
silviosz | 1:a5ccd53612ea | 755 | | (((d) & (1<<6)) << 3); \ |
silviosz | 1:a5ccd53612ea | 756 | GPIOF->REGS(BSRR) = ( ((d) & (1<<0)) << 12) \ |
silviosz | 1:a5ccd53612ea | 757 | | (((d) & (1<<2)) << 13) \ |
silviosz | 1:a5ccd53612ea | 758 | | (((d) & (1<<4)) << 10) \ |
silviosz | 1:a5ccd53612ea | 759 | | (((d) & (1<<7)) << 6); \ |
silviosz | 1:a5ccd53612ea | 760 | } |
silviosz | 1:a5ccd53612ea | 761 | |
silviosz | 1:a5ccd53612ea | 762 | #define read_8() ( ( ( (GPIOF->REGS(IDR) & (1<<12)) >> 12) \ |
silviosz | 1:a5ccd53612ea | 763 | | ((GPIOD->REGS(IDR) & (1<<15)) >> 14) \ |
silviosz | 1:a5ccd53612ea | 764 | | ((GPIOF->REGS(IDR) & (1<<15)) >> 13) \ |
silviosz | 1:a5ccd53612ea | 765 | | ((GPIOE->REGS(IDR) & (1<<13)) >> 10) \ |
silviosz | 1:a5ccd53612ea | 766 | | ((GPIOF->REGS(IDR) & (1<<14)) >> 10) \ |
silviosz | 1:a5ccd53612ea | 767 | | ((GPIOE->REGS(IDR) & (1<<11)) >> 6) \ |
silviosz | 1:a5ccd53612ea | 768 | | ((GPIOE->REGS(IDR) & (1<<9)) >> 3) \ |
silviosz | 1:a5ccd53612ea | 769 | | ((GPIOF->REGS(IDR) & (1<<13)) >> 6))) |
silviosz | 1:a5ccd53612ea | 770 | |
silviosz | 1:a5ccd53612ea | 771 | |
silviosz | 1:a5ccd53612ea | 772 | // PD15 PE13,PE11,PE9 PF15,PF14,PF13,PF12 |
silviosz | 1:a5ccd53612ea | 773 | #define setWriteDir() { setReadDir(); \ |
silviosz | 1:a5ccd53612ea | 774 | GPIOD->MODER |= 0x40000000; GPIOE->MODER |= 0x04440000; GPIOF->MODER |= 0x55000000; } |
silviosz | 1:a5ccd53612ea | 775 | #define setReadDir() { GPIOD->MODER &= ~0xC0000000; GPIOE->MODER &= ~0x0CCC0000; GPIOF->MODER &= ~0xFF000000; } |
silviosz | 1:a5ccd53612ea | 776 | |
silviosz | 1:a5ccd53612ea | 777 | #elif defined(ARDUINO_MAPLE_REV3) // Uno Shield on MAPLE_REV3 board |
silviosz | 1:a5ccd53612ea | 778 | #warning Uno Shield on MAPLE_REV3 board |
silviosz | 1:a5ccd53612ea | 779 | #define RD_PORT GPIOC |
silviosz | 1:a5ccd53612ea | 780 | #define RD_PIN 0 |
silviosz | 1:a5ccd53612ea | 781 | #define WR_PORT GPIOC |
silviosz | 1:a5ccd53612ea | 782 | #define WR_PIN 1 |
silviosz | 1:a5ccd53612ea | 783 | #define CD_PORT GPIOC |
silviosz | 1:a5ccd53612ea | 784 | #define CD_PIN 2 |
silviosz | 1:a5ccd53612ea | 785 | #define CS_PORT GPIOC |
silviosz | 1:a5ccd53612ea | 786 | #define CS_PIN 3 |
silviosz | 1:a5ccd53612ea | 787 | #define RESET_PORT GPIOC |
silviosz | 1:a5ccd53612ea | 788 | #define RESET_PIN 4 |
silviosz | 1:a5ccd53612ea | 789 | |
silviosz | 1:a5ccd53612ea | 790 | // configure macros for the data pins |
silviosz | 1:a5ccd53612ea | 791 | #define write_8(d) { \ |
silviosz | 1:a5ccd53612ea | 792 | GPIOA->REGS(BSRR) = 0x0703 << 16; \ |
silviosz | 1:a5ccd53612ea | 793 | GPIOB->REGS(BSRR) = 0x00E0 << 16; \ |
silviosz | 1:a5ccd53612ea | 794 | GPIOA->REGS(BSRR) = ( ((d) & (1<<0)) << 10) \ |
silviosz | 1:a5ccd53612ea | 795 | | (((d) & (1<<2)) >> 2) \ |
silviosz | 1:a5ccd53612ea | 796 | | (((d) & (1<<3)) >> 2) \ |
silviosz | 1:a5ccd53612ea | 797 | | (((d) & (1<<6)) << 2) \ |
silviosz | 1:a5ccd53612ea | 798 | | (((d) & (1<<7)) << 2); \ |
silviosz | 1:a5ccd53612ea | 799 | GPIOB->REGS(BSRR) = ( ((d) & (1<<1)) << 6) \ |
silviosz | 1:a5ccd53612ea | 800 | | (((d) & (1<<4)) << 1) \ |
silviosz | 1:a5ccd53612ea | 801 | | (((d) & (1<<5)) << 1); \ |
silviosz | 1:a5ccd53612ea | 802 | } |
silviosz | 1:a5ccd53612ea | 803 | |
silviosz | 1:a5ccd53612ea | 804 | #define read_8() ( ( ( (GPIOA->REGS(IDR) & (1<<10)) >> 10) \ |
silviosz | 1:a5ccd53612ea | 805 | | ((GPIOB->REGS(IDR) & (1<<7)) >> 6) \ |
silviosz | 1:a5ccd53612ea | 806 | | ((GPIOA->REGS(IDR) & (1<<0)) << 2) \ |
silviosz | 1:a5ccd53612ea | 807 | | ((GPIOA->REGS(IDR) & (1<<1)) << 2) \ |
silviosz | 1:a5ccd53612ea | 808 | | ((GPIOB->REGS(IDR) & (1<<5)) >> 1) \ |
silviosz | 1:a5ccd53612ea | 809 | | ((GPIOB->REGS(IDR) & (1<<6)) >> 1) \ |
silviosz | 1:a5ccd53612ea | 810 | | ((GPIOA->REGS(IDR) & (1<<8)) >> 2) \ |
silviosz | 1:a5ccd53612ea | 811 | | ((GPIOA->REGS(IDR) & (1<<9)) >> 2))) |
silviosz | 1:a5ccd53612ea | 812 | |
silviosz | 1:a5ccd53612ea | 813 | // PA10,PA9,PA8 PA1,PA0 PB7,PB6,PB5 |
silviosz | 1:a5ccd53612ea | 814 | #define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFFF); GP_OUT(GPIOA, CRL, 0xFF); GP_OUT(GPIOB, CRL, 0xFFF00000); } |
silviosz | 1:a5ccd53612ea | 815 | #define setReadDir() {GP_INP(GPIOA, CRH, 0xFFF); GP_INP(GPIOA, CRL, 0xFF); GP_INP(GPIOB, CRL, 0xFFF00000); } |
silviosz | 1:a5ccd53612ea | 816 | |
silviosz | 1:a5ccd53612ea | 817 | #else |
silviosz | 1:a5ccd53612ea | 818 | #error REGS group |
silviosz | 1:a5ccd53612ea | 819 | #endif |
silviosz | 1:a5ccd53612ea | 820 | |
silviosz | 1:a5ccd53612ea | 821 | #ifndef IDLE_DELAY |
silviosz | 1:a5ccd53612ea | 822 | #define IDLE_DELAY { WR_IDLE; } |
silviosz | 1:a5ccd53612ea | 823 | #endif |
silviosz | 1:a5ccd53612ea | 824 | |
silviosz | 1:a5ccd53612ea | 825 | #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; IDLE_DELAY; } |
silviosz | 1:a5ccd53612ea | 826 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
silviosz | 1:a5ccd53612ea | 827 | #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE2; RD_IDLE; } |
silviosz | 1:a5ccd53612ea | 828 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
silviosz | 1:a5ccd53612ea | 829 | |
silviosz | 1:a5ccd53612ea | 830 | //################################### ESP32 ############################## |
silviosz | 1:a5ccd53612ea | 831 | #elif defined(ESP32) //regular UNO shield on TTGO D1 R32 (ESP32) |
silviosz | 1:a5ccd53612ea | 832 | #define LCD_RD 2 //LED |
silviosz | 1:a5ccd53612ea | 833 | #define LCD_WR 4 |
silviosz | 1:a5ccd53612ea | 834 | #define LCD_RS 15 //hard-wired to A2 (GPIO35) |
silviosz | 1:a5ccd53612ea | 835 | #define LCD_CS 33 //hard-wired to A3 (GPIO34) |
silviosz | 1:a5ccd53612ea | 836 | #define LCD_RST 32 //hard-wired to A4 (GPIO36) |
silviosz | 1:a5ccd53612ea | 837 | |
silviosz | 1:a5ccd53612ea | 838 | #define LCD_D0 12 |
silviosz | 1:a5ccd53612ea | 839 | #define LCD_D1 13 |
silviosz | 1:a5ccd53612ea | 840 | #define LCD_D2 26 |
silviosz | 1:a5ccd53612ea | 841 | #define LCD_D3 25 |
silviosz | 1:a5ccd53612ea | 842 | #define LCD_D4 17 |
silviosz | 1:a5ccd53612ea | 843 | #define LCD_D5 16 |
silviosz | 1:a5ccd53612ea | 844 | #define LCD_D6 27 |
silviosz | 1:a5ccd53612ea | 845 | #define LCD_D7 14 |
silviosz | 1:a5ccd53612ea | 846 | |
silviosz | 1:a5ccd53612ea | 847 | #define RD_PORT GPIO.out |
silviosz | 1:a5ccd53612ea | 848 | #define RD_PIN LCD_RD |
silviosz | 1:a5ccd53612ea | 849 | #define WR_PORT GPIO.out |
silviosz | 1:a5ccd53612ea | 850 | #define WR_PIN LCD_WR |
silviosz | 1:a5ccd53612ea | 851 | #define CD_PORT GPIO.out |
silviosz | 1:a5ccd53612ea | 852 | #define CD_PIN LCD_RS |
silviosz | 1:a5ccd53612ea | 853 | #define CS_PORT GPIO.out1.val |
silviosz | 1:a5ccd53612ea | 854 | #define CS_PIN LCD_CS |
silviosz | 1:a5ccd53612ea | 855 | #define RESET_PORT GPIO.out1.val |
silviosz | 1:a5ccd53612ea | 856 | #define RESET_PIN LCD_RST |
silviosz | 1:a5ccd53612ea | 857 | |
silviosz | 1:a5ccd53612ea | 858 | static inline uint32_t map_8(uint32_t d) |
silviosz | 1:a5ccd53612ea | 859 | { |
silviosz | 1:a5ccd53612ea | 860 | return ( |
silviosz | 1:a5ccd53612ea | 861 | 0 |
silviosz | 1:a5ccd53612ea | 862 | | ((d & (1 << 0)) << (LCD_D0 - 0)) |
silviosz | 1:a5ccd53612ea | 863 | | ((d & (1 << 1)) << (LCD_D1 - 1)) |
silviosz | 1:a5ccd53612ea | 864 | | ((d & (1 << 2)) << (LCD_D2 - 2)) |
silviosz | 1:a5ccd53612ea | 865 | | ((d & (1 << 3)) << (LCD_D3 - 3)) |
silviosz | 1:a5ccd53612ea | 866 | | ((d & (1 << 4)) << (LCD_D4 - 4)) |
silviosz | 1:a5ccd53612ea | 867 | | ((d & (1 << 5)) << (LCD_D5 - 5)) |
silviosz | 1:a5ccd53612ea | 868 | | ((d & (1 << 6)) << (LCD_D6 - 6)) |
silviosz | 1:a5ccd53612ea | 869 | | ((d & (1 << 7)) << (LCD_D7 - 7)) |
silviosz | 1:a5ccd53612ea | 870 | ); |
silviosz | 1:a5ccd53612ea | 871 | } |
silviosz | 1:a5ccd53612ea | 872 | |
silviosz | 1:a5ccd53612ea | 873 | static inline uint8_t map_32(uint32_t d) |
silviosz | 1:a5ccd53612ea | 874 | { |
silviosz | 1:a5ccd53612ea | 875 | return ( |
silviosz | 1:a5ccd53612ea | 876 | 0 |
silviosz | 1:a5ccd53612ea | 877 | | ((d & (1 << LCD_D0)) >> (LCD_D0 - 0)) |
silviosz | 1:a5ccd53612ea | 878 | | ((d & (1 << LCD_D1)) >> (LCD_D1 - 1)) |
silviosz | 1:a5ccd53612ea | 879 | | ((d & (1 << LCD_D2)) >> (LCD_D2 - 2)) |
silviosz | 1:a5ccd53612ea | 880 | | ((d & (1 << LCD_D3)) >> (LCD_D3 - 3)) |
silviosz | 1:a5ccd53612ea | 881 | | ((d & (1 << LCD_D4)) >> (LCD_D4 - 4)) |
silviosz | 1:a5ccd53612ea | 882 | | ((d & (1 << LCD_D5)) >> (LCD_D5 - 5)) |
silviosz | 1:a5ccd53612ea | 883 | | ((d & (1 << LCD_D6)) >> (LCD_D6 - 6)) |
silviosz | 1:a5ccd53612ea | 884 | | ((d & (1 << LCD_D7)) >> (LCD_D7 - 7)) |
silviosz | 1:a5ccd53612ea | 885 | ); |
silviosz | 1:a5ccd53612ea | 886 | } |
silviosz | 1:a5ccd53612ea | 887 | |
silviosz | 1:a5ccd53612ea | 888 | static inline void write_8(uint16_t data) |
silviosz | 1:a5ccd53612ea | 889 | { |
silviosz | 1:a5ccd53612ea | 890 | GPIO.out_w1tc = map_8(0xFF); //could define once as DMASK |
silviosz | 1:a5ccd53612ea | 891 | GPIO.out_w1ts = map_8(data); |
silviosz | 1:a5ccd53612ea | 892 | } |
silviosz | 1:a5ccd53612ea | 893 | |
silviosz | 1:a5ccd53612ea | 894 | static inline uint8_t read_8() |
silviosz | 1:a5ccd53612ea | 895 | { |
silviosz | 1:a5ccd53612ea | 896 | return map_32(GPIO.in); |
silviosz | 1:a5ccd53612ea | 897 | } |
silviosz | 1:a5ccd53612ea | 898 | static void setWriteDir() |
silviosz | 1:a5ccd53612ea | 899 | { |
silviosz | 1:a5ccd53612ea | 900 | pinMode(LCD_D0, OUTPUT); |
silviosz | 1:a5ccd53612ea | 901 | pinMode(LCD_D1, OUTPUT); |
silviosz | 1:a5ccd53612ea | 902 | pinMode(LCD_D2, OUTPUT); |
silviosz | 1:a5ccd53612ea | 903 | pinMode(LCD_D3, OUTPUT); |
silviosz | 1:a5ccd53612ea | 904 | pinMode(LCD_D4, OUTPUT); |
silviosz | 1:a5ccd53612ea | 905 | pinMode(LCD_D5, OUTPUT); |
silviosz | 1:a5ccd53612ea | 906 | pinMode(LCD_D6, OUTPUT); |
silviosz | 1:a5ccd53612ea | 907 | pinMode(LCD_D7, OUTPUT); |
silviosz | 1:a5ccd53612ea | 908 | } |
silviosz | 1:a5ccd53612ea | 909 | |
silviosz | 1:a5ccd53612ea | 910 | static void setReadDir() |
silviosz | 1:a5ccd53612ea | 911 | { |
silviosz | 1:a5ccd53612ea | 912 | pinMode(LCD_D0, INPUT); |
silviosz | 1:a5ccd53612ea | 913 | pinMode(LCD_D1, INPUT); |
silviosz | 1:a5ccd53612ea | 914 | pinMode(LCD_D2, INPUT); |
silviosz | 1:a5ccd53612ea | 915 | pinMode(LCD_D3, INPUT); |
silviosz | 1:a5ccd53612ea | 916 | pinMode(LCD_D4, INPUT); |
silviosz | 1:a5ccd53612ea | 917 | pinMode(LCD_D5, INPUT); |
silviosz | 1:a5ccd53612ea | 918 | pinMode(LCD_D6, INPUT); |
silviosz | 1:a5ccd53612ea | 919 | pinMode(LCD_D7, INPUT); |
silviosz | 1:a5ccd53612ea | 920 | } |
silviosz | 1:a5ccd53612ea | 921 | |
silviosz | 1:a5ccd53612ea | 922 | #define WRITE_DELAY { } |
silviosz | 1:a5ccd53612ea | 923 | #define READ_DELAY { } |
silviosz | 1:a5ccd53612ea | 924 | |
silviosz | 1:a5ccd53612ea | 925 | #define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; } |
silviosz | 1:a5ccd53612ea | 926 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
silviosz | 1:a5ccd53612ea | 927 | #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } |
silviosz | 1:a5ccd53612ea | 928 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
silviosz | 1:a5ccd53612ea | 929 | |
silviosz | 1:a5ccd53612ea | 930 | #define PIN_LOW(p, b) (digitalWrite(b, LOW)) |
silviosz | 1:a5ccd53612ea | 931 | #define PIN_HIGH(p, b) (digitalWrite(b, HIGH)) |
silviosz | 1:a5ccd53612ea | 932 | #define PIN_OUTPUT(p, b) (pinMode(b, OUTPUT)) |
silviosz | 1:a5ccd53612ea | 933 | |
silviosz | 1:a5ccd53612ea | 934 | #else |
silviosz | 1:a5ccd53612ea | 935 | #error MCU unsupported |
silviosz | 1:a5ccd53612ea | 936 | #endif // regular UNO shields on Arduino boards |
silviosz | 1:a5ccd53612ea | 937 | |
silviosz | 1:a5ccd53612ea | 938 | #endif //!defined(USE_SPECIAL) || defined (USE_SPECIAL_FAIL) |
silviosz | 1:a5ccd53612ea | 939 | |
silviosz | 1:a5ccd53612ea | 940 | #define RD_ACTIVE PIN_LOW(RD_PORT, RD_PIN) |
silviosz | 1:a5ccd53612ea | 941 | #define RD_IDLE PIN_HIGH(RD_PORT, RD_PIN) |
silviosz | 1:a5ccd53612ea | 942 | #define RD_OUTPUT PIN_OUTPUT(RD_PORT, RD_PIN) |
silviosz | 1:a5ccd53612ea | 943 | #define WR_ACTIVE PIN_LOW(WR_PORT, WR_PIN) |
silviosz | 1:a5ccd53612ea | 944 | #define WR_IDLE PIN_HIGH(WR_PORT, WR_PIN) |
silviosz | 1:a5ccd53612ea | 945 | #define WR_OUTPUT PIN_OUTPUT(WR_PORT, WR_PIN) |
silviosz | 1:a5ccd53612ea | 946 | #define CD_COMMAND PIN_LOW(CD_PORT, CD_PIN) |
silviosz | 1:a5ccd53612ea | 947 | #define CD_DATA PIN_HIGH(CD_PORT, CD_PIN) |
silviosz | 1:a5ccd53612ea | 948 | #define CD_OUTPUT PIN_OUTPUT(CD_PORT, CD_PIN) |
silviosz | 1:a5ccd53612ea | 949 | #define CS_ACTIVE PIN_LOW(CS_PORT, CS_PIN) |
silviosz | 1:a5ccd53612ea | 950 | #define CS_IDLE PIN_HIGH(CS_PORT, CS_PIN) |
silviosz | 1:a5ccd53612ea | 951 | #define CS_OUTPUT PIN_OUTPUT(CS_PORT, CS_PIN) |
silviosz | 1:a5ccd53612ea | 952 | #define RESET_ACTIVE PIN_LOW(RESET_PORT, RESET_PIN) |
silviosz | 1:a5ccd53612ea | 953 | #define RESET_IDLE PIN_HIGH(RESET_PORT, RESET_PIN) |
silviosz | 1:a5ccd53612ea | 954 | #define RESET_OUTPUT PIN_OUTPUT(RESET_PORT, RESET_PIN) |
silviosz | 1:a5ccd53612ea | 955 | |
silviosz | 1:a5ccd53612ea | 956 | // General macros. IOCLR registers are 1 cycle when optimised. |
silviosz | 1:a5ccd53612ea | 957 | #define WR_STROBE { WR_ACTIVE; WR_IDLE; } //PWLW=TWRL=50ns |
silviosz | 1:a5ccd53612ea | 958 | #define RD_STROBE RD_IDLE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE //PWLR=TRDL=150ns, tDDR=100ns |
silviosz | 1:a5ccd53612ea | 959 | |
silviosz | 1:a5ccd53612ea | 960 | #if !defined(GPIO_INIT) |
silviosz | 1:a5ccd53612ea | 961 | #define GPIO_INIT() |
silviosz | 1:a5ccd53612ea | 962 | #endif |
silviosz | 1:a5ccd53612ea | 963 | #define CTL_INIT() { GPIO_INIT(); RD_OUTPUT; WR_OUTPUT; CD_OUTPUT; CS_OUTPUT; RESET_OUTPUT; } |
silviosz | 1:a5ccd53612ea | 964 | #define WriteCmd(x) { CD_COMMAND; write16(x); CD_DATA; } |
silviosz | 1:a5ccd53612ea | 965 | #define WriteData(x) { write16(x); } |
silviosz | 1:a5ccd53612ea | 966 |