Henrique Rosa
/
ILI9341_01_PAR8_Teste_V3
Testanto funções Display
MCUFRIEND_kbv/utility/mcufriend_serial.h@1:a5ccd53612ea, 2021-04-21 (annotated)
- Committer:
- silviosz
- Date:
- Wed Apr 21 14:54:37 2021 +0000
- Revision:
- 1:a5ccd53612ea
ILI9341 display controller; parallel connection (Arduino Shield); NUCLEO-F103RB tested (2021-04-21) = success!
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
silviosz | 1:a5ccd53612ea | 1 | #if ARDUINO >= 165 |
silviosz | 1:a5ccd53612ea | 2 | #include <SPI.h> |
silviosz | 1:a5ccd53612ea | 3 | #endif |
silviosz | 1:a5ccd53612ea | 4 | |
silviosz | 1:a5ccd53612ea | 5 | #if 0 |
silviosz | 1:a5ccd53612ea | 6 | #elif defined(__AVR_ATmega328P__) |
silviosz | 1:a5ccd53612ea | 7 | |
silviosz | 1:a5ccd53612ea | 8 | #define SPI_INIT() { DDRB |= (1<<5)|(1<<3)|(1<<2); SPCR = (1<<SPE)|(1<<MSTR); SPSR = (1<<SPI2X); SPSR; SPDR; } |
silviosz | 1:a5ccd53612ea | 9 | static inline uint8_t spi_xfer(uint8_t c) |
silviosz | 1:a5ccd53612ea | 10 | { |
silviosz | 1:a5ccd53612ea | 11 | SPDR = c; |
silviosz | 1:a5ccd53612ea | 12 | while ((SPSR & (1<<SPIF)) == 0) ; |
silviosz | 1:a5ccd53612ea | 13 | return SPDR; |
silviosz | 1:a5ccd53612ea | 14 | } |
silviosz | 1:a5ccd53612ea | 15 | extern uint8_t running; |
silviosz | 1:a5ccd53612ea | 16 | static inline void write8(uint8_t x) { |
silviosz | 1:a5ccd53612ea | 17 | if (running) { |
silviosz | 1:a5ccd53612ea | 18 | while ((SPSR & 0x80) == 0); |
silviosz | 1:a5ccd53612ea | 19 | SPDR; |
silviosz | 1:a5ccd53612ea | 20 | } |
silviosz | 1:a5ccd53612ea | 21 | SPDR = x; |
silviosz | 1:a5ccd53612ea | 22 | running = 1; |
silviosz | 1:a5ccd53612ea | 23 | } |
silviosz | 1:a5ccd53612ea | 24 | static inline uint8_t read8(void) { |
silviosz | 1:a5ccd53612ea | 25 | if (running) while ((SPSR & 0x80) == 0); |
silviosz | 1:a5ccd53612ea | 26 | running = 0; |
silviosz | 1:a5ccd53612ea | 27 | return SPDR; |
silviosz | 1:a5ccd53612ea | 28 | } |
silviosz | 1:a5ccd53612ea | 29 | static inline uint8_t xchg8(uint8_t x) { write8(x); return read8(); } |
silviosz | 1:a5ccd53612ea | 30 | static inline void flush(void) { |
silviosz | 1:a5ccd53612ea | 31 | if (running) { |
silviosz | 1:a5ccd53612ea | 32 | while ((SPSR & 0x80) == 0); |
silviosz | 1:a5ccd53612ea | 33 | } |
silviosz | 1:a5ccd53612ea | 34 | running = 0; |
silviosz | 1:a5ccd53612ea | 35 | SPDR; |
silviosz | 1:a5ccd53612ea | 36 | } |
silviosz | 1:a5ccd53612ea | 37 | |
silviosz | 1:a5ccd53612ea | 38 | #if defined(SUPPORT_8347D) |
silviosz | 1:a5ccd53612ea | 39 | #warning using HX8347D hardware |
silviosz | 1:a5ccd53612ea | 40 | #define CD_PORT PORTD |
silviosz | 1:a5ccd53612ea | 41 | #define CD_PIN PD7 |
silviosz | 1:a5ccd53612ea | 42 | #define CS_PORT PORTB |
silviosz | 1:a5ccd53612ea | 43 | #define CS_PIN PB2 |
silviosz | 1:a5ccd53612ea | 44 | #define RESET_PORT PORTB |
silviosz | 1:a5ccd53612ea | 45 | #define RESET_PIN PB1 |
silviosz | 1:a5ccd53612ea | 46 | #define SD_PIN PD5 |
silviosz | 1:a5ccd53612ea | 47 | #define XPT_PIN PD4 |
silviosz | 1:a5ccd53612ea | 48 | #define RD_IDLE |
silviosz | 1:a5ccd53612ea | 49 | #define WR_IDLE |
silviosz | 1:a5ccd53612ea | 50 | #else |
silviosz | 1:a5ccd53612ea | 51 | #warning using regular SPI hardware |
silviosz | 1:a5ccd53612ea | 52 | #define CD_PORT PORTB |
silviosz | 1:a5ccd53612ea | 53 | #define CD_PIN 1 |
silviosz | 1:a5ccd53612ea | 54 | #define CS_PORT PORTB |
silviosz | 1:a5ccd53612ea | 55 | #define CS_PIN 2 |
silviosz | 1:a5ccd53612ea | 56 | #define RESET_PORT PORTB |
silviosz | 1:a5ccd53612ea | 57 | #define RESET_PIN 0 |
silviosz | 1:a5ccd53612ea | 58 | #define RD_IDLE |
silviosz | 1:a5ccd53612ea | 59 | #define WR_IDLE |
silviosz | 1:a5ccd53612ea | 60 | #endif |
silviosz | 1:a5ccd53612ea | 61 | |
silviosz | 1:a5ccd53612ea | 62 | #define setWriteDir() { } |
silviosz | 1:a5ccd53612ea | 63 | #define setReadDir() { } |
silviosz | 1:a5ccd53612ea | 64 | //#define write8(x) spi_xfer(x) |
silviosz | 1:a5ccd53612ea | 65 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
silviosz | 1:a5ccd53612ea | 66 | #define READ_8(dst) { dst = xchg8(0); } |
silviosz | 1:a5ccd53612ea | 67 | #define READ_16(dst) { dst = xchg8(0); dst = (dst << 8) | xchg8(0); } |
silviosz | 1:a5ccd53612ea | 68 | |
silviosz | 1:a5ccd53612ea | 69 | #define PIN_LOW(p, b) (p) &= ~(1<<(b)) |
silviosz | 1:a5ccd53612ea | 70 | #define PIN_HIGH(p, b) (p) |= (1<<(b)) |
silviosz | 1:a5ccd53612ea | 71 | #define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b)) |
silviosz | 1:a5ccd53612ea | 72 | #elif defined(__SAMD21G18A__) |
silviosz | 1:a5ccd53612ea | 73 | |
silviosz | 1:a5ccd53612ea | 74 | #define SPI_INIT() { SPI.begin(); SPI.setDataMode(SPI_MODE0); SPI.setClockDivider(6); } |
silviosz | 1:a5ccd53612ea | 75 | |
silviosz | 1:a5ccd53612ea | 76 | #define CD_PORT PORT->Group[0] |
silviosz | 1:a5ccd53612ea | 77 | #define CD_PIN 7 |
silviosz | 1:a5ccd53612ea | 78 | #define CS_PORT PORT->Group[0] |
silviosz | 1:a5ccd53612ea | 79 | #define CS_PIN 18 |
silviosz | 1:a5ccd53612ea | 80 | #define RESET_PORT PORT->Group[0] |
silviosz | 1:a5ccd53612ea | 81 | #define RESET_PIN 6 |
silviosz | 1:a5ccd53612ea | 82 | #define RD_IDLE |
silviosz | 1:a5ccd53612ea | 83 | #define WR_IDLE |
silviosz | 1:a5ccd53612ea | 84 | |
silviosz | 1:a5ccd53612ea | 85 | |
silviosz | 1:a5ccd53612ea | 86 | uint8_t running; |
silviosz | 1:a5ccd53612ea | 87 | static inline void write8(uint8_t c) |
silviosz | 1:a5ccd53612ea | 88 | { |
silviosz | 1:a5ccd53612ea | 89 | running = 1; |
silviosz | 1:a5ccd53612ea | 90 | while( SERCOM1->SPI.INTFLAG.bit.DRE == 0) ; |
silviosz | 1:a5ccd53612ea | 91 | SERCOM1->SPI.DATA.bit.DATA = c; // Writing data into Data register |
silviosz | 1:a5ccd53612ea | 92 | } |
silviosz | 1:a5ccd53612ea | 93 | |
silviosz | 1:a5ccd53612ea | 94 | static inline void flush(void) |
silviosz | 1:a5ccd53612ea | 95 | { |
silviosz | 1:a5ccd53612ea | 96 | if (running) while( SERCOM1->SPI.INTFLAG.bit.TXC == 0) ; |
silviosz | 1:a5ccd53612ea | 97 | running = 0; |
silviosz | 1:a5ccd53612ea | 98 | } |
silviosz | 1:a5ccd53612ea | 99 | |
silviosz | 1:a5ccd53612ea | 100 | static inline uint8_t xchg8(uint8_t c) |
silviosz | 1:a5ccd53612ea | 101 | { |
silviosz | 1:a5ccd53612ea | 102 | // flush(); |
silviosz | 1:a5ccd53612ea | 103 | while( SERCOM1->SPI.INTFLAG.bit.RXC != 0) SERCOM1->SPI.DATA.bit.DATA; //eat up |
silviosz | 1:a5ccd53612ea | 104 | while( SERCOM1->SPI.INTFLAG.bit.DRE == 0) ; |
silviosz | 1:a5ccd53612ea | 105 | SERCOM1->SPI.DATA.bit.DATA = c; // Writing data into Data register |
silviosz | 1:a5ccd53612ea | 106 | while( SERCOM1->SPI.INTFLAG.bit.RXC == 0) ; |
silviosz | 1:a5ccd53612ea | 107 | return SERCOM1->SPI.DATA.bit.DATA; |
silviosz | 1:a5ccd53612ea | 108 | } |
silviosz | 1:a5ccd53612ea | 109 | |
silviosz | 1:a5ccd53612ea | 110 | |
silviosz | 1:a5ccd53612ea | 111 | #define setWriteDir() { } |
silviosz | 1:a5ccd53612ea | 112 | #define setReadDir() { } |
silviosz | 1:a5ccd53612ea | 113 | //#define flush() |
silviosz | 1:a5ccd53612ea | 114 | //#define write8(x) xchg8(x) |
silviosz | 1:a5ccd53612ea | 115 | //#define xchg8(x) SPI.transfer(x) |
silviosz | 1:a5ccd53612ea | 116 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
silviosz | 1:a5ccd53612ea | 117 | #define READ_8(dst) { dst = xchg8(0); } |
silviosz | 1:a5ccd53612ea | 118 | #define READ_16(dst) { dst = xchg8(0); dst = (dst << 8) | xchg8(0); } |
silviosz | 1:a5ccd53612ea | 119 | |
silviosz | 1:a5ccd53612ea | 120 | // Shield Control macros. |
silviosz | 1:a5ccd53612ea | 121 | #define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin)) |
silviosz | 1:a5ccd53612ea | 122 | #define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin)) |
silviosz | 1:a5ccd53612ea | 123 | #define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin)) |
silviosz | 1:a5ccd53612ea | 124 | |
silviosz | 1:a5ccd53612ea | 125 | #elif defined(__AVR_ATxmega128A1__) //3.49s @ 32MHz -O2 |
silviosz | 1:a5ccd53612ea | 126 | #define CD_PORT VPORT2 |
silviosz | 1:a5ccd53612ea | 127 | #define CD_PIN 1 |
silviosz | 1:a5ccd53612ea | 128 | #define CS_PORT VPORT3 |
silviosz | 1:a5ccd53612ea | 129 | #define CS_PIN 4 |
silviosz | 1:a5ccd53612ea | 130 | #define RESET_PORT VPORT2 |
silviosz | 1:a5ccd53612ea | 131 | #define RESET_PIN 0 |
silviosz | 1:a5ccd53612ea | 132 | #define SPCRVAL (USART_CLK2X_bm | USART_RXEN_bm | USART_TXEN_bm) |
silviosz | 1:a5ccd53612ea | 133 | #define SETDDR {VPORT3.DIR |= (1<<4)|(1<<5)|(1<<7); VPORT2.DIR |= 0x03; } |
silviosz | 1:a5ccd53612ea | 134 | #define SPI_INIT() { PORTCFG.VPCTRLB=PORTCFG_VP3MAP_PORTF_gc | PORTCFG_VP2MAP_PORTC_gc; CS_IDLE; RESET_IDLE; SETDDR; spi_init(); } |
silviosz | 1:a5ccd53612ea | 135 | |
silviosz | 1:a5ccd53612ea | 136 | void spi_init(void) |
silviosz | 1:a5ccd53612ea | 137 | { |
silviosz | 1:a5ccd53612ea | 138 | SPIF.CTRL=SPI_ENABLE_bm | SPI_MODE_3_gc | (1<<SPI_MASTER_bp) | (1<<SPI_CLK2X_bp); |
silviosz | 1:a5ccd53612ea | 139 | } |
silviosz | 1:a5ccd53612ea | 140 | |
silviosz | 1:a5ccd53612ea | 141 | #define write8(x) {\ |
silviosz | 1:a5ccd53612ea | 142 | SPIF.DATA=x;\ |
silviosz | 1:a5ccd53612ea | 143 | while ((SPIF.STATUS & SPI_IF_bm)==0);\ |
silviosz | 1:a5ccd53612ea | 144 | SPIF.DATA;\ |
silviosz | 1:a5ccd53612ea | 145 | } |
silviosz | 1:a5ccd53612ea | 146 | #define flush() {\ |
silviosz | 1:a5ccd53612ea | 147 | } |
silviosz | 1:a5ccd53612ea | 148 | |
silviosz | 1:a5ccd53612ea | 149 | #define PIN_LOW(p, b) (p).OUT &= ~(1<<(b)) |
silviosz | 1:a5ccd53612ea | 150 | #define PIN_HIGH(p, b) (p).OUT |= (1<<(b)) |
silviosz | 1:a5ccd53612ea | 151 | #define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b)) |
silviosz | 1:a5ccd53612ea | 152 | |
silviosz | 1:a5ccd53612ea | 153 | #elif defined(__AVR_ATxmega32A4U__) //3.49s @ 32MHz -O2. |
silviosz | 1:a5ccd53612ea | 154 | // 100ns/150ns for ILI9341 W/R cycle. 100ns/200ns for ILI920. 20ns/150ns HX8347 |
silviosz | 1:a5ccd53612ea | 155 | // Xmega @ 60MHz i.e. 30MHz SCK works with 9341. |
silviosz | 1:a5ccd53612ea | 156 | #warning Using ATxmega32A4U USART_MSPI |
silviosz | 1:a5ccd53612ea | 157 | #define CD_PORT VPORT2 |
silviosz | 1:a5ccd53612ea | 158 | #define CD_PIN 1 |
silviosz | 1:a5ccd53612ea | 159 | #define CS_PORT VPORT3 |
silviosz | 1:a5ccd53612ea | 160 | #define CS_PIN 0 |
silviosz | 1:a5ccd53612ea | 161 | #define RESET_PORT VPORT2 |
silviosz | 1:a5ccd53612ea | 162 | #define RESET_PIN 0 |
silviosz | 1:a5ccd53612ea | 163 | #define SD_PORT PORTC |
silviosz | 1:a5ccd53612ea | 164 | #define SD_PIN 4 |
silviosz | 1:a5ccd53612ea | 165 | #define SPCRVAL (USART_CLK2X_bm | USART_RXEN_bm | USART_TXEN_bm) |
silviosz | 1:a5ccd53612ea | 166 | #define SETDDR {PORTCFG.VPCTRLB=PORTCFG_VP13MAP_PORTD_gc | PORTCFG_VP02MAP_PORTC_gc; VPORT3.DIR |= (1<<0)|(1<<1)|(1<<3); VPORT2.DIR |= 0x03; PIN_HIGH(SD_PORT, SD_PIN); SD_PORT.DIR |= (1<<SD_PIN); } |
silviosz | 1:a5ccd53612ea | 167 | #define SPI_INIT() { CS_IDLE; RESET_IDLE; SETDDR; spi_init(); } |
silviosz | 1:a5ccd53612ea | 168 | |
silviosz | 1:a5ccd53612ea | 169 | static inline void spi_init(void) |
silviosz | 1:a5ccd53612ea | 170 | { |
silviosz | 1:a5ccd53612ea | 171 | USARTD0.CTRLB = SPCRVAL; |
silviosz | 1:a5ccd53612ea | 172 | USARTD0.CTRLC = USART_CMODE_MSPI_gc | 0x00 | 0x00; //mode #0 |
silviosz | 1:a5ccd53612ea | 173 | // PORTD.PIN1CTRL |= PORT_INVEN_bm; //CPOL |
silviosz | 1:a5ccd53612ea | 174 | USARTD0.BAUDCTRLA = 0x00; //F_CPU/2 |
silviosz | 1:a5ccd53612ea | 175 | USARTD0.BAUDCTRLB = ((0x00 << USART_BSCALE_gp) & USART_BSCALE_gm) | 0x00; |
silviosz | 1:a5ccd53612ea | 176 | USARTD0.DATA; |
silviosz | 1:a5ccd53612ea | 177 | } |
silviosz | 1:a5ccd53612ea | 178 | |
silviosz | 1:a5ccd53612ea | 179 | extern uint8_t running; |
silviosz | 1:a5ccd53612ea | 180 | |
silviosz | 1:a5ccd53612ea | 181 | #define write8(x) {\ |
silviosz | 1:a5ccd53612ea | 182 | while ((USARTD0.STATUS & USART_DREIF_bm) == 0) ;\ |
silviosz | 1:a5ccd53612ea | 183 | asm("cli");\ |
silviosz | 1:a5ccd53612ea | 184 | USARTD0.DATA = x;\ |
silviosz | 1:a5ccd53612ea | 185 | USARTD0.STATUS = USART_TXCIF_bm;\ |
silviosz | 1:a5ccd53612ea | 186 | asm("sei");\ |
silviosz | 1:a5ccd53612ea | 187 | running = 1;\ |
silviosz | 1:a5ccd53612ea | 188 | } |
silviosz | 1:a5ccd53612ea | 189 | static inline uint8_t read8(void) { |
silviosz | 1:a5ccd53612ea | 190 | if (running) while ((USARTD0.STATUS & USART_RXCIF_bm) == 0) ; |
silviosz | 1:a5ccd53612ea | 191 | return USARTD0.DATA; |
silviosz | 1:a5ccd53612ea | 192 | } |
silviosz | 1:a5ccd53612ea | 193 | #define flush() {\ |
silviosz | 1:a5ccd53612ea | 194 | if (running) while ((USARTD0.STATUS & USART_TXCIF_bm) == 0) ;\ |
silviosz | 1:a5ccd53612ea | 195 | while ((USARTD0.STATUS & USART_RXCIF_bm) != 0) USARTD0.DATA;\ |
silviosz | 1:a5ccd53612ea | 196 | running = 0;\ |
silviosz | 1:a5ccd53612ea | 197 | } |
silviosz | 1:a5ccd53612ea | 198 | static inline uint8_t xchg8(uint8_t x) { |
silviosz | 1:a5ccd53612ea | 199 | USARTD0.DATA = x; |
silviosz | 1:a5ccd53612ea | 200 | while ((USARTD0.STATUS & USART_RXCIF_bm) == 0) ; |
silviosz | 1:a5ccd53612ea | 201 | return USARTD0.DATA; |
silviosz | 1:a5ccd53612ea | 202 | } |
silviosz | 1:a5ccd53612ea | 203 | /* |
silviosz | 1:a5ccd53612ea | 204 | #define write8(x) {\ |
silviosz | 1:a5ccd53612ea | 205 | while ((USARTD0.STATUS & USART_DREIF_bm) == 0) ;\ |
silviosz | 1:a5ccd53612ea | 206 | USARTD0.DATA = x;\ |
silviosz | 1:a5ccd53612ea | 207 | while ((USARTD0.STATUS & USART_RXCIF_bm) == 0) ;\ |
silviosz | 1:a5ccd53612ea | 208 | USARTD0.DATA;\ |
silviosz | 1:a5ccd53612ea | 209 | } |
silviosz | 1:a5ccd53612ea | 210 | #define flush() |
silviosz | 1:a5ccd53612ea | 211 | */ |
silviosz | 1:a5ccd53612ea | 212 | |
silviosz | 1:a5ccd53612ea | 213 | #define RD_IDLE |
silviosz | 1:a5ccd53612ea | 214 | #define WR_IDLE |
silviosz | 1:a5ccd53612ea | 215 | //#define SPI_INIT() spi_init() |
silviosz | 1:a5ccd53612ea | 216 | #define setWriteDir() { } |
silviosz | 1:a5ccd53612ea | 217 | #define setReadDir() { } |
silviosz | 1:a5ccd53612ea | 218 | //#define write8(x) spi_xfer(x) |
silviosz | 1:a5ccd53612ea | 219 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
silviosz | 1:a5ccd53612ea | 220 | #define READ_8(dst) { dst = xchg8(0); } |
silviosz | 1:a5ccd53612ea | 221 | #define READ_16(dst) { dst = xchg8(0); dst = (dst << 8) | xchg8(0); } |
silviosz | 1:a5ccd53612ea | 222 | |
silviosz | 1:a5ccd53612ea | 223 | #define PIN_LOW(p, b) (p).OUT &= ~(1<<(b)) |
silviosz | 1:a5ccd53612ea | 224 | #define PIN_HIGH(p, b) (p).OUT |= (1<<(b)) |
silviosz | 1:a5ccd53612ea | 225 | #define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b)) |
silviosz | 1:a5ccd53612ea | 226 | |
silviosz | 1:a5ccd53612ea | 227 | #endif |
silviosz | 1:a5ccd53612ea | 228 | |
silviosz | 1:a5ccd53612ea | 229 | #define CD_COMMAND {flush(); PIN_LOW(CD_PORT, CD_PIN); } |
silviosz | 1:a5ccd53612ea | 230 | #define CD_DATA {flush(); PIN_HIGH(CD_PORT, CD_PIN); } |
silviosz | 1:a5ccd53612ea | 231 | #define CD_OUTPUT PIN_OUTPUT(CD_PORT, CD_PIN) |
silviosz | 1:a5ccd53612ea | 232 | #define CS_ACTIVE PIN_LOW(CS_PORT, CS_PIN) |
silviosz | 1:a5ccd53612ea | 233 | #define CS_IDLE {flush(); PIN_HIGH(CS_PORT, CS_PIN); } |
silviosz | 1:a5ccd53612ea | 234 | #define CS_OUTPUT PIN_OUTPUT(CS_PORT, CS_PIN) |
silviosz | 1:a5ccd53612ea | 235 | #define RESET_ACTIVE PIN_LOW(RESET_PORT, RESET_PIN) |
silviosz | 1:a5ccd53612ea | 236 | #define RESET_IDLE PIN_HIGH(RESET_PORT, RESET_PIN) |
silviosz | 1:a5ccd53612ea | 237 | #define RESET_OUTPUT PIN_OUTPUT(RESET_PORT, RESET_PIN) |
silviosz | 1:a5ccd53612ea | 238 | |
silviosz | 1:a5ccd53612ea | 239 | // General macros. IOCLR registers are 1 cycle when optimised. |
silviosz | 1:a5ccd53612ea | 240 | |
silviosz | 1:a5ccd53612ea | 241 | #define CTL_INIT() { CD_OUTPUT; CS_OUTPUT; RESET_OUTPUT; SPI_INIT(); } |
silviosz | 1:a5ccd53612ea | 242 | #define WriteCmd(x) { CD_COMMAND; write8(x); } |
silviosz | 1:a5ccd53612ea | 243 | #define WriteData(x) { CD_DATA; write16(x); } |
silviosz | 1:a5ccd53612ea | 244 |