Henrique Rosa
/
ILI9341_01_PAR8_Teste_V3
Testanto funções Display
MCUFRIEND_kbv/utility/mcufriend_mbed.h@4:2d8f54d22dbd, 2021-04-27 (annotated)
- Committer:
- henriquer
- Date:
- Tue Apr 27 21:18:52 2021 +0000
- Revision:
- 4:2d8f54d22dbd
- Parent:
- 1:a5ccd53612ea
Escrevendo um sinal analogico ( Seno e Cosseno) no display TFT
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
silviosz | 1:a5ccd53612ea | 1 | #ifndef MCUFRIEND_MBED_H_ |
silviosz | 1:a5ccd53612ea | 2 | #define MCUFRIEND_MBED_H_ |
silviosz | 1:a5ccd53612ea | 3 | |
silviosz | 1:a5ccd53612ea | 4 | #include <mbed.h> |
silviosz | 1:a5ccd53612ea | 5 | |
silviosz | 1:a5ccd53612ea | 6 | #if defined(USE_SERIAL) |
silviosz | 1:a5ccd53612ea | 7 | #include "mcufriend_keil_spi.h" |
silviosz | 1:a5ccd53612ea | 8 | #else |
silviosz | 1:a5ccd53612ea | 9 | |
silviosz | 1:a5ccd53612ea | 10 | BusOut digitalL(D0, D1, D2, D3, D4, D5, D6, D7); |
silviosz | 1:a5ccd53612ea | 11 | BusOut digitalH(D8, D9, D10, D11, D12, D13, NC, NC); |
silviosz | 1:a5ccd53612ea | 12 | BusOut analog(A0, A1, A2, A3, A4, A5, NC, NC); |
silviosz | 1:a5ccd53612ea | 13 | |
silviosz | 1:a5ccd53612ea | 14 | #include "pin_shield_1.h" //shield pin macros e.g. A2_PORT, PIN_OUTPUT() |
silviosz | 1:a5ccd53612ea | 15 | #include "pin_shield_8.h" //macros for write_8(), read_8(), setWriteDir(), ... |
silviosz | 1:a5ccd53612ea | 16 | |
silviosz | 1:a5ccd53612ea | 17 | // control pins as used in MCUFRIEND shields |
silviosz | 1:a5ccd53612ea | 18 | #define RD_PORT A0_PORT |
silviosz | 1:a5ccd53612ea | 19 | #define RD_PIN A0_PIN |
silviosz | 1:a5ccd53612ea | 20 | #define WR_PORT A1_PORT |
silviosz | 1:a5ccd53612ea | 21 | #define WR_PIN A1_PIN |
silviosz | 1:a5ccd53612ea | 22 | #define CD_PORT A2_PORT |
silviosz | 1:a5ccd53612ea | 23 | #define CD_PIN A2_PIN |
silviosz | 1:a5ccd53612ea | 24 | #define CS_PORT A3_PORT |
silviosz | 1:a5ccd53612ea | 25 | #define CS_PIN A3_PIN |
silviosz | 1:a5ccd53612ea | 26 | #define RESET_PORT A4_PORT |
silviosz | 1:a5ccd53612ea | 27 | #define RESET_PIN A4_PIN |
silviosz | 1:a5ccd53612ea | 28 | |
silviosz | 1:a5ccd53612ea | 29 | // general purpose pin macros |
silviosz | 1:a5ccd53612ea | 30 | #define RD_ACTIVE PIN_LOW(RD_PORT, RD_PIN) |
silviosz | 1:a5ccd53612ea | 31 | #define RD_IDLE PIN_HIGH(RD_PORT, RD_PIN) |
silviosz | 1:a5ccd53612ea | 32 | #define RD_OUTPUT PIN_OUTPUT(RD_PORT, RD_PIN) |
silviosz | 1:a5ccd53612ea | 33 | #define WR_ACTIVE PIN_LOW(WR_PORT, WR_PIN) |
silviosz | 1:a5ccd53612ea | 34 | #define WR_IDLE PIN_HIGH(WR_PORT, WR_PIN) |
silviosz | 1:a5ccd53612ea | 35 | #define WR_OUTPUT PIN_OUTPUT(WR_PORT, WR_PIN) |
silviosz | 1:a5ccd53612ea | 36 | #define CD_COMMAND PIN_LOW(CD_PORT, CD_PIN) |
silviosz | 1:a5ccd53612ea | 37 | #define CD_DATA PIN_HIGH(CD_PORT, CD_PIN) |
silviosz | 1:a5ccd53612ea | 38 | #define CD_OUTPUT PIN_OUTPUT(CD_PORT, CD_PIN) |
silviosz | 1:a5ccd53612ea | 39 | #define CS_ACTIVE PIN_LOW(CS_PORT, CS_PIN) |
silviosz | 1:a5ccd53612ea | 40 | #define CS_IDLE PIN_HIGH(CS_PORT, CS_PIN) |
silviosz | 1:a5ccd53612ea | 41 | #define CS_OUTPUT PIN_OUTPUT(CS_PORT, CS_PIN) |
silviosz | 1:a5ccd53612ea | 42 | #define RESET_ACTIVE PIN_LOW(RESET_PORT, RESET_PIN) |
silviosz | 1:a5ccd53612ea | 43 | #define RESET_IDLE PIN_HIGH(RESET_PORT, RESET_PIN) |
silviosz | 1:a5ccd53612ea | 44 | #define RESET_OUTPUT PIN_OUTPUT(RESET_PORT, RESET_PIN) |
silviosz | 1:a5ccd53612ea | 45 | |
silviosz | 1:a5ccd53612ea | 46 | #define WR_ACTIVE2 {WR_ACTIVE; WR_ACTIVE;} |
silviosz | 1:a5ccd53612ea | 47 | #define WR_ACTIVE4 {WR_ACTIVE2; WR_ACTIVE2;} |
silviosz | 1:a5ccd53612ea | 48 | #define WR_ACTIVE8 {WR_ACTIVE4; WR_ACTIVE4;} |
silviosz | 1:a5ccd53612ea | 49 | #define RD_ACTIVE2 {RD_ACTIVE; RD_ACTIVE;} |
silviosz | 1:a5ccd53612ea | 50 | #define RD_ACTIVE4 {RD_ACTIVE2; RD_ACTIVE2;} |
silviosz | 1:a5ccd53612ea | 51 | #define RD_ACTIVE8 {RD_ACTIVE4; RD_ACTIVE4;} |
silviosz | 1:a5ccd53612ea | 52 | #define RD_ACTIVE16 {RD_ACTIVE8; RD_ACTIVE8;} |
silviosz | 1:a5ccd53612ea | 53 | #define WR_IDLE2 {WR_IDLE; WR_IDLE;} |
silviosz | 1:a5ccd53612ea | 54 | #define WR_IDLE4 {WR_IDLE2; WR_IDLE2;} |
silviosz | 1:a5ccd53612ea | 55 | #define RD_IDLE2 {RD_IDLE; RD_IDLE;} |
silviosz | 1:a5ccd53612ea | 56 | #define RD_IDLE4 {RD_IDLE2; RD_IDLE2;} |
silviosz | 1:a5ccd53612ea | 57 | |
silviosz | 1:a5ccd53612ea | 58 | #if defined(__MK20DX128__) || defined(___MK20DX256__) // Teensy3.0 || 3.2 96MHz |
silviosz | 1:a5ccd53612ea | 59 | #define WRITE_DELAY { WR_ACTIVE2; } |
silviosz | 1:a5ccd53612ea | 60 | #define READ_DELAY { RD_ACTIVE4; RD_ACTIVE; } |
silviosz | 1:a5ccd53612ea | 61 | #elif defined(__MK64FX512__) || defined(TARGET_M4) // Teensy3.5 120MHz thanks to PeteJohno |
silviosz | 1:a5ccd53612ea | 62 | #define WRITE_DELAY { WR_ACTIVE4; } |
silviosz | 1:a5ccd53612ea | 63 | #define READ_DELAY { RD_ACTIVE8; } |
silviosz | 1:a5ccd53612ea | 64 | #elif defined(__MK66FX1M0__) || defined(TARGET_M4) // Teensy3.6 180MHz untested. delays can possibly be reduced. |
silviosz | 1:a5ccd53612ea | 65 | #define WRITE_DELAY { WR_ACTIVE8; } |
silviosz | 1:a5ccd53612ea | 66 | #define READ_DELAY { RD_ACTIVE8; RD_ACTIVE8; } |
silviosz | 1:a5ccd53612ea | 67 | #elif defined(TARGET_M7) // Nucleo-F767 216MHz untested. delays can possibly be reduced. |
silviosz | 1:a5ccd53612ea | 68 | #define WRITE_DELAY { WR_ACTIVE8; WR_ACTIVE2; } |
silviosz | 1:a5ccd53612ea | 69 | #define IDLE_DELAY { WR_IDLE2;WR_IDLE; } |
silviosz | 1:a5ccd53612ea | 70 | #define READ_DELAY { RD_ACTIVE16; RD_ACTIVE16; RD_ACTIVE4; } |
silviosz | 1:a5ccd53612ea | 71 | #define READ_IDLE { RD_IDLE2;RD_IDLE; } |
silviosz | 1:a5ccd53612ea | 72 | #else |
silviosz | 1:a5ccd53612ea | 73 | //#error unspecified delays |
silviosz | 1:a5ccd53612ea | 74 | //#define WRITE_DELAY { WR_ACTIVE2; } |
silviosz | 1:a5ccd53612ea | 75 | //#define READ_DELAY { RD_ACTIVE4; RD_ACTIVE; } |
silviosz | 1:a5ccd53612ea | 76 | #define WRITE_DELAY |
silviosz | 1:a5ccd53612ea | 77 | #define READ_DELAY |
silviosz | 1:a5ccd53612ea | 78 | #endif |
silviosz | 1:a5ccd53612ea | 79 | |
silviosz | 1:a5ccd53612ea | 80 | #if !defined(IDLE_DELAY) |
silviosz | 1:a5ccd53612ea | 81 | #define IDLE_DELAY WR_IDLE |
silviosz | 1:a5ccd53612ea | 82 | #endif |
silviosz | 1:a5ccd53612ea | 83 | #if !defined(READ_IDLE) |
silviosz | 1:a5ccd53612ea | 84 | #define READ_IDLE RD_IDLE |
silviosz | 1:a5ccd53612ea | 85 | #endif |
silviosz | 1:a5ccd53612ea | 86 | |
silviosz | 1:a5ccd53612ea | 87 | // General macros. IOCLR registers are 1 cycle when optimised. |
silviosz | 1:a5ccd53612ea | 88 | #define WR_STROBE { WR_ACTIVE; WR_IDLE; } //PWLW=TWRL=50ns |
silviosz | 1:a5ccd53612ea | 89 | #define RD_STROBE RD_IDLE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE //PWLR=TRDL=150ns |
silviosz | 1:a5ccd53612ea | 90 | #define write8(d) { write_8(d); WRITE_DELAY; WR_STROBE; IDLE_DELAY; } // STROBEs are defined later |
silviosz | 1:a5ccd53612ea | 91 | #define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); } |
silviosz | 1:a5ccd53612ea | 92 | #define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); READ_IDLE; } // read 250ns after RD_ACTIVE goes low |
silviosz | 1:a5ccd53612ea | 93 | #define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); } |
silviosz | 1:a5ccd53612ea | 94 | |
silviosz | 1:a5ccd53612ea | 95 | #define CTL_INIT() { RD_OUTPUT; WR_OUTPUT; CD_OUTPUT; CS_OUTPUT; RESET_OUTPUT; } |
silviosz | 1:a5ccd53612ea | 96 | #define WriteCmd(x) { CD_COMMAND; write16(x); CD_DATA; } |
silviosz | 1:a5ccd53612ea | 97 | #define WriteData(x) { write16(x); } |
silviosz | 1:a5ccd53612ea | 98 | |
silviosz | 1:a5ccd53612ea | 99 | #endif //!USE_SERIAL |
silviosz | 1:a5ccd53612ea | 100 | #endif //MCUFRIEND_KEIL_H_ |
silviosz | 1:a5ccd53612ea | 101 |