Huseyin Erdem / Mbed 2 deprecated PiSwarmTableController

Table controller for piswarm-office

Dependencies:   mbed

Fork of PiSwarmTableController by piswarm

alpha433.h@5:68a1ce96bfeb, 2014-08-14 (annotated)

Committer:
hee502
Date:
Thu Aug 14 09:06:31 2014 +0000
Revision:
5:68a1ce96bfeb
Parent:
2:c81f4ef63132 
Table controller for piswarm-office

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jah128 2:c81f4ef63132 1 /* University of York Robot Lab m3pi Library: 433MHz Alpha Transceiver
jah128 2:c81f4ef63132 2 *
jah128 2:c81f4ef63132 3 * (C) Dr James Hilder, Dept. Electronics & Computer Science, University of York
jah128 2:c81f4ef63132 4 *
jah128 2:c81f4ef63132 5 * October 2013
jah128 2:c81f4ef63132 6 *
jah128 2:c81f4ef63132 7 * Designed for use with the enhanced MBED sensor board
jah128 2:c81f4ef63132 8 *
jah128 2:c81f4ef63132 9 * Based on code developed by Tobias Dipper, University of Stuttgart
jah128 2:c81f4ef63132 10 *
jah128 2:c81f4ef63132 11 * Permission is hereby granted, free of charge, to any person obtaining a copy
jah128 2:c81f4ef63132 12 * of this software and associated documentation files (the "Software"), to deal
jah128 2:c81f4ef63132 13 * in the Software without restriction, including without limitation the rights
jah128 2:c81f4ef63132 14 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
jah128 2:c81f4ef63132 15 * copies of the Software, and to permit persons to whom the Software is
jah128 2:c81f4ef63132 16 * furnished to do so, subject to the following conditions:
jah128 2:c81f4ef63132 17 *
jah128 2:c81f4ef63132 18 * The above copyright notice and this permission notice shall be included in
jah128 2:c81f4ef63132 19 * all copies or substantial portions of the Software.
jah128 2:c81f4ef63132 20 *
jah128 2:c81f4ef63132 21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
jah128 2:c81f4ef63132 22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
jah128 2:c81f4ef63132 23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
jah128 2:c81f4ef63132 24 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
jah128 2:c81f4ef63132 25 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
jah128 2:c81f4ef63132 26 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
jah128 2:c81f4ef63132 27 * THE SOFTWARE.
jah128 2:c81f4ef63132 28 */
jah128 2:c81f4ef63132 29
jah128 2:c81f4ef63132 30 #ifndef ALPHA433_H
jah128 2:c81f4ef63132 31 #define ALPHA433_H
jah128 2:c81f4ef63132 32
jah128 2:c81f4ef63132 33
jah128 2:c81f4ef63132 34 //
jah128 2:c81f4ef63132 35 // Defines
jah128 2:c81f4ef63132 36 //
jah128 2:c81f4ef63132 37 #define ALPHA433_FREQUENCY_315 0x0000
jah128 2:c81f4ef63132 38 #define ALPHA433_FREQUENCY_433 0x0010
jah128 2:c81f4ef63132 39 #define ALPHA433_FREQUENCY_868 0x0020
jah128 2:c81f4ef63132 40 #define ALPHA433_FREQUENCY_915 0x0030
jah128 2:c81f4ef63132 41 #define ALPHA433_CRYSTAL_LOAD_85 0x0000
jah128 2:c81f4ef63132 42 #define ALPHA433_CRYSTAL_LOAD_90 0x0001
jah128 2:c81f4ef63132 43 #define ALPHA433_CRYSTAL_LOAD_95 0x0002
jah128 2:c81f4ef63132 44 #define ALPHA433_CRYSTAL_LOAD_100 0x0003
jah128 2:c81f4ef63132 45 #define ALPHA433_CRYSTAL_LOAD_105 0x0004
jah128 2:c81f4ef63132 46 #define ALPHA433_CRYSTAL_LOAD_110 0x0005
jah128 2:c81f4ef63132 47 #define ALPHA433_CRYSTAL_LOAD_115 0x0006
jah128 2:c81f4ef63132 48 #define ALPHA433_CRYSTAL_LOAD_120 0x0007
jah128 2:c81f4ef63132 49 #define ALPHA433_CRYSTAL_LOAD_125 0x0008
jah128 2:c81f4ef63132 50 #define ALPHA433_CRYSTAL_LOAD_130 0x0009
jah128 2:c81f4ef63132 51 #define ALPHA433_CRYSTAL_LOAD_135 0x000A
jah128 2:c81f4ef63132 52 #define ALPHA433_CRYSTAL_LOAD_140 0x000B
jah128 2:c81f4ef63132 53 #define ALPHA433_CRYSTAL_LOAD_145 0x000C
jah128 2:c81f4ef63132 54 #define ALPHA433_CRYSTAL_LOAD_150 0x000D
jah128 2:c81f4ef63132 55 #define ALPHA433_CRYSTAL_LOAD_155 0x000E
jah128 2:c81f4ef63132 56 #define ALPHA433_CRYSTAL_LOAD_160 0x000F
jah128 2:c81f4ef63132 57 #define ALPHA433_USE_FIFO_YES 0x00C0
jah128 2:c81f4ef63132 58 #define ALPHA433_USE_FIFO_NO 0x0000
jah128 2:c81f4ef63132 59 #define ALPHA433_PIN20_INTERRUPT_IN 0x0000
jah128 2:c81f4ef63132 60 #define ALPHA433_PIN20_VDI_OUT 0x0400
jah128 2:c81f4ef63132 61 #define ALPHA433_VDI_RESPONSE_FAST 0x0000
jah128 2:c81f4ef63132 62 #define ALPHA433_VDI_RESPONSE_MEDIUM 0x0100
jah128 2:c81f4ef63132 63 #define ALPHA433_VDI_RESPONSE_SLOW 0x0200
jah128 2:c81f4ef63132 64 #define ALPHA433_VDI_RESPONSE_ALWAYS 0x0300
jah128 2:c81f4ef63132 65 #define ALPHA433_BANDWIDTH_400 0x0020
jah128 2:c81f4ef63132 66 #define ALPHA433_BANDWIDTH_340 0x0040
jah128 2:c81f4ef63132 67 #define ALPHA433_BANDWIDTH_270 0x0060
jah128 2:c81f4ef63132 68 #define ALPHA433_BANDWIDTH_200 0x0080
jah128 2:c81f4ef63132 69 #define ALPHA433_BANDWIDTH_134 0x00A0
jah128 2:c81f4ef63132 70 #define ALPHA433_BANDWIDTH_67 0x00C0
jah128 2:c81f4ef63132 71 #define ALPHA433_LNA_GAIN_0 0x0000
jah128 2:c81f4ef63132 72 #define ALPHA433_LNA_GAIN_6 0x0080
jah128 2:c81f4ef63132 73 #define ALPHA433_LNA_GAIN_14 0x0100
jah128 2:c81f4ef63132 74 #define ALPHA433_LNA_GAIN_20 0x0180
jah128 2:c81f4ef63132 75 #define ALPHA433_RSSI_103 0x0000
jah128 2:c81f4ef63132 76 #define ALPHA433_RSSI_97 0x0001
jah128 2:c81f4ef63132 77 #define ALPHA433_RSSI_91 0x0002
jah128 2:c81f4ef63132 78 #define ALPHA433_RSSI_85 0x0003
jah128 2:c81f4ef63132 79 #define ALPHA433_RSSI_79 0x0004
jah128 2:c81f4ef63132 80 #define ALPHA433_RSSI_73 0x0005
jah128 2:c81f4ef63132 81 #define ALPHA433_RSSI_67 0x0006
jah128 2:c81f4ef63132 82 #define ALPHA433_RSSI_61 0x0007
jah128 2:c81f4ef63132 83 #define ALPHA433_CLOCK_RECOVERY_AUTO 0x0080
jah128 2:c81f4ef63132 84 #define ALPHA433_CLOCK_RECOVERY_FAST 0x0040
jah128 2:c81f4ef63132 85 #define ALPHA433_CLOCK_RECOVERY_SLOW 0x0000
jah128 2:c81f4ef63132 86 #define ALPHA433_FILTER_DIGITAL 0x0000
jah128 2:c81f4ef63132 87 #define ALPHA433_FILTER_ANALOG 0x0010
jah128 2:c81f4ef63132 88 #define ALPHA433_DQD_0 0x0000
jah128 2:c81f4ef63132 89 #define ALPHA433_DQD_1 0x0001
jah128 2:c81f4ef63132 90 #define ALPHA433_DQD_2 0x0002
jah128 2:c81f4ef63132 91 #define ALPHA433_DQD_3 0x0003
jah128 2:c81f4ef63132 92 #define ALPHA433_DQD_4 0x0004
jah128 2:c81f4ef63132 93 #define ALPHA433_DQD_5 0x0005
jah128 2:c81f4ef63132 94 #define ALPHA433_DQD_6 0x0006
jah128 2:c81f4ef63132 95 #define ALPHA433_DQD_7 0x0007
jah128 2:c81f4ef63132 96 #define ALPHA433_FIFO_LEVEL_0 0x0000
jah128 2:c81f4ef63132 97 #define ALPHA433_FIFO_LEVEL_1 0x0010
jah128 2:c81f4ef63132 98 #define ALPHA433_FIFO_LEVEL_2 0x0020
jah128 2:c81f4ef63132 99 #define ALPHA433_FIFO_LEVEL_3 0x0030
jah128 2:c81f4ef63132 100 #define ALPHA433_FIFO_LEVEL_4 0x0040
jah128 2:c81f4ef63132 101 #define ALPHA433_FIFO_LEVEL_5 0x0050
jah128 2:c81f4ef63132 102 #define ALPHA433_FIFO_LEVEL_6 0x0060
jah128 2:c81f4ef63132 103 #define ALPHA433_FIFO_LEVEL_7 0x0070
jah128 2:c81f4ef63132 104 #define ALPHA433_FIFO_LEVEL_8 0x0080
jah128 2:c81f4ef63132 105 #define ALPHA433_FIFO_LEVEL_9 0x0090
jah128 2:c81f4ef63132 106 #define ALPHA433_FIFO_LEVEL_10 0x00A0
jah128 2:c81f4ef63132 107 #define ALPHA433_FIFO_LEVEL_11 0x00B0
jah128 2:c81f4ef63132 108 #define ALPHA433_FIFO_LEVEL_12 0x00C0
jah128 2:c81f4ef63132 109 #define ALPHA433_FIFO_LEVEL_13 0x00D0
jah128 2:c81f4ef63132 110 #define ALPHA433_FIFO_LEVEL_14 0x00E0
jah128 2:c81f4ef63132 111 #define ALPHA433_FIFO_LEVEL_15 0x00F0
jah128 2:c81f4ef63132 112 #define ALPHA433_FIFO_FILL_PATTERN 0x0000
jah128 2:c81f4ef63132 113 #define ALPHA433_FIFO_FILL_ALWAYS 0x0004
jah128 2:c81f4ef63132 114 #define ALPHA433_HI_SENS_RESET_ENABLE 0x0000
jah128 2:c81f4ef63132 115 #define ALPHA433_HI_SENS_RESET_DISABLE 0x0001
jah128 2:c81f4ef63132 116 #define ALPHA433_AFC_MODE_NOAUTO 0x0000
jah128 2:c81f4ef63132 117 #define ALPHA433_AFC_MODE_ONCE 0x0040
jah128 2:c81f4ef63132 118 #define ALPHA433_AFC_MODE_VDI 0x0080
jah128 2:c81f4ef63132 119 #define ALPHA433_AFC_MODE_INDEPENDENT 0x00C0
jah128 2:c81f4ef63132 120 #define ALPHA433_AFC_RANGE_3TO4 0x0030
jah128 2:c81f4ef63132 121 #define ALPHA433_AFC_RANGE_7TO8 0x0020
jah128 2:c81f4ef63132 122 #define ALPHA433_AFC_RANGE_15TO16 0x0010
jah128 2:c81f4ef63132 123 #define ALPHA433_AFC_RANGE_NO_RES 0x0000
jah128 2:c81f4ef63132 124 #define ALPHA433_AFC_FINE_ENABLE 0x0004
jah128 2:c81f4ef63132 125 #define ALPHA433_AFC_FINE_DISABLE 0x0000
jah128 2:c81f4ef63132 126 #define ALPHA433_AFC_ENABLE 0x0003
jah128 2:c81f4ef63132 127 #define ALPHA433_AFC_DISABLE 0x0000
jah128 2:c81f4ef63132 128 #define ALPHA433_MOD_POLARITY_P 0x0000
jah128 2:c81f4ef63132 129 #define ALPHA433_MOD_POLARITY_N 0x0100
jah128 2:c81f4ef63132 130 #define ALPHA433_MOD_FREQUENCY_15 0x0000
jah128 2:c81f4ef63132 131 #define ALPHA433_MOD_FREQUENCY_30 0x0010
jah128 2:c81f4ef63132 132 #define ALPHA433_MOD_FREQUENCY_45 0x0020
jah128 2:c81f4ef63132 133 #define ALPHA433_MOD_FREQUENCY_60 0x0030
jah128 2:c81f4ef63132 134 #define ALPHA433_MOD_FREQUENCY_75 0x0040
jah128 2:c81f4ef63132 135 #define ALPHA433_MOD_FREQUENCY_90 0x0050
jah128 2:c81f4ef63132 136 #define ALPHA433_MOD_FREQUENCY_105 0x0060
jah128 2:c81f4ef63132 137 #define ALPHA433_MOD_FREQUENCY_120 0x0070
jah128 2:c81f4ef63132 138 #define ALPHA433_MOD_FREQUENCY_135 0x0080
jah128 2:c81f4ef63132 139 #define ALPHA433_MOD_FREQUENCY_150 0x0090
jah128 2:c81f4ef63132 140 #define ALPHA433_MOD_FREQUENCY_165 0x00A0
jah128 2:c81f4ef63132 141 #define ALPHA433_MOD_FREQUENCY_180 0x00B0
jah128 2:c81f4ef63132 142 #define ALPHA433_MOD_FREQUENCY_195 0x00C0
jah128 2:c81f4ef63132 143 #define ALPHA433_MOD_FREQUENCY_210 0x00D0
jah128 2:c81f4ef63132 144 #define ALPHA433_MOD_FREQUENCY_225 0x00E0
jah128 2:c81f4ef63132 145 #define ALPHA433_MOD_FREQUENCY_240 0x00F0
jah128 2:c81f4ef63132 146 #define ALPHA433_TX_POWER_0 0x0000
jah128 2:c81f4ef63132 147 #define ALPHA433_TX_POWER_3 0x0001
jah128 2:c81f4ef63132 148 #define ALPHA433_TX_POWER_6 0x0002
jah128 2:c81f4ef63132 149 #define ALPHA433_TX_POWER_9 0x0003
jah128 2:c81f4ef63132 150 #define ALPHA433_TX_POWER_12 0x0004
jah128 2:c81f4ef63132 151 #define ALPHA433_TX_POWER_15 0x0005
jah128 2:c81f4ef63132 152 #define ALPHA433_TX_POWER_18 0x0006
jah128 2:c81f4ef63132 153 #define ALPHA433_TX_POWER_21 0x0007
jah128 2:c81f4ef63132 154 #define ALPHA433_CLK_OUT_1 0x0000
jah128 2:c81f4ef63132 155 #define ALPHA433_CLK_OUT_125 0x0020
jah128 2:c81f4ef63132 156 #define ALPHA433_CLK_OUT_166 0x0040
jah128 2:c81f4ef63132 157 #define ALPHA433_CLK_OUT_2 0x0060
jah128 2:c81f4ef63132 158 #define ALPHA433_CLK_OUT_25 0x0080
jah128 2:c81f4ef63132 159 #define ALPHA433_CLK_OUT_333 0x00A0
jah128 2:c81f4ef63132 160 #define ALPHA433_CLK_OUT_5 0x00C0
jah128 2:c81f4ef63132 161 #define ALPHA433_CLK_OUT_10 0x00E0
jah128 2:c81f4ef63132 162 #define ALPHA433_LOW_BAT22 0x0000
jah128 2:c81f4ef63132 163 #define ALPHA433_STATUS_TX_NEXT_BYTE 0x8000
jah128 2:c81f4ef63132 164 #define ALPHA433_STATUS_FIFO_LIMIT_REACHED 0x8000
jah128 2:c81f4ef63132 165 #define ALPHA433_STATUS_POWER_ON_RESET 0x4000
jah128 2:c81f4ef63132 166 #define ALPHA433_STATUS_RX_OVERFLOW 0x2000
jah128 2:c81f4ef63132 167 #define ALPHA433_STATUS_TX_UNDERRUN 0x2000
jah128 2:c81f4ef63132 168 #define ALPHA433_STATUS_WAKEUP 0x1000
jah128 2:c81f4ef63132 169 #define ALPHA433_STATUS_EXT 0x0800
jah128 2:c81f4ef63132 170 #define ALPHA433_STATUS_LOW_BATTERY 0x0400
jah128 2:c81f4ef63132 171 #define ALPHA433_STATUS_FIFO_EMPTY 0x0200
jah128 2:c81f4ef63132 172 #define ALPHA433_STATUS_STRONG_SIGNAL 0x0100
jah128 2:c81f4ef63132 173 #define ALPHA433_STATUS_RSSI 0x0100
jah128 2:c81f4ef63132 174 #define ALPHA433_STATUS_DQD 0x0080
jah128 2:c81f4ef63132 175 #define ALPHA433_STATUS_CLOCK_LOCKED 0x0040
jah128 2:c81f4ef63132 176 #define ALPHA433_TRANSMIT_OK 0
jah128 2:c81f4ef63132 177 #define ALPHA433_TRANSMIT_TIMEOUT 1
jah128 2:c81f4ef63132 178 #define ALPHA433_TRANSMIT_PARITY_ERROR 2
jah128 2:c81f4ef63132 179 #define ALPHA433_RECEIVE_OK 0
jah128 2:c81f4ef63132 180 #define ALPHA433_RECEIVE_TIMEOUT 1
jah128 2:c81f4ef63132 181 #define ALPHA433_RECEIVE_PARITY_ERROR 2
jah128 2:c81f4ef63132 182 #define ALPHA433_NODATA 0
jah128 2:c81f4ef63132 183 #define ALPHA433_DATA_AVAIABLE 1
jah128 2:c81f4ef63132 184 #define ALPHA433_MODE_TRANSMITTING 1
jah128 2:c81f4ef63132 185 #define ALPHA433_MODE_RECEIVING 2
jah128 2:c81f4ef63132 186 #define ALPHA433_MODE_SWITCHING 0
jah128 2:c81f4ef63132 187
jah128 2:c81f4ef63132 188 // ----------------------------- default user configuration --------------------------------
jah128 2:c81f4ef63132 189
jah128 2:c81f4ef63132 190 #define ALPHA433_FREQUENCY ALPHA433_FREQUENCY_433
jah128 2:c81f4ef63132 191 #define ALPHA433_CRYSTAL_LOAD ALPHA433_CRYSTAL_LOAD_100
jah128 2:c81f4ef63132 192 #define ALPHA433_USE_FIFO ALPHA433_USE_FIFO_YES
jah128 2:c81f4ef63132 193 #define ALPHA433_PIN20 ALPHA433_PIN20_INTERRUPT_IN
jah128 2:c81f4ef63132 194 #define ALPHA433_VDI_RESPONSE ALPHA433_VDI_RESPONSE_SLOW
jah128 2:c81f4ef63132 195 #define ALPHA433_BANDWIDTH ALPHA433_BANDWIDTH_134
jah128 2:c81f4ef63132 196 #define ALPHA433_LNA_GAIN ALPHA433_LNA_GAIN_0
jah128 2:c81f4ef63132 197 #define ALPHA433_RSSI ALPHA433_RSSI_97
jah128 2:c81f4ef63132 198 #define ALPHA433_CLOCK_RECOVERY ALPHA433_CLOCK_RECOVERY_SLOW
jah128 2:c81f4ef63132 199 #define ALPHA433_FILTER ALPHA433_FILTER_DIGITAL
jah128 2:c81f4ef63132 200 #define ALPHA433_DQD ALPHA433_DQD_4
jah128 2:c81f4ef63132 201 #define ALPHA433_FIFO_LEVEL ALPHA433_FIFO_LEVEL_8
jah128 2:c81f4ef63132 202 #define ALPHA433_FIFO_FILL ALPHA433_FIFO_FILL_PATTERN
jah128 2:c81f4ef63132 203 #define ALPHA433_HI_SENS_RESET ALPHA433_HI_SENS_RESET_DISABLE
jah128 2:c81f4ef63132 204 #define ALPHA433_AFC_MODE ALPHA433_AFC_MODE_INDEPENDENT
jah128 2:c81f4ef63132 205 #define ALPHA433_AFC_RANGE ALPHA433_AFC_RANGE_3TO4
jah128 2:c81f4ef63132 206 #define ALPHA433_AFC_FINE_MODE ALPHA433_AFC_FINE_DISABLE
jah128 2:c81f4ef63132 207 #define ALPHA433_AFC ALPHA433_AFC_DISABLE
jah128 2:c81f4ef63132 208 #define ALPHA433_MOD_POLARITY ALPHA433_MOD_POLARITY_P
jah128 2:c81f4ef63132 209 #define ALPHA433_MOD_FREQUENCY ALPHA433_MOD_FREQUENCY_90
jah128 2:c81f4ef63132 210 #define ALPHA433_TX_POWER ALPHA433_TX_POWER_0
jah128 2:c81f4ef63132 211 #define ALPHA433_CLK_OUT ALPHA433_CLK_OUT_2
jah128 2:c81f4ef63132 212 #define ALPHA433_LOW_BAT ALPHA433_LOW_BAT22
jah128 2:c81f4ef63132 213 #define ALPHA433_TIMEOUT 100
jah128 2:c81f4ef63132 214 #define TIMEOUT 5.0
jah128 2:c81f4ef63132 215
jah128 2:c81f4ef63132 216 class Alpha433 : public Stream {
jah128 2:c81f4ef63132 217
jah128 2:c81f4ef63132 218 // Public Functions
jah128 2:c81f4ef63132 219
jah128 2:c81f4ef63132 220 public:
jah128 2:c81f4ef63132 221
jah128 2:c81f4ef63132 222 /** Create the alpha433 object connected to the default pins
jah128 2:c81f4ef63132 223 *
jah128 2:c81f4ef63132 224 * @param mosi pin - default is p5
jah128 2:c81f4ef63132 225 * @param miso pin - default is p6
jah128 2:c81f4ef63132 226 * @param sck pin - default is p7
jah128 2:c81f4ef63132 227 * @param fss pin - default is p8
jah128 2:c81f4ef63132 228 * @param nirq pin - default is p11
jah128 2:c81f4ef63132 229 */
jah128 2:c81f4ef63132 230 Alpha433();
jah128 2:c81f4ef63132 231
jah128 2:c81f4ef63132 232 /** Create the alpha433 object connected to specific pins
jah128 2:c81f4ef63132 233 *
jah128 2:c81f4ef63132 234 */
jah128 2:c81f4ef63132 235 Alpha433(PinName mosi, PinName miso, PinName sck, PinName fss, PinName nirq);
jah128 2:c81f4ef63132 236
jah128 2:c81f4ef63132 237
jah128 2:c81f4ef63132 238 // Send a string to the RF transmitter
jah128 2:c81f4ef63132 239 unsigned long sendString(char cCount, char* cBuffer);
jah128 2:c81f4ef63132 240
jah128 2:c81f4ef63132 241 // Enable RF Transmitter
jah128 2:c81f4ef63132 242 void enableTransmitter(void);
jah128 2:c81f4ef63132 243
jah128 2:c81f4ef63132 244 // Disable RF Transmitter
jah128 2:c81f4ef63132 245 void disableTransmitter(void);
jah128 2:c81f4ef63132 246
jah128 2:c81f4ef63132 247 // Enable RF Receiver
jah128 2:c81f4ef63132 248 void enableReceiver(void);
jah128 2:c81f4ef63132 249
jah128 2:c81f4ef63132 250 // Disable RF Receiver
jah128 2:c81f4ef63132 251 void disableReceiver(void);
jah128 2:c81f4ef63132 252
jah128 2:c81f4ef63132 253 // SSI FiFo Clear
jah128 2:c81f4ef63132 254 void clearBuffer(void);
jah128 2:c81f4ef63132 255
jah128 2:c81f4ef63132 256 // Reset RF
jah128 2:c81f4ef63132 257 void rf_reset(void);
jah128 2:c81f4ef63132 258
jah128 2:c81f4ef63132 259 // Initialise RF
jah128 2:c81f4ef63132 260 void rf_init(void);
jah128 2:c81f4ef63132 261
jah128 2:c81f4ef63132 262 // RF Interrupt
jah128 2:c81f4ef63132 263 void interrupt(void);
jah128 2:c81f4ef63132 264
jah128 2:c81f4ef63132 265 // RF Set Datarate
jah128 2:c81f4ef63132 266 void setDatarate(unsigned long ulValue);
jah128 2:c81f4ef63132 267
jah128 2:c81f4ef63132 268 // RF Set Frequency
jah128 2:c81f4ef63132 269 void setFrequency(unsigned long ulValue);
jah128 2:c81f4ef63132 270
jah128 2:c81f4ef63132 271 // Enable RF Receiver FiFo fill
jah128 2:c81f4ef63132 272 void enableFifoFill(void);
jah128 2:c81f4ef63132 273
jah128 2:c81f4ef63132 274 // Disable RF Receiver FiFo fill
jah128 2:c81f4ef63132 275 void disableFifoFill(void);
jah128 2:c81f4ef63132 276
jah128 2:c81f4ef63132 277 // Handle new RF Data
jah128 2:c81f4ef63132 278 void dataAvailable(char cCount, char* cBuffer);
jah128 2:c81f4ef63132 279
jah128 2:c81f4ef63132 280 // Read status byte
jah128 2:c81f4ef63132 281 int readStatusByte();
jah128 2:c81f4ef63132 282
jah128 2:c81f4ef63132 283 // Reset timeout: stops hanging on bad receive; resets alpha 433
jah128 2:c81f4ef63132 284 void timeout();
jah128 2:c81f4ef63132 285
jah128 2:c81f4ef63132 286 private :
jah128 2:c81f4ef63132 287
jah128 2:c81f4ef63132 288 DigitalOut _fss;
jah128 2:c81f4ef63132 289 SPI _spi;
jah128 2:c81f4ef63132 290 DigitalIn _nirq_test;
jah128 2:c81f4ef63132 291 InterruptIn _nirq;
jah128 2:c81f4ef63132 292
jah128 2:c81f4ef63132 293 //Write a byte (data) to address
jah128 2:c81f4ef63132 294 void _write(int address);
jah128 2:c81f4ef63132 295
jah128 2:c81f4ef63132 296 //Read a byte (return val) from address
jah128 2:c81f4ef63132 297 int _read(int address);
jah128 2:c81f4ef63132 298
jah128 2:c81f4ef63132 299 virtual int _putc(int c);
jah128 2:c81f4ef63132 300 virtual int _getc();
jah128 2:c81f4ef63132 301
jah128 2:c81f4ef63132 302 };
jah128 2:c81f4ef63132 303
jah128 2:c81f4ef63132 304 #endif // ALPHA433_H