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AnalogInDma.cpp@0:61544337ff5e, 2018-05-03 (annotated)
- Committer:
- gunarthon
- Date:
- Thu May 03 20:39:50 2018 +0000
- Revision:
- 0:61544337ff5e
Initial commit
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| gunarthon | 0:61544337ff5e | 1 | #include "AnalogInDma.h" |
| gunarthon | 0:61544337ff5e | 2 | |
| gunarthon | 0:61544337ff5e | 3 | |
| gunarthon | 0:61544337ff5e | 4 | AnalogInDma::AnalogInDma() |
| gunarthon | 0:61544337ff5e | 5 | { |
| gunarthon | 0:61544337ff5e | 6 | } |
| gunarthon | 0:61544337ff5e | 7 | AnalogInDma::~AnalogInDma() |
| gunarthon | 0:61544337ff5e | 8 | { |
| gunarthon | 0:61544337ff5e | 9 | |
| gunarthon | 0:61544337ff5e | 10 | } |
| gunarthon | 0:61544337ff5e | 11 | bool AnalogInDma::init() |
| gunarthon | 0:61544337ff5e | 12 | { |
| gunarthon | 0:61544337ff5e | 13 | MX_DMA_Init(); |
| gunarthon | 0:61544337ff5e | 14 | if(!MX_ADC1_Init()) |
| gunarthon | 0:61544337ff5e | 15 | return false; |
| gunarthon | 0:61544337ff5e | 16 | return true; |
| gunarthon | 0:61544337ff5e | 17 | } |
| gunarthon | 0:61544337ff5e | 18 | |
| gunarthon | 0:61544337ff5e | 19 | bool AnalogInDma::start(uint32_t* pData, uint32_t Length) |
| gunarthon | 0:61544337ff5e | 20 | { |
| gunarthon | 0:61544337ff5e | 21 | if (HAL_ADC_Start_DMA(&hadc1, pData, Length) != HAL_OK) |
| gunarthon | 0:61544337ff5e | 22 | return false; |
| gunarthon | 0:61544337ff5e | 23 | return true; |
| gunarthon | 0:61544337ff5e | 24 | } |
| gunarthon | 0:61544337ff5e | 25 | |
| gunarthon | 0:61544337ff5e | 26 | /* ADC1 init function */ |
| gunarthon | 0:61544337ff5e | 27 | bool AnalogInDma::MX_ADC1_Init() |
| gunarthon | 0:61544337ff5e | 28 | { |
| gunarthon | 0:61544337ff5e | 29 | ADC_MultiModeTypeDef multimode; |
| gunarthon | 0:61544337ff5e | 30 | ADC_ChannelConfTypeDef sConfig; |
| gunarthon | 0:61544337ff5e | 31 | |
| gunarthon | 0:61544337ff5e | 32 | /**Common config |
| gunarthon | 0:61544337ff5e | 33 | */ |
| gunarthon | 0:61544337ff5e | 34 | hadc1.Instance = ADC1; |
| gunarthon | 0:61544337ff5e | 35 | hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; |
| gunarthon | 0:61544337ff5e | 36 | hadc1.Init.Resolution = ADC_RESOLUTION_12B; |
| gunarthon | 0:61544337ff5e | 37 | hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; |
| gunarthon | 0:61544337ff5e | 38 | hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; |
| gunarthon | 0:61544337ff5e | 39 | hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; |
| gunarthon | 0:61544337ff5e | 40 | hadc1.Init.LowPowerAutoWait = DISABLE; |
| gunarthon | 0:61544337ff5e | 41 | hadc1.Init.ContinuousConvMode = ENABLE; |
| gunarthon | 0:61544337ff5e | 42 | hadc1.Init.NbrOfConversion = 4; |
| gunarthon | 0:61544337ff5e | 43 | hadc1.Init.DiscontinuousConvMode = DISABLE; |
| gunarthon | 0:61544337ff5e | 44 | hadc1.Init.NbrOfDiscConversion = 1; |
| gunarthon | 0:61544337ff5e | 45 | hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; |
| gunarthon | 0:61544337ff5e | 46 | hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; |
| gunarthon | 0:61544337ff5e | 47 | hadc1.Init.DMAContinuousRequests = ENABLE; |
| gunarthon | 0:61544337ff5e | 48 | hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; |
| gunarthon | 0:61544337ff5e | 49 | hadc1.Init.OversamplingMode = DISABLE; |
| gunarthon | 0:61544337ff5e | 50 | if (HAL_ADC_Init(&hadc1) != HAL_OK) |
| gunarthon | 0:61544337ff5e | 51 | return false; |
| gunarthon | 0:61544337ff5e | 52 | |
| gunarthon | 0:61544337ff5e | 53 | /**Configure the ADC multi-mode |
| gunarthon | 0:61544337ff5e | 54 | */ |
| gunarthon | 0:61544337ff5e | 55 | multimode.Mode = ADC_MODE_INDEPENDENT; |
| gunarthon | 0:61544337ff5e | 56 | if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) |
| gunarthon | 0:61544337ff5e | 57 | return false; |
| gunarthon | 0:61544337ff5e | 58 | |
| gunarthon | 0:61544337ff5e | 59 | /**Configure Regular Channel |
| gunarthon | 0:61544337ff5e | 60 | */ |
| gunarthon | 0:61544337ff5e | 61 | sConfig.Channel = ADC_CHANNEL_5; |
| gunarthon | 0:61544337ff5e | 62 | sConfig.Rank = 1; |
| gunarthon | 0:61544337ff5e | 63 | sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5; |
| gunarthon | 0:61544337ff5e | 64 | sConfig.SingleDiff = ADC_SINGLE_ENDED; |
| gunarthon | 0:61544337ff5e | 65 | sConfig.OffsetNumber = ADC_OFFSET_NONE; |
| gunarthon | 0:61544337ff5e | 66 | sConfig.Offset = 0; |
| gunarthon | 0:61544337ff5e | 67 | if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) |
| gunarthon | 0:61544337ff5e | 68 | return false; |
| gunarthon | 0:61544337ff5e | 69 | |
| gunarthon | 0:61544337ff5e | 70 | /**Configure Regular Channel |
| gunarthon | 0:61544337ff5e | 71 | */ |
| gunarthon | 0:61544337ff5e | 72 | sConfig.Channel = ADC_CHANNEL_6; |
| gunarthon | 0:61544337ff5e | 73 | sConfig.Rank = 2; |
| gunarthon | 0:61544337ff5e | 74 | if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) |
| gunarthon | 0:61544337ff5e | 75 | return false; |
| gunarthon | 0:61544337ff5e | 76 | |
| gunarthon | 0:61544337ff5e | 77 | /**Configure Regular Channel |
| gunarthon | 0:61544337ff5e | 78 | */ |
| gunarthon | 0:61544337ff5e | 79 | sConfig.Channel = ADC_CHANNEL_9; |
| gunarthon | 0:61544337ff5e | 80 | sConfig.Rank = 3; |
| gunarthon | 0:61544337ff5e | 81 | if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) |
| gunarthon | 0:61544337ff5e | 82 | return false; |
| gunarthon | 0:61544337ff5e | 83 | /**Configure Regular Channel |
| gunarthon | 0:61544337ff5e | 84 | */ |
| gunarthon | 0:61544337ff5e | 85 | sConfig.Channel = ADC_CHANNEL_15; |
| gunarthon | 0:61544337ff5e | 86 | sConfig.Rank = 4; |
| gunarthon | 0:61544337ff5e | 87 | if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) |
| gunarthon | 0:61544337ff5e | 88 | return false; |
| gunarthon | 0:61544337ff5e | 89 | return true; |
| gunarthon | 0:61544337ff5e | 90 | } |
| gunarthon | 0:61544337ff5e | 91 | |
| gunarthon | 0:61544337ff5e | 92 | /** |
| gunarthon | 0:61544337ff5e | 93 | * Enable DMA controller clock |
| gunarthon | 0:61544337ff5e | 94 | */ |
| gunarthon | 0:61544337ff5e | 95 | void AnalogInDma::MX_DMA_Init() |
| gunarthon | 0:61544337ff5e | 96 | { |
| gunarthon | 0:61544337ff5e | 97 | /* DMA controller clock enable */ |
| gunarthon | 0:61544337ff5e | 98 | __HAL_RCC_DMA1_CLK_ENABLE(); |
| gunarthon | 0:61544337ff5e | 99 | |
| gunarthon | 0:61544337ff5e | 100 | /* DMA interrupt init */ |
| gunarthon | 0:61544337ff5e | 101 | /* DMA1_Channel1_IRQn interrupt configuration */ |
| gunarthon | 0:61544337ff5e | 102 | HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); |
| gunarthon | 0:61544337ff5e | 103 | HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); |
| gunarthon | 0:61544337ff5e | 104 | } |
