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Fork of nRF51822 by Nordic Semiconductor

nordic-sdk/components/drivers_nrf/hal/nrf51_bitfields.h@343:6675661fa600, 2015-06-19 (annotated)

Committer:
rgrover1
Date:
Fri Jun 19 15:55:34 2015 +0100
Revision:
343:6675661fa600
Parent:
103:138bdc859cc9
Child:
345:dfde56236c36
Synchronized with git rev 6d1bf116

Author: Rohit Grover

fix #1: update license headers for all sources obtained from nordic-SDK using a new template obtained from Nordic.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rgrover1 343:6675661fa600 1 /*
rgrover1 343:6675661fa600 2 * Copyright (c) Nordic Semiconductor ASA
rgrover1 343:6675661fa600 3 * All rights reserved.
rgrover1 343:6675661fa600 4 *
rgrover1 343:6675661fa600 5 * Redistribution and use in source and binary forms, with or without modification,
rgrover1 343:6675661fa600 6 * are permitted provided that the following conditions are met:
rgrover1 343:6675661fa600 7 *
rgrover1 343:6675661fa600 8 * 1. Redistributions of source code must retain the above copyright notice, this
rgrover1 343:6675661fa600 9 * list of conditions and the following disclaimer.
rgrover1 343:6675661fa600 10 *
rgrover1 343:6675661fa600 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this
rgrover1 343:6675661fa600 12 * list of conditions and the following disclaimer in the documentation and/or
rgrover1 343:6675661fa600 13 * other materials provided with the distribution.
rgrover1 343:6675661fa600 14 *
rgrover1 343:6675661fa600 15 * 3. Neither the name of Nordic Semiconductor ASA nor the names of other
rgrover1 343:6675661fa600 16 * contributors to this software may be used to endorse or promote products
rgrover1 343:6675661fa600 17 * derived from this software without specific prior written permission.
rgrover1 343:6675661fa600 18 *
rgrover1 343:6675661fa600 19 *
rgrover1 343:6675661fa600 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
rgrover1 343:6675661fa600 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
rgrover1 343:6675661fa600 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
rgrover1 343:6675661fa600 23 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
rgrover1 343:6675661fa600 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
rgrover1 343:6675661fa600 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
rgrover1 343:6675661fa600 26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
rgrover1 343:6675661fa600 27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
rgrover1 343:6675661fa600 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
rgrover1 343:6675661fa600 29 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
rgrover1 343:6675661fa600 30 *
rgrover1 343:6675661fa600 31 */
rgrover1 343:6675661fa600 32 #ifndef __NRF51_BITS_H
rgrover1 343:6675661fa600 33 #define __NRF51_BITS_H
rgrover1 343:6675661fa600 34
rgrover1 343:6675661fa600 35 /*lint ++flb "Enter library region */
rgrover1 343:6675661fa600 36
rgrover1 343:6675661fa600 37 #include <core_cm0.h>
rgrover1 343:6675661fa600 38
rgrover1 343:6675661fa600 39 /* Peripheral: AAR */
rgrover1 343:6675661fa600 40 /* Description: Accelerated Address Resolver. */
rgrover1 343:6675661fa600 41
rgrover1 343:6675661fa600 42 /* Register: AAR_INTENSET */
rgrover1 343:6675661fa600 43 /* Description: Interrupt enable set register. */
rgrover1 343:6675661fa600 44
rgrover1 343:6675661fa600 45 /* Bit 2 : Enable interrupt on NOTRESOLVED event. */
rgrover1 343:6675661fa600 46 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
rgrover1 343:6675661fa600 47 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
rgrover1 343:6675661fa600 48 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 49 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 50 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 51
rgrover1 343:6675661fa600 52 /* Bit 1 : Enable interrupt on RESOLVED event. */
rgrover1 343:6675661fa600 53 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
rgrover1 343:6675661fa600 54 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
rgrover1 343:6675661fa600 55 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 56 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 57 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 58
rgrover1 343:6675661fa600 59 /* Bit 0 : Enable interrupt on END event. */
rgrover1 343:6675661fa600 60 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
rgrover1 343:6675661fa600 61 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
rgrover1 343:6675661fa600 62 #define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 63 #define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 64 #define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 65
rgrover1 343:6675661fa600 66 /* Register: AAR_INTENCLR */
rgrover1 343:6675661fa600 67 /* Description: Interrupt enable clear register. */
rgrover1 343:6675661fa600 68
rgrover1 343:6675661fa600 69 /* Bit 2 : Disable interrupt on NOTRESOLVED event. */
rgrover1 343:6675661fa600 70 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
rgrover1 343:6675661fa600 71 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
rgrover1 343:6675661fa600 72 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 73 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 74 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 75
rgrover1 343:6675661fa600 76 /* Bit 1 : Disable interrupt on RESOLVED event. */
rgrover1 343:6675661fa600 77 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
rgrover1 343:6675661fa600 78 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
rgrover1 343:6675661fa600 79 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 80 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 81 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 82
rgrover1 343:6675661fa600 83 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
rgrover1 343:6675661fa600 84 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
rgrover1 343:6675661fa600 85 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
rgrover1 343:6675661fa600 86 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 87 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 88 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 89
rgrover1 343:6675661fa600 90 /* Register: AAR_STATUS */
rgrover1 343:6675661fa600 91 /* Description: Resolution status. */
rgrover1 343:6675661fa600 92
rgrover1 343:6675661fa600 93 /* Bits 3..0 : The IRK used last time an address was resolved. */
rgrover1 343:6675661fa600 94 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
rgrover1 343:6675661fa600 95 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
rgrover1 343:6675661fa600 96
rgrover1 343:6675661fa600 97 /* Register: AAR_ENABLE */
rgrover1 343:6675661fa600 98 /* Description: Enable AAR. */
rgrover1 343:6675661fa600 99
rgrover1 343:6675661fa600 100 /* Bits 1..0 : Enable AAR. */
rgrover1 343:6675661fa600 101 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
rgrover1 343:6675661fa600 102 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
rgrover1 343:6675661fa600 103 #define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */
rgrover1 343:6675661fa600 104 #define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */
rgrover1 343:6675661fa600 105
rgrover1 343:6675661fa600 106 /* Register: AAR_NIRK */
rgrover1 343:6675661fa600 107 /* Description: Number of Identity root Keys in the IRK data structure. */
rgrover1 343:6675661fa600 108
rgrover1 343:6675661fa600 109 /* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
rgrover1 343:6675661fa600 110 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
rgrover1 343:6675661fa600 111 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
rgrover1 343:6675661fa600 112
rgrover1 343:6675661fa600 113 /* Register: AAR_POWER */
rgrover1 343:6675661fa600 114 /* Description: Peripheral power control. */
rgrover1 343:6675661fa600 115
rgrover1 343:6675661fa600 116 /* Bit 0 : Peripheral power control. */
rgrover1 343:6675661fa600 117 #define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
rgrover1 343:6675661fa600 118 #define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
rgrover1 343:6675661fa600 119 #define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
rgrover1 343:6675661fa600 120 #define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
rgrover1 343:6675661fa600 121
rgrover1 343:6675661fa600 122
rgrover1 343:6675661fa600 123 /* Peripheral: ADC */
rgrover1 343:6675661fa600 124 /* Description: Analog to digital converter. */
rgrover1 343:6675661fa600 125
rgrover1 343:6675661fa600 126 /* Register: ADC_INTENSET */
rgrover1 343:6675661fa600 127 /* Description: Interrupt enable set register. */
rgrover1 343:6675661fa600 128
rgrover1 343:6675661fa600 129 /* Bit 0 : Enable interrupt on END event. */
rgrover1 343:6675661fa600 130 #define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */
rgrover1 343:6675661fa600 131 #define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
rgrover1 343:6675661fa600 132 #define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 133 #define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 134 #define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 135
rgrover1 343:6675661fa600 136 /* Register: ADC_INTENCLR */
rgrover1 343:6675661fa600 137 /* Description: Interrupt enable clear register. */
rgrover1 343:6675661fa600 138
rgrover1 343:6675661fa600 139 /* Bit 0 : Disable interrupt on END event. */
rgrover1 343:6675661fa600 140 #define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
rgrover1 343:6675661fa600 141 #define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
rgrover1 343:6675661fa600 142 #define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 143 #define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 144 #define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 145
rgrover1 343:6675661fa600 146 /* Register: ADC_BUSY */
rgrover1 343:6675661fa600 147 /* Description: ADC busy register. */
rgrover1 343:6675661fa600 148
rgrover1 343:6675661fa600 149 /* Bit 0 : ADC busy register. */
rgrover1 343:6675661fa600 150 #define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */
rgrover1 343:6675661fa600 151 #define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */
rgrover1 343:6675661fa600 152 #define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */
rgrover1 343:6675661fa600 153 #define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */
rgrover1 343:6675661fa600 154
rgrover1 343:6675661fa600 155 /* Register: ADC_ENABLE */
rgrover1 343:6675661fa600 156 /* Description: ADC enable. */
rgrover1 343:6675661fa600 157
rgrover1 343:6675661fa600 158 /* Bits 1..0 : ADC enable. */
rgrover1 343:6675661fa600 159 #define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
rgrover1 343:6675661fa600 160 #define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
rgrover1 343:6675661fa600 161 #define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */
rgrover1 343:6675661fa600 162 #define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */
rgrover1 343:6675661fa600 163
rgrover1 343:6675661fa600 164 /* Register: ADC_CONFIG */
rgrover1 343:6675661fa600 165 /* Description: ADC configuration register. */
rgrover1 343:6675661fa600 166
rgrover1 343:6675661fa600 167 /* Bits 17..16 : ADC external reference pin selection. */
rgrover1 343:6675661fa600 168 #define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */
rgrover1 343:6675661fa600 169 #define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
rgrover1 343:6675661fa600 170 #define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */
rgrover1 343:6675661fa600 171 #define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */
rgrover1 343:6675661fa600 172 #define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */
rgrover1 343:6675661fa600 173
rgrover1 343:6675661fa600 174 /* Bits 15..8 : ADC analog pin selection. */
rgrover1 343:6675661fa600 175 #define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
rgrover1 343:6675661fa600 176 #define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
rgrover1 343:6675661fa600 177 #define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */
rgrover1 343:6675661fa600 178 #define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */
rgrover1 343:6675661fa600 179 #define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */
rgrover1 343:6675661fa600 180 #define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */
rgrover1 343:6675661fa600 181 #define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */
rgrover1 343:6675661fa600 182 #define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */
rgrover1 343:6675661fa600 183 #define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */
rgrover1 343:6675661fa600 184 #define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */
rgrover1 343:6675661fa600 185 #define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */
rgrover1 343:6675661fa600 186
rgrover1 343:6675661fa600 187 /* Bits 6..5 : ADC reference selection. */
rgrover1 343:6675661fa600 188 #define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */
rgrover1 343:6675661fa600 189 #define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
rgrover1 343:6675661fa600 190 #define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */
rgrover1 343:6675661fa600 191 #define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */
rgrover1 343:6675661fa600 192 #define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */
rgrover1 343:6675661fa600 193 #define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */
rgrover1 343:6675661fa600 194
rgrover1 343:6675661fa600 195 /* Bits 4..2 : ADC input selection. */
rgrover1 343:6675661fa600 196 #define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */
rgrover1 343:6675661fa600 197 #define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */
rgrover1 343:6675661fa600 198 #define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */
rgrover1 343:6675661fa600 199 #define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */
rgrover1 343:6675661fa600 200 #define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */
rgrover1 343:6675661fa600 201 #define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */
rgrover1 343:6675661fa600 202 #define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */
rgrover1 343:6675661fa600 203
rgrover1 343:6675661fa600 204 /* Bits 1..0 : ADC resolution. */
rgrover1 343:6675661fa600 205 #define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */
rgrover1 343:6675661fa600 206 #define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */
rgrover1 343:6675661fa600 207 #define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */
rgrover1 343:6675661fa600 208 #define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */
rgrover1 343:6675661fa600 209 #define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */
rgrover1 343:6675661fa600 210
rgrover1 343:6675661fa600 211 /* Register: ADC_RESULT */
rgrover1 343:6675661fa600 212 /* Description: Result of ADC conversion. */
rgrover1 343:6675661fa600 213
rgrover1 343:6675661fa600 214 /* Bits 9..0 : Result of ADC conversion. */
rgrover1 343:6675661fa600 215 #define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
rgrover1 343:6675661fa600 216 #define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
rgrover1 343:6675661fa600 217
rgrover1 343:6675661fa600 218 /* Register: ADC_POWER */
rgrover1 343:6675661fa600 219 /* Description: Peripheral power control. */
rgrover1 343:6675661fa600 220
rgrover1 343:6675661fa600 221 /* Bit 0 : Peripheral power control. */
rgrover1 343:6675661fa600 222 #define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
rgrover1 343:6675661fa600 223 #define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
rgrover1 343:6675661fa600 224 #define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
rgrover1 343:6675661fa600 225 #define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
rgrover1 343:6675661fa600 226
rgrover1 343:6675661fa600 227
rgrover1 343:6675661fa600 228 /* Peripheral: AMLI */
rgrover1 343:6675661fa600 229 /* Description: AHB Multi-Layer Interface. */
rgrover1 343:6675661fa600 230
rgrover1 343:6675661fa600 231 /* Register: AMLI_RAMPRI_CPU0 */
rgrover1 343:6675661fa600 232 /* Description: Configurable priority configuration register for CPU0. */
rgrover1 343:6675661fa600 233
rgrover1 343:6675661fa600 234 /* Bits 31..28 : Configuration field for RAM block 7. */
rgrover1 343:6675661fa600 235 #define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
rgrover1 343:6675661fa600 236 #define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */
rgrover1 343:6675661fa600 237 #define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 238 #define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 239 #define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 240 #define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 241 #define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 242 #define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 243 #define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 244 #define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 245
rgrover1 343:6675661fa600 246 /* Bits 27..24 : Configuration field for RAM block 6. */
rgrover1 343:6675661fa600 247 #define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
rgrover1 343:6675661fa600 248 #define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */
rgrover1 343:6675661fa600 249 #define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 250 #define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 251 #define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 252 #define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 253 #define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 254 #define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 255 #define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 256 #define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 257
rgrover1 343:6675661fa600 258 /* Bits 23..20 : Configuration field for RAM block 5. */
rgrover1 343:6675661fa600 259 #define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
rgrover1 343:6675661fa600 260 #define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */
rgrover1 343:6675661fa600 261 #define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 262 #define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 263 #define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 264 #define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 265 #define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 266 #define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 267 #define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 268 #define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 269
rgrover1 343:6675661fa600 270 /* Bits 19..16 : Configuration field for RAM block 4. */
rgrover1 343:6675661fa600 271 #define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
rgrover1 343:6675661fa600 272 #define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */
rgrover1 343:6675661fa600 273 #define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 274 #define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 275 #define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 276 #define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 277 #define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 278 #define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 279 #define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 280 #define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 281
rgrover1 343:6675661fa600 282 /* Bits 15..12 : Configuration field for RAM block 3. */
rgrover1 343:6675661fa600 283 #define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
rgrover1 343:6675661fa600 284 #define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
rgrover1 343:6675661fa600 285 #define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 286 #define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 287 #define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 288 #define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 289 #define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 290 #define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 291 #define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 292 #define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 293
rgrover1 343:6675661fa600 294 /* Bits 11..8 : Configuration field for RAM block 2. */
rgrover1 343:6675661fa600 295 #define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
rgrover1 343:6675661fa600 296 #define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
rgrover1 343:6675661fa600 297 #define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 298 #define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 299 #define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 300 #define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 301 #define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 302 #define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 303 #define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 304 #define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 305
rgrover1 343:6675661fa600 306 /* Bits 7..4 : Configuration field for RAM block 1. */
rgrover1 343:6675661fa600 307 #define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
rgrover1 343:6675661fa600 308 #define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
rgrover1 343:6675661fa600 309 #define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 310 #define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 311 #define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 312 #define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 313 #define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 314 #define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 315 #define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 316 #define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 317
rgrover1 343:6675661fa600 318 /* Bits 3..0 : Configuration field for RAM block 0. */
rgrover1 343:6675661fa600 319 #define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
rgrover1 343:6675661fa600 320 #define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
rgrover1 343:6675661fa600 321 #define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 322 #define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 323 #define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 324 #define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 325 #define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 326 #define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 327 #define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 328 #define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 329
rgrover1 343:6675661fa600 330 /* Register: AMLI_RAMPRI_SPIS1 */
rgrover1 343:6675661fa600 331 /* Description: Configurable priority configuration register for SPIS1. */
rgrover1 343:6675661fa600 332
rgrover1 343:6675661fa600 333 /* Bits 31..28 : Configuration field for RAM block 7. */
rgrover1 343:6675661fa600 334 #define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
rgrover1 343:6675661fa600 335 #define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */
rgrover1 343:6675661fa600 336 #define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 337 #define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 338 #define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 339 #define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 340 #define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 341 #define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 342 #define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 343 #define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 344
rgrover1 343:6675661fa600 345 /* Bits 27..24 : Configuration field for RAM block 6. */
rgrover1 343:6675661fa600 346 #define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
rgrover1 343:6675661fa600 347 #define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */
rgrover1 343:6675661fa600 348 #define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 349 #define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 350 #define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 351 #define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 352 #define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 353 #define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 354 #define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 355 #define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 356
rgrover1 343:6675661fa600 357 /* Bits 23..20 : Configuration field for RAM block 5. */
rgrover1 343:6675661fa600 358 #define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
rgrover1 343:6675661fa600 359 #define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */
rgrover1 343:6675661fa600 360 #define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 361 #define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 362 #define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 363 #define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 364 #define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 365 #define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 366 #define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 367 #define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 368
rgrover1 343:6675661fa600 369 /* Bits 19..16 : Configuration field for RAM block 4. */
rgrover1 343:6675661fa600 370 #define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
rgrover1 343:6675661fa600 371 #define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */
rgrover1 343:6675661fa600 372 #define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 373 #define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 374 #define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 375 #define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 376 #define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 377 #define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 378 #define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 379 #define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 380
rgrover1 343:6675661fa600 381 /* Bits 15..12 : Configuration field for RAM block 3. */
rgrover1 343:6675661fa600 382 #define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
rgrover1 343:6675661fa600 383 #define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */
rgrover1 343:6675661fa600 384 #define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 385 #define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 386 #define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 387 #define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 388 #define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 389 #define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 390 #define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 391 #define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 392
rgrover1 343:6675661fa600 393 /* Bits 11..8 : Configuration field for RAM block 2. */
rgrover1 343:6675661fa600 394 #define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
rgrover1 343:6675661fa600 395 #define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */
rgrover1 343:6675661fa600 396 #define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 397 #define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 398 #define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 399 #define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 400 #define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 401 #define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 402 #define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 403 #define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 404
rgrover1 343:6675661fa600 405 /* Bits 7..4 : Configuration field for RAM block 1. */
rgrover1 343:6675661fa600 406 #define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
rgrover1 343:6675661fa600 407 #define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */
rgrover1 343:6675661fa600 408 #define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 409 #define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 410 #define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 411 #define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 412 #define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 413 #define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 414 #define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 415 #define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 416
rgrover1 343:6675661fa600 417 /* Bits 3..0 : Configuration field for RAM block 0. */
rgrover1 343:6675661fa600 418 #define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
rgrover1 343:6675661fa600 419 #define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */
rgrover1 343:6675661fa600 420 #define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 421 #define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 422 #define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 423 #define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 424 #define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 425 #define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 426 #define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 427 #define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 428
rgrover1 343:6675661fa600 429 /* Register: AMLI_RAMPRI_RADIO */
rgrover1 343:6675661fa600 430 /* Description: Configurable priority configuration register for RADIO. */
rgrover1 343:6675661fa600 431
rgrover1 343:6675661fa600 432 /* Bits 31..28 : Configuration field for RAM block 7. */
rgrover1 343:6675661fa600 433 #define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
rgrover1 343:6675661fa600 434 #define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */
rgrover1 343:6675661fa600 435 #define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 436 #define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 437 #define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 438 #define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 439 #define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 440 #define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 441 #define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 442 #define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 443
rgrover1 343:6675661fa600 444 /* Bits 27..24 : Configuration field for RAM block 6. */
rgrover1 343:6675661fa600 445 #define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
rgrover1 343:6675661fa600 446 #define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */
rgrover1 343:6675661fa600 447 #define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 448 #define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 449 #define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 450 #define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 451 #define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 452 #define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 453 #define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 454 #define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 455
rgrover1 343:6675661fa600 456 /* Bits 23..20 : Configuration field for RAM block 5. */
rgrover1 343:6675661fa600 457 #define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
rgrover1 343:6675661fa600 458 #define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */
rgrover1 343:6675661fa600 459 #define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 460 #define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 461 #define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 462 #define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 463 #define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 464 #define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 465 #define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 466 #define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 467
rgrover1 343:6675661fa600 468 /* Bits 19..16 : Configuration field for RAM block 4. */
rgrover1 343:6675661fa600 469 #define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
rgrover1 343:6675661fa600 470 #define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */
rgrover1 343:6675661fa600 471 #define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 472 #define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 473 #define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 474 #define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 475 #define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 476 #define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 477 #define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 478 #define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 479
rgrover1 343:6675661fa600 480 /* Bits 15..12 : Configuration field for RAM block 3. */
rgrover1 343:6675661fa600 481 #define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
rgrover1 343:6675661fa600 482 #define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */
rgrover1 343:6675661fa600 483 #define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 484 #define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 485 #define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 486 #define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 487 #define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 488 #define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 489 #define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 490 #define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 491
rgrover1 343:6675661fa600 492 /* Bits 11..8 : Configuration field for RAM block 2. */
rgrover1 343:6675661fa600 493 #define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
rgrover1 343:6675661fa600 494 #define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */
rgrover1 343:6675661fa600 495 #define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 496 #define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 497 #define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 498 #define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 499 #define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 500 #define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 501 #define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 502 #define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 503
rgrover1 343:6675661fa600 504 /* Bits 7..4 : Configuration field for RAM block 1. */
rgrover1 343:6675661fa600 505 #define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
rgrover1 343:6675661fa600 506 #define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */
rgrover1 343:6675661fa600 507 #define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 508 #define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 509 #define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 510 #define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 511 #define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 512 #define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 513 #define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 514 #define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 515
rgrover1 343:6675661fa600 516 /* Bits 3..0 : Configuration field for RAM block 0. */
rgrover1 343:6675661fa600 517 #define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
rgrover1 343:6675661fa600 518 #define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */
rgrover1 343:6675661fa600 519 #define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 520 #define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 521 #define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 522 #define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 523 #define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 524 #define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 525 #define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 526 #define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 527
rgrover1 343:6675661fa600 528 /* Register: AMLI_RAMPRI_ECB */
rgrover1 343:6675661fa600 529 /* Description: Configurable priority configuration register for ECB. */
rgrover1 343:6675661fa600 530
rgrover1 343:6675661fa600 531 /* Bits 31..28 : Configuration field for RAM block 7. */
rgrover1 343:6675661fa600 532 #define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
rgrover1 343:6675661fa600 533 #define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */
rgrover1 343:6675661fa600 534 #define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 535 #define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 536 #define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 537 #define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 538 #define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 539 #define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 540 #define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 541 #define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 542
rgrover1 343:6675661fa600 543 /* Bits 27..24 : Configuration field for RAM block 6. */
rgrover1 343:6675661fa600 544 #define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
rgrover1 343:6675661fa600 545 #define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */
rgrover1 343:6675661fa600 546 #define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 547 #define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 548 #define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 549 #define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 550 #define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 551 #define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 552 #define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 553 #define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 554
rgrover1 343:6675661fa600 555 /* Bits 23..20 : Configuration field for RAM block 5. */
rgrover1 343:6675661fa600 556 #define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
rgrover1 343:6675661fa600 557 #define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */
rgrover1 343:6675661fa600 558 #define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 559 #define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 560 #define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 561 #define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 562 #define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 563 #define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 564 #define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 565 #define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 566
rgrover1 343:6675661fa600 567 /* Bits 19..16 : Configuration field for RAM block 4. */
rgrover1 343:6675661fa600 568 #define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
rgrover1 343:6675661fa600 569 #define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */
rgrover1 343:6675661fa600 570 #define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 571 #define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 572 #define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 573 #define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 574 #define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 575 #define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 576 #define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 577 #define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 578
rgrover1 343:6675661fa600 579 /* Bits 15..12 : Configuration field for RAM block 3. */
rgrover1 343:6675661fa600 580 #define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
rgrover1 343:6675661fa600 581 #define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */
rgrover1 343:6675661fa600 582 #define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 583 #define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 584 #define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 585 #define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 586 #define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 587 #define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 588 #define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 589 #define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 590
rgrover1 343:6675661fa600 591 /* Bits 11..8 : Configuration field for RAM block 2. */
rgrover1 343:6675661fa600 592 #define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
rgrover1 343:6675661fa600 593 #define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */
rgrover1 343:6675661fa600 594 #define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 595 #define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 596 #define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 597 #define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 598 #define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 599 #define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 600 #define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 601 #define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 602
rgrover1 343:6675661fa600 603 /* Bits 7..4 : Configuration field for RAM block 1. */
rgrover1 343:6675661fa600 604 #define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
rgrover1 343:6675661fa600 605 #define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */
rgrover1 343:6675661fa600 606 #define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 607 #define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 608 #define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 609 #define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 610 #define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 611 #define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 612 #define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 613 #define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 614
rgrover1 343:6675661fa600 615 /* Bits 3..0 : Configuration field for RAM block 0. */
rgrover1 343:6675661fa600 616 #define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
rgrover1 343:6675661fa600 617 #define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */
rgrover1 343:6675661fa600 618 #define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 619 #define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 620 #define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 621 #define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 622 #define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 623 #define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 624 #define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 625 #define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 626
rgrover1 343:6675661fa600 627 /* Register: AMLI_RAMPRI_CCM */
rgrover1 343:6675661fa600 628 /* Description: Configurable priority configuration register for CCM. */
rgrover1 343:6675661fa600 629
rgrover1 343:6675661fa600 630 /* Bits 31..28 : Configuration field for RAM block 7. */
rgrover1 343:6675661fa600 631 #define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
rgrover1 343:6675661fa600 632 #define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
rgrover1 343:6675661fa600 633 #define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 634 #define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 635 #define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 636 #define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 637 #define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 638 #define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 639 #define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 640 #define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 641
rgrover1 343:6675661fa600 642 /* Bits 27..24 : Configuration field for RAM block 6. */
rgrover1 343:6675661fa600 643 #define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
rgrover1 343:6675661fa600 644 #define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
rgrover1 343:6675661fa600 645 #define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 646 #define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 647 #define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 648 #define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 649 #define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 650 #define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 651 #define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 652 #define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 653
rgrover1 343:6675661fa600 654 /* Bits 23..20 : Configuration field for RAM block 5. */
rgrover1 343:6675661fa600 655 #define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
rgrover1 343:6675661fa600 656 #define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
rgrover1 343:6675661fa600 657 #define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 658 #define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 659 #define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 660 #define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 661 #define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 662 #define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 663 #define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 664 #define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 665
rgrover1 343:6675661fa600 666 /* Bits 19..16 : Configuration field for RAM block 4. */
rgrover1 343:6675661fa600 667 #define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
rgrover1 343:6675661fa600 668 #define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
rgrover1 343:6675661fa600 669 #define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 670 #define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 671 #define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 672 #define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 673 #define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 674 #define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 675 #define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 676 #define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 677
rgrover1 343:6675661fa600 678 /* Bits 15..12 : Configuration field for RAM block 3. */
rgrover1 343:6675661fa600 679 #define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
rgrover1 343:6675661fa600 680 #define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
rgrover1 343:6675661fa600 681 #define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 682 #define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 683 #define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 684 #define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 685 #define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 686 #define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 687 #define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 688 #define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 689
rgrover1 343:6675661fa600 690 /* Bits 11..8 : Configuration field for RAM block 2. */
rgrover1 343:6675661fa600 691 #define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
rgrover1 343:6675661fa600 692 #define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
rgrover1 343:6675661fa600 693 #define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 694 #define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 695 #define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 696 #define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 697 #define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 698 #define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 699 #define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 700 #define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 701
rgrover1 343:6675661fa600 702 /* Bits 7..4 : Configuration field for RAM block 1. */
rgrover1 343:6675661fa600 703 #define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
rgrover1 343:6675661fa600 704 #define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
rgrover1 343:6675661fa600 705 #define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 706 #define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 707 #define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 708 #define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 709 #define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 710 #define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 711 #define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 712 #define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 713
rgrover1 343:6675661fa600 714 /* Bits 3..0 : Configuration field for RAM block 0. */
rgrover1 343:6675661fa600 715 #define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
rgrover1 343:6675661fa600 716 #define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
rgrover1 343:6675661fa600 717 #define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 718 #define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 719 #define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 720 #define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 721 #define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 722 #define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 723 #define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 724 #define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 725
rgrover1 343:6675661fa600 726 /* Register: AMLI_RAMPRI_AAR */
rgrover1 343:6675661fa600 727 /* Description: Configurable priority configuration register for AAR. */
rgrover1 343:6675661fa600 728
rgrover1 343:6675661fa600 729 /* Bits 31..28 : Configuration field for RAM block 7. */
rgrover1 343:6675661fa600 730 #define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
rgrover1 343:6675661fa600 731 #define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */
rgrover1 343:6675661fa600 732 #define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 733 #define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 734 #define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 735 #define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 736 #define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 737 #define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 738 #define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 739 #define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 740
rgrover1 343:6675661fa600 741 /* Bits 27..24 : Configuration field for RAM block 6. */
rgrover1 343:6675661fa600 742 #define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
rgrover1 343:6675661fa600 743 #define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */
rgrover1 343:6675661fa600 744 #define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 745 #define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 746 #define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 747 #define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 748 #define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 749 #define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 750 #define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 751 #define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 752
rgrover1 343:6675661fa600 753 /* Bits 23..20 : Configuration field for RAM block 5. */
rgrover1 343:6675661fa600 754 #define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
rgrover1 343:6675661fa600 755 #define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */
rgrover1 343:6675661fa600 756 #define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 757 #define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 758 #define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 759 #define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 760 #define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 761 #define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 762 #define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 763 #define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 764
rgrover1 343:6675661fa600 765 /* Bits 19..16 : Configuration field for RAM block 4. */
rgrover1 343:6675661fa600 766 #define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
rgrover1 343:6675661fa600 767 #define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */
rgrover1 343:6675661fa600 768 #define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 769 #define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 770 #define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 771 #define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 772 #define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 773 #define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 774 #define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 775 #define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 776
rgrover1 343:6675661fa600 777 /* Bits 15..12 : Configuration field for RAM block 3. */
rgrover1 343:6675661fa600 778 #define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
rgrover1 343:6675661fa600 779 #define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */
rgrover1 343:6675661fa600 780 #define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 781 #define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 782 #define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 783 #define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 784 #define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 785 #define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 786 #define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 787 #define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 788
rgrover1 343:6675661fa600 789 /* Bits 11..8 : Configuration field for RAM block 2. */
rgrover1 343:6675661fa600 790 #define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
rgrover1 343:6675661fa600 791 #define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */
rgrover1 343:6675661fa600 792 #define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 793 #define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 794 #define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 795 #define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 796 #define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 797 #define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 798 #define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 799 #define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 800
rgrover1 343:6675661fa600 801 /* Bits 7..4 : Configuration field for RAM block 1. */
rgrover1 343:6675661fa600 802 #define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
rgrover1 343:6675661fa600 803 #define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */
rgrover1 343:6675661fa600 804 #define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 805 #define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 806 #define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 807 #define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 808 #define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 809 #define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 810 #define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 811 #define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 812
rgrover1 343:6675661fa600 813 /* Bits 3..0 : Configuration field for RAM block 0. */
rgrover1 343:6675661fa600 814 #define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
rgrover1 343:6675661fa600 815 #define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */
rgrover1 343:6675661fa600 816 #define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
rgrover1 343:6675661fa600 817 #define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
rgrover1 343:6675661fa600 818 #define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
rgrover1 343:6675661fa600 819 #define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
rgrover1 343:6675661fa600 820 #define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
rgrover1 343:6675661fa600 821 #define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
rgrover1 343:6675661fa600 822 #define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
rgrover1 343:6675661fa600 823 #define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
rgrover1 343:6675661fa600 824
rgrover1 343:6675661fa600 825 /* Peripheral: CCM */
rgrover1 343:6675661fa600 826 /* Description: AES CCM Mode Encryption. */
rgrover1 343:6675661fa600 827
rgrover1 343:6675661fa600 828 /* Register: CCM_SHORTS */
rgrover1 343:6675661fa600 829 /* Description: Shortcuts for the CCM. */
rgrover1 343:6675661fa600 830
rgrover1 343:6675661fa600 831 /* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
rgrover1 343:6675661fa600 832 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
rgrover1 343:6675661fa600 833 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
rgrover1 343:6675661fa600 834 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 835 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 836
rgrover1 343:6675661fa600 837 /* Register: CCM_INTENSET */
rgrover1 343:6675661fa600 838 /* Description: Interrupt enable set register. */
rgrover1 343:6675661fa600 839
rgrover1 343:6675661fa600 840 /* Bit 2 : Enable interrupt on ERROR event. */
rgrover1 343:6675661fa600 841 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
rgrover1 343:6675661fa600 842 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
rgrover1 343:6675661fa600 843 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 844 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 845 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 846
rgrover1 343:6675661fa600 847 /* Bit 1 : Enable interrupt on ENDCRYPT event. */
rgrover1 343:6675661fa600 848 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
rgrover1 343:6675661fa600 849 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
rgrover1 343:6675661fa600 850 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 851 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 852 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 853
rgrover1 343:6675661fa600 854 /* Bit 0 : Enable interrupt on ENDKSGEN event. */
rgrover1 343:6675661fa600 855 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
rgrover1 343:6675661fa600 856 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
rgrover1 343:6675661fa600 857 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 858 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 859 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 860
rgrover1 343:6675661fa600 861 /* Register: CCM_INTENCLR */
rgrover1 343:6675661fa600 862 /* Description: Interrupt enable clear register. */
rgrover1 343:6675661fa600 863
rgrover1 343:6675661fa600 864 /* Bit 2 : Disable interrupt on ERROR event. */
rgrover1 343:6675661fa600 865 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
rgrover1 343:6675661fa600 866 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
rgrover1 343:6675661fa600 867 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 868 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 869 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 870
rgrover1 343:6675661fa600 871 /* Bit 1 : Disable interrupt on ENDCRYPT event. */
rgrover1 343:6675661fa600 872 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
rgrover1 343:6675661fa600 873 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
rgrover1 343:6675661fa600 874 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 875 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 876 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 877
rgrover1 343:6675661fa600 878 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
rgrover1 343:6675661fa600 879 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
rgrover1 343:6675661fa600 880 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
rgrover1 343:6675661fa600 881 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 882 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 883 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 884
rgrover1 343:6675661fa600 885 /* Register: CCM_MICSTATUS */
rgrover1 343:6675661fa600 886 /* Description: CCM RX MIC check result. */
rgrover1 343:6675661fa600 887
rgrover1 343:6675661fa600 888 /* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
rgrover1 343:6675661fa600 889 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
rgrover1 343:6675661fa600 890 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
rgrover1 343:6675661fa600 891 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */
rgrover1 343:6675661fa600 892 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */
rgrover1 343:6675661fa600 893
rgrover1 343:6675661fa600 894 /* Register: CCM_ENABLE */
rgrover1 343:6675661fa600 895 /* Description: CCM enable. */
rgrover1 343:6675661fa600 896
rgrover1 343:6675661fa600 897 /* Bits 1..0 : CCM enable. */
rgrover1 343:6675661fa600 898 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
rgrover1 343:6675661fa600 899 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
rgrover1 343:6675661fa600 900 #define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */
rgrover1 343:6675661fa600 901 #define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */
rgrover1 343:6675661fa600 902
rgrover1 343:6675661fa600 903 /* Register: CCM_MODE */
rgrover1 343:6675661fa600 904 /* Description: Operation mode. */
rgrover1 343:6675661fa600 905
rgrover1 343:6675661fa600 906 /* Bit 0 : CCM mode operation. */
rgrover1 343:6675661fa600 907 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
rgrover1 343:6675661fa600 908 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
rgrover1 343:6675661fa600 909 #define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */
rgrover1 343:6675661fa600 910 #define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */
rgrover1 343:6675661fa600 911
rgrover1 343:6675661fa600 912 /* Register: CCM_POWER */
rgrover1 343:6675661fa600 913 /* Description: Peripheral power control. */
rgrover1 343:6675661fa600 914
rgrover1 343:6675661fa600 915 /* Bit 0 : Peripheral power control. */
rgrover1 343:6675661fa600 916 #define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
rgrover1 343:6675661fa600 917 #define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
rgrover1 343:6675661fa600 918 #define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
rgrover1 343:6675661fa600 919 #define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
rgrover1 343:6675661fa600 920
rgrover1 343:6675661fa600 921
rgrover1 343:6675661fa600 922 /* Peripheral: CLOCK */
rgrover1 343:6675661fa600 923 /* Description: Clock control. */
rgrover1 343:6675661fa600 924
rgrover1 343:6675661fa600 925 /* Register: CLOCK_INTENSET */
rgrover1 343:6675661fa600 926 /* Description: Interrupt enable set register. */
rgrover1 343:6675661fa600 927
rgrover1 343:6675661fa600 928 /* Bit 4 : Enable interrupt on CTTO event. */
rgrover1 343:6675661fa600 929 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
rgrover1 343:6675661fa600 930 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
rgrover1 343:6675661fa600 931 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 932 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 933 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 934
rgrover1 343:6675661fa600 935 /* Bit 3 : Enable interrupt on DONE event. */
rgrover1 343:6675661fa600 936 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
rgrover1 343:6675661fa600 937 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
rgrover1 343:6675661fa600 938 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 939 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 940 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 941
rgrover1 343:6675661fa600 942 /* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
rgrover1 343:6675661fa600 943 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
rgrover1 343:6675661fa600 944 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
rgrover1 343:6675661fa600 945 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 946 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 947 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 948
rgrover1 343:6675661fa600 949 /* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
rgrover1 343:6675661fa600 950 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
rgrover1 343:6675661fa600 951 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
rgrover1 343:6675661fa600 952 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 953 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 954 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 955
rgrover1 343:6675661fa600 956 /* Register: CLOCK_INTENCLR */
rgrover1 343:6675661fa600 957 /* Description: Interrupt enable clear register. */
rgrover1 343:6675661fa600 958
rgrover1 343:6675661fa600 959 /* Bit 4 : Disable interrupt on CTTO event. */
rgrover1 343:6675661fa600 960 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
rgrover1 343:6675661fa600 961 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
rgrover1 343:6675661fa600 962 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 963 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 964 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 965
rgrover1 343:6675661fa600 966 /* Bit 3 : Disable interrupt on DONE event. */
rgrover1 343:6675661fa600 967 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
rgrover1 343:6675661fa600 968 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
rgrover1 343:6675661fa600 969 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 970 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 971 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 972
rgrover1 343:6675661fa600 973 /* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
rgrover1 343:6675661fa600 974 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
rgrover1 343:6675661fa600 975 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
rgrover1 343:6675661fa600 976 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 977 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 978 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 979
rgrover1 343:6675661fa600 980 /* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
rgrover1 343:6675661fa600 981 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
rgrover1 343:6675661fa600 982 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
rgrover1 343:6675661fa600 983 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 984 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 985 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 986
rgrover1 343:6675661fa600 987 /* Register: CLOCK_HFCLKRUN */
rgrover1 343:6675661fa600 988 /* Description: Task HFCLKSTART trigger status. */
rgrover1 343:6675661fa600 989
rgrover1 343:6675661fa600 990 /* Bit 0 : Task HFCLKSTART trigger status. */
rgrover1 343:6675661fa600 991 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
rgrover1 343:6675661fa600 992 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
rgrover1 343:6675661fa600 993 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */
rgrover1 343:6675661fa600 994 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */
rgrover1 343:6675661fa600 995
rgrover1 343:6675661fa600 996 /* Register: CLOCK_HFCLKSTAT */
rgrover1 343:6675661fa600 997 /* Description: High frequency clock status. */
rgrover1 343:6675661fa600 998
rgrover1 343:6675661fa600 999 /* Bit 16 : State for the HFCLK. */
rgrover1 343:6675661fa600 1000 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
rgrover1 343:6675661fa600 1001 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
rgrover1 343:6675661fa600 1002 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */
rgrover1 343:6675661fa600 1003 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */
rgrover1 343:6675661fa600 1004
rgrover1 343:6675661fa600 1005 /* Bit 0 : Active clock source for the HF clock. */
rgrover1 343:6675661fa600 1006 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
rgrover1 343:6675661fa600 1007 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
rgrover1 343:6675661fa600 1008 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */
rgrover1 343:6675661fa600 1009 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */
rgrover1 343:6675661fa600 1010
rgrover1 343:6675661fa600 1011 /* Register: CLOCK_LFCLKRUN */
rgrover1 343:6675661fa600 1012 /* Description: Task LFCLKSTART triggered status. */
rgrover1 343:6675661fa600 1013
rgrover1 343:6675661fa600 1014 /* Bit 0 : Task LFCLKSTART triggered status. */
rgrover1 343:6675661fa600 1015 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
rgrover1 343:6675661fa600 1016 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
rgrover1 343:6675661fa600 1017 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */
rgrover1 343:6675661fa600 1018 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */
rgrover1 343:6675661fa600 1019
rgrover1 343:6675661fa600 1020 /* Register: CLOCK_LFCLKSTAT */
rgrover1 343:6675661fa600 1021 /* Description: Low frequency clock status. */
rgrover1 343:6675661fa600 1022
rgrover1 343:6675661fa600 1023 /* Bit 16 : State for the LF clock. */
rgrover1 343:6675661fa600 1024 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
rgrover1 343:6675661fa600 1025 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
rgrover1 343:6675661fa600 1026 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */
rgrover1 343:6675661fa600 1027 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */
rgrover1 343:6675661fa600 1028
rgrover1 343:6675661fa600 1029 /* Bits 1..0 : Active clock source for the LF clock. */
rgrover1 343:6675661fa600 1030 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
rgrover1 343:6675661fa600 1031 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
rgrover1 343:6675661fa600 1032 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */
rgrover1 343:6675661fa600 1033 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */
rgrover1 343:6675661fa600 1034 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */
rgrover1 343:6675661fa600 1035
rgrover1 343:6675661fa600 1036 /* Register: CLOCK_LFCLKSRCCOPY */
rgrover1 343:6675661fa600 1037 /* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
rgrover1 343:6675661fa600 1038
rgrover1 343:6675661fa600 1039 /* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
rgrover1 343:6675661fa600 1040 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
rgrover1 343:6675661fa600 1041 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
rgrover1 343:6675661fa600 1042 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
rgrover1 343:6675661fa600 1043 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
rgrover1 343:6675661fa600 1044 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
rgrover1 343:6675661fa600 1045
rgrover1 343:6675661fa600 1046 /* Register: CLOCK_LFCLKSRC */
rgrover1 343:6675661fa600 1047 /* Description: Clock source for the LFCLK clock. */
rgrover1 343:6675661fa600 1048
rgrover1 343:6675661fa600 1049 /* Bits 1..0 : Clock source. */
rgrover1 343:6675661fa600 1050 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
rgrover1 343:6675661fa600 1051 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
rgrover1 343:6675661fa600 1052 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
rgrover1 343:6675661fa600 1053 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
rgrover1 343:6675661fa600 1054 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
rgrover1 343:6675661fa600 1055
rgrover1 343:6675661fa600 1056 /* Register: CLOCK_CTIV */
rgrover1 343:6675661fa600 1057 /* Description: Calibration timer interval. */
rgrover1 343:6675661fa600 1058
rgrover1 343:6675661fa600 1059 /* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
rgrover1 343:6675661fa600 1060 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
rgrover1 343:6675661fa600 1061 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
rgrover1 343:6675661fa600 1062
rgrover1 343:6675661fa600 1063 /* Register: CLOCK_XTALFREQ */
rgrover1 343:6675661fa600 1064 /* Description: Crystal frequency. */
rgrover1 343:6675661fa600 1065
rgrover1 343:6675661fa600 1066 /* Bits 7..0 : External Xtal frequency selection. */
rgrover1 343:6675661fa600 1067 #define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
rgrover1 343:6675661fa600 1068 #define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
rgrover1 343:6675661fa600 1069 #define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */
rgrover1 343:6675661fa600 1070 #define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */
rgrover1 343:6675661fa600 1071
rgrover1 343:6675661fa600 1072
rgrover1 343:6675661fa600 1073 /* Peripheral: ECB */
rgrover1 343:6675661fa600 1074 /* Description: AES ECB Mode Encryption. */
rgrover1 343:6675661fa600 1075
rgrover1 343:6675661fa600 1076 /* Register: ECB_INTENSET */
rgrover1 343:6675661fa600 1077 /* Description: Interrupt enable set register. */
rgrover1 343:6675661fa600 1078
rgrover1 343:6675661fa600 1079 /* Bit 1 : Enable interrupt on ERRORECB event. */
rgrover1 343:6675661fa600 1080 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
rgrover1 343:6675661fa600 1081 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
rgrover1 343:6675661fa600 1082 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 1083 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 1084 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 1085
rgrover1 343:6675661fa600 1086 /* Bit 0 : Enable interrupt on ENDECB event. */
rgrover1 343:6675661fa600 1087 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
rgrover1 343:6675661fa600 1088 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
rgrover1 343:6675661fa600 1089 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 1090 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 1091 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 1092
rgrover1 343:6675661fa600 1093 /* Register: ECB_INTENCLR */
rgrover1 343:6675661fa600 1094 /* Description: Interrupt enable clear register. */
rgrover1 343:6675661fa600 1095
rgrover1 343:6675661fa600 1096 /* Bit 1 : Disable interrupt on ERRORECB event. */
rgrover1 343:6675661fa600 1097 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
rgrover1 343:6675661fa600 1098 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
rgrover1 343:6675661fa600 1099 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 1100 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 1101 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 1102
rgrover1 343:6675661fa600 1103 /* Bit 0 : Disable interrupt on ENDECB event. */
rgrover1 343:6675661fa600 1104 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
rgrover1 343:6675661fa600 1105 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
rgrover1 343:6675661fa600 1106 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 1107 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 1108 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 1109
rgrover1 343:6675661fa600 1110 /* Register: ECB_POWER */
rgrover1 343:6675661fa600 1111 /* Description: Peripheral power control. */
rgrover1 343:6675661fa600 1112
rgrover1 343:6675661fa600 1113 /* Bit 0 : Peripheral power control. */
rgrover1 343:6675661fa600 1114 #define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
rgrover1 343:6675661fa600 1115 #define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
rgrover1 343:6675661fa600 1116 #define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
rgrover1 343:6675661fa600 1117 #define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
rgrover1 343:6675661fa600 1118
rgrover1 343:6675661fa600 1119
rgrover1 343:6675661fa600 1120 /* Peripheral: FICR */
rgrover1 343:6675661fa600 1121 /* Description: Factory Information Configuration. */
rgrover1 343:6675661fa600 1122
rgrover1 343:6675661fa600 1123 /* Register: FICR_PPFC */
rgrover1 343:6675661fa600 1124 /* Description: Pre-programmed factory code present. */
rgrover1 343:6675661fa600 1125
rgrover1 343:6675661fa600 1126 /* Bits 7..0 : Pre-programmed factory code present. */
rgrover1 343:6675661fa600 1127 #define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */
rgrover1 343:6675661fa600 1128 #define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */
rgrover1 343:6675661fa600 1129 #define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */
rgrover1 343:6675661fa600 1130 #define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */
rgrover1 343:6675661fa600 1131
rgrover1 343:6675661fa600 1132 /* Register: FICR_CONFIGID */
rgrover1 343:6675661fa600 1133 /* Description: Configuration identifier. */
rgrover1 343:6675661fa600 1134
rgrover1 343:6675661fa600 1135 /* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
rgrover1 343:6675661fa600 1136 #define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */
rgrover1 343:6675661fa600 1137 #define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */
rgrover1 343:6675661fa600 1138
rgrover1 343:6675661fa600 1139 /* Bits 15..0 : Hardware Identification Number. */
rgrover1 343:6675661fa600 1140 #define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
rgrover1 343:6675661fa600 1141 #define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */
rgrover1 343:6675661fa600 1142
rgrover1 343:6675661fa600 1143 /* Register: FICR_DEVICEADDRTYPE */
rgrover1 343:6675661fa600 1144 /* Description: Device address type. */
rgrover1 343:6675661fa600 1145
rgrover1 343:6675661fa600 1146 /* Bit 0 : Device address type. */
rgrover1 343:6675661fa600 1147 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
rgrover1 343:6675661fa600 1148 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
rgrover1 343:6675661fa600 1149 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */
rgrover1 343:6675661fa600 1150 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */
rgrover1 343:6675661fa600 1151
rgrover1 343:6675661fa600 1152 /* Register: FICR_OVERRIDEEN */
rgrover1 343:6675661fa600 1153 /* Description: Radio calibration override enable. */
rgrover1 343:6675661fa600 1154
rgrover1 343:6675661fa600 1155 /* Bit 3 : Override default values for BLE_1Mbit mode. */
rgrover1 343:6675661fa600 1156 #define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */
rgrover1 343:6675661fa600 1157 #define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */
rgrover1 343:6675661fa600 1158 #define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */
rgrover1 343:6675661fa600 1159 #define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */
rgrover1 343:6675661fa600 1160
rgrover1 343:6675661fa600 1161 /* Bit 0 : Override default values for NRF_1Mbit mode. */
rgrover1 343:6675661fa600 1162 #define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */
rgrover1 343:6675661fa600 1163 #define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */
rgrover1 343:6675661fa600 1164 #define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */
rgrover1 343:6675661fa600 1165 #define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */
rgrover1 343:6675661fa600 1166
rgrover1 343:6675661fa600 1167 /* Register: FICR_INFO_PART */
rgrover1 343:6675661fa600 1168 /* Description: Part code */
rgrover1 343:6675661fa600 1169
rgrover1 343:6675661fa600 1170 /* Bits 31..0 : Part code */
rgrover1 343:6675661fa600 1171 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
rgrover1 343:6675661fa600 1172 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
rgrover1 343:6675661fa600 1173 #define FICR_INFO_PART_PART_N51822 (0x51822UL) /*!< nRF51822 */
rgrover1 343:6675661fa600 1174 #define FICR_INFO_PART_PART_N51422 (0x51422UL) /*!< nRF51422 */
rgrover1 343:6675661fa600 1175 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
rgrover1 343:6675661fa600 1176
rgrover1 343:6675661fa600 1177 /* Register: FICR_INFO_VARIANT */
rgrover1 343:6675661fa600 1178 /* Description: Part variant */
rgrover1 343:6675661fa600 1179
rgrover1 343:6675661fa600 1180 /* Bits 31..0 : Part variant */
rgrover1 343:6675661fa600 1181 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
rgrover1 343:6675661fa600 1182 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
rgrover1 343:6675661fa600 1183 #define FICR_INFO_VARIANT_VARIANT_nRF51C (0x1002UL) /*!< nRF51-C (XLR3) */
rgrover1 343:6675661fa600 1184 #define FICR_INFO_VARIANT_VARIANT_nRF51D (0x1003UL) /*!< nRF51-D (L3) */
rgrover1 343:6675661fa600 1185 #define FICR_INFO_VARIANT_VARIANT_nRF51E (0x1004UL) /*!< nRF51-E (XLR3P) */
rgrover1 343:6675661fa600 1186 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
rgrover1 343:6675661fa600 1187
rgrover1 343:6675661fa600 1188 /* Register: FICR_INFO_PACKAGE */
rgrover1 343:6675661fa600 1189 /* Description: Package option */
rgrover1 343:6675661fa600 1190
rgrover1 343:6675661fa600 1191 /* Bits 31..0 : Package option */
rgrover1 343:6675661fa600 1192 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
rgrover1 343:6675661fa600 1193 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
rgrover1 343:6675661fa600 1194 #define FICR_INFO_PACKAGE_PACKAGE_QFN48 (0x0000UL) /*!< 48-pin QFN with 31 GPIO */
rgrover1 343:6675661fa600 1195 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP56A (0x1000UL) /*!< nRF51x22 CDxx - WLCSP 56 balls */
rgrover1 343:6675661fa600 1196 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62A (0x1001UL) /*!< nRF51x22 CExx - WLCSP 62 balls */
rgrover1 343:6675661fa600 1197 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62B (0x1002UL) /*!< nRF51x22 CFxx - WLCSP 62 balls */
rgrover1 343:6675661fa600 1198 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62C (0x1003UL) /*!< nRF51x22 CTxx - WLCSP 62 balls */
rgrover1 343:6675661fa600 1199 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
rgrover1 343:6675661fa600 1200
rgrover1 343:6675661fa600 1201 /* Register: FICR_INFO_RAM */
rgrover1 343:6675661fa600 1202 /* Description: RAM variant */
rgrover1 343:6675661fa600 1203
rgrover1 343:6675661fa600 1204 /* Bits 31..0 : RAM variant */
rgrover1 343:6675661fa600 1205 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
rgrover1 343:6675661fa600 1206 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
rgrover1 343:6675661fa600 1207 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
rgrover1 343:6675661fa600 1208 #define FICR_INFO_RAM_RAM_K16 (16UL) /*!< 16 kByte RAM. */
rgrover1 343:6675661fa600 1209 #define FICR_INFO_RAM_RAM_K32 (32UL) /*!< 32 kByte RAM. */
rgrover1 343:6675661fa600 1210
rgrover1 343:6675661fa600 1211 /* Register: FICR_INFO_FLASH */
rgrover1 343:6675661fa600 1212 /* Description: Flash variant */
rgrover1 343:6675661fa600 1213
rgrover1 343:6675661fa600 1214 /* Bits 31..0 : Flash variant */
rgrover1 343:6675661fa600 1215 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
rgrover1 343:6675661fa600 1216 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
rgrover1 343:6675661fa600 1217 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
rgrover1 343:6675661fa600 1218 #define FICR_INFO_FLASH_FLASH_K128 (128UL) /*!< 128 kByte FLASH. */
rgrover1 343:6675661fa600 1219 #define FICR_INFO_FLASH_FLASH_K256 (256UL) /*!< 256 kByte FLASH. */
rgrover1 343:6675661fa600 1220
rgrover1 343:6675661fa600 1221
rgrover1 343:6675661fa600 1222 /* Peripheral: GPIO */
rgrover1 343:6675661fa600 1223 /* Description: General purpose input and output. */
rgrover1 343:6675661fa600 1224
rgrover1 343:6675661fa600 1225 /* Register: GPIO_OUT */
rgrover1 343:6675661fa600 1226 /* Description: Write GPIO port. */
rgrover1 343:6675661fa600 1227
rgrover1 343:6675661fa600 1228 /* Bit 31 : Pin 31. */
rgrover1 343:6675661fa600 1229 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
rgrover1 343:6675661fa600 1230 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
rgrover1 343:6675661fa600 1231 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1232 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1233
rgrover1 343:6675661fa600 1234 /* Bit 30 : Pin 30. */
rgrover1 343:6675661fa600 1235 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
rgrover1 343:6675661fa600 1236 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
rgrover1 343:6675661fa600 1237 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1238 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1239
rgrover1 343:6675661fa600 1240 /* Bit 29 : Pin 29. */
rgrover1 343:6675661fa600 1241 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
rgrover1 343:6675661fa600 1242 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
rgrover1 343:6675661fa600 1243 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1244 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1245
rgrover1 343:6675661fa600 1246 /* Bit 28 : Pin 28. */
rgrover1 343:6675661fa600 1247 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
rgrover1 343:6675661fa600 1248 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
rgrover1 343:6675661fa600 1249 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1250 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1251
rgrover1 343:6675661fa600 1252 /* Bit 27 : Pin 27. */
rgrover1 343:6675661fa600 1253 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
rgrover1 343:6675661fa600 1254 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
rgrover1 343:6675661fa600 1255 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1256 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1257
rgrover1 343:6675661fa600 1258 /* Bit 26 : Pin 26. */
rgrover1 343:6675661fa600 1259 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
rgrover1 343:6675661fa600 1260 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
rgrover1 343:6675661fa600 1261 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1262 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1263
rgrover1 343:6675661fa600 1264 /* Bit 25 : Pin 25. */
rgrover1 343:6675661fa600 1265 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
rgrover1 343:6675661fa600 1266 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
rgrover1 343:6675661fa600 1267 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1268 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1269
rgrover1 343:6675661fa600 1270 /* Bit 24 : Pin 24. */
rgrover1 343:6675661fa600 1271 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
rgrover1 343:6675661fa600 1272 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
rgrover1 343:6675661fa600 1273 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1274 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1275
rgrover1 343:6675661fa600 1276 /* Bit 23 : Pin 23. */
rgrover1 343:6675661fa600 1277 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
rgrover1 343:6675661fa600 1278 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
rgrover1 343:6675661fa600 1279 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1280 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1281
rgrover1 343:6675661fa600 1282 /* Bit 22 : Pin 22. */
rgrover1 343:6675661fa600 1283 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
rgrover1 343:6675661fa600 1284 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
rgrover1 343:6675661fa600 1285 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1286 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1287
rgrover1 343:6675661fa600 1288 /* Bit 21 : Pin 21. */
rgrover1 343:6675661fa600 1289 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
rgrover1 343:6675661fa600 1290 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
rgrover1 343:6675661fa600 1291 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1292 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1293
rgrover1 343:6675661fa600 1294 /* Bit 20 : Pin 20. */
rgrover1 343:6675661fa600 1295 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
rgrover1 343:6675661fa600 1296 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
rgrover1 343:6675661fa600 1297 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1298 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1299
rgrover1 343:6675661fa600 1300 /* Bit 19 : Pin 19. */
rgrover1 343:6675661fa600 1301 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
rgrover1 343:6675661fa600 1302 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
rgrover1 343:6675661fa600 1303 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1304 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1305
rgrover1 343:6675661fa600 1306 /* Bit 18 : Pin 18. */
rgrover1 343:6675661fa600 1307 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
rgrover1 343:6675661fa600 1308 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
rgrover1 343:6675661fa600 1309 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1310 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1311
rgrover1 343:6675661fa600 1312 /* Bit 17 : Pin 17. */
rgrover1 343:6675661fa600 1313 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
rgrover1 343:6675661fa600 1314 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
rgrover1 343:6675661fa600 1315 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1316 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1317
rgrover1 343:6675661fa600 1318 /* Bit 16 : Pin 16. */
rgrover1 343:6675661fa600 1319 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
rgrover1 343:6675661fa600 1320 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
rgrover1 343:6675661fa600 1321 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1322 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1323
rgrover1 343:6675661fa600 1324 /* Bit 15 : Pin 15. */
rgrover1 343:6675661fa600 1325 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
rgrover1 343:6675661fa600 1326 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
rgrover1 343:6675661fa600 1327 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1328 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1329
rgrover1 343:6675661fa600 1330 /* Bit 14 : Pin 14. */
rgrover1 343:6675661fa600 1331 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
rgrover1 343:6675661fa600 1332 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
rgrover1 343:6675661fa600 1333 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1334 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1335
rgrover1 343:6675661fa600 1336 /* Bit 13 : Pin 13. */
rgrover1 343:6675661fa600 1337 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
rgrover1 343:6675661fa600 1338 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
rgrover1 343:6675661fa600 1339 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1340 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1341
rgrover1 343:6675661fa600 1342 /* Bit 12 : Pin 12. */
rgrover1 343:6675661fa600 1343 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
rgrover1 343:6675661fa600 1344 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
rgrover1 343:6675661fa600 1345 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1346 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1347
rgrover1 343:6675661fa600 1348 /* Bit 11 : Pin 11. */
rgrover1 343:6675661fa600 1349 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
rgrover1 343:6675661fa600 1350 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
rgrover1 343:6675661fa600 1351 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1352 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1353
rgrover1 343:6675661fa600 1354 /* Bit 10 : Pin 10. */
rgrover1 343:6675661fa600 1355 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
rgrover1 343:6675661fa600 1356 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
rgrover1 343:6675661fa600 1357 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1358 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1359
rgrover1 343:6675661fa600 1360 /* Bit 9 : Pin 9. */
rgrover1 343:6675661fa600 1361 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
rgrover1 343:6675661fa600 1362 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
rgrover1 343:6675661fa600 1363 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1364 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1365
rgrover1 343:6675661fa600 1366 /* Bit 8 : Pin 8. */
rgrover1 343:6675661fa600 1367 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
rgrover1 343:6675661fa600 1368 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
rgrover1 343:6675661fa600 1369 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1370 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1371
rgrover1 343:6675661fa600 1372 /* Bit 7 : Pin 7. */
rgrover1 343:6675661fa600 1373 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
rgrover1 343:6675661fa600 1374 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
rgrover1 343:6675661fa600 1375 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1376 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1377
rgrover1 343:6675661fa600 1378 /* Bit 6 : Pin 6. */
rgrover1 343:6675661fa600 1379 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
rgrover1 343:6675661fa600 1380 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
rgrover1 343:6675661fa600 1381 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1382 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1383
rgrover1 343:6675661fa600 1384 /* Bit 5 : Pin 5. */
rgrover1 343:6675661fa600 1385 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
rgrover1 343:6675661fa600 1386 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
rgrover1 343:6675661fa600 1387 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1388 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1389
rgrover1 343:6675661fa600 1390 /* Bit 4 : Pin 4. */
rgrover1 343:6675661fa600 1391 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
rgrover1 343:6675661fa600 1392 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
rgrover1 343:6675661fa600 1393 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1394 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1395
rgrover1 343:6675661fa600 1396 /* Bit 3 : Pin 3. */
rgrover1 343:6675661fa600 1397 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
rgrover1 343:6675661fa600 1398 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
rgrover1 343:6675661fa600 1399 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1400 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1401
rgrover1 343:6675661fa600 1402 /* Bit 2 : Pin 2. */
rgrover1 343:6675661fa600 1403 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
rgrover1 343:6675661fa600 1404 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
rgrover1 343:6675661fa600 1405 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1406 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1407
rgrover1 343:6675661fa600 1408 /* Bit 1 : Pin 1. */
rgrover1 343:6675661fa600 1409 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
rgrover1 343:6675661fa600 1410 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
rgrover1 343:6675661fa600 1411 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1412 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1413
rgrover1 343:6675661fa600 1414 /* Bit 0 : Pin 0. */
rgrover1 343:6675661fa600 1415 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
rgrover1 343:6675661fa600 1416 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
rgrover1 343:6675661fa600 1417 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1418 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1419
rgrover1 343:6675661fa600 1420 /* Register: GPIO_OUTSET */
rgrover1 343:6675661fa600 1421 /* Description: Set individual bits in GPIO port. */
rgrover1 343:6675661fa600 1422
rgrover1 343:6675661fa600 1423 /* Bit 31 : Pin 31. */
rgrover1 343:6675661fa600 1424 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
rgrover1 343:6675661fa600 1425 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
rgrover1 343:6675661fa600 1426 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1427 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1428 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1429
rgrover1 343:6675661fa600 1430 /* Bit 30 : Pin 30. */
rgrover1 343:6675661fa600 1431 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
rgrover1 343:6675661fa600 1432 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
rgrover1 343:6675661fa600 1433 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1434 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1435 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1436
rgrover1 343:6675661fa600 1437 /* Bit 29 : Pin 29. */
rgrover1 343:6675661fa600 1438 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
rgrover1 343:6675661fa600 1439 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
rgrover1 343:6675661fa600 1440 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1441 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1442 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1443
rgrover1 343:6675661fa600 1444 /* Bit 28 : Pin 28. */
rgrover1 343:6675661fa600 1445 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
rgrover1 343:6675661fa600 1446 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
rgrover1 343:6675661fa600 1447 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1448 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1449 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1450
rgrover1 343:6675661fa600 1451 /* Bit 27 : Pin 27. */
rgrover1 343:6675661fa600 1452 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
rgrover1 343:6675661fa600 1453 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
rgrover1 343:6675661fa600 1454 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1455 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1456 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1457
rgrover1 343:6675661fa600 1458 /* Bit 26 : Pin 26. */
rgrover1 343:6675661fa600 1459 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
rgrover1 343:6675661fa600 1460 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
rgrover1 343:6675661fa600 1461 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1462 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1463 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1464
rgrover1 343:6675661fa600 1465 /* Bit 25 : Pin 25. */
rgrover1 343:6675661fa600 1466 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
rgrover1 343:6675661fa600 1467 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
rgrover1 343:6675661fa600 1468 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1469 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1470 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1471
rgrover1 343:6675661fa600 1472 /* Bit 24 : Pin 24. */
rgrover1 343:6675661fa600 1473 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
rgrover1 343:6675661fa600 1474 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
rgrover1 343:6675661fa600 1475 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1476 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1477 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1478
rgrover1 343:6675661fa600 1479 /* Bit 23 : Pin 23. */
rgrover1 343:6675661fa600 1480 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
rgrover1 343:6675661fa600 1481 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
rgrover1 343:6675661fa600 1482 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1483 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1484 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1485
rgrover1 343:6675661fa600 1486 /* Bit 22 : Pin 22. */
rgrover1 343:6675661fa600 1487 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
rgrover1 343:6675661fa600 1488 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
rgrover1 343:6675661fa600 1489 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1490 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1491 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1492
rgrover1 343:6675661fa600 1493 /* Bit 21 : Pin 21. */
rgrover1 343:6675661fa600 1494 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
rgrover1 343:6675661fa600 1495 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
rgrover1 343:6675661fa600 1496 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1497 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1498 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1499
rgrover1 343:6675661fa600 1500 /* Bit 20 : Pin 20. */
rgrover1 343:6675661fa600 1501 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
rgrover1 343:6675661fa600 1502 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
rgrover1 343:6675661fa600 1503 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1504 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1505 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1506
rgrover1 343:6675661fa600 1507 /* Bit 19 : Pin 19. */
rgrover1 343:6675661fa600 1508 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
rgrover1 343:6675661fa600 1509 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
rgrover1 343:6675661fa600 1510 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1511 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1512 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1513
rgrover1 343:6675661fa600 1514 /* Bit 18 : Pin 18. */
rgrover1 343:6675661fa600 1515 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
rgrover1 343:6675661fa600 1516 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
rgrover1 343:6675661fa600 1517 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1518 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1519 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1520
rgrover1 343:6675661fa600 1521 /* Bit 17 : Pin 17. */
rgrover1 343:6675661fa600 1522 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
rgrover1 343:6675661fa600 1523 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
rgrover1 343:6675661fa600 1524 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1525 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1526 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1527
rgrover1 343:6675661fa600 1528 /* Bit 16 : Pin 16. */
rgrover1 343:6675661fa600 1529 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
rgrover1 343:6675661fa600 1530 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
rgrover1 343:6675661fa600 1531 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1532 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1533 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1534
rgrover1 343:6675661fa600 1535 /* Bit 15 : Pin 15. */
rgrover1 343:6675661fa600 1536 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
rgrover1 343:6675661fa600 1537 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
rgrover1 343:6675661fa600 1538 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1539 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1540 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1541
rgrover1 343:6675661fa600 1542 /* Bit 14 : Pin 14. */
rgrover1 343:6675661fa600 1543 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
rgrover1 343:6675661fa600 1544 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
rgrover1 343:6675661fa600 1545 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1546 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1547 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1548
rgrover1 343:6675661fa600 1549 /* Bit 13 : Pin 13. */
rgrover1 343:6675661fa600 1550 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
rgrover1 343:6675661fa600 1551 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
rgrover1 343:6675661fa600 1552 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1553 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1554 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1555
rgrover1 343:6675661fa600 1556 /* Bit 12 : Pin 12. */
rgrover1 343:6675661fa600 1557 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
rgrover1 343:6675661fa600 1558 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
rgrover1 343:6675661fa600 1559 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1560 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1561 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1562
rgrover1 343:6675661fa600 1563 /* Bit 11 : Pin 11. */
rgrover1 343:6675661fa600 1564 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
rgrover1 343:6675661fa600 1565 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
rgrover1 343:6675661fa600 1566 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1567 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1568 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1569
rgrover1 343:6675661fa600 1570 /* Bit 10 : Pin 10. */
rgrover1 343:6675661fa600 1571 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
rgrover1 343:6675661fa600 1572 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
rgrover1 343:6675661fa600 1573 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1574 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1575 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1576
rgrover1 343:6675661fa600 1577 /* Bit 9 : Pin 9. */
rgrover1 343:6675661fa600 1578 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
rgrover1 343:6675661fa600 1579 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
rgrover1 343:6675661fa600 1580 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1581 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1582 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1583
rgrover1 343:6675661fa600 1584 /* Bit 8 : Pin 8. */
rgrover1 343:6675661fa600 1585 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
rgrover1 343:6675661fa600 1586 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
rgrover1 343:6675661fa600 1587 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1588 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1589 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1590
rgrover1 343:6675661fa600 1591 /* Bit 7 : Pin 7. */
rgrover1 343:6675661fa600 1592 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
rgrover1 343:6675661fa600 1593 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
rgrover1 343:6675661fa600 1594 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1595 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1596 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1597
rgrover1 343:6675661fa600 1598 /* Bit 6 : Pin 6. */
rgrover1 343:6675661fa600 1599 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
rgrover1 343:6675661fa600 1600 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
rgrover1 343:6675661fa600 1601 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1602 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1603 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1604
rgrover1 343:6675661fa600 1605 /* Bit 5 : Pin 5. */
rgrover1 343:6675661fa600 1606 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
rgrover1 343:6675661fa600 1607 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
rgrover1 343:6675661fa600 1608 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1609 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1610 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1611
rgrover1 343:6675661fa600 1612 /* Bit 4 : Pin 4. */
rgrover1 343:6675661fa600 1613 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
rgrover1 343:6675661fa600 1614 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
rgrover1 343:6675661fa600 1615 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1616 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1617 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1618
rgrover1 343:6675661fa600 1619 /* Bit 3 : Pin 3. */
rgrover1 343:6675661fa600 1620 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
rgrover1 343:6675661fa600 1621 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
rgrover1 343:6675661fa600 1622 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1623 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1624 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1625
rgrover1 343:6675661fa600 1626 /* Bit 2 : Pin 2. */
rgrover1 343:6675661fa600 1627 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
rgrover1 343:6675661fa600 1628 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
rgrover1 343:6675661fa600 1629 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1630 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1631 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1632
rgrover1 343:6675661fa600 1633 /* Bit 1 : Pin 1. */
rgrover1 343:6675661fa600 1634 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
rgrover1 343:6675661fa600 1635 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
rgrover1 343:6675661fa600 1636 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1637 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1638 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1639
rgrover1 343:6675661fa600 1640 /* Bit 0 : Pin 0. */
rgrover1 343:6675661fa600 1641 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
rgrover1 343:6675661fa600 1642 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
rgrover1 343:6675661fa600 1643 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1644 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1645 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */
rgrover1 343:6675661fa600 1646
rgrover1 343:6675661fa600 1647 /* Register: GPIO_OUTCLR */
rgrover1 343:6675661fa600 1648 /* Description: Clear individual bits in GPIO port. */
rgrover1 343:6675661fa600 1649
rgrover1 343:6675661fa600 1650 /* Bit 31 : Pin 31. */
rgrover1 343:6675661fa600 1651 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
rgrover1 343:6675661fa600 1652 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
rgrover1 343:6675661fa600 1653 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1654 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1655 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1656
rgrover1 343:6675661fa600 1657 /* Bit 30 : Pin 30. */
rgrover1 343:6675661fa600 1658 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
rgrover1 343:6675661fa600 1659 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
rgrover1 343:6675661fa600 1660 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1661 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1662 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1663
rgrover1 343:6675661fa600 1664 /* Bit 29 : Pin 29. */
rgrover1 343:6675661fa600 1665 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
rgrover1 343:6675661fa600 1666 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
rgrover1 343:6675661fa600 1667 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1668 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1669 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1670
rgrover1 343:6675661fa600 1671 /* Bit 28 : Pin 28. */
rgrover1 343:6675661fa600 1672 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
rgrover1 343:6675661fa600 1673 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
rgrover1 343:6675661fa600 1674 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1675 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1676 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1677
rgrover1 343:6675661fa600 1678 /* Bit 27 : Pin 27. */
rgrover1 343:6675661fa600 1679 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
rgrover1 343:6675661fa600 1680 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
rgrover1 343:6675661fa600 1681 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1682 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1683 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1684
rgrover1 343:6675661fa600 1685 /* Bit 26 : Pin 26. */
rgrover1 343:6675661fa600 1686 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
rgrover1 343:6675661fa600 1687 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
rgrover1 343:6675661fa600 1688 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1689 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1690 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1691
rgrover1 343:6675661fa600 1692 /* Bit 25 : Pin 25. */
rgrover1 343:6675661fa600 1693 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
rgrover1 343:6675661fa600 1694 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
rgrover1 343:6675661fa600 1695 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1696 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1697 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1698
rgrover1 343:6675661fa600 1699 /* Bit 24 : Pin 24. */
rgrover1 343:6675661fa600 1700 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
rgrover1 343:6675661fa600 1701 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
rgrover1 343:6675661fa600 1702 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1703 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1704 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1705
rgrover1 343:6675661fa600 1706 /* Bit 23 : Pin 23. */
rgrover1 343:6675661fa600 1707 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
rgrover1 343:6675661fa600 1708 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
rgrover1 343:6675661fa600 1709 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1710 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1711 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1712
rgrover1 343:6675661fa600 1713 /* Bit 22 : Pin 22. */
rgrover1 343:6675661fa600 1714 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
rgrover1 343:6675661fa600 1715 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
rgrover1 343:6675661fa600 1716 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1717 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1718 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1719
rgrover1 343:6675661fa600 1720 /* Bit 21 : Pin 21. */
rgrover1 343:6675661fa600 1721 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
rgrover1 343:6675661fa600 1722 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
rgrover1 343:6675661fa600 1723 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1724 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1725 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1726
rgrover1 343:6675661fa600 1727 /* Bit 20 : Pin 20. */
rgrover1 343:6675661fa600 1728 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
rgrover1 343:6675661fa600 1729 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
rgrover1 343:6675661fa600 1730 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1731 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1732 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1733
rgrover1 343:6675661fa600 1734 /* Bit 19 : Pin 19. */
rgrover1 343:6675661fa600 1735 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
rgrover1 343:6675661fa600 1736 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
rgrover1 343:6675661fa600 1737 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1738 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1739 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1740
rgrover1 343:6675661fa600 1741 /* Bit 18 : Pin 18. */
rgrover1 343:6675661fa600 1742 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
rgrover1 343:6675661fa600 1743 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
rgrover1 343:6675661fa600 1744 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1745 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1746 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1747
rgrover1 343:6675661fa600 1748 /* Bit 17 : Pin 17. */
rgrover1 343:6675661fa600 1749 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
rgrover1 343:6675661fa600 1750 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
rgrover1 343:6675661fa600 1751 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1752 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1753 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1754
rgrover1 343:6675661fa600 1755 /* Bit 16 : Pin 16. */
rgrover1 343:6675661fa600 1756 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
rgrover1 343:6675661fa600 1757 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
rgrover1 343:6675661fa600 1758 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1759 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1760 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1761
rgrover1 343:6675661fa600 1762 /* Bit 15 : Pin 15. */
rgrover1 343:6675661fa600 1763 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
rgrover1 343:6675661fa600 1764 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
rgrover1 343:6675661fa600 1765 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1766 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1767 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1768
rgrover1 343:6675661fa600 1769 /* Bit 14 : Pin 14. */
rgrover1 343:6675661fa600 1770 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
rgrover1 343:6675661fa600 1771 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
rgrover1 343:6675661fa600 1772 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1773 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1774 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1775
rgrover1 343:6675661fa600 1776 /* Bit 13 : Pin 13. */
rgrover1 343:6675661fa600 1777 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
rgrover1 343:6675661fa600 1778 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
rgrover1 343:6675661fa600 1779 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1780 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1781 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1782
rgrover1 343:6675661fa600 1783 /* Bit 12 : Pin 12. */
rgrover1 343:6675661fa600 1784 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
rgrover1 343:6675661fa600 1785 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
rgrover1 343:6675661fa600 1786 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1787 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1788 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1789
rgrover1 343:6675661fa600 1790 /* Bit 11 : Pin 11. */
rgrover1 343:6675661fa600 1791 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
rgrover1 343:6675661fa600 1792 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
rgrover1 343:6675661fa600 1793 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1794 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1795 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1796
rgrover1 343:6675661fa600 1797 /* Bit 10 : Pin 10. */
rgrover1 343:6675661fa600 1798 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
rgrover1 343:6675661fa600 1799 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
rgrover1 343:6675661fa600 1800 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1801 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1802 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1803
rgrover1 343:6675661fa600 1804 /* Bit 9 : Pin 9. */
rgrover1 343:6675661fa600 1805 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
rgrover1 343:6675661fa600 1806 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
rgrover1 343:6675661fa600 1807 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1808 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1809 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1810
rgrover1 343:6675661fa600 1811 /* Bit 8 : Pin 8. */
rgrover1 343:6675661fa600 1812 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
rgrover1 343:6675661fa600 1813 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
rgrover1 343:6675661fa600 1814 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1815 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1816 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1817
rgrover1 343:6675661fa600 1818 /* Bit 7 : Pin 7. */
rgrover1 343:6675661fa600 1819 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
rgrover1 343:6675661fa600 1820 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
rgrover1 343:6675661fa600 1821 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1822 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1823 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1824
rgrover1 343:6675661fa600 1825 /* Bit 6 : Pin 6. */
rgrover1 343:6675661fa600 1826 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
rgrover1 343:6675661fa600 1827 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
rgrover1 343:6675661fa600 1828 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1829 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1830 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1831
rgrover1 343:6675661fa600 1832 /* Bit 5 : Pin 5. */
rgrover1 343:6675661fa600 1833 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
rgrover1 343:6675661fa600 1834 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
rgrover1 343:6675661fa600 1835 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1836 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1837 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1838
rgrover1 343:6675661fa600 1839 /* Bit 4 : Pin 4. */
rgrover1 343:6675661fa600 1840 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
rgrover1 343:6675661fa600 1841 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
rgrover1 343:6675661fa600 1842 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1843 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1844 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1845
rgrover1 343:6675661fa600 1846 /* Bit 3 : Pin 3. */
rgrover1 343:6675661fa600 1847 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
rgrover1 343:6675661fa600 1848 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
rgrover1 343:6675661fa600 1849 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1850 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1851 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1852
rgrover1 343:6675661fa600 1853 /* Bit 2 : Pin 2. */
rgrover1 343:6675661fa600 1854 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
rgrover1 343:6675661fa600 1855 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
rgrover1 343:6675661fa600 1856 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1857 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1858 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1859
rgrover1 343:6675661fa600 1860 /* Bit 1 : Pin 1. */
rgrover1 343:6675661fa600 1861 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
rgrover1 343:6675661fa600 1862 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
rgrover1 343:6675661fa600 1863 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1864 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1865 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1866
rgrover1 343:6675661fa600 1867 /* Bit 0 : Pin 0. */
rgrover1 343:6675661fa600 1868 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
rgrover1 343:6675661fa600 1869 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
rgrover1 343:6675661fa600 1870 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */
rgrover1 343:6675661fa600 1871 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */
rgrover1 343:6675661fa600 1872 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */
rgrover1 343:6675661fa600 1873
rgrover1 343:6675661fa600 1874 /* Register: GPIO_IN */
rgrover1 343:6675661fa600 1875 /* Description: Read GPIO port. */
rgrover1 343:6675661fa600 1876
rgrover1 343:6675661fa600 1877 /* Bit 31 : Pin 31. */
rgrover1 343:6675661fa600 1878 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
rgrover1 343:6675661fa600 1879 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
rgrover1 343:6675661fa600 1880 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 1881 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 1882
rgrover1 343:6675661fa600 1883 /* Bit 30 : Pin 30. */
rgrover1 343:6675661fa600 1884 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
rgrover1 343:6675661fa600 1885 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
rgrover1 343:6675661fa600 1886 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 1887 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 1888
rgrover1 343:6675661fa600 1889 /* Bit 29 : Pin 29. */
rgrover1 343:6675661fa600 1890 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
rgrover1 343:6675661fa600 1891 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
rgrover1 343:6675661fa600 1892 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 1893 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 1894
rgrover1 343:6675661fa600 1895 /* Bit 28 : Pin 28. */
rgrover1 343:6675661fa600 1896 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
rgrover1 343:6675661fa600 1897 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
rgrover1 343:6675661fa600 1898 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 1899 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 1900
rgrover1 343:6675661fa600 1901 /* Bit 27 : Pin 27. */
rgrover1 343:6675661fa600 1902 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
rgrover1 343:6675661fa600 1903 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
rgrover1 343:6675661fa600 1904 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 1905 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 1906
rgrover1 343:6675661fa600 1907 /* Bit 26 : Pin 26. */
rgrover1 343:6675661fa600 1908 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
rgrover1 343:6675661fa600 1909 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
rgrover1 343:6675661fa600 1910 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 1911 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 1912
rgrover1 343:6675661fa600 1913 /* Bit 25 : Pin 25. */
rgrover1 343:6675661fa600 1914 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
rgrover1 343:6675661fa600 1915 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
rgrover1 343:6675661fa600 1916 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 1917 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 1918
rgrover1 343:6675661fa600 1919 /* Bit 24 : Pin 24. */
rgrover1 343:6675661fa600 1920 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
rgrover1 343:6675661fa600 1921 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
rgrover1 343:6675661fa600 1922 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 1923 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 1924
rgrover1 343:6675661fa600 1925 /* Bit 23 : Pin 23. */
rgrover1 343:6675661fa600 1926 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
rgrover1 343:6675661fa600 1927 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
rgrover1 343:6675661fa600 1928 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 1929 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 1930
rgrover1 343:6675661fa600 1931 /* Bit 22 : Pin 22. */
rgrover1 343:6675661fa600 1932 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
rgrover1 343:6675661fa600 1933 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
rgrover1 343:6675661fa600 1934 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 1935 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 1936
rgrover1 343:6675661fa600 1937 /* Bit 21 : Pin 21. */
rgrover1 343:6675661fa600 1938 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
rgrover1 343:6675661fa600 1939 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
rgrover1 343:6675661fa600 1940 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 1941 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 1942
rgrover1 343:6675661fa600 1943 /* Bit 20 : Pin 20. */
rgrover1 343:6675661fa600 1944 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
rgrover1 343:6675661fa600 1945 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
rgrover1 343:6675661fa600 1946 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 1947 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 1948
rgrover1 343:6675661fa600 1949 /* Bit 19 : Pin 19. */
rgrover1 343:6675661fa600 1950 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
rgrover1 343:6675661fa600 1951 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
rgrover1 343:6675661fa600 1952 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 1953 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 1954
rgrover1 343:6675661fa600 1955 /* Bit 18 : Pin 18. */
rgrover1 343:6675661fa600 1956 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
rgrover1 343:6675661fa600 1957 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
rgrover1 343:6675661fa600 1958 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 1959 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 1960
rgrover1 343:6675661fa600 1961 /* Bit 17 : Pin 17. */
rgrover1 343:6675661fa600 1962 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
rgrover1 343:6675661fa600 1963 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
rgrover1 343:6675661fa600 1964 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 1965 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 1966
rgrover1 343:6675661fa600 1967 /* Bit 16 : Pin 16. */
rgrover1 343:6675661fa600 1968 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
rgrover1 343:6675661fa600 1969 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
rgrover1 343:6675661fa600 1970 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 1971 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 1972
rgrover1 343:6675661fa600 1973 /* Bit 15 : Pin 15. */
rgrover1 343:6675661fa600 1974 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
rgrover1 343:6675661fa600 1975 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
rgrover1 343:6675661fa600 1976 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 1977 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 1978
rgrover1 343:6675661fa600 1979 /* Bit 14 : Pin 14. */
rgrover1 343:6675661fa600 1980 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
rgrover1 343:6675661fa600 1981 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
rgrover1 343:6675661fa600 1982 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 1983 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 1984
rgrover1 343:6675661fa600 1985 /* Bit 13 : Pin 13. */
rgrover1 343:6675661fa600 1986 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
rgrover1 343:6675661fa600 1987 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
rgrover1 343:6675661fa600 1988 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 1989 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 1990
rgrover1 343:6675661fa600 1991 /* Bit 12 : Pin 12. */
rgrover1 343:6675661fa600 1992 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
rgrover1 343:6675661fa600 1993 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
rgrover1 343:6675661fa600 1994 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 1995 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 1996
rgrover1 343:6675661fa600 1997 /* Bit 11 : Pin 11. */
rgrover1 343:6675661fa600 1998 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
rgrover1 343:6675661fa600 1999 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
rgrover1 343:6675661fa600 2000 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 2001 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 2002
rgrover1 343:6675661fa600 2003 /* Bit 10 : Pin 10. */
rgrover1 343:6675661fa600 2004 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
rgrover1 343:6675661fa600 2005 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
rgrover1 343:6675661fa600 2006 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 2007 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 2008
rgrover1 343:6675661fa600 2009 /* Bit 9 : Pin 9. */
rgrover1 343:6675661fa600 2010 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
rgrover1 343:6675661fa600 2011 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
rgrover1 343:6675661fa600 2012 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 2013 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 2014
rgrover1 343:6675661fa600 2015 /* Bit 8 : Pin 8. */
rgrover1 343:6675661fa600 2016 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
rgrover1 343:6675661fa600 2017 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
rgrover1 343:6675661fa600 2018 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 2019 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 2020
rgrover1 343:6675661fa600 2021 /* Bit 7 : Pin 7. */
rgrover1 343:6675661fa600 2022 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
rgrover1 343:6675661fa600 2023 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
rgrover1 343:6675661fa600 2024 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 2025 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 2026
rgrover1 343:6675661fa600 2027 /* Bit 6 : Pin 6. */
rgrover1 343:6675661fa600 2028 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
rgrover1 343:6675661fa600 2029 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
rgrover1 343:6675661fa600 2030 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 2031 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 2032
rgrover1 343:6675661fa600 2033 /* Bit 5 : Pin 5. */
rgrover1 343:6675661fa600 2034 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
rgrover1 343:6675661fa600 2035 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
rgrover1 343:6675661fa600 2036 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 2037 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 2038
rgrover1 343:6675661fa600 2039 /* Bit 4 : Pin 4. */
rgrover1 343:6675661fa600 2040 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
rgrover1 343:6675661fa600 2041 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
rgrover1 343:6675661fa600 2042 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 2043 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 2044
rgrover1 343:6675661fa600 2045 /* Bit 3 : Pin 3. */
rgrover1 343:6675661fa600 2046 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
rgrover1 343:6675661fa600 2047 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
rgrover1 343:6675661fa600 2048 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 2049 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 2050
rgrover1 343:6675661fa600 2051 /* Bit 2 : Pin 2. */
rgrover1 343:6675661fa600 2052 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
rgrover1 343:6675661fa600 2053 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
rgrover1 343:6675661fa600 2054 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 2055 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 2056
rgrover1 343:6675661fa600 2057 /* Bit 1 : Pin 1. */
rgrover1 343:6675661fa600 2058 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
rgrover1 343:6675661fa600 2059 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
rgrover1 343:6675661fa600 2060 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 2061 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 2062
rgrover1 343:6675661fa600 2063 /* Bit 0 : Pin 0. */
rgrover1 343:6675661fa600 2064 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
rgrover1 343:6675661fa600 2065 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
rgrover1 343:6675661fa600 2066 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */
rgrover1 343:6675661fa600 2067 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */
rgrover1 343:6675661fa600 2068
rgrover1 343:6675661fa600 2069 /* Register: GPIO_DIR */
rgrover1 343:6675661fa600 2070 /* Description: Direction of GPIO pins. */
rgrover1 343:6675661fa600 2071
rgrover1 343:6675661fa600 2072 /* Bit 31 : Pin 31. */
rgrover1 343:6675661fa600 2073 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
rgrover1 343:6675661fa600 2074 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
rgrover1 343:6675661fa600 2075 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2076 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2077
rgrover1 343:6675661fa600 2078 /* Bit 30 : Pin 30. */
rgrover1 343:6675661fa600 2079 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
rgrover1 343:6675661fa600 2080 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
rgrover1 343:6675661fa600 2081 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2082 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2083
rgrover1 343:6675661fa600 2084 /* Bit 29 : Pin 29. */
rgrover1 343:6675661fa600 2085 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
rgrover1 343:6675661fa600 2086 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
rgrover1 343:6675661fa600 2087 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2088 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2089
rgrover1 343:6675661fa600 2090 /* Bit 28 : Pin 28. */
rgrover1 343:6675661fa600 2091 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
rgrover1 343:6675661fa600 2092 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
rgrover1 343:6675661fa600 2093 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2094 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2095
rgrover1 343:6675661fa600 2096 /* Bit 27 : Pin 27. */
rgrover1 343:6675661fa600 2097 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
rgrover1 343:6675661fa600 2098 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
rgrover1 343:6675661fa600 2099 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2100 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2101
rgrover1 343:6675661fa600 2102 /* Bit 26 : Pin 26. */
rgrover1 343:6675661fa600 2103 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
rgrover1 343:6675661fa600 2104 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
rgrover1 343:6675661fa600 2105 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2106 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2107
rgrover1 343:6675661fa600 2108 /* Bit 25 : Pin 25. */
rgrover1 343:6675661fa600 2109 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
rgrover1 343:6675661fa600 2110 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
rgrover1 343:6675661fa600 2111 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2112 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2113
rgrover1 343:6675661fa600 2114 /* Bit 24 : Pin 24. */
rgrover1 343:6675661fa600 2115 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
rgrover1 343:6675661fa600 2116 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
rgrover1 343:6675661fa600 2117 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2118 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2119
rgrover1 343:6675661fa600 2120 /* Bit 23 : Pin 23. */
rgrover1 343:6675661fa600 2121 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
rgrover1 343:6675661fa600 2122 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
rgrover1 343:6675661fa600 2123 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2124 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2125
rgrover1 343:6675661fa600 2126 /* Bit 22 : Pin 22. */
rgrover1 343:6675661fa600 2127 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
rgrover1 343:6675661fa600 2128 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
rgrover1 343:6675661fa600 2129 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2130 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2131
rgrover1 343:6675661fa600 2132 /* Bit 21 : Pin 21. */
rgrover1 343:6675661fa600 2133 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
rgrover1 343:6675661fa600 2134 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
rgrover1 343:6675661fa600 2135 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2136 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2137
rgrover1 343:6675661fa600 2138 /* Bit 20 : Pin 20. */
rgrover1 343:6675661fa600 2139 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
rgrover1 343:6675661fa600 2140 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
rgrover1 343:6675661fa600 2141 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2142 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2143
rgrover1 343:6675661fa600 2144 /* Bit 19 : Pin 19. */
rgrover1 343:6675661fa600 2145 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
rgrover1 343:6675661fa600 2146 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
rgrover1 343:6675661fa600 2147 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2148 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2149
rgrover1 343:6675661fa600 2150 /* Bit 18 : Pin 18. */
rgrover1 343:6675661fa600 2151 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
rgrover1 343:6675661fa600 2152 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
rgrover1 343:6675661fa600 2153 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2154 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2155
rgrover1 343:6675661fa600 2156 /* Bit 17 : Pin 17. */
rgrover1 343:6675661fa600 2157 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
rgrover1 343:6675661fa600 2158 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
rgrover1 343:6675661fa600 2159 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2160 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2161
rgrover1 343:6675661fa600 2162 /* Bit 16 : Pin 16. */
rgrover1 343:6675661fa600 2163 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
rgrover1 343:6675661fa600 2164 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
rgrover1 343:6675661fa600 2165 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2166 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2167
rgrover1 343:6675661fa600 2168 /* Bit 15 : Pin 15. */
rgrover1 343:6675661fa600 2169 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
rgrover1 343:6675661fa600 2170 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
rgrover1 343:6675661fa600 2171 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2172 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2173
rgrover1 343:6675661fa600 2174 /* Bit 14 : Pin 14. */
rgrover1 343:6675661fa600 2175 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
rgrover1 343:6675661fa600 2176 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
rgrover1 343:6675661fa600 2177 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2178 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2179
rgrover1 343:6675661fa600 2180 /* Bit 13 : Pin 13. */
rgrover1 343:6675661fa600 2181 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
rgrover1 343:6675661fa600 2182 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
rgrover1 343:6675661fa600 2183 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2184 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2185
rgrover1 343:6675661fa600 2186 /* Bit 12 : Pin 12. */
rgrover1 343:6675661fa600 2187 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
rgrover1 343:6675661fa600 2188 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
rgrover1 343:6675661fa600 2189 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2190 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2191
rgrover1 343:6675661fa600 2192 /* Bit 11 : Pin 11. */
rgrover1 343:6675661fa600 2193 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
rgrover1 343:6675661fa600 2194 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
rgrover1 343:6675661fa600 2195 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2196 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2197
rgrover1 343:6675661fa600 2198 /* Bit 10 : Pin 10. */
rgrover1 343:6675661fa600 2199 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
rgrover1 343:6675661fa600 2200 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
rgrover1 343:6675661fa600 2201 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2202 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2203
rgrover1 343:6675661fa600 2204 /* Bit 9 : Pin 9. */
rgrover1 343:6675661fa600 2205 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
rgrover1 343:6675661fa600 2206 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
rgrover1 343:6675661fa600 2207 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2208 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2209
rgrover1 343:6675661fa600 2210 /* Bit 8 : Pin 8. */
rgrover1 343:6675661fa600 2211 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
rgrover1 343:6675661fa600 2212 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
rgrover1 343:6675661fa600 2213 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2214 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2215
rgrover1 343:6675661fa600 2216 /* Bit 7 : Pin 7. */
rgrover1 343:6675661fa600 2217 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
rgrover1 343:6675661fa600 2218 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
rgrover1 343:6675661fa600 2219 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2220 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2221
rgrover1 343:6675661fa600 2222 /* Bit 6 : Pin 6. */
rgrover1 343:6675661fa600 2223 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
rgrover1 343:6675661fa600 2224 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
rgrover1 343:6675661fa600 2225 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2226 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2227
rgrover1 343:6675661fa600 2228 /* Bit 5 : Pin 5. */
rgrover1 343:6675661fa600 2229 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
rgrover1 343:6675661fa600 2230 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
rgrover1 343:6675661fa600 2231 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2232 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2233
rgrover1 343:6675661fa600 2234 /* Bit 4 : Pin 4. */
rgrover1 343:6675661fa600 2235 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
rgrover1 343:6675661fa600 2236 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
rgrover1 343:6675661fa600 2237 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2238 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2239
rgrover1 343:6675661fa600 2240 /* Bit 3 : Pin 3. */
rgrover1 343:6675661fa600 2241 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
rgrover1 343:6675661fa600 2242 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
rgrover1 343:6675661fa600 2243 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2244 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2245
rgrover1 343:6675661fa600 2246 /* Bit 2 : Pin 2. */
rgrover1 343:6675661fa600 2247 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
rgrover1 343:6675661fa600 2248 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
rgrover1 343:6675661fa600 2249 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2250 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2251
rgrover1 343:6675661fa600 2252 /* Bit 1 : Pin 1. */
rgrover1 343:6675661fa600 2253 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
rgrover1 343:6675661fa600 2254 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
rgrover1 343:6675661fa600 2255 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2256 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2257
rgrover1 343:6675661fa600 2258 /* Bit 0 : Pin 0. */
rgrover1 343:6675661fa600 2259 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
rgrover1 343:6675661fa600 2260 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
rgrover1 343:6675661fa600 2261 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2262 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2263
rgrover1 343:6675661fa600 2264 /* Register: GPIO_DIRSET */
rgrover1 343:6675661fa600 2265 /* Description: DIR set register. */
rgrover1 343:6675661fa600 2266
rgrover1 343:6675661fa600 2267 /* Bit 31 : Set as output pin 31. */
rgrover1 343:6675661fa600 2268 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
rgrover1 343:6675661fa600 2269 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
rgrover1 343:6675661fa600 2270 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2271 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2272 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2273
rgrover1 343:6675661fa600 2274 /* Bit 30 : Set as output pin 30. */
rgrover1 343:6675661fa600 2275 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
rgrover1 343:6675661fa600 2276 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
rgrover1 343:6675661fa600 2277 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2278 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2279 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2280
rgrover1 343:6675661fa600 2281 /* Bit 29 : Set as output pin 29. */
rgrover1 343:6675661fa600 2282 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
rgrover1 343:6675661fa600 2283 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
rgrover1 343:6675661fa600 2284 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2285 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2286 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2287
rgrover1 343:6675661fa600 2288 /* Bit 28 : Set as output pin 28. */
rgrover1 343:6675661fa600 2289 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
rgrover1 343:6675661fa600 2290 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
rgrover1 343:6675661fa600 2291 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2292 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2293 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2294
rgrover1 343:6675661fa600 2295 /* Bit 27 : Set as output pin 27. */
rgrover1 343:6675661fa600 2296 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
rgrover1 343:6675661fa600 2297 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
rgrover1 343:6675661fa600 2298 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2299 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2300 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2301
rgrover1 343:6675661fa600 2302 /* Bit 26 : Set as output pin 26. */
rgrover1 343:6675661fa600 2303 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
rgrover1 343:6675661fa600 2304 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
rgrover1 343:6675661fa600 2305 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2306 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2307 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2308
rgrover1 343:6675661fa600 2309 /* Bit 25 : Set as output pin 25. */
rgrover1 343:6675661fa600 2310 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
rgrover1 343:6675661fa600 2311 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
rgrover1 343:6675661fa600 2312 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2313 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2314 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2315
rgrover1 343:6675661fa600 2316 /* Bit 24 : Set as output pin 24. */
rgrover1 343:6675661fa600 2317 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
rgrover1 343:6675661fa600 2318 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
rgrover1 343:6675661fa600 2319 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2320 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2321 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2322
rgrover1 343:6675661fa600 2323 /* Bit 23 : Set as output pin 23. */
rgrover1 343:6675661fa600 2324 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
rgrover1 343:6675661fa600 2325 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
rgrover1 343:6675661fa600 2326 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2327 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2328 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2329
rgrover1 343:6675661fa600 2330 /* Bit 22 : Set as output pin 22. */
rgrover1 343:6675661fa600 2331 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
rgrover1 343:6675661fa600 2332 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
rgrover1 343:6675661fa600 2333 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2334 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2335 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2336
rgrover1 343:6675661fa600 2337 /* Bit 21 : Set as output pin 21. */
rgrover1 343:6675661fa600 2338 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
rgrover1 343:6675661fa600 2339 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
rgrover1 343:6675661fa600 2340 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2341 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2342 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2343
rgrover1 343:6675661fa600 2344 /* Bit 20 : Set as output pin 20. */
rgrover1 343:6675661fa600 2345 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
rgrover1 343:6675661fa600 2346 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
rgrover1 343:6675661fa600 2347 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2348 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2349 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2350
rgrover1 343:6675661fa600 2351 /* Bit 19 : Set as output pin 19. */
rgrover1 343:6675661fa600 2352 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
rgrover1 343:6675661fa600 2353 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
rgrover1 343:6675661fa600 2354 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2355 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2356 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2357
rgrover1 343:6675661fa600 2358 /* Bit 18 : Set as output pin 18. */
rgrover1 343:6675661fa600 2359 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
rgrover1 343:6675661fa600 2360 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
rgrover1 343:6675661fa600 2361 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2362 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2363 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2364
rgrover1 343:6675661fa600 2365 /* Bit 17 : Set as output pin 17. */
rgrover1 343:6675661fa600 2366 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
rgrover1 343:6675661fa600 2367 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
rgrover1 343:6675661fa600 2368 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2369 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2370 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2371
rgrover1 343:6675661fa600 2372 /* Bit 16 : Set as output pin 16. */
rgrover1 343:6675661fa600 2373 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
rgrover1 343:6675661fa600 2374 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
rgrover1 343:6675661fa600 2375 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2376 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2377 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2378
rgrover1 343:6675661fa600 2379 /* Bit 15 : Set as output pin 15. */
rgrover1 343:6675661fa600 2380 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
rgrover1 343:6675661fa600 2381 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
rgrover1 343:6675661fa600 2382 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2383 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2384 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2385
rgrover1 343:6675661fa600 2386 /* Bit 14 : Set as output pin 14. */
rgrover1 343:6675661fa600 2387 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
rgrover1 343:6675661fa600 2388 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
rgrover1 343:6675661fa600 2389 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2390 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2391 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2392
rgrover1 343:6675661fa600 2393 /* Bit 13 : Set as output pin 13. */
rgrover1 343:6675661fa600 2394 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
rgrover1 343:6675661fa600 2395 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
rgrover1 343:6675661fa600 2396 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2397 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2398 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2399
rgrover1 343:6675661fa600 2400 /* Bit 12 : Set as output pin 12. */
rgrover1 343:6675661fa600 2401 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
rgrover1 343:6675661fa600 2402 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
rgrover1 343:6675661fa600 2403 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2404 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2405 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2406
rgrover1 343:6675661fa600 2407 /* Bit 11 : Set as output pin 11. */
rgrover1 343:6675661fa600 2408 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
rgrover1 343:6675661fa600 2409 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
rgrover1 343:6675661fa600 2410 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2411 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2412 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2413
rgrover1 343:6675661fa600 2414 /* Bit 10 : Set as output pin 10. */
rgrover1 343:6675661fa600 2415 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
rgrover1 343:6675661fa600 2416 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
rgrover1 343:6675661fa600 2417 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2418 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2419 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2420
rgrover1 343:6675661fa600 2421 /* Bit 9 : Set as output pin 9. */
rgrover1 343:6675661fa600 2422 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
rgrover1 343:6675661fa600 2423 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
rgrover1 343:6675661fa600 2424 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2425 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2426 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2427
rgrover1 343:6675661fa600 2428 /* Bit 8 : Set as output pin 8. */
rgrover1 343:6675661fa600 2429 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
rgrover1 343:6675661fa600 2430 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
rgrover1 343:6675661fa600 2431 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2432 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2433 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2434
rgrover1 343:6675661fa600 2435 /* Bit 7 : Set as output pin 7. */
rgrover1 343:6675661fa600 2436 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
rgrover1 343:6675661fa600 2437 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
rgrover1 343:6675661fa600 2438 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2439 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2440 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2441
rgrover1 343:6675661fa600 2442 /* Bit 6 : Set as output pin 6. */
rgrover1 343:6675661fa600 2443 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
rgrover1 343:6675661fa600 2444 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
rgrover1 343:6675661fa600 2445 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2446 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2447 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2448
rgrover1 343:6675661fa600 2449 /* Bit 5 : Set as output pin 5. */
rgrover1 343:6675661fa600 2450 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
rgrover1 343:6675661fa600 2451 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
rgrover1 343:6675661fa600 2452 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2453 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2454 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2455
rgrover1 343:6675661fa600 2456 /* Bit 4 : Set as output pin 4. */
rgrover1 343:6675661fa600 2457 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
rgrover1 343:6675661fa600 2458 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
rgrover1 343:6675661fa600 2459 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2460 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2461 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2462
rgrover1 343:6675661fa600 2463 /* Bit 3 : Set as output pin 3. */
rgrover1 343:6675661fa600 2464 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
rgrover1 343:6675661fa600 2465 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
rgrover1 343:6675661fa600 2466 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2467 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2468 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2469
rgrover1 343:6675661fa600 2470 /* Bit 2 : Set as output pin 2. */
rgrover1 343:6675661fa600 2471 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
rgrover1 343:6675661fa600 2472 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
rgrover1 343:6675661fa600 2473 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2474 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2475 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2476
rgrover1 343:6675661fa600 2477 /* Bit 1 : Set as output pin 1. */
rgrover1 343:6675661fa600 2478 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
rgrover1 343:6675661fa600 2479 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
rgrover1 343:6675661fa600 2480 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2481 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2482 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2483
rgrover1 343:6675661fa600 2484 /* Bit 0 : Set as output pin 0. */
rgrover1 343:6675661fa600 2485 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
rgrover1 343:6675661fa600 2486 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
rgrover1 343:6675661fa600 2487 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2488 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2489 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */
rgrover1 343:6675661fa600 2490
rgrover1 343:6675661fa600 2491 /* Register: GPIO_DIRCLR */
rgrover1 343:6675661fa600 2492 /* Description: DIR clear register. */
rgrover1 343:6675661fa600 2493
rgrover1 343:6675661fa600 2494 /* Bit 31 : Set as input pin 31. */
rgrover1 343:6675661fa600 2495 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
rgrover1 343:6675661fa600 2496 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
rgrover1 343:6675661fa600 2497 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2498 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2499 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2500
rgrover1 343:6675661fa600 2501 /* Bit 30 : Set as input pin 30. */
rgrover1 343:6675661fa600 2502 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
rgrover1 343:6675661fa600 2503 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
rgrover1 343:6675661fa600 2504 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2505 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2506 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2507
rgrover1 343:6675661fa600 2508 /* Bit 29 : Set as input pin 29. */
rgrover1 343:6675661fa600 2509 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
rgrover1 343:6675661fa600 2510 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
rgrover1 343:6675661fa600 2511 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2512 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2513 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2514
rgrover1 343:6675661fa600 2515 /* Bit 28 : Set as input pin 28. */
rgrover1 343:6675661fa600 2516 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
rgrover1 343:6675661fa600 2517 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
rgrover1 343:6675661fa600 2518 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2519 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2520 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2521
rgrover1 343:6675661fa600 2522 /* Bit 27 : Set as input pin 27. */
rgrover1 343:6675661fa600 2523 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
rgrover1 343:6675661fa600 2524 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
rgrover1 343:6675661fa600 2525 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2526 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2527 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2528
rgrover1 343:6675661fa600 2529 /* Bit 26 : Set as input pin 26. */
rgrover1 343:6675661fa600 2530 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
rgrover1 343:6675661fa600 2531 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
rgrover1 343:6675661fa600 2532 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2533 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2534 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2535
rgrover1 343:6675661fa600 2536 /* Bit 25 : Set as input pin 25. */
rgrover1 343:6675661fa600 2537 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
rgrover1 343:6675661fa600 2538 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
rgrover1 343:6675661fa600 2539 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2540 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2541 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2542
rgrover1 343:6675661fa600 2543 /* Bit 24 : Set as input pin 24. */
rgrover1 343:6675661fa600 2544 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
rgrover1 343:6675661fa600 2545 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
rgrover1 343:6675661fa600 2546 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2547 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2548 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2549
rgrover1 343:6675661fa600 2550 /* Bit 23 : Set as input pin 23. */
rgrover1 343:6675661fa600 2551 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
rgrover1 343:6675661fa600 2552 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
rgrover1 343:6675661fa600 2553 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2554 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2555 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2556
rgrover1 343:6675661fa600 2557 /* Bit 22 : Set as input pin 22. */
rgrover1 343:6675661fa600 2558 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
rgrover1 343:6675661fa600 2559 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
rgrover1 343:6675661fa600 2560 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2561 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2562 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2563
rgrover1 343:6675661fa600 2564 /* Bit 21 : Set as input pin 21. */
rgrover1 343:6675661fa600 2565 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
rgrover1 343:6675661fa600 2566 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
rgrover1 343:6675661fa600 2567 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2568 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2569 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2570
rgrover1 343:6675661fa600 2571 /* Bit 20 : Set as input pin 20. */
rgrover1 343:6675661fa600 2572 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
rgrover1 343:6675661fa600 2573 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
rgrover1 343:6675661fa600 2574 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2575 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2576 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2577
rgrover1 343:6675661fa600 2578 /* Bit 19 : Set as input pin 19. */
rgrover1 343:6675661fa600 2579 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
rgrover1 343:6675661fa600 2580 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
rgrover1 343:6675661fa600 2581 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2582 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2583 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2584
rgrover1 343:6675661fa600 2585 /* Bit 18 : Set as input pin 18. */
rgrover1 343:6675661fa600 2586 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
rgrover1 343:6675661fa600 2587 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
rgrover1 343:6675661fa600 2588 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2589 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2590 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2591
rgrover1 343:6675661fa600 2592 /* Bit 17 : Set as input pin 17. */
rgrover1 343:6675661fa600 2593 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
rgrover1 343:6675661fa600 2594 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
rgrover1 343:6675661fa600 2595 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2596 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2597 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2598
rgrover1 343:6675661fa600 2599 /* Bit 16 : Set as input pin 16. */
rgrover1 343:6675661fa600 2600 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
rgrover1 343:6675661fa600 2601 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
rgrover1 343:6675661fa600 2602 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2603 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2604 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2605
rgrover1 343:6675661fa600 2606 /* Bit 15 : Set as input pin 15. */
rgrover1 343:6675661fa600 2607 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
rgrover1 343:6675661fa600 2608 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
rgrover1 343:6675661fa600 2609 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2610 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2611 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2612
rgrover1 343:6675661fa600 2613 /* Bit 14 : Set as input pin 14. */
rgrover1 343:6675661fa600 2614 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
rgrover1 343:6675661fa600 2615 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
rgrover1 343:6675661fa600 2616 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2617 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2618 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2619
rgrover1 343:6675661fa600 2620 /* Bit 13 : Set as input pin 13. */
rgrover1 343:6675661fa600 2621 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
rgrover1 343:6675661fa600 2622 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
rgrover1 343:6675661fa600 2623 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2624 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2625 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2626
rgrover1 343:6675661fa600 2627 /* Bit 12 : Set as input pin 12. */
rgrover1 343:6675661fa600 2628 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
rgrover1 343:6675661fa600 2629 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
rgrover1 343:6675661fa600 2630 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2631 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2632 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2633
rgrover1 343:6675661fa600 2634 /* Bit 11 : Set as input pin 11. */
rgrover1 343:6675661fa600 2635 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
rgrover1 343:6675661fa600 2636 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
rgrover1 343:6675661fa600 2637 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2638 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2639 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2640
rgrover1 343:6675661fa600 2641 /* Bit 10 : Set as input pin 10. */
rgrover1 343:6675661fa600 2642 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
rgrover1 343:6675661fa600 2643 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
rgrover1 343:6675661fa600 2644 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2645 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2646 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2647
rgrover1 343:6675661fa600 2648 /* Bit 9 : Set as input pin 9. */
rgrover1 343:6675661fa600 2649 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
rgrover1 343:6675661fa600 2650 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
rgrover1 343:6675661fa600 2651 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2652 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2653 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2654
rgrover1 343:6675661fa600 2655 /* Bit 8 : Set as input pin 8. */
rgrover1 343:6675661fa600 2656 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
rgrover1 343:6675661fa600 2657 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
rgrover1 343:6675661fa600 2658 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2659 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2660 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2661
rgrover1 343:6675661fa600 2662 /* Bit 7 : Set as input pin 7. */
rgrover1 343:6675661fa600 2663 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
rgrover1 343:6675661fa600 2664 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
rgrover1 343:6675661fa600 2665 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2666 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2667 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2668
rgrover1 343:6675661fa600 2669 /* Bit 6 : Set as input pin 6. */
rgrover1 343:6675661fa600 2670 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
rgrover1 343:6675661fa600 2671 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
rgrover1 343:6675661fa600 2672 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2673 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2674 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2675
rgrover1 343:6675661fa600 2676 /* Bit 5 : Set as input pin 5. */
rgrover1 343:6675661fa600 2677 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
rgrover1 343:6675661fa600 2678 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
rgrover1 343:6675661fa600 2679 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2680 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2681 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2682
rgrover1 343:6675661fa600 2683 /* Bit 4 : Set as input pin 4. */
rgrover1 343:6675661fa600 2684 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
rgrover1 343:6675661fa600 2685 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
rgrover1 343:6675661fa600 2686 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2687 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2688 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2689
rgrover1 343:6675661fa600 2690 /* Bit 3 : Set as input pin 3. */
rgrover1 343:6675661fa600 2691 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
rgrover1 343:6675661fa600 2692 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
rgrover1 343:6675661fa600 2693 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2694 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2695 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2696
rgrover1 343:6675661fa600 2697 /* Bit 2 : Set as input pin 2. */
rgrover1 343:6675661fa600 2698 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
rgrover1 343:6675661fa600 2699 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
rgrover1 343:6675661fa600 2700 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2701 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2702 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2703
rgrover1 343:6675661fa600 2704 /* Bit 1 : Set as input pin 1. */
rgrover1 343:6675661fa600 2705 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
rgrover1 343:6675661fa600 2706 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
rgrover1 343:6675661fa600 2707 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2708 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2709 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2710
rgrover1 343:6675661fa600 2711 /* Bit 0 : Set as input pin 0. */
rgrover1 343:6675661fa600 2712 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
rgrover1 343:6675661fa600 2713 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
rgrover1 343:6675661fa600 2714 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */
rgrover1 343:6675661fa600 2715 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */
rgrover1 343:6675661fa600 2716 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */
rgrover1 343:6675661fa600 2717
rgrover1 343:6675661fa600 2718 /* Register: GPIO_PIN_CNF */
rgrover1 343:6675661fa600 2719 /* Description: Configuration of GPIO pins. */
rgrover1 343:6675661fa600 2720
rgrover1 343:6675661fa600 2721 /* Bits 17..16 : Pin sensing mechanism. */
rgrover1 343:6675661fa600 2722 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
rgrover1 343:6675661fa600 2723 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
rgrover1 343:6675661fa600 2724 #define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */
rgrover1 343:6675661fa600 2725 #define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */
rgrover1 343:6675661fa600 2726 #define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */
rgrover1 343:6675661fa600 2727
rgrover1 343:6675661fa600 2728 /* Bits 10..8 : Drive configuration. */
rgrover1 343:6675661fa600 2729 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
rgrover1 343:6675661fa600 2730 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
rgrover1 343:6675661fa600 2731 #define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */
rgrover1 343:6675661fa600 2732 #define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */
rgrover1 343:6675661fa600 2733 #define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */
rgrover1 343:6675661fa600 2734 #define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */
rgrover1 343:6675661fa600 2735 #define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */
rgrover1 343:6675661fa600 2736 #define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */
rgrover1 343:6675661fa600 2737 #define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */
rgrover1 343:6675661fa600 2738 #define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */
rgrover1 343:6675661fa600 2739
rgrover1 343:6675661fa600 2740 /* Bits 3..2 : Pull-up or -down configuration. */
rgrover1 343:6675661fa600 2741 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
rgrover1 343:6675661fa600 2742 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
rgrover1 343:6675661fa600 2743 #define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */
rgrover1 343:6675661fa600 2744 #define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */
rgrover1 343:6675661fa600 2745 #define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */
rgrover1 343:6675661fa600 2746
rgrover1 343:6675661fa600 2747 /* Bit 1 : Connect or disconnect input path. */
rgrover1 343:6675661fa600 2748 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
rgrover1 343:6675661fa600 2749 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
rgrover1 343:6675661fa600 2750 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */
rgrover1 343:6675661fa600 2751 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */
rgrover1 343:6675661fa600 2752
rgrover1 343:6675661fa600 2753 /* Bit 0 : Pin direction. */
rgrover1 343:6675661fa600 2754 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
rgrover1 343:6675661fa600 2755 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
rgrover1 343:6675661fa600 2756 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */
rgrover1 343:6675661fa600 2757 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */
rgrover1 343:6675661fa600 2758
rgrover1 343:6675661fa600 2759
rgrover1 343:6675661fa600 2760 /* Peripheral: GPIOTE */
rgrover1 343:6675661fa600 2761 /* Description: GPIO tasks and events. */
rgrover1 343:6675661fa600 2762
rgrover1 343:6675661fa600 2763 /* Register: GPIOTE_INTENSET */
rgrover1 343:6675661fa600 2764 /* Description: Interrupt enable set register. */
rgrover1 343:6675661fa600 2765
rgrover1 343:6675661fa600 2766 /* Bit 31 : Enable interrupt on PORT event. */
rgrover1 343:6675661fa600 2767 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
rgrover1 343:6675661fa600 2768 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
rgrover1 343:6675661fa600 2769 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 2770 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 2771 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 2772
rgrover1 343:6675661fa600 2773 /* Bit 3 : Enable interrupt on IN[3] event. */
rgrover1 343:6675661fa600 2774 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
rgrover1 343:6675661fa600 2775 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
rgrover1 343:6675661fa600 2776 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 2777 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 2778 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 2779
rgrover1 343:6675661fa600 2780 /* Bit 2 : Enable interrupt on IN[2] event. */
rgrover1 343:6675661fa600 2781 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
rgrover1 343:6675661fa600 2782 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
rgrover1 343:6675661fa600 2783 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 2784 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 2785 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 2786
rgrover1 343:6675661fa600 2787 /* Bit 1 : Enable interrupt on IN[1] event. */
rgrover1 343:6675661fa600 2788 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
rgrover1 343:6675661fa600 2789 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
rgrover1 343:6675661fa600 2790 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 2791 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 2792 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 2793
rgrover1 343:6675661fa600 2794 /* Bit 0 : Enable interrupt on IN[0] event. */
rgrover1 343:6675661fa600 2795 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
rgrover1 343:6675661fa600 2796 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
rgrover1 343:6675661fa600 2797 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 2798 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 2799 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 2800
rgrover1 343:6675661fa600 2801 /* Register: GPIOTE_INTENCLR */
rgrover1 343:6675661fa600 2802 /* Description: Interrupt enable clear register. */
rgrover1 343:6675661fa600 2803
rgrover1 343:6675661fa600 2804 /* Bit 31 : Disable interrupt on PORT event. */
rgrover1 343:6675661fa600 2805 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
rgrover1 343:6675661fa600 2806 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
rgrover1 343:6675661fa600 2807 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 2808 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 2809 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 2810
rgrover1 343:6675661fa600 2811 /* Bit 3 : Disable interrupt on IN[3] event. */
rgrover1 343:6675661fa600 2812 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
rgrover1 343:6675661fa600 2813 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
rgrover1 343:6675661fa600 2814 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 2815 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 2816 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 2817
rgrover1 343:6675661fa600 2818 /* Bit 2 : Disable interrupt on IN[2] event. */
rgrover1 343:6675661fa600 2819 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
rgrover1 343:6675661fa600 2820 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
rgrover1 343:6675661fa600 2821 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 2822 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 2823 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 2824
rgrover1 343:6675661fa600 2825 /* Bit 1 : Disable interrupt on IN[1] event. */
rgrover1 343:6675661fa600 2826 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
rgrover1 343:6675661fa600 2827 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
rgrover1 343:6675661fa600 2828 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 2829 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 2830 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 2831
rgrover1 343:6675661fa600 2832 /* Bit 0 : Disable interrupt on IN[0] event. */
rgrover1 343:6675661fa600 2833 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
rgrover1 343:6675661fa600 2834 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
rgrover1 343:6675661fa600 2835 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 2836 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 2837 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 2838
rgrover1 343:6675661fa600 2839 /* Register: GPIOTE_CONFIG */
rgrover1 343:6675661fa600 2840 /* Description: Channel configuration registers. */
rgrover1 343:6675661fa600 2841
rgrover1 343:6675661fa600 2842 /* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
rgrover1 343:6675661fa600 2843 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
rgrover1 343:6675661fa600 2844 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
rgrover1 343:6675661fa600 2845 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */
rgrover1 343:6675661fa600 2846 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */
rgrover1 343:6675661fa600 2847
rgrover1 343:6675661fa600 2848 /* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
rgrover1 343:6675661fa600 2849 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
rgrover1 343:6675661fa600 2850 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
rgrover1 343:6675661fa600 2851 #define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */
rgrover1 343:6675661fa600 2852 #define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */
rgrover1 343:6675661fa600 2853 #define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */
rgrover1 343:6675661fa600 2854
rgrover1 343:6675661fa600 2855 /* Bits 12..8 : Pin select. */
rgrover1 343:6675661fa600 2856 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
rgrover1 343:6675661fa600 2857 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
rgrover1 343:6675661fa600 2858
rgrover1 343:6675661fa600 2859 /* Bits 1..0 : Mode */
rgrover1 343:6675661fa600 2860 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
rgrover1 343:6675661fa600 2861 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
rgrover1 343:6675661fa600 2862 #define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */
rgrover1 343:6675661fa600 2863 #define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */
rgrover1 343:6675661fa600 2864 #define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */
rgrover1 343:6675661fa600 2865
rgrover1 343:6675661fa600 2866 /* Register: GPIOTE_POWER */
rgrover1 343:6675661fa600 2867 /* Description: Peripheral power control. */
rgrover1 343:6675661fa600 2868
rgrover1 343:6675661fa600 2869 /* Bit 0 : Peripheral power control. */
rgrover1 343:6675661fa600 2870 #define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
rgrover1 343:6675661fa600 2871 #define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
rgrover1 343:6675661fa600 2872 #define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
rgrover1 343:6675661fa600 2873 #define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
rgrover1 343:6675661fa600 2874
rgrover1 343:6675661fa600 2875
rgrover1 343:6675661fa600 2876 /* Peripheral: LPCOMP */
rgrover1 343:6675661fa600 2877 /* Description: Low power comparator. */
rgrover1 343:6675661fa600 2878
rgrover1 343:6675661fa600 2879 /* Register: LPCOMP_SHORTS */
rgrover1 343:6675661fa600 2880 /* Description: Shortcuts for the LPCOMP. */
rgrover1 343:6675661fa600 2881
rgrover1 343:6675661fa600 2882 /* Bit 4 : Shortcut between CROSS event and STOP task. */
rgrover1 343:6675661fa600 2883 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
rgrover1 343:6675661fa600 2884 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
rgrover1 343:6675661fa600 2885 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 2886 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 2887
rgrover1 343:6675661fa600 2888 /* Bit 3 : Shortcut between UP event and STOP task. */
rgrover1 343:6675661fa600 2889 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
rgrover1 343:6675661fa600 2890 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
rgrover1 343:6675661fa600 2891 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 2892 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 2893
rgrover1 343:6675661fa600 2894 /* Bit 2 : Shortcut between DOWN event and STOP task. */
rgrover1 343:6675661fa600 2895 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
rgrover1 343:6675661fa600 2896 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
rgrover1 343:6675661fa600 2897 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 2898 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 2899
rgrover1 343:6675661fa600 2900 /* Bit 1 : Shortcut between RADY event and STOP task. */
rgrover1 343:6675661fa600 2901 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
rgrover1 343:6675661fa600 2902 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
rgrover1 343:6675661fa600 2903 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 2904 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 2905
rgrover1 343:6675661fa600 2906 /* Bit 0 : Shortcut between READY event and SAMPLE task. */
rgrover1 343:6675661fa600 2907 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
rgrover1 343:6675661fa600 2908 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
rgrover1 343:6675661fa600 2909 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 2910 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 2911
rgrover1 343:6675661fa600 2912 /* Register: LPCOMP_INTENSET */
rgrover1 343:6675661fa600 2913 /* Description: Interrupt enable set register. */
rgrover1 343:6675661fa600 2914
rgrover1 343:6675661fa600 2915 /* Bit 3 : Enable interrupt on CROSS event. */
rgrover1 343:6675661fa600 2916 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
rgrover1 343:6675661fa600 2917 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
rgrover1 343:6675661fa600 2918 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 2919 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 2920 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 2921
rgrover1 343:6675661fa600 2922 /* Bit 2 : Enable interrupt on UP event. */
rgrover1 343:6675661fa600 2923 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
rgrover1 343:6675661fa600 2924 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
rgrover1 343:6675661fa600 2925 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 2926 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 2927 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 2928
rgrover1 343:6675661fa600 2929 /* Bit 1 : Enable interrupt on DOWN event. */
rgrover1 343:6675661fa600 2930 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
rgrover1 343:6675661fa600 2931 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
rgrover1 343:6675661fa600 2932 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 2933 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 2934 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 2935
rgrover1 343:6675661fa600 2936 /* Bit 0 : Enable interrupt on READY event. */
rgrover1 343:6675661fa600 2937 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
rgrover1 343:6675661fa600 2938 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
rgrover1 343:6675661fa600 2939 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 2940 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 2941 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 2942
rgrover1 343:6675661fa600 2943 /* Register: LPCOMP_INTENCLR */
rgrover1 343:6675661fa600 2944 /* Description: Interrupt enable clear register. */
rgrover1 343:6675661fa600 2945
rgrover1 343:6675661fa600 2946 /* Bit 3 : Disable interrupt on CROSS event. */
rgrover1 343:6675661fa600 2947 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
rgrover1 343:6675661fa600 2948 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
rgrover1 343:6675661fa600 2949 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 2950 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 2951 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 2952
rgrover1 343:6675661fa600 2953 /* Bit 2 : Disable interrupt on UP event. */
rgrover1 343:6675661fa600 2954 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
rgrover1 343:6675661fa600 2955 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
rgrover1 343:6675661fa600 2956 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 2957 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 2958 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 2959
rgrover1 343:6675661fa600 2960 /* Bit 1 : Disable interrupt on DOWN event. */
rgrover1 343:6675661fa600 2961 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
rgrover1 343:6675661fa600 2962 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
rgrover1 343:6675661fa600 2963 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 2964 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 2965 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 2966
rgrover1 343:6675661fa600 2967 /* Bit 0 : Disable interrupt on READY event. */
rgrover1 343:6675661fa600 2968 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
rgrover1 343:6675661fa600 2969 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
rgrover1 343:6675661fa600 2970 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 2971 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 2972 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 2973
rgrover1 343:6675661fa600 2974 /* Register: LPCOMP_RESULT */
rgrover1 343:6675661fa600 2975 /* Description: Result of last compare. */
rgrover1 343:6675661fa600 2976
rgrover1 343:6675661fa600 2977 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
rgrover1 343:6675661fa600 2978 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
rgrover1 343:6675661fa600 2979 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
rgrover1 343:6675661fa600 2980 #define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */
rgrover1 343:6675661fa600 2981 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
rgrover1 343:6675661fa600 2982
rgrover1 343:6675661fa600 2983 /* Register: LPCOMP_ENABLE */
rgrover1 343:6675661fa600 2984 /* Description: Enable the LPCOMP. */
rgrover1 343:6675661fa600 2985
rgrover1 343:6675661fa600 2986 /* Bits 1..0 : Enable or disable LPCOMP. */
rgrover1 343:6675661fa600 2987 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
rgrover1 343:6675661fa600 2988 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
rgrover1 343:6675661fa600 2989 #define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */
rgrover1 343:6675661fa600 2990 #define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */
rgrover1 343:6675661fa600 2991
rgrover1 343:6675661fa600 2992 /* Register: LPCOMP_PSEL */
rgrover1 343:6675661fa600 2993 /* Description: Input pin select. */
rgrover1 343:6675661fa600 2994
rgrover1 343:6675661fa600 2995 /* Bits 2..0 : Analog input pin select. */
rgrover1 343:6675661fa600 2996 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
rgrover1 343:6675661fa600 2997 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
rgrover1 343:6675661fa600 2998 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
rgrover1 343:6675661fa600 2999 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
rgrover1 343:6675661fa600 3000 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
rgrover1 343:6675661fa600 3001 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
rgrover1 343:6675661fa600 3002 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
rgrover1 343:6675661fa600 3003 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
rgrover1 343:6675661fa600 3004 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
rgrover1 343:6675661fa600 3005 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
rgrover1 343:6675661fa600 3006
rgrover1 343:6675661fa600 3007 /* Register: LPCOMP_REFSEL */
rgrover1 343:6675661fa600 3008 /* Description: Reference select. */
rgrover1 343:6675661fa600 3009
rgrover1 343:6675661fa600 3010 /* Bits 2..0 : Reference select. */
rgrover1 343:6675661fa600 3011 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
rgrover1 343:6675661fa600 3012 #define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
rgrover1 343:6675661fa600 3013 #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */
rgrover1 343:6675661fa600 3014 #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */
rgrover1 343:6675661fa600 3015 #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */
rgrover1 343:6675661fa600 3016 #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */
rgrover1 343:6675661fa600 3017 #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */
rgrover1 343:6675661fa600 3018 #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */
rgrover1 343:6675661fa600 3019 #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */
rgrover1 343:6675661fa600 3020 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */
rgrover1 343:6675661fa600 3021
rgrover1 343:6675661fa600 3022 /* Register: LPCOMP_EXTREFSEL */
rgrover1 343:6675661fa600 3023 /* Description: External reference select. */
rgrover1 343:6675661fa600 3024
rgrover1 343:6675661fa600 3025 /* Bit 0 : External analog reference pin selection. */
rgrover1 343:6675661fa600 3026 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
rgrover1 343:6675661fa600 3027 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
rgrover1 343:6675661fa600 3028 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
rgrover1 343:6675661fa600 3029 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
rgrover1 343:6675661fa600 3030
rgrover1 343:6675661fa600 3031 /* Register: LPCOMP_ANADETECT */
rgrover1 343:6675661fa600 3032 /* Description: Analog detect configuration. */
rgrover1 343:6675661fa600 3033
rgrover1 343:6675661fa600 3034 /* Bits 1..0 : Analog detect configuration. */
rgrover1 343:6675661fa600 3035 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
rgrover1 343:6675661fa600 3036 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
rgrover1 343:6675661fa600 3037 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */
rgrover1 343:6675661fa600 3038 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */
rgrover1 343:6675661fa600 3039 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */
rgrover1 343:6675661fa600 3040
rgrover1 343:6675661fa600 3041 /* Register: LPCOMP_POWER */
rgrover1 343:6675661fa600 3042 /* Description: Peripheral power control. */
rgrover1 343:6675661fa600 3043
rgrover1 343:6675661fa600 3044 /* Bit 0 : Peripheral power control. */
rgrover1 343:6675661fa600 3045 #define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
rgrover1 343:6675661fa600 3046 #define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
rgrover1 343:6675661fa600 3047 #define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
rgrover1 343:6675661fa600 3048 #define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
rgrover1 343:6675661fa600 3049
rgrover1 343:6675661fa600 3050
rgrover1 343:6675661fa600 3051 /* Peripheral: MPU */
rgrover1 343:6675661fa600 3052 /* Description: Memory Protection Unit. */
rgrover1 343:6675661fa600 3053
rgrover1 343:6675661fa600 3054 /* Register: MPU_PERR0 */
rgrover1 343:6675661fa600 3055 /* Description: Configuration of peripherals in mpu regions. */
rgrover1 343:6675661fa600 3056
rgrover1 343:6675661fa600 3057 /* Bit 31 : PPI region configuration. */
rgrover1 343:6675661fa600 3058 #define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */
rgrover1 343:6675661fa600 3059 #define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */
rgrover1 343:6675661fa600 3060 #define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
rgrover1 343:6675661fa600 3061 #define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
rgrover1 343:6675661fa600 3062
rgrover1 343:6675661fa600 3063 /* Bit 30 : NVMC region configuration. */
rgrover1 343:6675661fa600 3064 #define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */
rgrover1 343:6675661fa600 3065 #define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */
rgrover1 343:6675661fa600 3066 #define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
rgrover1 343:6675661fa600 3067 #define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
rgrover1 343:6675661fa600 3068
rgrover1 343:6675661fa600 3069 /* Bit 19 : LPCOMP region configuration. */
rgrover1 343:6675661fa600 3070 #define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */
rgrover1 343:6675661fa600 3071 #define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
rgrover1 343:6675661fa600 3072 #define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
rgrover1 343:6675661fa600 3073 #define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
rgrover1 343:6675661fa600 3074
rgrover1 343:6675661fa600 3075 /* Bit 18 : QDEC region configuration. */
rgrover1 343:6675661fa600 3076 #define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */
rgrover1 343:6675661fa600 3077 #define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */
rgrover1 343:6675661fa600 3078 #define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
rgrover1 343:6675661fa600 3079 #define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
rgrover1 343:6675661fa600 3080
rgrover1 343:6675661fa600 3081 /* Bit 17 : RTC1 region configuration. */
rgrover1 343:6675661fa600 3082 #define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */
rgrover1 343:6675661fa600 3083 #define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */
rgrover1 343:6675661fa600 3084 #define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
rgrover1 343:6675661fa600 3085 #define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
rgrover1 343:6675661fa600 3086
rgrover1 343:6675661fa600 3087 /* Bit 16 : WDT region configuration. */
rgrover1 343:6675661fa600 3088 #define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */
rgrover1 343:6675661fa600 3089 #define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */
rgrover1 343:6675661fa600 3090 #define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
rgrover1 343:6675661fa600 3091 #define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
rgrover1 343:6675661fa600 3092
rgrover1 343:6675661fa600 3093 /* Bit 15 : CCM and AAR region configuration. */
rgrover1 343:6675661fa600 3094 #define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */
rgrover1 343:6675661fa600 3095 #define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */
rgrover1 343:6675661fa600 3096 #define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
rgrover1 343:6675661fa600 3097 #define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
rgrover1 343:6675661fa600 3098
rgrover1 343:6675661fa600 3099 /* Bit 14 : ECB region configuration. */
rgrover1 343:6675661fa600 3100 #define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */
rgrover1 343:6675661fa600 3101 #define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */
rgrover1 343:6675661fa600 3102 #define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
rgrover1 343:6675661fa600 3103 #define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
rgrover1 343:6675661fa600 3104
rgrover1 343:6675661fa600 3105 /* Bit 13 : RNG region configuration. */
rgrover1 343:6675661fa600 3106 #define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */
rgrover1 343:6675661fa600 3107 #define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */
rgrover1 343:6675661fa600 3108 #define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
rgrover1 343:6675661fa600 3109 #define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
rgrover1 343:6675661fa600 3110
rgrover1 343:6675661fa600 3111 /* Bit 12 : TEMP region configuration. */
rgrover1 343:6675661fa600 3112 #define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */
rgrover1 343:6675661fa600 3113 #define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */
rgrover1 343:6675661fa600 3114 #define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
rgrover1 343:6675661fa600 3115 #define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
rgrover1 343:6675661fa600 3116
rgrover1 343:6675661fa600 3117 /* Bit 11 : RTC0 region configuration. */
rgrover1 343:6675661fa600 3118 #define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */
rgrover1 343:6675661fa600 3119 #define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */
rgrover1 343:6675661fa600 3120 #define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
rgrover1 343:6675661fa600 3121 #define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
rgrover1 343:6675661fa600 3122
rgrover1 343:6675661fa600 3123 /* Bit 10 : TIMER2 region configuration. */
rgrover1 343:6675661fa600 3124 #define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */
rgrover1 343:6675661fa600 3125 #define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */
rgrover1 343:6675661fa600 3126 #define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
rgrover1 343:6675661fa600 3127 #define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
rgrover1 343:6675661fa600 3128
rgrover1 343:6675661fa600 3129 /* Bit 9 : TIMER1 region configuration. */
rgrover1 343:6675661fa600 3130 #define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */
rgrover1 343:6675661fa600 3131 #define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */
rgrover1 343:6675661fa600 3132 #define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
rgrover1 343:6675661fa600 3133 #define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
rgrover1 343:6675661fa600 3134
rgrover1 343:6675661fa600 3135 /* Bit 8 : TIMER0 region configuration. */
rgrover1 343:6675661fa600 3136 #define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */
rgrover1 343:6675661fa600 3137 #define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */
rgrover1 343:6675661fa600 3138 #define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
rgrover1 343:6675661fa600 3139 #define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
rgrover1 343:6675661fa600 3140
rgrover1 343:6675661fa600 3141 /* Bit 7 : ADC region configuration. */
rgrover1 343:6675661fa600 3142 #define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */
rgrover1 343:6675661fa600 3143 #define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */
rgrover1 343:6675661fa600 3144 #define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
rgrover1 343:6675661fa600 3145 #define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
rgrover1 343:6675661fa600 3146
rgrover1 343:6675661fa600 3147 /* Bit 6 : GPIOTE region configuration. */
rgrover1 343:6675661fa600 3148 #define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */
rgrover1 343:6675661fa600 3149 #define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */
rgrover1 343:6675661fa600 3150 #define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
rgrover1 343:6675661fa600 3151 #define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
rgrover1 343:6675661fa600 3152
rgrover1 343:6675661fa600 3153 /* Bit 4 : SPI1 and TWI1 region configuration. */
rgrover1 343:6675661fa600 3154 #define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */
rgrover1 343:6675661fa600 3155 #define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */
rgrover1 343:6675661fa600 3156 #define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
rgrover1 343:6675661fa600 3157 #define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
rgrover1 343:6675661fa600 3158
rgrover1 343:6675661fa600 3159 /* Bit 3 : SPI0 and TWI0 region configuration. */
rgrover1 343:6675661fa600 3160 #define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */
rgrover1 343:6675661fa600 3161 #define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */
rgrover1 343:6675661fa600 3162 #define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
rgrover1 343:6675661fa600 3163 #define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
rgrover1 343:6675661fa600 3164
rgrover1 343:6675661fa600 3165 /* Bit 2 : UART0 region configuration. */
rgrover1 343:6675661fa600 3166 #define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */
rgrover1 343:6675661fa600 3167 #define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */
rgrover1 343:6675661fa600 3168 #define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
rgrover1 343:6675661fa600 3169 #define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
rgrover1 343:6675661fa600 3170
rgrover1 343:6675661fa600 3171 /* Bit 1 : RADIO region configuration. */
rgrover1 343:6675661fa600 3172 #define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */
rgrover1 343:6675661fa600 3173 #define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */
rgrover1 343:6675661fa600 3174 #define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
rgrover1 343:6675661fa600 3175 #define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
rgrover1 343:6675661fa600 3176
rgrover1 343:6675661fa600 3177 /* Bit 0 : POWER_CLOCK region configuration. */
rgrover1 343:6675661fa600 3178 #define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */
rgrover1 343:6675661fa600 3179 #define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */
rgrover1 343:6675661fa600 3180 #define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
rgrover1 343:6675661fa600 3181 #define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
rgrover1 343:6675661fa600 3182
rgrover1 343:6675661fa600 3183 /* Register: MPU_PROTENSET0 */
rgrover1 343:6675661fa600 3184 /* Description: Erase and write protection bit enable set register. */
rgrover1 343:6675661fa600 3185
rgrover1 343:6675661fa600 3186 /* Bit 31 : Protection enable for region 31. */
rgrover1 343:6675661fa600 3187 #define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */
rgrover1 343:6675661fa600 3188 #define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */
rgrover1 343:6675661fa600 3189 #define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3190 #define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3191 #define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3192
rgrover1 343:6675661fa600 3193 /* Bit 30 : Protection enable for region 30. */
rgrover1 343:6675661fa600 3194 #define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */
rgrover1 343:6675661fa600 3195 #define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */
rgrover1 343:6675661fa600 3196 #define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3197 #define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3198 #define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3199
rgrover1 343:6675661fa600 3200 /* Bit 29 : Protection enable for region 29. */
rgrover1 343:6675661fa600 3201 #define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */
rgrover1 343:6675661fa600 3202 #define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */
rgrover1 343:6675661fa600 3203 #define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3204 #define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3205 #define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3206
rgrover1 343:6675661fa600 3207 /* Bit 28 : Protection enable for region 28. */
rgrover1 343:6675661fa600 3208 #define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */
rgrover1 343:6675661fa600 3209 #define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */
rgrover1 343:6675661fa600 3210 #define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3211 #define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3212 #define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3213
rgrover1 343:6675661fa600 3214 /* Bit 27 : Protection enable for region 27. */
rgrover1 343:6675661fa600 3215 #define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */
rgrover1 343:6675661fa600 3216 #define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */
rgrover1 343:6675661fa600 3217 #define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3218 #define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3219 #define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3220
rgrover1 343:6675661fa600 3221 /* Bit 26 : Protection enable for region 26. */
rgrover1 343:6675661fa600 3222 #define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */
rgrover1 343:6675661fa600 3223 #define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */
rgrover1 343:6675661fa600 3224 #define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3225 #define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3226 #define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3227
rgrover1 343:6675661fa600 3228 /* Bit 25 : Protection enable for region 25. */
rgrover1 343:6675661fa600 3229 #define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */
rgrover1 343:6675661fa600 3230 #define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */
rgrover1 343:6675661fa600 3231 #define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3232 #define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3233 #define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3234
rgrover1 343:6675661fa600 3235 /* Bit 24 : Protection enable for region 24. */
rgrover1 343:6675661fa600 3236 #define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */
rgrover1 343:6675661fa600 3237 #define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */
rgrover1 343:6675661fa600 3238 #define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3239 #define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3240 #define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3241
rgrover1 343:6675661fa600 3242 /* Bit 23 : Protection enable for region 23. */
rgrover1 343:6675661fa600 3243 #define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */
rgrover1 343:6675661fa600 3244 #define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */
rgrover1 343:6675661fa600 3245 #define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3246 #define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3247 #define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3248
rgrover1 343:6675661fa600 3249 /* Bit 22 : Protection enable for region 22. */
rgrover1 343:6675661fa600 3250 #define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */
rgrover1 343:6675661fa600 3251 #define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */
rgrover1 343:6675661fa600 3252 #define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3253 #define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3254 #define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3255
rgrover1 343:6675661fa600 3256 /* Bit 21 : Protection enable for region 21. */
rgrover1 343:6675661fa600 3257 #define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */
rgrover1 343:6675661fa600 3258 #define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */
rgrover1 343:6675661fa600 3259 #define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3260 #define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3261 #define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3262
rgrover1 343:6675661fa600 3263 /* Bit 20 : Protection enable for region 20. */
rgrover1 343:6675661fa600 3264 #define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */
rgrover1 343:6675661fa600 3265 #define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */
rgrover1 343:6675661fa600 3266 #define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3267 #define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3268 #define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3269
rgrover1 343:6675661fa600 3270 /* Bit 19 : Protection enable for region 19. */
rgrover1 343:6675661fa600 3271 #define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */
rgrover1 343:6675661fa600 3272 #define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */
rgrover1 343:6675661fa600 3273 #define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3274 #define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3275 #define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3276
rgrover1 343:6675661fa600 3277 /* Bit 18 : Protection enable for region 18. */
rgrover1 343:6675661fa600 3278 #define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */
rgrover1 343:6675661fa600 3279 #define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */
rgrover1 343:6675661fa600 3280 #define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3281 #define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3282 #define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3283
rgrover1 343:6675661fa600 3284 /* Bit 17 : Protection enable for region 17. */
rgrover1 343:6675661fa600 3285 #define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */
rgrover1 343:6675661fa600 3286 #define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */
rgrover1 343:6675661fa600 3287 #define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3288 #define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3289 #define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3290
rgrover1 343:6675661fa600 3291 /* Bit 16 : Protection enable for region 16. */
rgrover1 343:6675661fa600 3292 #define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */
rgrover1 343:6675661fa600 3293 #define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */
rgrover1 343:6675661fa600 3294 #define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3295 #define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3296 #define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3297
rgrover1 343:6675661fa600 3298 /* Bit 15 : Protection enable for region 15. */
rgrover1 343:6675661fa600 3299 #define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */
rgrover1 343:6675661fa600 3300 #define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */
rgrover1 343:6675661fa600 3301 #define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3302 #define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3303 #define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3304
rgrover1 343:6675661fa600 3305 /* Bit 14 : Protection enable for region 14. */
rgrover1 343:6675661fa600 3306 #define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */
rgrover1 343:6675661fa600 3307 #define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */
rgrover1 343:6675661fa600 3308 #define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3309 #define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3310 #define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3311
rgrover1 343:6675661fa600 3312 /* Bit 13 : Protection enable for region 13. */
rgrover1 343:6675661fa600 3313 #define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */
rgrover1 343:6675661fa600 3314 #define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */
rgrover1 343:6675661fa600 3315 #define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3316 #define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3317 #define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3318
rgrover1 343:6675661fa600 3319 /* Bit 12 : Protection enable for region 12. */
rgrover1 343:6675661fa600 3320 #define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */
rgrover1 343:6675661fa600 3321 #define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */
rgrover1 343:6675661fa600 3322 #define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3323 #define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3324 #define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3325
rgrover1 343:6675661fa600 3326 /* Bit 11 : Protection enable for region 11. */
rgrover1 343:6675661fa600 3327 #define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */
rgrover1 343:6675661fa600 3328 #define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */
rgrover1 343:6675661fa600 3329 #define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3330 #define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3331 #define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3332
rgrover1 343:6675661fa600 3333 /* Bit 10 : Protection enable for region 10. */
rgrover1 343:6675661fa600 3334 #define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */
rgrover1 343:6675661fa600 3335 #define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */
rgrover1 343:6675661fa600 3336 #define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3337 #define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3338 #define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3339
rgrover1 343:6675661fa600 3340 /* Bit 9 : Protection enable for region 9. */
rgrover1 343:6675661fa600 3341 #define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */
rgrover1 343:6675661fa600 3342 #define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */
rgrover1 343:6675661fa600 3343 #define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3344 #define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3345 #define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3346
rgrover1 343:6675661fa600 3347 /* Bit 8 : Protection enable for region 8. */
rgrover1 343:6675661fa600 3348 #define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */
rgrover1 343:6675661fa600 3349 #define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */
rgrover1 343:6675661fa600 3350 #define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3351 #define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3352 #define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3353
rgrover1 343:6675661fa600 3354 /* Bit 7 : Protection enable for region 7. */
rgrover1 343:6675661fa600 3355 #define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */
rgrover1 343:6675661fa600 3356 #define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */
rgrover1 343:6675661fa600 3357 #define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3358 #define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3359 #define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3360
rgrover1 343:6675661fa600 3361 /* Bit 6 : Protection enable for region 6. */
rgrover1 343:6675661fa600 3362 #define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */
rgrover1 343:6675661fa600 3363 #define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */
rgrover1 343:6675661fa600 3364 #define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3365 #define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3366 #define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3367
rgrover1 343:6675661fa600 3368 /* Bit 5 : Protection enable for region 5. */
rgrover1 343:6675661fa600 3369 #define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */
rgrover1 343:6675661fa600 3370 #define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */
rgrover1 343:6675661fa600 3371 #define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3372 #define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3373 #define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3374
rgrover1 343:6675661fa600 3375 /* Bit 4 : Protection enable for region 4. */
rgrover1 343:6675661fa600 3376 #define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */
rgrover1 343:6675661fa600 3377 #define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */
rgrover1 343:6675661fa600 3378 #define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3379 #define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3380 #define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3381
rgrover1 343:6675661fa600 3382 /* Bit 3 : Protection enable for region 3. */
rgrover1 343:6675661fa600 3383 #define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */
rgrover1 343:6675661fa600 3384 #define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */
rgrover1 343:6675661fa600 3385 #define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3386 #define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3387 #define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3388
rgrover1 343:6675661fa600 3389 /* Bit 2 : Protection enable for region 2. */
rgrover1 343:6675661fa600 3390 #define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */
rgrover1 343:6675661fa600 3391 #define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */
rgrover1 343:6675661fa600 3392 #define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3393 #define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3394 #define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3395
rgrover1 343:6675661fa600 3396 /* Bit 1 : Protection enable for region 1. */
rgrover1 343:6675661fa600 3397 #define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */
rgrover1 343:6675661fa600 3398 #define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */
rgrover1 343:6675661fa600 3399 #define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3400 #define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3401 #define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3402
rgrover1 343:6675661fa600 3403 /* Bit 0 : Protection enable for region 0. */
rgrover1 343:6675661fa600 3404 #define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */
rgrover1 343:6675661fa600 3405 #define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */
rgrover1 343:6675661fa600 3406 #define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3407 #define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3408 #define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3409
rgrover1 343:6675661fa600 3410 /* Register: MPU_PROTENSET1 */
rgrover1 343:6675661fa600 3411 /* Description: Erase and write protection bit enable set register. */
rgrover1 343:6675661fa600 3412
rgrover1 343:6675661fa600 3413 /* Bit 31 : Protection enable for region 63. */
rgrover1 343:6675661fa600 3414 #define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */
rgrover1 343:6675661fa600 3415 #define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */
rgrover1 343:6675661fa600 3416 #define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3417 #define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3418 #define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3419
rgrover1 343:6675661fa600 3420 /* Bit 30 : Protection enable for region 62. */
rgrover1 343:6675661fa600 3421 #define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */
rgrover1 343:6675661fa600 3422 #define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */
rgrover1 343:6675661fa600 3423 #define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3424 #define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3425 #define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3426
rgrover1 343:6675661fa600 3427 /* Bit 29 : Protection enable for region 61. */
rgrover1 343:6675661fa600 3428 #define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */
rgrover1 343:6675661fa600 3429 #define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */
rgrover1 343:6675661fa600 3430 #define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3431 #define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3432 #define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3433
rgrover1 343:6675661fa600 3434 /* Bit 28 : Protection enable for region 60. */
rgrover1 343:6675661fa600 3435 #define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */
rgrover1 343:6675661fa600 3436 #define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */
rgrover1 343:6675661fa600 3437 #define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3438 #define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3439 #define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3440
rgrover1 343:6675661fa600 3441 /* Bit 27 : Protection enable for region 59. */
rgrover1 343:6675661fa600 3442 #define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */
rgrover1 343:6675661fa600 3443 #define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */
rgrover1 343:6675661fa600 3444 #define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3445 #define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3446 #define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3447
rgrover1 343:6675661fa600 3448 /* Bit 26 : Protection enable for region 58. */
rgrover1 343:6675661fa600 3449 #define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */
rgrover1 343:6675661fa600 3450 #define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */
rgrover1 343:6675661fa600 3451 #define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3452 #define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3453 #define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3454
rgrover1 343:6675661fa600 3455 /* Bit 25 : Protection enable for region 57. */
rgrover1 343:6675661fa600 3456 #define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */
rgrover1 343:6675661fa600 3457 #define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */
rgrover1 343:6675661fa600 3458 #define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3459 #define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3460 #define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3461
rgrover1 343:6675661fa600 3462 /* Bit 24 : Protection enable for region 56. */
rgrover1 343:6675661fa600 3463 #define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */
rgrover1 343:6675661fa600 3464 #define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */
rgrover1 343:6675661fa600 3465 #define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3466 #define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3467 #define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3468
rgrover1 343:6675661fa600 3469 /* Bit 23 : Protection enable for region 55. */
rgrover1 343:6675661fa600 3470 #define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */
rgrover1 343:6675661fa600 3471 #define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */
rgrover1 343:6675661fa600 3472 #define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3473 #define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3474 #define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3475
rgrover1 343:6675661fa600 3476 /* Bit 22 : Protection enable for region 54. */
rgrover1 343:6675661fa600 3477 #define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */
rgrover1 343:6675661fa600 3478 #define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */
rgrover1 343:6675661fa600 3479 #define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3480 #define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3481 #define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3482
rgrover1 343:6675661fa600 3483 /* Bit 21 : Protection enable for region 53. */
rgrover1 343:6675661fa600 3484 #define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */
rgrover1 343:6675661fa600 3485 #define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */
rgrover1 343:6675661fa600 3486 #define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3487 #define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3488 #define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3489
rgrover1 343:6675661fa600 3490 /* Bit 20 : Protection enable for region 52. */
rgrover1 343:6675661fa600 3491 #define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */
rgrover1 343:6675661fa600 3492 #define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */
rgrover1 343:6675661fa600 3493 #define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3494 #define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3495 #define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3496
rgrover1 343:6675661fa600 3497 /* Bit 19 : Protection enable for region 51. */
rgrover1 343:6675661fa600 3498 #define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */
rgrover1 343:6675661fa600 3499 #define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */
rgrover1 343:6675661fa600 3500 #define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3501 #define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3502 #define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3503
rgrover1 343:6675661fa600 3504 /* Bit 18 : Protection enable for region 50. */
rgrover1 343:6675661fa600 3505 #define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */
rgrover1 343:6675661fa600 3506 #define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */
rgrover1 343:6675661fa600 3507 #define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3508 #define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3509 #define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3510
rgrover1 343:6675661fa600 3511 /* Bit 17 : Protection enable for region 49. */
rgrover1 343:6675661fa600 3512 #define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */
rgrover1 343:6675661fa600 3513 #define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */
rgrover1 343:6675661fa600 3514 #define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3515 #define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3516 #define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3517
rgrover1 343:6675661fa600 3518 /* Bit 16 : Protection enable for region 48. */
rgrover1 343:6675661fa600 3519 #define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */
rgrover1 343:6675661fa600 3520 #define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */
rgrover1 343:6675661fa600 3521 #define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3522 #define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3523 #define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3524
rgrover1 343:6675661fa600 3525 /* Bit 15 : Protection enable for region 47. */
rgrover1 343:6675661fa600 3526 #define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */
rgrover1 343:6675661fa600 3527 #define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */
rgrover1 343:6675661fa600 3528 #define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3529 #define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3530 #define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3531
rgrover1 343:6675661fa600 3532 /* Bit 14 : Protection enable for region 46. */
rgrover1 343:6675661fa600 3533 #define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */
rgrover1 343:6675661fa600 3534 #define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */
rgrover1 343:6675661fa600 3535 #define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3536 #define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3537 #define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3538
rgrover1 343:6675661fa600 3539 /* Bit 13 : Protection enable for region 45. */
rgrover1 343:6675661fa600 3540 #define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */
rgrover1 343:6675661fa600 3541 #define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */
rgrover1 343:6675661fa600 3542 #define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3543 #define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3544 #define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3545
rgrover1 343:6675661fa600 3546 /* Bit 12 : Protection enable for region 44. */
rgrover1 343:6675661fa600 3547 #define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */
rgrover1 343:6675661fa600 3548 #define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */
rgrover1 343:6675661fa600 3549 #define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3550 #define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3551 #define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3552
rgrover1 343:6675661fa600 3553 /* Bit 11 : Protection enable for region 43. */
rgrover1 343:6675661fa600 3554 #define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */
rgrover1 343:6675661fa600 3555 #define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */
rgrover1 343:6675661fa600 3556 #define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3557 #define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3558 #define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3559
rgrover1 343:6675661fa600 3560 /* Bit 10 : Protection enable for region 42. */
rgrover1 343:6675661fa600 3561 #define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */
rgrover1 343:6675661fa600 3562 #define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */
rgrover1 343:6675661fa600 3563 #define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3564 #define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3565 #define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3566
rgrover1 343:6675661fa600 3567 /* Bit 9 : Protection enable for region 41. */
rgrover1 343:6675661fa600 3568 #define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */
rgrover1 343:6675661fa600 3569 #define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */
rgrover1 343:6675661fa600 3570 #define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3571 #define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3572 #define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3573
rgrover1 343:6675661fa600 3574 /* Bit 8 : Protection enable for region 40. */
rgrover1 343:6675661fa600 3575 #define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */
rgrover1 343:6675661fa600 3576 #define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */
rgrover1 343:6675661fa600 3577 #define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3578 #define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3579 #define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3580
rgrover1 343:6675661fa600 3581 /* Bit 7 : Protection enable for region 39. */
rgrover1 343:6675661fa600 3582 #define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */
rgrover1 343:6675661fa600 3583 #define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */
rgrover1 343:6675661fa600 3584 #define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3585 #define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3586 #define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3587
rgrover1 343:6675661fa600 3588 /* Bit 6 : Protection enable for region 38. */
rgrover1 343:6675661fa600 3589 #define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */
rgrover1 343:6675661fa600 3590 #define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */
rgrover1 343:6675661fa600 3591 #define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3592 #define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3593 #define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3594
rgrover1 343:6675661fa600 3595 /* Bit 5 : Protection enable for region 37. */
rgrover1 343:6675661fa600 3596 #define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */
rgrover1 343:6675661fa600 3597 #define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */
rgrover1 343:6675661fa600 3598 #define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3599 #define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3600 #define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3601
rgrover1 343:6675661fa600 3602 /* Bit 4 : Protection enable for region 36. */
rgrover1 343:6675661fa600 3603 #define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */
rgrover1 343:6675661fa600 3604 #define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */
rgrover1 343:6675661fa600 3605 #define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3606 #define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3607 #define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3608
rgrover1 343:6675661fa600 3609 /* Bit 3 : Protection enable for region 35. */
rgrover1 343:6675661fa600 3610 #define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */
rgrover1 343:6675661fa600 3611 #define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */
rgrover1 343:6675661fa600 3612 #define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3613 #define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3614 #define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3615
rgrover1 343:6675661fa600 3616 /* Bit 2 : Protection enable for region 34. */
rgrover1 343:6675661fa600 3617 #define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */
rgrover1 343:6675661fa600 3618 #define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */
rgrover1 343:6675661fa600 3619 #define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3620 #define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3621 #define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3622
rgrover1 343:6675661fa600 3623 /* Bit 1 : Protection enable for region 33. */
rgrover1 343:6675661fa600 3624 #define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */
rgrover1 343:6675661fa600 3625 #define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */
rgrover1 343:6675661fa600 3626 #define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3627 #define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3628 #define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3629
rgrover1 343:6675661fa600 3630 /* Bit 0 : Protection enable for region 32. */
rgrover1 343:6675661fa600 3631 #define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */
rgrover1 343:6675661fa600 3632 #define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */
rgrover1 343:6675661fa600 3633 #define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3634 #define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3635 #define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */
rgrover1 343:6675661fa600 3636
rgrover1 343:6675661fa600 3637 /* Register: MPU_DISABLEINDEBUG */
rgrover1 343:6675661fa600 3638 /* Description: Disable erase and write protection mechanism in debug mode. */
rgrover1 343:6675661fa600 3639
rgrover1 343:6675661fa600 3640 /* Bit 0 : Disable protection mechanism in debug mode. */
rgrover1 343:6675661fa600 3641 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
rgrover1 343:6675661fa600 3642 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
rgrover1 343:6675661fa600 3643 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */
rgrover1 343:6675661fa600 3644 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */
rgrover1 343:6675661fa600 3645
rgrover1 343:6675661fa600 3646 /* Register: MPU_PROTBLOCKSIZE */
rgrover1 343:6675661fa600 3647 /* Description: Erase and write protection block size. */
rgrover1 343:6675661fa600 3648
rgrover1 343:6675661fa600 3649 /* Bits 1..0 : Erase and write protection block size. */
rgrover1 343:6675661fa600 3650 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */
rgrover1 343:6675661fa600 3651 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */
rgrover1 343:6675661fa600 3652 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */
rgrover1 343:6675661fa600 3653
rgrover1 343:6675661fa600 3654
rgrover1 343:6675661fa600 3655 /* Peripheral: NVMC */
rgrover1 343:6675661fa600 3656 /* Description: Non Volatile Memory Controller. */
rgrover1 343:6675661fa600 3657
rgrover1 343:6675661fa600 3658 /* Register: NVMC_READY */
rgrover1 343:6675661fa600 3659 /* Description: Ready flag. */
rgrover1 343:6675661fa600 3660
rgrover1 343:6675661fa600 3661 /* Bit 0 : NVMC ready. */
rgrover1 343:6675661fa600 3662 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
rgrover1 343:6675661fa600 3663 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
rgrover1 343:6675661fa600 3664 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */
rgrover1 343:6675661fa600 3665 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */
rgrover1 343:6675661fa600 3666
rgrover1 343:6675661fa600 3667 /* Register: NVMC_CONFIG */
rgrover1 343:6675661fa600 3668 /* Description: Configuration register. */
rgrover1 343:6675661fa600 3669
rgrover1 343:6675661fa600 3670 /* Bits 1..0 : Program write enable. */
rgrover1 343:6675661fa600 3671 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
rgrover1 343:6675661fa600 3672 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
rgrover1 343:6675661fa600 3673 #define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */
rgrover1 343:6675661fa600 3674 #define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */
rgrover1 343:6675661fa600 3675 #define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */
rgrover1 343:6675661fa600 3676
rgrover1 343:6675661fa600 3677 /* Register: NVMC_ERASEALL */
rgrover1 343:6675661fa600 3678 /* Description: Register for erasing all non-volatile user memory. */
rgrover1 343:6675661fa600 3679
rgrover1 343:6675661fa600 3680 /* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
rgrover1 343:6675661fa600 3681 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
rgrover1 343:6675661fa600 3682 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
rgrover1 343:6675661fa600 3683 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */
rgrover1 343:6675661fa600 3684 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */
rgrover1 343:6675661fa600 3685
rgrover1 343:6675661fa600 3686 /* Register: NVMC_ERASEUICR */
rgrover1 343:6675661fa600 3687 /* Description: Register for start erasing User Information Congfiguration Registers. */
rgrover1 343:6675661fa600 3688
rgrover1 343:6675661fa600 3689 /* Bit 0 : It can only be used when all contents of code region 1 are erased. */
rgrover1 343:6675661fa600 3690 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
rgrover1 343:6675661fa600 3691 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
rgrover1 343:6675661fa600 3692 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */
rgrover1 343:6675661fa600 3693 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */
rgrover1 343:6675661fa600 3694
rgrover1 343:6675661fa600 3695
rgrover1 343:6675661fa600 3696 /* Peripheral: POWER */
rgrover1 343:6675661fa600 3697 /* Description: Power Control. */
rgrover1 343:6675661fa600 3698
rgrover1 343:6675661fa600 3699 /* Register: POWER_INTENSET */
rgrover1 343:6675661fa600 3700 /* Description: Interrupt enable set register. */
rgrover1 343:6675661fa600 3701
rgrover1 343:6675661fa600 3702 /* Bit 2 : Enable interrupt on POFWARN event. */
rgrover1 343:6675661fa600 3703 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
rgrover1 343:6675661fa600 3704 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
rgrover1 343:6675661fa600 3705 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 3706 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 3707 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 3708
rgrover1 343:6675661fa600 3709 /* Register: POWER_INTENCLR */
rgrover1 343:6675661fa600 3710 /* Description: Interrupt enable clear register. */
rgrover1 343:6675661fa600 3711
rgrover1 343:6675661fa600 3712 /* Bit 2 : Disable interrupt on POFWARN event. */
rgrover1 343:6675661fa600 3713 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
rgrover1 343:6675661fa600 3714 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
rgrover1 343:6675661fa600 3715 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 3716 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 3717 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 3718
rgrover1 343:6675661fa600 3719 /* Register: POWER_RESETREAS */
rgrover1 343:6675661fa600 3720 /* Description: Reset reason. */
rgrover1 343:6675661fa600 3721
rgrover1 343:6675661fa600 3722 /* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
rgrover1 343:6675661fa600 3723 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
rgrover1 343:6675661fa600 3724 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
rgrover1 343:6675661fa600 3725
rgrover1 343:6675661fa600 3726 /* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
rgrover1 343:6675661fa600 3727 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
rgrover1 343:6675661fa600 3728 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
rgrover1 343:6675661fa600 3729
rgrover1 343:6675661fa600 3730 /* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
rgrover1 343:6675661fa600 3731 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
rgrover1 343:6675661fa600 3732 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
rgrover1 343:6675661fa600 3733
rgrover1 343:6675661fa600 3734 /* Bit 3 : Reset from CPU lock-up detected. */
rgrover1 343:6675661fa600 3735 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
rgrover1 343:6675661fa600 3736 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
rgrover1 343:6675661fa600 3737
rgrover1 343:6675661fa600 3738 /* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
rgrover1 343:6675661fa600 3739 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
rgrover1 343:6675661fa600 3740 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
rgrover1 343:6675661fa600 3741
rgrover1 343:6675661fa600 3742 /* Bit 1 : Reset from watchdog detected. */
rgrover1 343:6675661fa600 3743 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
rgrover1 343:6675661fa600 3744 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
rgrover1 343:6675661fa600 3745
rgrover1 343:6675661fa600 3746 /* Bit 0 : Reset from pin-reset detected. */
rgrover1 343:6675661fa600 3747 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
rgrover1 343:6675661fa600 3748 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
rgrover1 343:6675661fa600 3749
rgrover1 343:6675661fa600 3750 /* Register: POWER_RAMSTATUS */
rgrover1 343:6675661fa600 3751 /* Description: Ram status register. */
rgrover1 343:6675661fa600 3752
rgrover1 343:6675661fa600 3753 /* Bit 3 : RAM block 3 status. */
rgrover1 343:6675661fa600 3754 #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
rgrover1 343:6675661fa600 3755 #define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
rgrover1 343:6675661fa600 3756 #define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */
rgrover1 343:6675661fa600 3757 #define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */
rgrover1 343:6675661fa600 3758
rgrover1 343:6675661fa600 3759 /* Bit 2 : RAM block 2 status. */
rgrover1 343:6675661fa600 3760 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
rgrover1 343:6675661fa600 3761 #define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
rgrover1 343:6675661fa600 3762 #define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */
rgrover1 343:6675661fa600 3763 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */
rgrover1 343:6675661fa600 3764
rgrover1 343:6675661fa600 3765 /* Bit 1 : RAM block 1 status. */
rgrover1 343:6675661fa600 3766 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
rgrover1 343:6675661fa600 3767 #define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
rgrover1 343:6675661fa600 3768 #define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */
rgrover1 343:6675661fa600 3769 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */
rgrover1 343:6675661fa600 3770
rgrover1 343:6675661fa600 3771 /* Bit 0 : RAM block 0 status. */
rgrover1 343:6675661fa600 3772 #define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
rgrover1 343:6675661fa600 3773 #define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
rgrover1 343:6675661fa600 3774 #define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */
rgrover1 343:6675661fa600 3775 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */
rgrover1 343:6675661fa600 3776
rgrover1 343:6675661fa600 3777 /* Register: POWER_SYSTEMOFF */
rgrover1 343:6675661fa600 3778 /* Description: System off register. */
rgrover1 343:6675661fa600 3779
rgrover1 343:6675661fa600 3780 /* Bit 0 : Enter system off mode. */
rgrover1 343:6675661fa600 3781 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
rgrover1 343:6675661fa600 3782 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
rgrover1 343:6675661fa600 3783 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */
rgrover1 343:6675661fa600 3784
rgrover1 343:6675661fa600 3785 /* Register: POWER_POFCON */
rgrover1 343:6675661fa600 3786 /* Description: Power failure configuration. */
rgrover1 343:6675661fa600 3787
rgrover1 343:6675661fa600 3788 /* Bits 2..1 : Set threshold level. */
rgrover1 343:6675661fa600 3789 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
rgrover1 343:6675661fa600 3790 #define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
rgrover1 343:6675661fa600 3791 #define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */
rgrover1 343:6675661fa600 3792 #define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */
rgrover1 343:6675661fa600 3793 #define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */
rgrover1 343:6675661fa600 3794 #define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */
rgrover1 343:6675661fa600 3795
rgrover1 343:6675661fa600 3796 /* Bit 0 : Power failure comparator enable. */
rgrover1 343:6675661fa600 3797 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
rgrover1 343:6675661fa600 3798 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
rgrover1 343:6675661fa600 3799 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */
rgrover1 343:6675661fa600 3800 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */
rgrover1 343:6675661fa600 3801
rgrover1 343:6675661fa600 3802 /* Register: POWER_GPREGRET */
rgrover1 343:6675661fa600 3803 /* Description: General purpose retention register. This register is a retained register. */
rgrover1 343:6675661fa600 3804
rgrover1 343:6675661fa600 3805 /* Bits 7..0 : General purpose retention register. */
rgrover1 343:6675661fa600 3806 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
rgrover1 343:6675661fa600 3807 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
rgrover1 343:6675661fa600 3808
rgrover1 343:6675661fa600 3809 /* Register: POWER_RAMON */
rgrover1 343:6675661fa600 3810 /* Description: Ram on/off. */
rgrover1 343:6675661fa600 3811
rgrover1 343:6675661fa600 3812 /* Bit 17 : RAM block 1 behaviour in OFF mode. */
rgrover1 343:6675661fa600 3813 #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
rgrover1 343:6675661fa600 3814 #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
rgrover1 343:6675661fa600 3815 #define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */
rgrover1 343:6675661fa600 3816 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */
rgrover1 343:6675661fa600 3817
rgrover1 343:6675661fa600 3818 /* Bit 16 : RAM block 0 behaviour in OFF mode. */
rgrover1 343:6675661fa600 3819 #define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
rgrover1 343:6675661fa600 3820 #define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
rgrover1 343:6675661fa600 3821 #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */
rgrover1 343:6675661fa600 3822 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */
rgrover1 343:6675661fa600 3823
rgrover1 343:6675661fa600 3824 /* Bit 1 : RAM block 1 behaviour in ON mode. */
rgrover1 343:6675661fa600 3825 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
rgrover1 343:6675661fa600 3826 #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
rgrover1 343:6675661fa600 3827 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */
rgrover1 343:6675661fa600 3828 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */
rgrover1 343:6675661fa600 3829
rgrover1 343:6675661fa600 3830 /* Bit 0 : RAM block 0 behaviour in ON mode. */
rgrover1 343:6675661fa600 3831 #define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
rgrover1 343:6675661fa600 3832 #define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
rgrover1 343:6675661fa600 3833 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */
rgrover1 343:6675661fa600 3834 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */
rgrover1 343:6675661fa600 3835
rgrover1 343:6675661fa600 3836 /* Register: POWER_RESET */
rgrover1 343:6675661fa600 3837 /* Description: Pin reset functionality configuration register. This register is a retained register. */
rgrover1 343:6675661fa600 3838
rgrover1 343:6675661fa600 3839 /* Bit 0 : Enable or disable pin reset in debug interface mode. */
rgrover1 343:6675661fa600 3840 #define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
rgrover1 343:6675661fa600 3841 #define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
rgrover1 343:6675661fa600 3842 #define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */
rgrover1 343:6675661fa600 3843 #define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */
rgrover1 343:6675661fa600 3844
rgrover1 343:6675661fa600 3845 /* Register: POWER_RAMONB */
rgrover1 343:6675661fa600 3846 /* Description: Ram on/off. */
rgrover1 343:6675661fa600 3847
rgrover1 343:6675661fa600 3848 /* Bit 17 : RAM block 3 behaviour in OFF mode. */
rgrover1 343:6675661fa600 3849 #define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
rgrover1 343:6675661fa600 3850 #define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
rgrover1 343:6675661fa600 3851 #define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */
rgrover1 343:6675661fa600 3852 #define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */
rgrover1 343:6675661fa600 3853
rgrover1 343:6675661fa600 3854 /* Bit 16 : RAM block 2 behaviour in OFF mode. */
rgrover1 343:6675661fa600 3855 #define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
rgrover1 343:6675661fa600 3856 #define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
rgrover1 343:6675661fa600 3857 #define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */
rgrover1 343:6675661fa600 3858 #define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */
rgrover1 343:6675661fa600 3859
rgrover1 343:6675661fa600 3860 /* Bit 1 : RAM block 3 behaviour in ON mode. */
rgrover1 343:6675661fa600 3861 #define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
rgrover1 343:6675661fa600 3862 #define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
rgrover1 343:6675661fa600 3863 #define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */
rgrover1 343:6675661fa600 3864 #define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */
rgrover1 343:6675661fa600 3865
rgrover1 343:6675661fa600 3866 /* Bit 0 : RAM block 2 behaviour in ON mode. */
rgrover1 343:6675661fa600 3867 #define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
rgrover1 343:6675661fa600 3868 #define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
rgrover1 343:6675661fa600 3869 #define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */
rgrover1 343:6675661fa600 3870 #define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */
rgrover1 343:6675661fa600 3871
rgrover1 343:6675661fa600 3872 /* Register: POWER_DCDCEN */
rgrover1 343:6675661fa600 3873 /* Description: DCDC converter enable configuration register. */
rgrover1 343:6675661fa600 3874
rgrover1 343:6675661fa600 3875 /* Bit 0 : Enable DCDC converter. */
rgrover1 343:6675661fa600 3876 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
rgrover1 343:6675661fa600 3877 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
rgrover1 343:6675661fa600 3878 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */
rgrover1 343:6675661fa600 3879 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */
rgrover1 343:6675661fa600 3880
rgrover1 343:6675661fa600 3881 /* Register: POWER_DCDCFORCE */
rgrover1 343:6675661fa600 3882 /* Description: DCDC power-up force register. */
rgrover1 343:6675661fa600 3883
rgrover1 343:6675661fa600 3884 /* Bit 1 : DCDC power-up force on. */
rgrover1 343:6675661fa600 3885 #define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */
rgrover1 343:6675661fa600 3886 #define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */
rgrover1 343:6675661fa600 3887 #define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */
rgrover1 343:6675661fa600 3888 #define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */
rgrover1 343:6675661fa600 3889
rgrover1 343:6675661fa600 3890 /* Bit 0 : DCDC power-up force off. */
rgrover1 343:6675661fa600 3891 #define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */
rgrover1 343:6675661fa600 3892 #define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */
rgrover1 343:6675661fa600 3893 #define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */
rgrover1 343:6675661fa600 3894 #define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */
rgrover1 343:6675661fa600 3895
rgrover1 343:6675661fa600 3896
rgrover1 343:6675661fa600 3897 /* Peripheral: PPI */
rgrover1 343:6675661fa600 3898 /* Description: PPI controller. */
rgrover1 343:6675661fa600 3899
rgrover1 343:6675661fa600 3900 /* Register: PPI_CHEN */
rgrover1 343:6675661fa600 3901 /* Description: Channel enable. */
rgrover1 343:6675661fa600 3902
rgrover1 343:6675661fa600 3903 /* Bit 31 : Enable PPI channel 31. */
rgrover1 343:6675661fa600 3904 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
rgrover1 343:6675661fa600 3905 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
rgrover1 343:6675661fa600 3906 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 3907 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 3908
rgrover1 343:6675661fa600 3909 /* Bit 30 : Enable PPI channel 30. */
rgrover1 343:6675661fa600 3910 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
rgrover1 343:6675661fa600 3911 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
rgrover1 343:6675661fa600 3912 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 3913 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 3914
rgrover1 343:6675661fa600 3915 /* Bit 29 : Enable PPI channel 29. */
rgrover1 343:6675661fa600 3916 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
rgrover1 343:6675661fa600 3917 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
rgrover1 343:6675661fa600 3918 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 3919 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 3920
rgrover1 343:6675661fa600 3921 /* Bit 28 : Enable PPI channel 28. */
rgrover1 343:6675661fa600 3922 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
rgrover1 343:6675661fa600 3923 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
rgrover1 343:6675661fa600 3924 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 3925 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 3926
rgrover1 343:6675661fa600 3927 /* Bit 27 : Enable PPI channel 27. */
rgrover1 343:6675661fa600 3928 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
rgrover1 343:6675661fa600 3929 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
rgrover1 343:6675661fa600 3930 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 3931 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 3932
rgrover1 343:6675661fa600 3933 /* Bit 26 : Enable PPI channel 26. */
rgrover1 343:6675661fa600 3934 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
rgrover1 343:6675661fa600 3935 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
rgrover1 343:6675661fa600 3936 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 3937 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 3938
rgrover1 343:6675661fa600 3939 /* Bit 25 : Enable PPI channel 25. */
rgrover1 343:6675661fa600 3940 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
rgrover1 343:6675661fa600 3941 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
rgrover1 343:6675661fa600 3942 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 3943 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 3944
rgrover1 343:6675661fa600 3945 /* Bit 24 : Enable PPI channel 24. */
rgrover1 343:6675661fa600 3946 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
rgrover1 343:6675661fa600 3947 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
rgrover1 343:6675661fa600 3948 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 3949 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 3950
rgrover1 343:6675661fa600 3951 /* Bit 23 : Enable PPI channel 23. */
rgrover1 343:6675661fa600 3952 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
rgrover1 343:6675661fa600 3953 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
rgrover1 343:6675661fa600 3954 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 3955 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 3956
rgrover1 343:6675661fa600 3957 /* Bit 22 : Enable PPI channel 22. */
rgrover1 343:6675661fa600 3958 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
rgrover1 343:6675661fa600 3959 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
rgrover1 343:6675661fa600 3960 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 3961 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 3962
rgrover1 343:6675661fa600 3963 /* Bit 21 : Enable PPI channel 21. */
rgrover1 343:6675661fa600 3964 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
rgrover1 343:6675661fa600 3965 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
rgrover1 343:6675661fa600 3966 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 3967 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 3968
rgrover1 343:6675661fa600 3969 /* Bit 20 : Enable PPI channel 20. */
rgrover1 343:6675661fa600 3970 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
rgrover1 343:6675661fa600 3971 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
rgrover1 343:6675661fa600 3972 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 3973 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 3974
rgrover1 343:6675661fa600 3975 /* Bit 15 : Enable PPI channel 15. */
rgrover1 343:6675661fa600 3976 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
rgrover1 343:6675661fa600 3977 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
rgrover1 343:6675661fa600 3978 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 3979 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 3980
rgrover1 343:6675661fa600 3981 /* Bit 14 : Enable PPI channel 14. */
rgrover1 343:6675661fa600 3982 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
rgrover1 343:6675661fa600 3983 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
rgrover1 343:6675661fa600 3984 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 3985 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 3986
rgrover1 343:6675661fa600 3987 /* Bit 13 : Enable PPI channel 13. */
rgrover1 343:6675661fa600 3988 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
rgrover1 343:6675661fa600 3989 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
rgrover1 343:6675661fa600 3990 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 3991 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 3992
rgrover1 343:6675661fa600 3993 /* Bit 12 : Enable PPI channel 12. */
rgrover1 343:6675661fa600 3994 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
rgrover1 343:6675661fa600 3995 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
rgrover1 343:6675661fa600 3996 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 3997 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 3998
rgrover1 343:6675661fa600 3999 /* Bit 11 : Enable PPI channel 11. */
rgrover1 343:6675661fa600 4000 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
rgrover1 343:6675661fa600 4001 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
rgrover1 343:6675661fa600 4002 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4003 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4004
rgrover1 343:6675661fa600 4005 /* Bit 10 : Enable PPI channel 10. */
rgrover1 343:6675661fa600 4006 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
rgrover1 343:6675661fa600 4007 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
rgrover1 343:6675661fa600 4008 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4009 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4010
rgrover1 343:6675661fa600 4011 /* Bit 9 : Enable PPI channel 9. */
rgrover1 343:6675661fa600 4012 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
rgrover1 343:6675661fa600 4013 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
rgrover1 343:6675661fa600 4014 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4015 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4016
rgrover1 343:6675661fa600 4017 /* Bit 8 : Enable PPI channel 8. */
rgrover1 343:6675661fa600 4018 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
rgrover1 343:6675661fa600 4019 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
rgrover1 343:6675661fa600 4020 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4021 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4022
rgrover1 343:6675661fa600 4023 /* Bit 7 : Enable PPI channel 7. */
rgrover1 343:6675661fa600 4024 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
rgrover1 343:6675661fa600 4025 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
rgrover1 343:6675661fa600 4026 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4027 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4028
rgrover1 343:6675661fa600 4029 /* Bit 6 : Enable PPI channel 6. */
rgrover1 343:6675661fa600 4030 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
rgrover1 343:6675661fa600 4031 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
rgrover1 343:6675661fa600 4032 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4033 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4034
rgrover1 343:6675661fa600 4035 /* Bit 5 : Enable PPI channel 5. */
rgrover1 343:6675661fa600 4036 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
rgrover1 343:6675661fa600 4037 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
rgrover1 343:6675661fa600 4038 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4039 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4040
rgrover1 343:6675661fa600 4041 /* Bit 4 : Enable PPI channel 4. */
rgrover1 343:6675661fa600 4042 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
rgrover1 343:6675661fa600 4043 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
rgrover1 343:6675661fa600 4044 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4045 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4046
rgrover1 343:6675661fa600 4047 /* Bit 3 : Enable PPI channel 3. */
rgrover1 343:6675661fa600 4048 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
rgrover1 343:6675661fa600 4049 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
rgrover1 343:6675661fa600 4050 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */
rgrover1 343:6675661fa600 4051 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */
rgrover1 343:6675661fa600 4052
rgrover1 343:6675661fa600 4053 /* Bit 2 : Enable PPI channel 2. */
rgrover1 343:6675661fa600 4054 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
rgrover1 343:6675661fa600 4055 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
rgrover1 343:6675661fa600 4056 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4057 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4058
rgrover1 343:6675661fa600 4059 /* Bit 1 : Enable PPI channel 1. */
rgrover1 343:6675661fa600 4060 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
rgrover1 343:6675661fa600 4061 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
rgrover1 343:6675661fa600 4062 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4063 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4064
rgrover1 343:6675661fa600 4065 /* Bit 0 : Enable PPI channel 0. */
rgrover1 343:6675661fa600 4066 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
rgrover1 343:6675661fa600 4067 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
rgrover1 343:6675661fa600 4068 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4069 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4070
rgrover1 343:6675661fa600 4071 /* Register: PPI_CHENSET */
rgrover1 343:6675661fa600 4072 /* Description: Channel enable set. */
rgrover1 343:6675661fa600 4073
rgrover1 343:6675661fa600 4074 /* Bit 31 : Enable PPI channel 31. */
rgrover1 343:6675661fa600 4075 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
rgrover1 343:6675661fa600 4076 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
rgrover1 343:6675661fa600 4077 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4078 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4079 #define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4080
rgrover1 343:6675661fa600 4081 /* Bit 30 : Enable PPI channel 30. */
rgrover1 343:6675661fa600 4082 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
rgrover1 343:6675661fa600 4083 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
rgrover1 343:6675661fa600 4084 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4085 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4086 #define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4087
rgrover1 343:6675661fa600 4088 /* Bit 29 : Enable PPI channel 29. */
rgrover1 343:6675661fa600 4089 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
rgrover1 343:6675661fa600 4090 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
rgrover1 343:6675661fa600 4091 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4092 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4093 #define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4094
rgrover1 343:6675661fa600 4095 /* Bit 28 : Enable PPI channel 28. */
rgrover1 343:6675661fa600 4096 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
rgrover1 343:6675661fa600 4097 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
rgrover1 343:6675661fa600 4098 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4099 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4100 #define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4101
rgrover1 343:6675661fa600 4102 /* Bit 27 : Enable PPI channel 27. */
rgrover1 343:6675661fa600 4103 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
rgrover1 343:6675661fa600 4104 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
rgrover1 343:6675661fa600 4105 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4106 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4107 #define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4108
rgrover1 343:6675661fa600 4109 /* Bit 26 : Enable PPI channel 26. */
rgrover1 343:6675661fa600 4110 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
rgrover1 343:6675661fa600 4111 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
rgrover1 343:6675661fa600 4112 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4113 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4114 #define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4115
rgrover1 343:6675661fa600 4116 /* Bit 25 : Enable PPI channel 25. */
rgrover1 343:6675661fa600 4117 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
rgrover1 343:6675661fa600 4118 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
rgrover1 343:6675661fa600 4119 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4120 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4121 #define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4122
rgrover1 343:6675661fa600 4123 /* Bit 24 : Enable PPI channel 24. */
rgrover1 343:6675661fa600 4124 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
rgrover1 343:6675661fa600 4125 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
rgrover1 343:6675661fa600 4126 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4127 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4128 #define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4129
rgrover1 343:6675661fa600 4130 /* Bit 23 : Enable PPI channel 23. */
rgrover1 343:6675661fa600 4131 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
rgrover1 343:6675661fa600 4132 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
rgrover1 343:6675661fa600 4133 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4134 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4135 #define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4136
rgrover1 343:6675661fa600 4137 /* Bit 22 : Enable PPI channel 22. */
rgrover1 343:6675661fa600 4138 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
rgrover1 343:6675661fa600 4139 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
rgrover1 343:6675661fa600 4140 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4141 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4142 #define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4143
rgrover1 343:6675661fa600 4144 /* Bit 21 : Enable PPI channel 21. */
rgrover1 343:6675661fa600 4145 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
rgrover1 343:6675661fa600 4146 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
rgrover1 343:6675661fa600 4147 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4148 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4149 #define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4150
rgrover1 343:6675661fa600 4151 /* Bit 20 : Enable PPI channel 20. */
rgrover1 343:6675661fa600 4152 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
rgrover1 343:6675661fa600 4153 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
rgrover1 343:6675661fa600 4154 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4155 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4156 #define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4157
rgrover1 343:6675661fa600 4158 /* Bit 15 : Enable PPI channel 15. */
rgrover1 343:6675661fa600 4159 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
rgrover1 343:6675661fa600 4160 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
rgrover1 343:6675661fa600 4161 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4162 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4163 #define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4164
rgrover1 343:6675661fa600 4165 /* Bit 14 : Enable PPI channel 14. */
rgrover1 343:6675661fa600 4166 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
rgrover1 343:6675661fa600 4167 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
rgrover1 343:6675661fa600 4168 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4169 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4170 #define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4171
rgrover1 343:6675661fa600 4172 /* Bit 13 : Enable PPI channel 13. */
rgrover1 343:6675661fa600 4173 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
rgrover1 343:6675661fa600 4174 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
rgrover1 343:6675661fa600 4175 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4176 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4177 #define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4178
rgrover1 343:6675661fa600 4179 /* Bit 12 : Enable PPI channel 12. */
rgrover1 343:6675661fa600 4180 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
rgrover1 343:6675661fa600 4181 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
rgrover1 343:6675661fa600 4182 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4183 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4184 #define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4185
rgrover1 343:6675661fa600 4186 /* Bit 11 : Enable PPI channel 11. */
rgrover1 343:6675661fa600 4187 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
rgrover1 343:6675661fa600 4188 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
rgrover1 343:6675661fa600 4189 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4190 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4191 #define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4192
rgrover1 343:6675661fa600 4193 /* Bit 10 : Enable PPI channel 10. */
rgrover1 343:6675661fa600 4194 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
rgrover1 343:6675661fa600 4195 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
rgrover1 343:6675661fa600 4196 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4197 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4198 #define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4199
rgrover1 343:6675661fa600 4200 /* Bit 9 : Enable PPI channel 9. */
rgrover1 343:6675661fa600 4201 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
rgrover1 343:6675661fa600 4202 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
rgrover1 343:6675661fa600 4203 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4204 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4205 #define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4206
rgrover1 343:6675661fa600 4207 /* Bit 8 : Enable PPI channel 8. */
rgrover1 343:6675661fa600 4208 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
rgrover1 343:6675661fa600 4209 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
rgrover1 343:6675661fa600 4210 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4211 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4212 #define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4213
rgrover1 343:6675661fa600 4214 /* Bit 7 : Enable PPI channel 7. */
rgrover1 343:6675661fa600 4215 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
rgrover1 343:6675661fa600 4216 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
rgrover1 343:6675661fa600 4217 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4218 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4219 #define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4220
rgrover1 343:6675661fa600 4221 /* Bit 6 : Enable PPI channel 6. */
rgrover1 343:6675661fa600 4222 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
rgrover1 343:6675661fa600 4223 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
rgrover1 343:6675661fa600 4224 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4225 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4226 #define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4227
rgrover1 343:6675661fa600 4228 /* Bit 5 : Enable PPI channel 5. */
rgrover1 343:6675661fa600 4229 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
rgrover1 343:6675661fa600 4230 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
rgrover1 343:6675661fa600 4231 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4232 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4233 #define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4234
rgrover1 343:6675661fa600 4235 /* Bit 4 : Enable PPI channel 4. */
rgrover1 343:6675661fa600 4236 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
rgrover1 343:6675661fa600 4237 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
rgrover1 343:6675661fa600 4238 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4239 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4240 #define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4241
rgrover1 343:6675661fa600 4242 /* Bit 3 : Enable PPI channel 3. */
rgrover1 343:6675661fa600 4243 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
rgrover1 343:6675661fa600 4244 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
rgrover1 343:6675661fa600 4245 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4246 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4247 #define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4248
rgrover1 343:6675661fa600 4249 /* Bit 2 : Enable PPI channel 2. */
rgrover1 343:6675661fa600 4250 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
rgrover1 343:6675661fa600 4251 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
rgrover1 343:6675661fa600 4252 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4253 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4254 #define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4255
rgrover1 343:6675661fa600 4256 /* Bit 1 : Enable PPI channel 1. */
rgrover1 343:6675661fa600 4257 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
rgrover1 343:6675661fa600 4258 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
rgrover1 343:6675661fa600 4259 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4260 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4261 #define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4262
rgrover1 343:6675661fa600 4263 /* Bit 0 : Enable PPI channel 0. */
rgrover1 343:6675661fa600 4264 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
rgrover1 343:6675661fa600 4265 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
rgrover1 343:6675661fa600 4266 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4267 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4268 #define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */
rgrover1 343:6675661fa600 4269
rgrover1 343:6675661fa600 4270 /* Register: PPI_CHENCLR */
rgrover1 343:6675661fa600 4271 /* Description: Channel enable clear. */
rgrover1 343:6675661fa600 4272
rgrover1 343:6675661fa600 4273 /* Bit 31 : Disable PPI channel 31. */
rgrover1 343:6675661fa600 4274 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
rgrover1 343:6675661fa600 4275 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
rgrover1 343:6675661fa600 4276 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4277 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4278 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4279
rgrover1 343:6675661fa600 4280 /* Bit 30 : Disable PPI channel 30. */
rgrover1 343:6675661fa600 4281 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
rgrover1 343:6675661fa600 4282 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
rgrover1 343:6675661fa600 4283 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4284 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4285 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4286
rgrover1 343:6675661fa600 4287 /* Bit 29 : Disable PPI channel 29. */
rgrover1 343:6675661fa600 4288 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
rgrover1 343:6675661fa600 4289 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
rgrover1 343:6675661fa600 4290 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4291 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4292 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4293
rgrover1 343:6675661fa600 4294 /* Bit 28 : Disable PPI channel 28. */
rgrover1 343:6675661fa600 4295 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
rgrover1 343:6675661fa600 4296 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
rgrover1 343:6675661fa600 4297 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4298 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4299 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4300
rgrover1 343:6675661fa600 4301 /* Bit 27 : Disable PPI channel 27. */
rgrover1 343:6675661fa600 4302 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
rgrover1 343:6675661fa600 4303 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
rgrover1 343:6675661fa600 4304 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4305 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4306 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4307
rgrover1 343:6675661fa600 4308 /* Bit 26 : Disable PPI channel 26. */
rgrover1 343:6675661fa600 4309 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
rgrover1 343:6675661fa600 4310 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
rgrover1 343:6675661fa600 4311 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4312 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4313 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4314
rgrover1 343:6675661fa600 4315 /* Bit 25 : Disable PPI channel 25. */
rgrover1 343:6675661fa600 4316 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
rgrover1 343:6675661fa600 4317 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
rgrover1 343:6675661fa600 4318 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4319 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4320 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4321
rgrover1 343:6675661fa600 4322 /* Bit 24 : Disable PPI channel 24. */
rgrover1 343:6675661fa600 4323 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
rgrover1 343:6675661fa600 4324 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
rgrover1 343:6675661fa600 4325 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4326 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4327 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4328
rgrover1 343:6675661fa600 4329 /* Bit 23 : Disable PPI channel 23. */
rgrover1 343:6675661fa600 4330 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
rgrover1 343:6675661fa600 4331 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
rgrover1 343:6675661fa600 4332 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4333 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4334 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4335
rgrover1 343:6675661fa600 4336 /* Bit 22 : Disable PPI channel 22. */
rgrover1 343:6675661fa600 4337 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
rgrover1 343:6675661fa600 4338 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
rgrover1 343:6675661fa600 4339 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4340 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4341 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4342
rgrover1 343:6675661fa600 4343 /* Bit 21 : Disable PPI channel 21. */
rgrover1 343:6675661fa600 4344 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
rgrover1 343:6675661fa600 4345 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
rgrover1 343:6675661fa600 4346 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4347 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4348 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4349
rgrover1 343:6675661fa600 4350 /* Bit 20 : Disable PPI channel 20. */
rgrover1 343:6675661fa600 4351 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
rgrover1 343:6675661fa600 4352 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
rgrover1 343:6675661fa600 4353 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4354 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4355 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4356
rgrover1 343:6675661fa600 4357 /* Bit 15 : Disable PPI channel 15. */
rgrover1 343:6675661fa600 4358 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
rgrover1 343:6675661fa600 4359 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
rgrover1 343:6675661fa600 4360 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4361 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4362 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4363
rgrover1 343:6675661fa600 4364 /* Bit 14 : Disable PPI channel 14. */
rgrover1 343:6675661fa600 4365 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
rgrover1 343:6675661fa600 4366 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
rgrover1 343:6675661fa600 4367 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4368 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4369 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4370
rgrover1 343:6675661fa600 4371 /* Bit 13 : Disable PPI channel 13. */
rgrover1 343:6675661fa600 4372 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
rgrover1 343:6675661fa600 4373 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
rgrover1 343:6675661fa600 4374 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4375 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4376 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4377
rgrover1 343:6675661fa600 4378 /* Bit 12 : Disable PPI channel 12. */
rgrover1 343:6675661fa600 4379 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
rgrover1 343:6675661fa600 4380 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
rgrover1 343:6675661fa600 4381 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4382 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4383 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4384
rgrover1 343:6675661fa600 4385 /* Bit 11 : Disable PPI channel 11. */
rgrover1 343:6675661fa600 4386 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
rgrover1 343:6675661fa600 4387 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
rgrover1 343:6675661fa600 4388 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4389 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4390 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4391
rgrover1 343:6675661fa600 4392 /* Bit 10 : Disable PPI channel 10. */
rgrover1 343:6675661fa600 4393 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
rgrover1 343:6675661fa600 4394 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
rgrover1 343:6675661fa600 4395 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4396 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4397 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4398
rgrover1 343:6675661fa600 4399 /* Bit 9 : Disable PPI channel 9. */
rgrover1 343:6675661fa600 4400 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
rgrover1 343:6675661fa600 4401 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
rgrover1 343:6675661fa600 4402 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4403 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4404 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4405
rgrover1 343:6675661fa600 4406 /* Bit 8 : Disable PPI channel 8. */
rgrover1 343:6675661fa600 4407 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
rgrover1 343:6675661fa600 4408 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
rgrover1 343:6675661fa600 4409 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4410 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4411 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4412
rgrover1 343:6675661fa600 4413 /* Bit 7 : Disable PPI channel 7. */
rgrover1 343:6675661fa600 4414 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
rgrover1 343:6675661fa600 4415 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
rgrover1 343:6675661fa600 4416 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4417 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4418 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4419
rgrover1 343:6675661fa600 4420 /* Bit 6 : Disable PPI channel 6. */
rgrover1 343:6675661fa600 4421 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
rgrover1 343:6675661fa600 4422 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
rgrover1 343:6675661fa600 4423 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4424 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4425 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4426
rgrover1 343:6675661fa600 4427 /* Bit 5 : Disable PPI channel 5. */
rgrover1 343:6675661fa600 4428 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
rgrover1 343:6675661fa600 4429 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
rgrover1 343:6675661fa600 4430 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4431 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4432 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4433
rgrover1 343:6675661fa600 4434 /* Bit 4 : Disable PPI channel 4. */
rgrover1 343:6675661fa600 4435 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
rgrover1 343:6675661fa600 4436 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
rgrover1 343:6675661fa600 4437 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4438 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4439 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4440
rgrover1 343:6675661fa600 4441 /* Bit 3 : Disable PPI channel 3. */
rgrover1 343:6675661fa600 4442 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
rgrover1 343:6675661fa600 4443 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
rgrover1 343:6675661fa600 4444 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4445 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4446 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4447
rgrover1 343:6675661fa600 4448 /* Bit 2 : Disable PPI channel 2. */
rgrover1 343:6675661fa600 4449 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
rgrover1 343:6675661fa600 4450 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
rgrover1 343:6675661fa600 4451 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4452 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4453 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4454
rgrover1 343:6675661fa600 4455 /* Bit 1 : Disable PPI channel 1. */
rgrover1 343:6675661fa600 4456 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
rgrover1 343:6675661fa600 4457 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
rgrover1 343:6675661fa600 4458 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4459 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4460 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4461
rgrover1 343:6675661fa600 4462 /* Bit 0 : Disable PPI channel 0. */
rgrover1 343:6675661fa600 4463 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
rgrover1 343:6675661fa600 4464 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
rgrover1 343:6675661fa600 4465 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */
rgrover1 343:6675661fa600 4466 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */
rgrover1 343:6675661fa600 4467 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */
rgrover1 343:6675661fa600 4468
rgrover1 343:6675661fa600 4469 /* Register: PPI_CHG */
rgrover1 343:6675661fa600 4470 /* Description: Channel group configuration. */
rgrover1 343:6675661fa600 4471
rgrover1 343:6675661fa600 4472 /* Bit 31 : Include CH31 in channel group. */
rgrover1 343:6675661fa600 4473 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
rgrover1 343:6675661fa600 4474 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
rgrover1 343:6675661fa600 4475 #define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4476 #define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4477
rgrover1 343:6675661fa600 4478 /* Bit 30 : Include CH30 in channel group. */
rgrover1 343:6675661fa600 4479 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
rgrover1 343:6675661fa600 4480 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
rgrover1 343:6675661fa600 4481 #define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4482 #define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4483
rgrover1 343:6675661fa600 4484 /* Bit 29 : Include CH29 in channel group. */
rgrover1 343:6675661fa600 4485 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
rgrover1 343:6675661fa600 4486 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
rgrover1 343:6675661fa600 4487 #define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4488 #define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4489
rgrover1 343:6675661fa600 4490 /* Bit 28 : Include CH28 in channel group. */
rgrover1 343:6675661fa600 4491 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
rgrover1 343:6675661fa600 4492 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
rgrover1 343:6675661fa600 4493 #define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4494 #define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4495
rgrover1 343:6675661fa600 4496 /* Bit 27 : Include CH27 in channel group. */
rgrover1 343:6675661fa600 4497 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
rgrover1 343:6675661fa600 4498 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
rgrover1 343:6675661fa600 4499 #define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4500 #define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4501
rgrover1 343:6675661fa600 4502 /* Bit 26 : Include CH26 in channel group. */
rgrover1 343:6675661fa600 4503 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
rgrover1 343:6675661fa600 4504 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
rgrover1 343:6675661fa600 4505 #define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4506 #define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4507
rgrover1 343:6675661fa600 4508 /* Bit 25 : Include CH25 in channel group. */
rgrover1 343:6675661fa600 4509 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
rgrover1 343:6675661fa600 4510 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
rgrover1 343:6675661fa600 4511 #define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4512 #define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4513
rgrover1 343:6675661fa600 4514 /* Bit 24 : Include CH24 in channel group. */
rgrover1 343:6675661fa600 4515 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
rgrover1 343:6675661fa600 4516 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
rgrover1 343:6675661fa600 4517 #define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4518 #define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4519
rgrover1 343:6675661fa600 4520 /* Bit 23 : Include CH23 in channel group. */
rgrover1 343:6675661fa600 4521 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
rgrover1 343:6675661fa600 4522 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
rgrover1 343:6675661fa600 4523 #define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4524 #define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4525
rgrover1 343:6675661fa600 4526 /* Bit 22 : Include CH22 in channel group. */
rgrover1 343:6675661fa600 4527 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
rgrover1 343:6675661fa600 4528 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
rgrover1 343:6675661fa600 4529 #define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4530 #define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4531
rgrover1 343:6675661fa600 4532 /* Bit 21 : Include CH21 in channel group. */
rgrover1 343:6675661fa600 4533 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
rgrover1 343:6675661fa600 4534 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
rgrover1 343:6675661fa600 4535 #define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4536 #define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4537
rgrover1 343:6675661fa600 4538 /* Bit 20 : Include CH20 in channel group. */
rgrover1 343:6675661fa600 4539 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
rgrover1 343:6675661fa600 4540 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
rgrover1 343:6675661fa600 4541 #define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4542 #define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4543
rgrover1 343:6675661fa600 4544 /* Bit 15 : Include CH15 in channel group. */
rgrover1 343:6675661fa600 4545 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
rgrover1 343:6675661fa600 4546 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
rgrover1 343:6675661fa600 4547 #define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4548 #define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4549
rgrover1 343:6675661fa600 4550 /* Bit 14 : Include CH14 in channel group. */
rgrover1 343:6675661fa600 4551 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
rgrover1 343:6675661fa600 4552 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
rgrover1 343:6675661fa600 4553 #define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4554 #define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4555
rgrover1 343:6675661fa600 4556 /* Bit 13 : Include CH13 in channel group. */
rgrover1 343:6675661fa600 4557 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
rgrover1 343:6675661fa600 4558 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
rgrover1 343:6675661fa600 4559 #define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4560 #define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4561
rgrover1 343:6675661fa600 4562 /* Bit 12 : Include CH12 in channel group. */
rgrover1 343:6675661fa600 4563 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
rgrover1 343:6675661fa600 4564 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
rgrover1 343:6675661fa600 4565 #define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4566 #define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4567
rgrover1 343:6675661fa600 4568 /* Bit 11 : Include CH11 in channel group. */
rgrover1 343:6675661fa600 4569 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
rgrover1 343:6675661fa600 4570 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
rgrover1 343:6675661fa600 4571 #define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4572 #define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4573
rgrover1 343:6675661fa600 4574 /* Bit 10 : Include CH10 in channel group. */
rgrover1 343:6675661fa600 4575 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
rgrover1 343:6675661fa600 4576 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
rgrover1 343:6675661fa600 4577 #define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4578 #define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4579
rgrover1 343:6675661fa600 4580 /* Bit 9 : Include CH9 in channel group. */
rgrover1 343:6675661fa600 4581 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
rgrover1 343:6675661fa600 4582 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
rgrover1 343:6675661fa600 4583 #define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4584 #define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4585
rgrover1 343:6675661fa600 4586 /* Bit 8 : Include CH8 in channel group. */
rgrover1 343:6675661fa600 4587 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
rgrover1 343:6675661fa600 4588 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
rgrover1 343:6675661fa600 4589 #define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4590 #define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4591
rgrover1 343:6675661fa600 4592 /* Bit 7 : Include CH7 in channel group. */
rgrover1 343:6675661fa600 4593 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
rgrover1 343:6675661fa600 4594 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
rgrover1 343:6675661fa600 4595 #define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4596 #define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4597
rgrover1 343:6675661fa600 4598 /* Bit 6 : Include CH6 in channel group. */
rgrover1 343:6675661fa600 4599 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
rgrover1 343:6675661fa600 4600 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
rgrover1 343:6675661fa600 4601 #define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4602 #define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4603
rgrover1 343:6675661fa600 4604 /* Bit 5 : Include CH5 in channel group. */
rgrover1 343:6675661fa600 4605 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
rgrover1 343:6675661fa600 4606 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
rgrover1 343:6675661fa600 4607 #define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4608 #define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4609
rgrover1 343:6675661fa600 4610 /* Bit 4 : Include CH4 in channel group. */
rgrover1 343:6675661fa600 4611 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
rgrover1 343:6675661fa600 4612 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
rgrover1 343:6675661fa600 4613 #define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4614 #define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4615
rgrover1 343:6675661fa600 4616 /* Bit 3 : Include CH3 in channel group. */
rgrover1 343:6675661fa600 4617 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
rgrover1 343:6675661fa600 4618 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
rgrover1 343:6675661fa600 4619 #define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4620 #define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4621
rgrover1 343:6675661fa600 4622 /* Bit 2 : Include CH2 in channel group. */
rgrover1 343:6675661fa600 4623 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
rgrover1 343:6675661fa600 4624 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
rgrover1 343:6675661fa600 4625 #define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4626 #define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4627
rgrover1 343:6675661fa600 4628 /* Bit 1 : Include CH1 in channel group. */
rgrover1 343:6675661fa600 4629 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
rgrover1 343:6675661fa600 4630 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
rgrover1 343:6675661fa600 4631 #define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4632 #define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4633
rgrover1 343:6675661fa600 4634 /* Bit 0 : Include CH0 in channel group. */
rgrover1 343:6675661fa600 4635 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
rgrover1 343:6675661fa600 4636 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
rgrover1 343:6675661fa600 4637 #define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */
rgrover1 343:6675661fa600 4638 #define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */
rgrover1 343:6675661fa600 4639
rgrover1 343:6675661fa600 4640
rgrover1 343:6675661fa600 4641 /* Peripheral: PU */
rgrover1 343:6675661fa600 4642 /* Description: Patch unit. */
rgrover1 343:6675661fa600 4643
rgrover1 343:6675661fa600 4644 /* Register: PU_PATCHADDR */
rgrover1 343:6675661fa600 4645 /* Description: Relative address of patch instructions. */
rgrover1 343:6675661fa600 4646
rgrover1 343:6675661fa600 4647 /* Bits 24..0 : Relative address of patch instructions. */
rgrover1 343:6675661fa600 4648 #define PU_PATCHADDR_PATCHADDR_Pos (0UL) /*!< Position of PATCHADDR field. */
rgrover1 343:6675661fa600 4649 #define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /*!< Bit mask of PATCHADDR field. */
rgrover1 343:6675661fa600 4650
rgrover1 343:6675661fa600 4651 /* Register: PU_PATCHEN */
rgrover1 343:6675661fa600 4652 /* Description: Patch enable register. */
rgrover1 343:6675661fa600 4653
rgrover1 343:6675661fa600 4654 /* Bit 7 : Patch 7 enabled. */
rgrover1 343:6675661fa600 4655 #define PU_PATCHEN_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
rgrover1 343:6675661fa600 4656 #define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
rgrover1 343:6675661fa600 4657 #define PU_PATCHEN_PATCH7_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4658 #define PU_PATCHEN_PATCH7_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4659
rgrover1 343:6675661fa600 4660 /* Bit 6 : Patch 6 enabled. */
rgrover1 343:6675661fa600 4661 #define PU_PATCHEN_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
rgrover1 343:6675661fa600 4662 #define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
rgrover1 343:6675661fa600 4663 #define PU_PATCHEN_PATCH6_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4664 #define PU_PATCHEN_PATCH6_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4665
rgrover1 343:6675661fa600 4666 /* Bit 5 : Patch 5 enabled. */
rgrover1 343:6675661fa600 4667 #define PU_PATCHEN_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
rgrover1 343:6675661fa600 4668 #define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
rgrover1 343:6675661fa600 4669 #define PU_PATCHEN_PATCH5_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4670 #define PU_PATCHEN_PATCH5_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4671
rgrover1 343:6675661fa600 4672 /* Bit 4 : Patch 4 enabled. */
rgrover1 343:6675661fa600 4673 #define PU_PATCHEN_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
rgrover1 343:6675661fa600 4674 #define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
rgrover1 343:6675661fa600 4675 #define PU_PATCHEN_PATCH4_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4676 #define PU_PATCHEN_PATCH4_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4677
rgrover1 343:6675661fa600 4678 /* Bit 3 : Patch 3 enabled. */
rgrover1 343:6675661fa600 4679 #define PU_PATCHEN_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
rgrover1 343:6675661fa600 4680 #define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
rgrover1 343:6675661fa600 4681 #define PU_PATCHEN_PATCH3_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4682 #define PU_PATCHEN_PATCH3_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4683
rgrover1 343:6675661fa600 4684 /* Bit 2 : Patch 2 enabled. */
rgrover1 343:6675661fa600 4685 #define PU_PATCHEN_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
rgrover1 343:6675661fa600 4686 #define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
rgrover1 343:6675661fa600 4687 #define PU_PATCHEN_PATCH2_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4688 #define PU_PATCHEN_PATCH2_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4689
rgrover1 343:6675661fa600 4690 /* Bit 1 : Patch 1 enabled. */
rgrover1 343:6675661fa600 4691 #define PU_PATCHEN_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
rgrover1 343:6675661fa600 4692 #define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
rgrover1 343:6675661fa600 4693 #define PU_PATCHEN_PATCH1_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4694 #define PU_PATCHEN_PATCH1_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4695
rgrover1 343:6675661fa600 4696 /* Bit 0 : Patch 0 enabled. */
rgrover1 343:6675661fa600 4697 #define PU_PATCHEN_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
rgrover1 343:6675661fa600 4698 #define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
rgrover1 343:6675661fa600 4699 #define PU_PATCHEN_PATCH0_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4700 #define PU_PATCHEN_PATCH0_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4701
rgrover1 343:6675661fa600 4702 /* Register: PU_PATCHENSET */
rgrover1 343:6675661fa600 4703 /* Description: Patch enable register. */
rgrover1 343:6675661fa600 4704
rgrover1 343:6675661fa600 4705 /* Bit 7 : Patch 7 enabled. */
rgrover1 343:6675661fa600 4706 #define PU_PATCHENSET_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
rgrover1 343:6675661fa600 4707 #define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
rgrover1 343:6675661fa600 4708 #define PU_PATCHENSET_PATCH7_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4709 #define PU_PATCHENSET_PATCH7_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4710 #define PU_PATCHENSET_PATCH7_Set (1UL) /*!< Enable patch on write. */
rgrover1 343:6675661fa600 4711
rgrover1 343:6675661fa600 4712 /* Bit 6 : Patch 6 enabled. */
rgrover1 343:6675661fa600 4713 #define PU_PATCHENSET_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
rgrover1 343:6675661fa600 4714 #define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
rgrover1 343:6675661fa600 4715 #define PU_PATCHENSET_PATCH6_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4716 #define PU_PATCHENSET_PATCH6_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4717 #define PU_PATCHENSET_PATCH6_Set (1UL) /*!< Enable patch on write. */
rgrover1 343:6675661fa600 4718
rgrover1 343:6675661fa600 4719 /* Bit 5 : Patch 5 enabled. */
rgrover1 343:6675661fa600 4720 #define PU_PATCHENSET_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
rgrover1 343:6675661fa600 4721 #define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
rgrover1 343:6675661fa600 4722 #define PU_PATCHENSET_PATCH5_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4723 #define PU_PATCHENSET_PATCH5_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4724 #define PU_PATCHENSET_PATCH5_Set (1UL) /*!< Enable patch on write. */
rgrover1 343:6675661fa600 4725
rgrover1 343:6675661fa600 4726 /* Bit 4 : Patch 4 enabled. */
rgrover1 343:6675661fa600 4727 #define PU_PATCHENSET_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
rgrover1 343:6675661fa600 4728 #define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
rgrover1 343:6675661fa600 4729 #define PU_PATCHENSET_PATCH4_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4730 #define PU_PATCHENSET_PATCH4_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4731 #define PU_PATCHENSET_PATCH4_Set (1UL) /*!< Enable patch on write. */
rgrover1 343:6675661fa600 4732
rgrover1 343:6675661fa600 4733 /* Bit 3 : Patch 3 enabled. */
rgrover1 343:6675661fa600 4734 #define PU_PATCHENSET_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
rgrover1 343:6675661fa600 4735 #define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
rgrover1 343:6675661fa600 4736 #define PU_PATCHENSET_PATCH3_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4737 #define PU_PATCHENSET_PATCH3_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4738 #define PU_PATCHENSET_PATCH3_Set (1UL) /*!< Enable patch on write. */
rgrover1 343:6675661fa600 4739
rgrover1 343:6675661fa600 4740 /* Bit 2 : Patch 2 enabled. */
rgrover1 343:6675661fa600 4741 #define PU_PATCHENSET_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
rgrover1 343:6675661fa600 4742 #define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
rgrover1 343:6675661fa600 4743 #define PU_PATCHENSET_PATCH2_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4744 #define PU_PATCHENSET_PATCH2_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4745 #define PU_PATCHENSET_PATCH2_Set (1UL) /*!< Enable patch on write. */
rgrover1 343:6675661fa600 4746
rgrover1 343:6675661fa600 4747 /* Bit 1 : Patch 1 enabled. */
rgrover1 343:6675661fa600 4748 #define PU_PATCHENSET_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
rgrover1 343:6675661fa600 4749 #define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
rgrover1 343:6675661fa600 4750 #define PU_PATCHENSET_PATCH1_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4751 #define PU_PATCHENSET_PATCH1_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4752 #define PU_PATCHENSET_PATCH1_Set (1UL) /*!< Enable patch on write. */
rgrover1 343:6675661fa600 4753
rgrover1 343:6675661fa600 4754 /* Bit 0 : Patch 0 enabled. */
rgrover1 343:6675661fa600 4755 #define PU_PATCHENSET_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
rgrover1 343:6675661fa600 4756 #define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
rgrover1 343:6675661fa600 4757 #define PU_PATCHENSET_PATCH0_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4758 #define PU_PATCHENSET_PATCH0_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4759 #define PU_PATCHENSET_PATCH0_Set (1UL) /*!< Enable patch on write. */
rgrover1 343:6675661fa600 4760
rgrover1 343:6675661fa600 4761 /* Register: PU_PATCHENCLR */
rgrover1 343:6675661fa600 4762 /* Description: Patch disable register. */
rgrover1 343:6675661fa600 4763
rgrover1 343:6675661fa600 4764 /* Bit 7 : Patch 7 enabled. */
rgrover1 343:6675661fa600 4765 #define PU_PATCHENCLR_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
rgrover1 343:6675661fa600 4766 #define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
rgrover1 343:6675661fa600 4767 #define PU_PATCHENCLR_PATCH7_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4768 #define PU_PATCHENCLR_PATCH7_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4769 #define PU_PATCHENCLR_PATCH7_Clear (1UL) /*!< Disable patch on write. */
rgrover1 343:6675661fa600 4770
rgrover1 343:6675661fa600 4771 /* Bit 6 : Patch 6 enabled. */
rgrover1 343:6675661fa600 4772 #define PU_PATCHENCLR_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
rgrover1 343:6675661fa600 4773 #define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
rgrover1 343:6675661fa600 4774 #define PU_PATCHENCLR_PATCH6_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4775 #define PU_PATCHENCLR_PATCH6_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4776 #define PU_PATCHENCLR_PATCH6_Clear (1UL) /*!< Disable patch on write. */
rgrover1 343:6675661fa600 4777
rgrover1 343:6675661fa600 4778 /* Bit 5 : Patch 5 enabled. */
rgrover1 343:6675661fa600 4779 #define PU_PATCHENCLR_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
rgrover1 343:6675661fa600 4780 #define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
rgrover1 343:6675661fa600 4781 #define PU_PATCHENCLR_PATCH5_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4782 #define PU_PATCHENCLR_PATCH5_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4783 #define PU_PATCHENCLR_PATCH5_Clear (1UL) /*!< Disable patch on write. */
rgrover1 343:6675661fa600 4784
rgrover1 343:6675661fa600 4785 /* Bit 4 : Patch 4 enabled. */
rgrover1 343:6675661fa600 4786 #define PU_PATCHENCLR_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
rgrover1 343:6675661fa600 4787 #define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
rgrover1 343:6675661fa600 4788 #define PU_PATCHENCLR_PATCH4_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4789 #define PU_PATCHENCLR_PATCH4_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4790 #define PU_PATCHENCLR_PATCH4_Clear (1UL) /*!< Disable patch on write. */
rgrover1 343:6675661fa600 4791
rgrover1 343:6675661fa600 4792 /* Bit 3 : Patch 3 enabled. */
rgrover1 343:6675661fa600 4793 #define PU_PATCHENCLR_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
rgrover1 343:6675661fa600 4794 #define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
rgrover1 343:6675661fa600 4795 #define PU_PATCHENCLR_PATCH3_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4796 #define PU_PATCHENCLR_PATCH3_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4797 #define PU_PATCHENCLR_PATCH3_Clear (1UL) /*!< Disable patch on write. */
rgrover1 343:6675661fa600 4798
rgrover1 343:6675661fa600 4799 /* Bit 2 : Patch 2 enabled. */
rgrover1 343:6675661fa600 4800 #define PU_PATCHENCLR_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
rgrover1 343:6675661fa600 4801 #define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
rgrover1 343:6675661fa600 4802 #define PU_PATCHENCLR_PATCH2_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4803 #define PU_PATCHENCLR_PATCH2_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4804 #define PU_PATCHENCLR_PATCH2_Clear (1UL) /*!< Disable patch on write. */
rgrover1 343:6675661fa600 4805
rgrover1 343:6675661fa600 4806 /* Bit 1 : Patch 1 enabled. */
rgrover1 343:6675661fa600 4807 #define PU_PATCHENCLR_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
rgrover1 343:6675661fa600 4808 #define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
rgrover1 343:6675661fa600 4809 #define PU_PATCHENCLR_PATCH1_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4810 #define PU_PATCHENCLR_PATCH1_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4811 #define PU_PATCHENCLR_PATCH1_Clear (1UL) /*!< Disable patch on write. */
rgrover1 343:6675661fa600 4812
rgrover1 343:6675661fa600 4813 /* Bit 0 : Patch 0 enabled. */
rgrover1 343:6675661fa600 4814 #define PU_PATCHENCLR_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
rgrover1 343:6675661fa600 4815 #define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
rgrover1 343:6675661fa600 4816 #define PU_PATCHENCLR_PATCH0_Disabled (0UL) /*!< Patch disabled. */
rgrover1 343:6675661fa600 4817 #define PU_PATCHENCLR_PATCH0_Enabled (1UL) /*!< Patch enabled. */
rgrover1 343:6675661fa600 4818 #define PU_PATCHENCLR_PATCH0_Clear (1UL) /*!< Disable patch on write. */
rgrover1 343:6675661fa600 4819
rgrover1 343:6675661fa600 4820
rgrover1 343:6675661fa600 4821 /* Peripheral: QDEC */
rgrover1 343:6675661fa600 4822 /* Description: Rotary decoder. */
rgrover1 343:6675661fa600 4823
rgrover1 343:6675661fa600 4824 /* Register: QDEC_SHORTS */
rgrover1 343:6675661fa600 4825 /* Description: Shortcuts for the QDEC. */
rgrover1 343:6675661fa600 4826
rgrover1 343:6675661fa600 4827 /* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
rgrover1 343:6675661fa600 4828 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
rgrover1 343:6675661fa600 4829 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
rgrover1 343:6675661fa600 4830 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 4831 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 4832
rgrover1 343:6675661fa600 4833 /* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
rgrover1 343:6675661fa600 4834 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
rgrover1 343:6675661fa600 4835 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
rgrover1 343:6675661fa600 4836 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 4837 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 4838
rgrover1 343:6675661fa600 4839 /* Register: QDEC_INTENSET */
rgrover1 343:6675661fa600 4840 /* Description: Interrupt enable set register. */
rgrover1 343:6675661fa600 4841
rgrover1 343:6675661fa600 4842 /* Bit 2 : Enable interrupt on ACCOF event. */
rgrover1 343:6675661fa600 4843 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
rgrover1 343:6675661fa600 4844 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
rgrover1 343:6675661fa600 4845 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 4846 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 4847 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 4848
rgrover1 343:6675661fa600 4849 /* Bit 1 : Enable interrupt on REPORTRDY event. */
rgrover1 343:6675661fa600 4850 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
rgrover1 343:6675661fa600 4851 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
rgrover1 343:6675661fa600 4852 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 4853 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 4854 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 4855
rgrover1 343:6675661fa600 4856 /* Bit 0 : Enable interrupt on SAMPLERDY event. */
rgrover1 343:6675661fa600 4857 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
rgrover1 343:6675661fa600 4858 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
rgrover1 343:6675661fa600 4859 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 4860 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 4861 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 4862
rgrover1 343:6675661fa600 4863 /* Register: QDEC_INTENCLR */
rgrover1 343:6675661fa600 4864 /* Description: Interrupt enable clear register. */
rgrover1 343:6675661fa600 4865
rgrover1 343:6675661fa600 4866 /* Bit 2 : Disable interrupt on ACCOF event. */
rgrover1 343:6675661fa600 4867 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
rgrover1 343:6675661fa600 4868 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
rgrover1 343:6675661fa600 4869 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 4870 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 4871 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 4872
rgrover1 343:6675661fa600 4873 /* Bit 1 : Disable interrupt on REPORTRDY event. */
rgrover1 343:6675661fa600 4874 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
rgrover1 343:6675661fa600 4875 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
rgrover1 343:6675661fa600 4876 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 4877 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 4878 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 4879
rgrover1 343:6675661fa600 4880 /* Bit 0 : Disable interrupt on SAMPLERDY event. */
rgrover1 343:6675661fa600 4881 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
rgrover1 343:6675661fa600 4882 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
rgrover1 343:6675661fa600 4883 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 4884 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 4885 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 4886
rgrover1 343:6675661fa600 4887 /* Register: QDEC_ENABLE */
rgrover1 343:6675661fa600 4888 /* Description: Enable the QDEC. */
rgrover1 343:6675661fa600 4889
rgrover1 343:6675661fa600 4890 /* Bit 0 : Enable or disable QDEC. */
rgrover1 343:6675661fa600 4891 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
rgrover1 343:6675661fa600 4892 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
rgrover1 343:6675661fa600 4893 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */
rgrover1 343:6675661fa600 4894 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */
rgrover1 343:6675661fa600 4895
rgrover1 343:6675661fa600 4896 /* Register: QDEC_LEDPOL */
rgrover1 343:6675661fa600 4897 /* Description: LED output pin polarity. */
rgrover1 343:6675661fa600 4898
rgrover1 343:6675661fa600 4899 /* Bit 0 : LED output pin polarity. */
rgrover1 343:6675661fa600 4900 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
rgrover1 343:6675661fa600 4901 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
rgrover1 343:6675661fa600 4902 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */
rgrover1 343:6675661fa600 4903 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */
rgrover1 343:6675661fa600 4904
rgrover1 343:6675661fa600 4905 /* Register: QDEC_SAMPLEPER */
rgrover1 343:6675661fa600 4906 /* Description: Sample period. */
rgrover1 343:6675661fa600 4907
rgrover1 343:6675661fa600 4908 /* Bits 2..0 : Sample period. */
rgrover1 343:6675661fa600 4909 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
rgrover1 343:6675661fa600 4910 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
rgrover1 343:6675661fa600 4911 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */
rgrover1 343:6675661fa600 4912 #define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */
rgrover1 343:6675661fa600 4913 #define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */
rgrover1 343:6675661fa600 4914 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */
rgrover1 343:6675661fa600 4915 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */
rgrover1 343:6675661fa600 4916 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */
rgrover1 343:6675661fa600 4917 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */
rgrover1 343:6675661fa600 4918 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */
rgrover1 343:6675661fa600 4919
rgrover1 343:6675661fa600 4920 /* Register: QDEC_SAMPLE */
rgrover1 343:6675661fa600 4921 /* Description: Motion sample value. */
rgrover1 343:6675661fa600 4922
rgrover1 343:6675661fa600 4923 /* Bits 31..0 : Last sample taken in compliment to 2. */
rgrover1 343:6675661fa600 4924 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
rgrover1 343:6675661fa600 4925 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
rgrover1 343:6675661fa600 4926
rgrover1 343:6675661fa600 4927 /* Register: QDEC_REPORTPER */
rgrover1 343:6675661fa600 4928 /* Description: Number of samples to generate an EVENT_REPORTRDY. */
rgrover1 343:6675661fa600 4929
rgrover1 343:6675661fa600 4930 /* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
rgrover1 343:6675661fa600 4931 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
rgrover1 343:6675661fa600 4932 #define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
rgrover1 343:6675661fa600 4933 #define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */
rgrover1 343:6675661fa600 4934 #define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */
rgrover1 343:6675661fa600 4935 #define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */
rgrover1 343:6675661fa600 4936 #define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */
rgrover1 343:6675661fa600 4937 #define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */
rgrover1 343:6675661fa600 4938 #define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */
rgrover1 343:6675661fa600 4939 #define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */
rgrover1 343:6675661fa600 4940 #define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */
rgrover1 343:6675661fa600 4941
rgrover1 343:6675661fa600 4942 /* Register: QDEC_DBFEN */
rgrover1 343:6675661fa600 4943 /* Description: Enable debouncer input filters. */
rgrover1 343:6675661fa600 4944
rgrover1 343:6675661fa600 4945 /* Bit 0 : Enable debounce input filters. */
rgrover1 343:6675661fa600 4946 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
rgrover1 343:6675661fa600 4947 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
rgrover1 343:6675661fa600 4948 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */
rgrover1 343:6675661fa600 4949 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */
rgrover1 343:6675661fa600 4950
rgrover1 343:6675661fa600 4951 /* Register: QDEC_LEDPRE */
rgrover1 343:6675661fa600 4952 /* Description: Time LED is switched ON before the sample. */
rgrover1 343:6675661fa600 4953
rgrover1 343:6675661fa600 4954 /* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
rgrover1 343:6675661fa600 4955 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
rgrover1 343:6675661fa600 4956 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
rgrover1 343:6675661fa600 4957
rgrover1 343:6675661fa600 4958 /* Register: QDEC_ACCDBL */
rgrover1 343:6675661fa600 4959 /* Description: Accumulated double (error) transitions register. */
rgrover1 343:6675661fa600 4960
rgrover1 343:6675661fa600 4961 /* Bits 3..0 : Accumulated double (error) transitions. */
rgrover1 343:6675661fa600 4962 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
rgrover1 343:6675661fa600 4963 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
rgrover1 343:6675661fa600 4964
rgrover1 343:6675661fa600 4965 /* Register: QDEC_ACCDBLREAD */
rgrover1 343:6675661fa600 4966 /* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
rgrover1 343:6675661fa600 4967
rgrover1 343:6675661fa600 4968 /* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
rgrover1 343:6675661fa600 4969 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
rgrover1 343:6675661fa600 4970 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
rgrover1 343:6675661fa600 4971
rgrover1 343:6675661fa600 4972 /* Register: QDEC_POWER */
rgrover1 343:6675661fa600 4973 /* Description: Peripheral power control. */
rgrover1 343:6675661fa600 4974
rgrover1 343:6675661fa600 4975 /* Bit 0 : Peripheral power control. */
rgrover1 343:6675661fa600 4976 #define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
rgrover1 343:6675661fa600 4977 #define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
rgrover1 343:6675661fa600 4978 #define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
rgrover1 343:6675661fa600 4979 #define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
rgrover1 343:6675661fa600 4980
rgrover1 343:6675661fa600 4981
rgrover1 343:6675661fa600 4982 /* Peripheral: RADIO */
rgrover1 343:6675661fa600 4983 /* Description: The radio. */
rgrover1 343:6675661fa600 4984
rgrover1 343:6675661fa600 4985 /* Register: RADIO_SHORTS */
rgrover1 343:6675661fa600 4986 /* Description: Shortcuts for the radio. */
rgrover1 343:6675661fa600 4987
rgrover1 343:6675661fa600 4988 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
rgrover1 343:6675661fa600 4989 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
rgrover1 343:6675661fa600 4990 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
rgrover1 343:6675661fa600 4991 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 4992 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 4993
rgrover1 343:6675661fa600 4994 /* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
rgrover1 343:6675661fa600 4995 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
rgrover1 343:6675661fa600 4996 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
rgrover1 343:6675661fa600 4997 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 4998 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 4999
rgrover1 343:6675661fa600 5000 /* Bit 5 : Shortcut between END event and START task. */
rgrover1 343:6675661fa600 5001 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
rgrover1 343:6675661fa600 5002 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
rgrover1 343:6675661fa600 5003 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 5004 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 5005
rgrover1 343:6675661fa600 5006 /* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
rgrover1 343:6675661fa600 5007 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
rgrover1 343:6675661fa600 5008 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
rgrover1 343:6675661fa600 5009 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 5010 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 5011
rgrover1 343:6675661fa600 5012 /* Bit 3 : Shortcut between DISABLED event and RXEN task. */
rgrover1 343:6675661fa600 5013 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
rgrover1 343:6675661fa600 5014 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
rgrover1 343:6675661fa600 5015 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 5016 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 5017
rgrover1 343:6675661fa600 5018 /* Bit 2 : Shortcut between DISABLED event and TXEN task. */
rgrover1 343:6675661fa600 5019 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
rgrover1 343:6675661fa600 5020 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
rgrover1 343:6675661fa600 5021 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 5022 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 5023
rgrover1 343:6675661fa600 5024 /* Bit 1 : Shortcut between END event and DISABLE task. */
rgrover1 343:6675661fa600 5025 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
rgrover1 343:6675661fa600 5026 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
rgrover1 343:6675661fa600 5027 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 5028 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 5029
rgrover1 343:6675661fa600 5030 /* Bit 0 : Shortcut between READY event and START task. */
rgrover1 343:6675661fa600 5031 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
rgrover1 343:6675661fa600 5032 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
rgrover1 343:6675661fa600 5033 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 5034 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 5035
rgrover1 343:6675661fa600 5036 /* Register: RADIO_INTENSET */
rgrover1 343:6675661fa600 5037 /* Description: Interrupt enable set register. */
rgrover1 343:6675661fa600 5038
rgrover1 343:6675661fa600 5039 /* Bit 10 : Enable interrupt on BCMATCH event. */
rgrover1 343:6675661fa600 5040 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
rgrover1 343:6675661fa600 5041 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
rgrover1 343:6675661fa600 5042 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5043 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5044 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 5045
rgrover1 343:6675661fa600 5046 /* Bit 7 : Enable interrupt on RSSIEND event. */
rgrover1 343:6675661fa600 5047 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
rgrover1 343:6675661fa600 5048 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
rgrover1 343:6675661fa600 5049 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5050 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5051 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 5052
rgrover1 343:6675661fa600 5053 /* Bit 6 : Enable interrupt on DEVMISS event. */
rgrover1 343:6675661fa600 5054 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
rgrover1 343:6675661fa600 5055 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
rgrover1 343:6675661fa600 5056 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5057 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5058 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 5059
rgrover1 343:6675661fa600 5060 /* Bit 5 : Enable interrupt on DEVMATCH event. */
rgrover1 343:6675661fa600 5061 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
rgrover1 343:6675661fa600 5062 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
rgrover1 343:6675661fa600 5063 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5064 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5065 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 5066
rgrover1 343:6675661fa600 5067 /* Bit 4 : Enable interrupt on DISABLED event. */
rgrover1 343:6675661fa600 5068 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
rgrover1 343:6675661fa600 5069 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
rgrover1 343:6675661fa600 5070 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5071 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5072 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 5073
rgrover1 343:6675661fa600 5074 /* Bit 3 : Enable interrupt on END event. */
rgrover1 343:6675661fa600 5075 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
rgrover1 343:6675661fa600 5076 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
rgrover1 343:6675661fa600 5077 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5078 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5079 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 5080
rgrover1 343:6675661fa600 5081 /* Bit 2 : Enable interrupt on PAYLOAD event. */
rgrover1 343:6675661fa600 5082 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
rgrover1 343:6675661fa600 5083 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
rgrover1 343:6675661fa600 5084 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5085 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5086 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 5087
rgrover1 343:6675661fa600 5088 /* Bit 1 : Enable interrupt on ADDRESS event. */
rgrover1 343:6675661fa600 5089 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
rgrover1 343:6675661fa600 5090 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
rgrover1 343:6675661fa600 5091 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5092 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5093 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 5094
rgrover1 343:6675661fa600 5095 /* Bit 0 : Enable interrupt on READY event. */
rgrover1 343:6675661fa600 5096 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
rgrover1 343:6675661fa600 5097 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
rgrover1 343:6675661fa600 5098 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5099 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5100 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 5101
rgrover1 343:6675661fa600 5102 /* Register: RADIO_INTENCLR */
rgrover1 343:6675661fa600 5103 /* Description: Interrupt enable clear register. */
rgrover1 343:6675661fa600 5104
rgrover1 343:6675661fa600 5105 /* Bit 10 : Disable interrupt on BCMATCH event. */
rgrover1 343:6675661fa600 5106 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
rgrover1 343:6675661fa600 5107 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
rgrover1 343:6675661fa600 5108 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5109 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5110 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 5111
rgrover1 343:6675661fa600 5112 /* Bit 7 : Disable interrupt on RSSIEND event. */
rgrover1 343:6675661fa600 5113 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
rgrover1 343:6675661fa600 5114 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
rgrover1 343:6675661fa600 5115 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5116 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5117 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 5118
rgrover1 343:6675661fa600 5119 /* Bit 6 : Disable interrupt on DEVMISS event. */
rgrover1 343:6675661fa600 5120 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
rgrover1 343:6675661fa600 5121 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
rgrover1 343:6675661fa600 5122 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5123 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5124 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 5125
rgrover1 343:6675661fa600 5126 /* Bit 5 : Disable interrupt on DEVMATCH event. */
rgrover1 343:6675661fa600 5127 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
rgrover1 343:6675661fa600 5128 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
rgrover1 343:6675661fa600 5129 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5130 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5131 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 5132
rgrover1 343:6675661fa600 5133 /* Bit 4 : Disable interrupt on DISABLED event. */
rgrover1 343:6675661fa600 5134 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
rgrover1 343:6675661fa600 5135 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
rgrover1 343:6675661fa600 5136 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5137 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5138 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 5139
rgrover1 343:6675661fa600 5140 /* Bit 3 : Disable interrupt on END event. */
rgrover1 343:6675661fa600 5141 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
rgrover1 343:6675661fa600 5142 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
rgrover1 343:6675661fa600 5143 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5144 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5145 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 5146
rgrover1 343:6675661fa600 5147 /* Bit 2 : Disable interrupt on PAYLOAD event. */
rgrover1 343:6675661fa600 5148 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
rgrover1 343:6675661fa600 5149 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
rgrover1 343:6675661fa600 5150 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5151 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5152 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 5153
rgrover1 343:6675661fa600 5154 /* Bit 1 : Disable interrupt on ADDRESS event. */
rgrover1 343:6675661fa600 5155 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
rgrover1 343:6675661fa600 5156 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
rgrover1 343:6675661fa600 5157 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5158 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5159 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 5160
rgrover1 343:6675661fa600 5161 /* Bit 0 : Disable interrupt on READY event. */
rgrover1 343:6675661fa600 5162 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
rgrover1 343:6675661fa600 5163 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
rgrover1 343:6675661fa600 5164 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5165 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5166 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 5167
rgrover1 343:6675661fa600 5168 /* Register: RADIO_CRCSTATUS */
rgrover1 343:6675661fa600 5169 /* Description: CRC status of received packet. */
rgrover1 343:6675661fa600 5170
rgrover1 343:6675661fa600 5171 /* Bit 0 : CRC status of received packet. */
rgrover1 343:6675661fa600 5172 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
rgrover1 343:6675661fa600 5173 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
rgrover1 343:6675661fa600 5174 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */
rgrover1 343:6675661fa600 5175 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */
rgrover1 343:6675661fa600 5176
rgrover1 343:6675661fa600 5177 /* Register: RADIO_CD */
rgrover1 343:6675661fa600 5178 /* Description: Carrier detect. */
rgrover1 343:6675661fa600 5179
rgrover1 343:6675661fa600 5180 /* Bit 0 : Carrier detect. */
rgrover1 343:6675661fa600 5181 #define RADIO_CD_CD_Pos (0UL) /*!< Position of CD field. */
rgrover1 343:6675661fa600 5182 #define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /*!< Bit mask of CD field. */
rgrover1 343:6675661fa600 5183
rgrover1 343:6675661fa600 5184 /* Register: RADIO_RXMATCH */
rgrover1 343:6675661fa600 5185 /* Description: Received address. */
rgrover1 343:6675661fa600 5186
rgrover1 343:6675661fa600 5187 /* Bits 2..0 : Logical address in which previous packet was received. */
rgrover1 343:6675661fa600 5188 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
rgrover1 343:6675661fa600 5189 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
rgrover1 343:6675661fa600 5190
rgrover1 343:6675661fa600 5191 /* Register: RADIO_RXCRC */
rgrover1 343:6675661fa600 5192 /* Description: Received CRC. */
rgrover1 343:6675661fa600 5193
rgrover1 343:6675661fa600 5194 /* Bits 23..0 : CRC field of previously received packet. */
rgrover1 343:6675661fa600 5195 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
rgrover1 343:6675661fa600 5196 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
rgrover1 343:6675661fa600 5197
rgrover1 343:6675661fa600 5198 /* Register: RADIO_DAI */
rgrover1 343:6675661fa600 5199 /* Description: Device address match index. */
rgrover1 343:6675661fa600 5200
rgrover1 343:6675661fa600 5201 /* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
rgrover1 343:6675661fa600 5202 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
rgrover1 343:6675661fa600 5203 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
rgrover1 343:6675661fa600 5204
rgrover1 343:6675661fa600 5205 /* Register: RADIO_FREQUENCY */
rgrover1 343:6675661fa600 5206 /* Description: Frequency. */
rgrover1 343:6675661fa600 5207
rgrover1 343:6675661fa600 5208 /* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
rgrover1 343:6675661fa600 5209 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
rgrover1 343:6675661fa600 5210 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
rgrover1 343:6675661fa600 5211
rgrover1 343:6675661fa600 5212 /* Register: RADIO_TXPOWER */
rgrover1 343:6675661fa600 5213 /* Description: Output power. */
rgrover1 343:6675661fa600 5214
rgrover1 343:6675661fa600 5215 /* Bits 7..0 : Radio output power. Decision point: TXEN task. */
rgrover1 343:6675661fa600 5216 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
rgrover1 343:6675661fa600 5217 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
rgrover1 343:6675661fa600 5218 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */
rgrover1 343:6675661fa600 5219 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */
rgrover1 343:6675661fa600 5220 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */
rgrover1 343:6675661fa600 5221 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */
rgrover1 343:6675661fa600 5222 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */
rgrover1 343:6675661fa600 5223 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */
rgrover1 343:6675661fa600 5224 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */
rgrover1 343:6675661fa600 5225 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */
rgrover1 343:6675661fa600 5226
rgrover1 343:6675661fa600 5227 /* Register: RADIO_MODE */
rgrover1 343:6675661fa600 5228 /* Description: Data rate and modulation. */
rgrover1 343:6675661fa600 5229
rgrover1 343:6675661fa600 5230 /* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
rgrover1 343:6675661fa600 5231 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
rgrover1 343:6675661fa600 5232 #define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
rgrover1 343:6675661fa600 5233 #define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */
rgrover1 343:6675661fa600 5234 #define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */
rgrover1 343:6675661fa600 5235 #define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */
rgrover1 343:6675661fa600 5236 #define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */
rgrover1 343:6675661fa600 5237
rgrover1 343:6675661fa600 5238 /* Register: RADIO_PCNF0 */
rgrover1 343:6675661fa600 5239 /* Description: Packet configuration 0. */
rgrover1 343:6675661fa600 5240
rgrover1 343:6675661fa600 5241 /* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
rgrover1 343:6675661fa600 5242 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
rgrover1 343:6675661fa600 5243 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
rgrover1 343:6675661fa600 5244
rgrover1 343:6675661fa600 5245 /* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
rgrover1 343:6675661fa600 5246 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
rgrover1 343:6675661fa600 5247 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
rgrover1 343:6675661fa600 5248
rgrover1 343:6675661fa600 5249 /* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
rgrover1 343:6675661fa600 5250 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
rgrover1 343:6675661fa600 5251 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
rgrover1 343:6675661fa600 5252
rgrover1 343:6675661fa600 5253 /* Register: RADIO_PCNF1 */
rgrover1 343:6675661fa600 5254 /* Description: Packet configuration 1. */
rgrover1 343:6675661fa600 5255
rgrover1 343:6675661fa600 5256 /* Bit 25 : Packet whitening enable. */
rgrover1 343:6675661fa600 5257 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
rgrover1 343:6675661fa600 5258 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
rgrover1 343:6675661fa600 5259 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */
rgrover1 343:6675661fa600 5260 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */
rgrover1 343:6675661fa600 5261
rgrover1 343:6675661fa600 5262 /* Bit 24 : On air endianness of packet length field. Decision point: START task. */
rgrover1 343:6675661fa600 5263 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
rgrover1 343:6675661fa600 5264 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
rgrover1 343:6675661fa600 5265 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
rgrover1 343:6675661fa600 5266 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
rgrover1 343:6675661fa600 5267
rgrover1 343:6675661fa600 5268 /* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
rgrover1 343:6675661fa600 5269 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
rgrover1 343:6675661fa600 5270 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
rgrover1 343:6675661fa600 5271
rgrover1 343:6675661fa600 5272 /* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
rgrover1 343:6675661fa600 5273 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
rgrover1 343:6675661fa600 5274 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
rgrover1 343:6675661fa600 5275
rgrover1 343:6675661fa600 5276 /* Bits 7..0 : Maximum length of packet payload in number of bytes. */
rgrover1 343:6675661fa600 5277 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
rgrover1 343:6675661fa600 5278 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
rgrover1 343:6675661fa600 5279
rgrover1 343:6675661fa600 5280 /* Register: RADIO_PREFIX0 */
rgrover1 343:6675661fa600 5281 /* Description: Prefixes bytes for logical addresses 0 to 3. */
rgrover1 343:6675661fa600 5282
rgrover1 343:6675661fa600 5283 /* Bits 31..24 : Address prefix 3. Decision point: START task. */
rgrover1 343:6675661fa600 5284 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
rgrover1 343:6675661fa600 5285 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
rgrover1 343:6675661fa600 5286
rgrover1 343:6675661fa600 5287 /* Bits 23..16 : Address prefix 2. Decision point: START task. */
rgrover1 343:6675661fa600 5288 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
rgrover1 343:6675661fa600 5289 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
rgrover1 343:6675661fa600 5290
rgrover1 343:6675661fa600 5291 /* Bits 15..8 : Address prefix 1. Decision point: START task. */
rgrover1 343:6675661fa600 5292 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
rgrover1 343:6675661fa600 5293 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
rgrover1 343:6675661fa600 5294
rgrover1 343:6675661fa600 5295 /* Bits 7..0 : Address prefix 0. Decision point: START task. */
rgrover1 343:6675661fa600 5296 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
rgrover1 343:6675661fa600 5297 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
rgrover1 343:6675661fa600 5298
rgrover1 343:6675661fa600 5299 /* Register: RADIO_PREFIX1 */
rgrover1 343:6675661fa600 5300 /* Description: Prefixes bytes for logical addresses 4 to 7. */
rgrover1 343:6675661fa600 5301
rgrover1 343:6675661fa600 5302 /* Bits 31..24 : Address prefix 7. Decision point: START task. */
rgrover1 343:6675661fa600 5303 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
rgrover1 343:6675661fa600 5304 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
rgrover1 343:6675661fa600 5305
rgrover1 343:6675661fa600 5306 /* Bits 23..16 : Address prefix 6. Decision point: START task. */
rgrover1 343:6675661fa600 5307 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
rgrover1 343:6675661fa600 5308 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
rgrover1 343:6675661fa600 5309
rgrover1 343:6675661fa600 5310 /* Bits 15..8 : Address prefix 5. Decision point: START task. */
rgrover1 343:6675661fa600 5311 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
rgrover1 343:6675661fa600 5312 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
rgrover1 343:6675661fa600 5313
rgrover1 343:6675661fa600 5314 /* Bits 7..0 : Address prefix 4. Decision point: START task. */
rgrover1 343:6675661fa600 5315 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
rgrover1 343:6675661fa600 5316 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
rgrover1 343:6675661fa600 5317
rgrover1 343:6675661fa600 5318 /* Register: RADIO_TXADDRESS */
rgrover1 343:6675661fa600 5319 /* Description: Transmit address select. */
rgrover1 343:6675661fa600 5320
rgrover1 343:6675661fa600 5321 /* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
rgrover1 343:6675661fa600 5322 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
rgrover1 343:6675661fa600 5323 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
rgrover1 343:6675661fa600 5324
rgrover1 343:6675661fa600 5325 /* Register: RADIO_RXADDRESSES */
rgrover1 343:6675661fa600 5326 /* Description: Receive address select. */
rgrover1 343:6675661fa600 5327
rgrover1 343:6675661fa600 5328 /* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
rgrover1 343:6675661fa600 5329 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
rgrover1 343:6675661fa600 5330 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
rgrover1 343:6675661fa600 5331 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */
rgrover1 343:6675661fa600 5332 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */
rgrover1 343:6675661fa600 5333
rgrover1 343:6675661fa600 5334 /* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
rgrover1 343:6675661fa600 5335 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
rgrover1 343:6675661fa600 5336 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
rgrover1 343:6675661fa600 5337 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */
rgrover1 343:6675661fa600 5338 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */
rgrover1 343:6675661fa600 5339
rgrover1 343:6675661fa600 5340 /* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
rgrover1 343:6675661fa600 5341 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
rgrover1 343:6675661fa600 5342 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
rgrover1 343:6675661fa600 5343 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */
rgrover1 343:6675661fa600 5344 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */
rgrover1 343:6675661fa600 5345
rgrover1 343:6675661fa600 5346 /* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
rgrover1 343:6675661fa600 5347 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
rgrover1 343:6675661fa600 5348 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
rgrover1 343:6675661fa600 5349 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */
rgrover1 343:6675661fa600 5350 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */
rgrover1 343:6675661fa600 5351
rgrover1 343:6675661fa600 5352 /* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
rgrover1 343:6675661fa600 5353 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
rgrover1 343:6675661fa600 5354 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
rgrover1 343:6675661fa600 5355 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */
rgrover1 343:6675661fa600 5356 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */
rgrover1 343:6675661fa600 5357
rgrover1 343:6675661fa600 5358 /* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
rgrover1 343:6675661fa600 5359 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
rgrover1 343:6675661fa600 5360 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
rgrover1 343:6675661fa600 5361 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */
rgrover1 343:6675661fa600 5362 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */
rgrover1 343:6675661fa600 5363
rgrover1 343:6675661fa600 5364 /* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
rgrover1 343:6675661fa600 5365 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
rgrover1 343:6675661fa600 5366 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
rgrover1 343:6675661fa600 5367 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */
rgrover1 343:6675661fa600 5368 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */
rgrover1 343:6675661fa600 5369
rgrover1 343:6675661fa600 5370 /* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
rgrover1 343:6675661fa600 5371 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
rgrover1 343:6675661fa600 5372 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
rgrover1 343:6675661fa600 5373 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */
rgrover1 343:6675661fa600 5374 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */
rgrover1 343:6675661fa600 5375
rgrover1 343:6675661fa600 5376 /* Register: RADIO_CRCCNF */
rgrover1 343:6675661fa600 5377 /* Description: CRC configuration. */
rgrover1 343:6675661fa600 5378
rgrover1 343:6675661fa600 5379 /* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
rgrover1 343:6675661fa600 5380 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
rgrover1 343:6675661fa600 5381 #define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
rgrover1 343:6675661fa600 5382 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */
rgrover1 343:6675661fa600 5383 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */
rgrover1 343:6675661fa600 5384
rgrover1 343:6675661fa600 5385 /* Bits 1..0 : CRC length. Decision point: START task. */
rgrover1 343:6675661fa600 5386 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
rgrover1 343:6675661fa600 5387 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
rgrover1 343:6675661fa600 5388 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */
rgrover1 343:6675661fa600 5389 #define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */
rgrover1 343:6675661fa600 5390 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */
rgrover1 343:6675661fa600 5391 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */
rgrover1 343:6675661fa600 5392
rgrover1 343:6675661fa600 5393 /* Register: RADIO_CRCPOLY */
rgrover1 343:6675661fa600 5394 /* Description: CRC polynomial. */
rgrover1 343:6675661fa600 5395
rgrover1 343:6675661fa600 5396 /* Bits 23..0 : CRC polynomial. Decision point: START task. */
rgrover1 343:6675661fa600 5397 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
rgrover1 343:6675661fa600 5398 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
rgrover1 343:6675661fa600 5399
rgrover1 343:6675661fa600 5400 /* Register: RADIO_CRCINIT */
rgrover1 343:6675661fa600 5401 /* Description: CRC initial value. */
rgrover1 343:6675661fa600 5402
rgrover1 343:6675661fa600 5403 /* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
rgrover1 343:6675661fa600 5404 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
rgrover1 343:6675661fa600 5405 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
rgrover1 343:6675661fa600 5406
rgrover1 343:6675661fa600 5407 /* Register: RADIO_TEST */
rgrover1 343:6675661fa600 5408 /* Description: Test features enable register. */
rgrover1 343:6675661fa600 5409
rgrover1 343:6675661fa600 5410 /* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
rgrover1 343:6675661fa600 5411 #define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */
rgrover1 343:6675661fa600 5412 #define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */
rgrover1 343:6675661fa600 5413 #define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */
rgrover1 343:6675661fa600 5414 #define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */
rgrover1 343:6675661fa600 5415
rgrover1 343:6675661fa600 5416 /* Bit 0 : Constant carrier. Decision point: TXEN task. */
rgrover1 343:6675661fa600 5417 #define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */
rgrover1 343:6675661fa600 5418 #define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */
rgrover1 343:6675661fa600 5419 #define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */
rgrover1 343:6675661fa600 5420 #define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */
rgrover1 343:6675661fa600 5421
rgrover1 343:6675661fa600 5422 /* Register: RADIO_TIFS */
rgrover1 343:6675661fa600 5423 /* Description: Inter Frame Spacing in microseconds. */
rgrover1 343:6675661fa600 5424
rgrover1 343:6675661fa600 5425 /* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
rgrover1 343:6675661fa600 5426 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
rgrover1 343:6675661fa600 5427 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
rgrover1 343:6675661fa600 5428
rgrover1 343:6675661fa600 5429 /* Register: RADIO_RSSISAMPLE */
rgrover1 343:6675661fa600 5430 /* Description: RSSI sample. */
rgrover1 343:6675661fa600 5431
rgrover1 343:6675661fa600 5432 /* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
rgrover1 343:6675661fa600 5433 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
rgrover1 343:6675661fa600 5434 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
rgrover1 343:6675661fa600 5435
rgrover1 343:6675661fa600 5436 /* Register: RADIO_STATE */
rgrover1 343:6675661fa600 5437 /* Description: Current radio state. */
rgrover1 343:6675661fa600 5438
rgrover1 343:6675661fa600 5439 /* Bits 3..0 : Current radio state. */
rgrover1 343:6675661fa600 5440 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
rgrover1 343:6675661fa600 5441 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
rgrover1 343:6675661fa600 5442 #define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */
rgrover1 343:6675661fa600 5443 #define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */
rgrover1 343:6675661fa600 5444 #define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */
rgrover1 343:6675661fa600 5445 #define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */
rgrover1 343:6675661fa600 5446 #define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */
rgrover1 343:6675661fa600 5447 #define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */
rgrover1 343:6675661fa600 5448 #define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */
rgrover1 343:6675661fa600 5449 #define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */
rgrover1 343:6675661fa600 5450 #define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */
rgrover1 343:6675661fa600 5451
rgrover1 343:6675661fa600 5452 /* Register: RADIO_DATAWHITEIV */
rgrover1 343:6675661fa600 5453 /* Description: Data whitening initial value. */
rgrover1 343:6675661fa600 5454
rgrover1 343:6675661fa600 5455 /* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
rgrover1 343:6675661fa600 5456 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
rgrover1 343:6675661fa600 5457 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
rgrover1 343:6675661fa600 5458
rgrover1 343:6675661fa600 5459 /* Register: RADIO_DAP */
rgrover1 343:6675661fa600 5460 /* Description: Device address prefix. */
rgrover1 343:6675661fa600 5461
rgrover1 343:6675661fa600 5462 /* Bits 15..0 : Device address prefix. */
rgrover1 343:6675661fa600 5463 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
rgrover1 343:6675661fa600 5464 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
rgrover1 343:6675661fa600 5465
rgrover1 343:6675661fa600 5466 /* Register: RADIO_DACNF */
rgrover1 343:6675661fa600 5467 /* Description: Device address match configuration. */
rgrover1 343:6675661fa600 5468
rgrover1 343:6675661fa600 5469 /* Bit 15 : TxAdd for device address 7. */
rgrover1 343:6675661fa600 5470 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
rgrover1 343:6675661fa600 5471 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
rgrover1 343:6675661fa600 5472
rgrover1 343:6675661fa600 5473 /* Bit 14 : TxAdd for device address 6. */
rgrover1 343:6675661fa600 5474 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
rgrover1 343:6675661fa600 5475 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
rgrover1 343:6675661fa600 5476
rgrover1 343:6675661fa600 5477 /* Bit 13 : TxAdd for device address 5. */
rgrover1 343:6675661fa600 5478 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
rgrover1 343:6675661fa600 5479 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
rgrover1 343:6675661fa600 5480
rgrover1 343:6675661fa600 5481 /* Bit 12 : TxAdd for device address 4. */
rgrover1 343:6675661fa600 5482 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
rgrover1 343:6675661fa600 5483 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
rgrover1 343:6675661fa600 5484
rgrover1 343:6675661fa600 5485 /* Bit 11 : TxAdd for device address 3. */
rgrover1 343:6675661fa600 5486 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
rgrover1 343:6675661fa600 5487 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
rgrover1 343:6675661fa600 5488
rgrover1 343:6675661fa600 5489 /* Bit 10 : TxAdd for device address 2. */
rgrover1 343:6675661fa600 5490 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
rgrover1 343:6675661fa600 5491 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
rgrover1 343:6675661fa600 5492
rgrover1 343:6675661fa600 5493 /* Bit 9 : TxAdd for device address 1. */
rgrover1 343:6675661fa600 5494 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
rgrover1 343:6675661fa600 5495 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
rgrover1 343:6675661fa600 5496
rgrover1 343:6675661fa600 5497 /* Bit 8 : TxAdd for device address 0. */
rgrover1 343:6675661fa600 5498 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
rgrover1 343:6675661fa600 5499 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
rgrover1 343:6675661fa600 5500
rgrover1 343:6675661fa600 5501 /* Bit 7 : Enable or disable device address matching using device address 7. */
rgrover1 343:6675661fa600 5502 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
rgrover1 343:6675661fa600 5503 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
rgrover1 343:6675661fa600 5504 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */
rgrover1 343:6675661fa600 5505 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */
rgrover1 343:6675661fa600 5506
rgrover1 343:6675661fa600 5507 /* Bit 6 : Enable or disable device address matching using device address 6. */
rgrover1 343:6675661fa600 5508 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
rgrover1 343:6675661fa600 5509 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
rgrover1 343:6675661fa600 5510 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */
rgrover1 343:6675661fa600 5511 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */
rgrover1 343:6675661fa600 5512
rgrover1 343:6675661fa600 5513 /* Bit 5 : Enable or disable device address matching using device address 5. */
rgrover1 343:6675661fa600 5514 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
rgrover1 343:6675661fa600 5515 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
rgrover1 343:6675661fa600 5516 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */
rgrover1 343:6675661fa600 5517 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */
rgrover1 343:6675661fa600 5518
rgrover1 343:6675661fa600 5519 /* Bit 4 : Enable or disable device address matching using device address 4. */
rgrover1 343:6675661fa600 5520 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
rgrover1 343:6675661fa600 5521 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
rgrover1 343:6675661fa600 5522 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */
rgrover1 343:6675661fa600 5523 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */
rgrover1 343:6675661fa600 5524
rgrover1 343:6675661fa600 5525 /* Bit 3 : Enable or disable device address matching using device address 3. */
rgrover1 343:6675661fa600 5526 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
rgrover1 343:6675661fa600 5527 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
rgrover1 343:6675661fa600 5528 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */
rgrover1 343:6675661fa600 5529 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */
rgrover1 343:6675661fa600 5530
rgrover1 343:6675661fa600 5531 /* Bit 2 : Enable or disable device address matching using device address 2. */
rgrover1 343:6675661fa600 5532 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
rgrover1 343:6675661fa600 5533 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
rgrover1 343:6675661fa600 5534 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */
rgrover1 343:6675661fa600 5535 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */
rgrover1 343:6675661fa600 5536
rgrover1 343:6675661fa600 5537 /* Bit 1 : Enable or disable device address matching using device address 1. */
rgrover1 343:6675661fa600 5538 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
rgrover1 343:6675661fa600 5539 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
rgrover1 343:6675661fa600 5540 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */
rgrover1 343:6675661fa600 5541 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */
rgrover1 343:6675661fa600 5542
rgrover1 343:6675661fa600 5543 /* Bit 0 : Enable or disable device address matching using device address 0. */
rgrover1 343:6675661fa600 5544 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
rgrover1 343:6675661fa600 5545 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
rgrover1 343:6675661fa600 5546 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */
rgrover1 343:6675661fa600 5547 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */
rgrover1 343:6675661fa600 5548
rgrover1 343:6675661fa600 5549 /* Register: RADIO_OVERRIDE0 */
rgrover1 343:6675661fa600 5550 /* Description: Trim value override register 0. */
rgrover1 343:6675661fa600 5551
rgrover1 343:6675661fa600 5552 /* Bits 31..0 : Trim value override 0. */
rgrover1 343:6675661fa600 5553 #define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */
rgrover1 343:6675661fa600 5554 #define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */
rgrover1 343:6675661fa600 5555
rgrover1 343:6675661fa600 5556 /* Register: RADIO_OVERRIDE1 */
rgrover1 343:6675661fa600 5557 /* Description: Trim value override register 1. */
rgrover1 343:6675661fa600 5558
rgrover1 343:6675661fa600 5559 /* Bits 31..0 : Trim value override 1. */
rgrover1 343:6675661fa600 5560 #define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */
rgrover1 343:6675661fa600 5561 #define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */
rgrover1 343:6675661fa600 5562
rgrover1 343:6675661fa600 5563 /* Register: RADIO_OVERRIDE2 */
rgrover1 343:6675661fa600 5564 /* Description: Trim value override register 2. */
rgrover1 343:6675661fa600 5565
rgrover1 343:6675661fa600 5566 /* Bits 31..0 : Trim value override 2. */
rgrover1 343:6675661fa600 5567 #define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */
rgrover1 343:6675661fa600 5568 #define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */
rgrover1 343:6675661fa600 5569
rgrover1 343:6675661fa600 5570 /* Register: RADIO_OVERRIDE3 */
rgrover1 343:6675661fa600 5571 /* Description: Trim value override register 3. */
rgrover1 343:6675661fa600 5572
rgrover1 343:6675661fa600 5573 /* Bits 31..0 : Trim value override 3. */
rgrover1 343:6675661fa600 5574 #define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */
rgrover1 343:6675661fa600 5575 #define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */
rgrover1 343:6675661fa600 5576
rgrover1 343:6675661fa600 5577 /* Register: RADIO_OVERRIDE4 */
rgrover1 343:6675661fa600 5578 /* Description: Trim value override register 4. */
rgrover1 343:6675661fa600 5579
rgrover1 343:6675661fa600 5580 /* Bit 31 : Enable or disable override of default trim values. */
rgrover1 343:6675661fa600 5581 #define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */
rgrover1 343:6675661fa600 5582 #define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
rgrover1 343:6675661fa600 5583 #define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */
rgrover1 343:6675661fa600 5584 #define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */
rgrover1 343:6675661fa600 5585
rgrover1 343:6675661fa600 5586 /* Bits 27..0 : Trim value override 4. */
rgrover1 343:6675661fa600 5587 #define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */
rgrover1 343:6675661fa600 5588 #define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */
rgrover1 343:6675661fa600 5589
rgrover1 343:6675661fa600 5590 /* Register: RADIO_POWER */
rgrover1 343:6675661fa600 5591 /* Description: Peripheral power control. */
rgrover1 343:6675661fa600 5592
rgrover1 343:6675661fa600 5593 /* Bit 0 : Peripheral power control. */
rgrover1 343:6675661fa600 5594 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
rgrover1 343:6675661fa600 5595 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
rgrover1 343:6675661fa600 5596 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
rgrover1 343:6675661fa600 5597 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
rgrover1 343:6675661fa600 5598
rgrover1 343:6675661fa600 5599
rgrover1 343:6675661fa600 5600 /* Peripheral: RNG */
rgrover1 343:6675661fa600 5601 /* Description: Random Number Generator. */
rgrover1 343:6675661fa600 5602
rgrover1 343:6675661fa600 5603 /* Register: RNG_SHORTS */
rgrover1 343:6675661fa600 5604 /* Description: Shortcuts for the RNG. */
rgrover1 343:6675661fa600 5605
rgrover1 343:6675661fa600 5606 /* Bit 0 : Shortcut between VALRDY event and STOP task. */
rgrover1 343:6675661fa600 5607 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
rgrover1 343:6675661fa600 5608 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
rgrover1 343:6675661fa600 5609 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 5610 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 5611
rgrover1 343:6675661fa600 5612 /* Register: RNG_INTENSET */
rgrover1 343:6675661fa600 5613 /* Description: Interrupt enable set register */
rgrover1 343:6675661fa600 5614
rgrover1 343:6675661fa600 5615 /* Bit 0 : Enable interrupt on VALRDY event. */
rgrover1 343:6675661fa600 5616 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
rgrover1 343:6675661fa600 5617 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
rgrover1 343:6675661fa600 5618 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5619 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5620 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 5621
rgrover1 343:6675661fa600 5622 /* Register: RNG_INTENCLR */
rgrover1 343:6675661fa600 5623 /* Description: Interrupt enable clear register */
rgrover1 343:6675661fa600 5624
rgrover1 343:6675661fa600 5625 /* Bit 0 : Disable interrupt on VALRDY event. */
rgrover1 343:6675661fa600 5626 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
rgrover1 343:6675661fa600 5627 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
rgrover1 343:6675661fa600 5628 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5629 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5630 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 5631
rgrover1 343:6675661fa600 5632 /* Register: RNG_CONFIG */
rgrover1 343:6675661fa600 5633 /* Description: Configuration register. */
rgrover1 343:6675661fa600 5634
rgrover1 343:6675661fa600 5635 /* Bit 0 : Digital error correction enable. */
rgrover1 343:6675661fa600 5636 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
rgrover1 343:6675661fa600 5637 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
rgrover1 343:6675661fa600 5638 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */
rgrover1 343:6675661fa600 5639 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */
rgrover1 343:6675661fa600 5640
rgrover1 343:6675661fa600 5641 /* Register: RNG_VALUE */
rgrover1 343:6675661fa600 5642 /* Description: RNG random number. */
rgrover1 343:6675661fa600 5643
rgrover1 343:6675661fa600 5644 /* Bits 7..0 : Generated random number. */
rgrover1 343:6675661fa600 5645 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
rgrover1 343:6675661fa600 5646 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
rgrover1 343:6675661fa600 5647
rgrover1 343:6675661fa600 5648 /* Register: RNG_POWER */
rgrover1 343:6675661fa600 5649 /* Description: Peripheral power control. */
rgrover1 343:6675661fa600 5650
rgrover1 343:6675661fa600 5651 /* Bit 0 : Peripheral power control. */
rgrover1 343:6675661fa600 5652 #define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
rgrover1 343:6675661fa600 5653 #define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
rgrover1 343:6675661fa600 5654 #define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
rgrover1 343:6675661fa600 5655 #define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
rgrover1 343:6675661fa600 5656
rgrover1 343:6675661fa600 5657
rgrover1 343:6675661fa600 5658 /* Peripheral: RTC */
rgrover1 343:6675661fa600 5659 /* Description: Real time counter 0. */
rgrover1 343:6675661fa600 5660
rgrover1 343:6675661fa600 5661 /* Register: RTC_INTENSET */
rgrover1 343:6675661fa600 5662 /* Description: Interrupt enable set register. */
rgrover1 343:6675661fa600 5663
rgrover1 343:6675661fa600 5664 /* Bit 19 : Enable interrupt on COMPARE[3] event. */
rgrover1 343:6675661fa600 5665 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
rgrover1 343:6675661fa600 5666 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
rgrover1 343:6675661fa600 5667 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5668 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5669 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 5670
rgrover1 343:6675661fa600 5671 /* Bit 18 : Enable interrupt on COMPARE[2] event. */
rgrover1 343:6675661fa600 5672 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
rgrover1 343:6675661fa600 5673 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
rgrover1 343:6675661fa600 5674 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5675 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5676 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 5677
rgrover1 343:6675661fa600 5678 /* Bit 17 : Enable interrupt on COMPARE[1] event. */
rgrover1 343:6675661fa600 5679 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
rgrover1 343:6675661fa600 5680 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
rgrover1 343:6675661fa600 5681 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5682 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5683 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 5684
rgrover1 343:6675661fa600 5685 /* Bit 16 : Enable interrupt on COMPARE[0] event. */
rgrover1 343:6675661fa600 5686 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
rgrover1 343:6675661fa600 5687 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
rgrover1 343:6675661fa600 5688 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5689 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5690 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 5691
rgrover1 343:6675661fa600 5692 /* Bit 1 : Enable interrupt on OVRFLW event. */
rgrover1 343:6675661fa600 5693 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
rgrover1 343:6675661fa600 5694 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
rgrover1 343:6675661fa600 5695 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5696 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5697 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 5698
rgrover1 343:6675661fa600 5699 /* Bit 0 : Enable interrupt on TICK event. */
rgrover1 343:6675661fa600 5700 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
rgrover1 343:6675661fa600 5701 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
rgrover1 343:6675661fa600 5702 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5703 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5704 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 5705
rgrover1 343:6675661fa600 5706 /* Register: RTC_INTENCLR */
rgrover1 343:6675661fa600 5707 /* Description: Interrupt enable clear register. */
rgrover1 343:6675661fa600 5708
rgrover1 343:6675661fa600 5709 /* Bit 19 : Disable interrupt on COMPARE[3] event. */
rgrover1 343:6675661fa600 5710 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
rgrover1 343:6675661fa600 5711 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
rgrover1 343:6675661fa600 5712 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5713 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5714 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 5715
rgrover1 343:6675661fa600 5716 /* Bit 18 : Disable interrupt on COMPARE[2] event. */
rgrover1 343:6675661fa600 5717 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
rgrover1 343:6675661fa600 5718 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
rgrover1 343:6675661fa600 5719 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5720 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5721 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 5722
rgrover1 343:6675661fa600 5723 /* Bit 17 : Disable interrupt on COMPARE[1] event. */
rgrover1 343:6675661fa600 5724 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
rgrover1 343:6675661fa600 5725 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
rgrover1 343:6675661fa600 5726 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5727 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5728 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 5729
rgrover1 343:6675661fa600 5730 /* Bit 16 : Disable interrupt on COMPARE[0] event. */
rgrover1 343:6675661fa600 5731 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
rgrover1 343:6675661fa600 5732 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
rgrover1 343:6675661fa600 5733 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5734 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5735 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 5736
rgrover1 343:6675661fa600 5737 /* Bit 1 : Disable interrupt on OVRFLW event. */
rgrover1 343:6675661fa600 5738 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
rgrover1 343:6675661fa600 5739 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
rgrover1 343:6675661fa600 5740 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5741 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5742 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 5743
rgrover1 343:6675661fa600 5744 /* Bit 0 : Disable interrupt on TICK event. */
rgrover1 343:6675661fa600 5745 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
rgrover1 343:6675661fa600 5746 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
rgrover1 343:6675661fa600 5747 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5748 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5749 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 5750
rgrover1 343:6675661fa600 5751 /* Register: RTC_EVTEN */
rgrover1 343:6675661fa600 5752 /* Description: Configures event enable routing to PPI for each RTC event. */
rgrover1 343:6675661fa600 5753
rgrover1 343:6675661fa600 5754 /* Bit 19 : COMPARE[3] event enable. */
rgrover1 343:6675661fa600 5755 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
rgrover1 343:6675661fa600 5756 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
rgrover1 343:6675661fa600 5757 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */
rgrover1 343:6675661fa600 5758 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */
rgrover1 343:6675661fa600 5759
rgrover1 343:6675661fa600 5760 /* Bit 18 : COMPARE[2] event enable. */
rgrover1 343:6675661fa600 5761 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
rgrover1 343:6675661fa600 5762 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
rgrover1 343:6675661fa600 5763 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */
rgrover1 343:6675661fa600 5764 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */
rgrover1 343:6675661fa600 5765
rgrover1 343:6675661fa600 5766 /* Bit 17 : COMPARE[1] event enable. */
rgrover1 343:6675661fa600 5767 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
rgrover1 343:6675661fa600 5768 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
rgrover1 343:6675661fa600 5769 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */
rgrover1 343:6675661fa600 5770 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */
rgrover1 343:6675661fa600 5771
rgrover1 343:6675661fa600 5772 /* Bit 16 : COMPARE[0] event enable. */
rgrover1 343:6675661fa600 5773 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
rgrover1 343:6675661fa600 5774 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
rgrover1 343:6675661fa600 5775 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */
rgrover1 343:6675661fa600 5776 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */
rgrover1 343:6675661fa600 5777
rgrover1 343:6675661fa600 5778 /* Bit 1 : OVRFLW event enable. */
rgrover1 343:6675661fa600 5779 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
rgrover1 343:6675661fa600 5780 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
rgrover1 343:6675661fa600 5781 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */
rgrover1 343:6675661fa600 5782 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */
rgrover1 343:6675661fa600 5783
rgrover1 343:6675661fa600 5784 /* Bit 0 : TICK event enable. */
rgrover1 343:6675661fa600 5785 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
rgrover1 343:6675661fa600 5786 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
rgrover1 343:6675661fa600 5787 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */
rgrover1 343:6675661fa600 5788 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */
rgrover1 343:6675661fa600 5789
rgrover1 343:6675661fa600 5790 /* Register: RTC_EVTENSET */
rgrover1 343:6675661fa600 5791 /* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
rgrover1 343:6675661fa600 5792
rgrover1 343:6675661fa600 5793 /* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
rgrover1 343:6675661fa600 5794 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
rgrover1 343:6675661fa600 5795 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
rgrover1 343:6675661fa600 5796 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */
rgrover1 343:6675661fa600 5797 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */
rgrover1 343:6675661fa600 5798 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */
rgrover1 343:6675661fa600 5799
rgrover1 343:6675661fa600 5800 /* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
rgrover1 343:6675661fa600 5801 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
rgrover1 343:6675661fa600 5802 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
rgrover1 343:6675661fa600 5803 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */
rgrover1 343:6675661fa600 5804 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */
rgrover1 343:6675661fa600 5805 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */
rgrover1 343:6675661fa600 5806
rgrover1 343:6675661fa600 5807 /* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
rgrover1 343:6675661fa600 5808 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
rgrover1 343:6675661fa600 5809 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
rgrover1 343:6675661fa600 5810 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */
rgrover1 343:6675661fa600 5811 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */
rgrover1 343:6675661fa600 5812 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */
rgrover1 343:6675661fa600 5813
rgrover1 343:6675661fa600 5814 /* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
rgrover1 343:6675661fa600 5815 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
rgrover1 343:6675661fa600 5816 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
rgrover1 343:6675661fa600 5817 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */
rgrover1 343:6675661fa600 5818 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */
rgrover1 343:6675661fa600 5819 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */
rgrover1 343:6675661fa600 5820
rgrover1 343:6675661fa600 5821 /* Bit 1 : Enable routing to PPI of OVRFLW event. */
rgrover1 343:6675661fa600 5822 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
rgrover1 343:6675661fa600 5823 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
rgrover1 343:6675661fa600 5824 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */
rgrover1 343:6675661fa600 5825 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */
rgrover1 343:6675661fa600 5826 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */
rgrover1 343:6675661fa600 5827
rgrover1 343:6675661fa600 5828 /* Bit 0 : Enable routing to PPI of TICK event. */
rgrover1 343:6675661fa600 5829 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
rgrover1 343:6675661fa600 5830 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
rgrover1 343:6675661fa600 5831 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */
rgrover1 343:6675661fa600 5832 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */
rgrover1 343:6675661fa600 5833 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */
rgrover1 343:6675661fa600 5834
rgrover1 343:6675661fa600 5835 /* Register: RTC_EVTENCLR */
rgrover1 343:6675661fa600 5836 /* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
rgrover1 343:6675661fa600 5837
rgrover1 343:6675661fa600 5838 /* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
rgrover1 343:6675661fa600 5839 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
rgrover1 343:6675661fa600 5840 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
rgrover1 343:6675661fa600 5841 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */
rgrover1 343:6675661fa600 5842 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */
rgrover1 343:6675661fa600 5843 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */
rgrover1 343:6675661fa600 5844
rgrover1 343:6675661fa600 5845 /* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
rgrover1 343:6675661fa600 5846 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
rgrover1 343:6675661fa600 5847 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
rgrover1 343:6675661fa600 5848 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */
rgrover1 343:6675661fa600 5849 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */
rgrover1 343:6675661fa600 5850 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */
rgrover1 343:6675661fa600 5851
rgrover1 343:6675661fa600 5852 /* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
rgrover1 343:6675661fa600 5853 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
rgrover1 343:6675661fa600 5854 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
rgrover1 343:6675661fa600 5855 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */
rgrover1 343:6675661fa600 5856 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */
rgrover1 343:6675661fa600 5857 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */
rgrover1 343:6675661fa600 5858
rgrover1 343:6675661fa600 5859 /* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
rgrover1 343:6675661fa600 5860 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
rgrover1 343:6675661fa600 5861 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
rgrover1 343:6675661fa600 5862 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */
rgrover1 343:6675661fa600 5863 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */
rgrover1 343:6675661fa600 5864 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */
rgrover1 343:6675661fa600 5865
rgrover1 343:6675661fa600 5866 /* Bit 1 : Disable routing to PPI of OVRFLW event. */
rgrover1 343:6675661fa600 5867 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
rgrover1 343:6675661fa600 5868 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
rgrover1 343:6675661fa600 5869 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */
rgrover1 343:6675661fa600 5870 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */
rgrover1 343:6675661fa600 5871 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */
rgrover1 343:6675661fa600 5872
rgrover1 343:6675661fa600 5873 /* Bit 0 : Disable routing to PPI of TICK event. */
rgrover1 343:6675661fa600 5874 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
rgrover1 343:6675661fa600 5875 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
rgrover1 343:6675661fa600 5876 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */
rgrover1 343:6675661fa600 5877 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */
rgrover1 343:6675661fa600 5878 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */
rgrover1 343:6675661fa600 5879
rgrover1 343:6675661fa600 5880 /* Register: RTC_COUNTER */
rgrover1 343:6675661fa600 5881 /* Description: Current COUNTER value. */
rgrover1 343:6675661fa600 5882
rgrover1 343:6675661fa600 5883 /* Bits 23..0 : Counter value. */
rgrover1 343:6675661fa600 5884 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
rgrover1 343:6675661fa600 5885 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
rgrover1 343:6675661fa600 5886
rgrover1 343:6675661fa600 5887 /* Register: RTC_PRESCALER */
rgrover1 343:6675661fa600 5888 /* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
rgrover1 343:6675661fa600 5889
rgrover1 343:6675661fa600 5890 /* Bits 11..0 : RTC PRESCALER value. */
rgrover1 343:6675661fa600 5891 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
rgrover1 343:6675661fa600 5892 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
rgrover1 343:6675661fa600 5893
rgrover1 343:6675661fa600 5894 /* Register: RTC_CC */
rgrover1 343:6675661fa600 5895 /* Description: Capture/compare registers. */
rgrover1 343:6675661fa600 5896
rgrover1 343:6675661fa600 5897 /* Bits 23..0 : Compare value. */
rgrover1 343:6675661fa600 5898 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
rgrover1 343:6675661fa600 5899 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
rgrover1 343:6675661fa600 5900
rgrover1 343:6675661fa600 5901 /* Register: RTC_POWER */
rgrover1 343:6675661fa600 5902 /* Description: Peripheral power control. */
rgrover1 343:6675661fa600 5903
rgrover1 343:6675661fa600 5904 /* Bit 0 : Peripheral power control. */
rgrover1 343:6675661fa600 5905 #define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
rgrover1 343:6675661fa600 5906 #define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
rgrover1 343:6675661fa600 5907 #define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
rgrover1 343:6675661fa600 5908 #define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
rgrover1 343:6675661fa600 5909
rgrover1 343:6675661fa600 5910
rgrover1 343:6675661fa600 5911 /* Peripheral: SPI */
rgrover1 343:6675661fa600 5912 /* Description: SPI master 0. */
rgrover1 343:6675661fa600 5913
rgrover1 343:6675661fa600 5914 /* Register: SPI_INTENSET */
rgrover1 343:6675661fa600 5915 /* Description: Interrupt enable set register. */
rgrover1 343:6675661fa600 5916
rgrover1 343:6675661fa600 5917 /* Bit 2 : Enable interrupt on READY event. */
rgrover1 343:6675661fa600 5918 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
rgrover1 343:6675661fa600 5919 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
rgrover1 343:6675661fa600 5920 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5921 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5922 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 5923
rgrover1 343:6675661fa600 5924 /* Register: SPI_INTENCLR */
rgrover1 343:6675661fa600 5925 /* Description: Interrupt enable clear register. */
rgrover1 343:6675661fa600 5926
rgrover1 343:6675661fa600 5927 /* Bit 2 : Disable interrupt on READY event. */
rgrover1 343:6675661fa600 5928 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
rgrover1 343:6675661fa600 5929 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
rgrover1 343:6675661fa600 5930 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 5931 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 5932 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 5933
rgrover1 343:6675661fa600 5934 /* Register: SPI_ENABLE */
rgrover1 343:6675661fa600 5935 /* Description: Enable SPI. */
rgrover1 343:6675661fa600 5936
rgrover1 343:6675661fa600 5937 /* Bits 2..0 : Enable or disable SPI. */
rgrover1 343:6675661fa600 5938 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
rgrover1 343:6675661fa600 5939 #define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
rgrover1 343:6675661fa600 5940 #define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */
rgrover1 343:6675661fa600 5941 #define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */
rgrover1 343:6675661fa600 5942
rgrover1 343:6675661fa600 5943 /* Register: SPI_RXD */
rgrover1 343:6675661fa600 5944 /* Description: RX data. */
rgrover1 343:6675661fa600 5945
rgrover1 343:6675661fa600 5946 /* Bits 7..0 : RX data from last transfer. */
rgrover1 343:6675661fa600 5947 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
rgrover1 343:6675661fa600 5948 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
rgrover1 343:6675661fa600 5949
rgrover1 343:6675661fa600 5950 /* Register: SPI_TXD */
rgrover1 343:6675661fa600 5951 /* Description: TX data. */
rgrover1 343:6675661fa600 5952
rgrover1 343:6675661fa600 5953 /* Bits 7..0 : TX data for next transfer. */
rgrover1 343:6675661fa600 5954 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
rgrover1 343:6675661fa600 5955 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
rgrover1 343:6675661fa600 5956
rgrover1 343:6675661fa600 5957 /* Register: SPI_FREQUENCY */
rgrover1 343:6675661fa600 5958 /* Description: SPI frequency */
rgrover1 343:6675661fa600 5959
rgrover1 343:6675661fa600 5960 /* Bits 31..0 : SPI data rate. */
rgrover1 343:6675661fa600 5961 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
rgrover1 343:6675661fa600 5962 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
rgrover1 343:6675661fa600 5963 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */
rgrover1 343:6675661fa600 5964 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */
rgrover1 343:6675661fa600 5965 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */
rgrover1 343:6675661fa600 5966 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */
rgrover1 343:6675661fa600 5967 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */
rgrover1 343:6675661fa600 5968 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */
rgrover1 343:6675661fa600 5969 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */
rgrover1 343:6675661fa600 5970
rgrover1 343:6675661fa600 5971 /* Register: SPI_CONFIG */
rgrover1 343:6675661fa600 5972 /* Description: Configuration register. */
rgrover1 343:6675661fa600 5973
rgrover1 343:6675661fa600 5974 /* Bit 2 : Serial clock (SCK) polarity. */
rgrover1 343:6675661fa600 5975 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
rgrover1 343:6675661fa600 5976 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
rgrover1 343:6675661fa600 5977 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
rgrover1 343:6675661fa600 5978 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
rgrover1 343:6675661fa600 5979
rgrover1 343:6675661fa600 5980 /* Bit 1 : Serial clock (SCK) phase. */
rgrover1 343:6675661fa600 5981 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
rgrover1 343:6675661fa600 5982 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
rgrover1 343:6675661fa600 5983 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
rgrover1 343:6675661fa600 5984 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
rgrover1 343:6675661fa600 5985
rgrover1 343:6675661fa600 5986 /* Bit 0 : Bit order. */
rgrover1 343:6675661fa600 5987 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
rgrover1 343:6675661fa600 5988 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
rgrover1 343:6675661fa600 5989 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
rgrover1 343:6675661fa600 5990 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
rgrover1 343:6675661fa600 5991
rgrover1 343:6675661fa600 5992 /* Register: SPI_POWER */
rgrover1 343:6675661fa600 5993 /* Description: Peripheral power control. */
rgrover1 343:6675661fa600 5994
rgrover1 343:6675661fa600 5995 /* Bit 0 : Peripheral power control. */
rgrover1 343:6675661fa600 5996 #define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
rgrover1 343:6675661fa600 5997 #define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
rgrover1 343:6675661fa600 5998 #define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
rgrover1 343:6675661fa600 5999 #define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
rgrover1 343:6675661fa600 6000
rgrover1 343:6675661fa600 6001
rgrover1 343:6675661fa600 6002 /* Peripheral: SPIM */
rgrover1 343:6675661fa600 6003 /* Description: SPI master with easyDMA 1. */
rgrover1 343:6675661fa600 6004
rgrover1 343:6675661fa600 6005 /* Register: SPIM_SHORTS */
rgrover1 343:6675661fa600 6006 /* Description: Shortcuts for SPIM. */
rgrover1 343:6675661fa600 6007
rgrover1 343:6675661fa600 6008 /* Bit 17 : Shortcut between END event and START task. */
rgrover1 343:6675661fa600 6009 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
rgrover1 343:6675661fa600 6010 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
rgrover1 343:6675661fa600 6011 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 6012 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 6013
rgrover1 343:6675661fa600 6014 /* Register: SPIM_INTENSET */
rgrover1 343:6675661fa600 6015 /* Description: Interrupt enable set register. */
rgrover1 343:6675661fa600 6016
rgrover1 343:6675661fa600 6017 /* Bit 19 : Enable interrupt on STARTED event. */
rgrover1 343:6675661fa600 6018 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
rgrover1 343:6675661fa600 6019 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
rgrover1 343:6675661fa600 6020 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6021 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6022 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6023
rgrover1 343:6675661fa600 6024 /* Bit 8 : Enable interrupt on ENDTX event. */
rgrover1 343:6675661fa600 6025 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
rgrover1 343:6675661fa600 6026 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
rgrover1 343:6675661fa600 6027 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6028 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6029 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6030
rgrover1 343:6675661fa600 6031 /* Bit 6 : Enable interrupt on END event. */
rgrover1 343:6675661fa600 6032 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
rgrover1 343:6675661fa600 6033 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
rgrover1 343:6675661fa600 6034 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6035 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6036 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6037
rgrover1 343:6675661fa600 6038 /* Bit 4 : Enable interrupt on ENDRX event. */
rgrover1 343:6675661fa600 6039 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
rgrover1 343:6675661fa600 6040 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
rgrover1 343:6675661fa600 6041 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6042 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6043 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6044
rgrover1 343:6675661fa600 6045 /* Bit 1 : Enable interrupt on STOPPED event. */
rgrover1 343:6675661fa600 6046 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
rgrover1 343:6675661fa600 6047 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
rgrover1 343:6675661fa600 6048 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6049 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6050 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6051
rgrover1 343:6675661fa600 6052 /* Register: SPIM_INTENCLR */
rgrover1 343:6675661fa600 6053 /* Description: Interrupt enable clear register. */
rgrover1 343:6675661fa600 6054
rgrover1 343:6675661fa600 6055 /* Bit 19 : Disable interrupt on STARTED event. */
rgrover1 343:6675661fa600 6056 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
rgrover1 343:6675661fa600 6057 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
rgrover1 343:6675661fa600 6058 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6059 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6060 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6061
rgrover1 343:6675661fa600 6062 /* Bit 8 : Disable interrupt on ENDTX event. */
rgrover1 343:6675661fa600 6063 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
rgrover1 343:6675661fa600 6064 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
rgrover1 343:6675661fa600 6065 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6066 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6067 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6068
rgrover1 343:6675661fa600 6069 /* Bit 6 : Disable interrupt on END event. */
rgrover1 343:6675661fa600 6070 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
rgrover1 343:6675661fa600 6071 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
rgrover1 343:6675661fa600 6072 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6073 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6074 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6075
rgrover1 343:6675661fa600 6076 /* Bit 4 : Disable interrupt on ENDRX event. */
rgrover1 343:6675661fa600 6077 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
rgrover1 343:6675661fa600 6078 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
rgrover1 343:6675661fa600 6079 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6080 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6081 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6082
rgrover1 343:6675661fa600 6083 /* Bit 1 : Disable interrupt on STOPPED event. */
rgrover1 343:6675661fa600 6084 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
rgrover1 343:6675661fa600 6085 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
rgrover1 343:6675661fa600 6086 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6087 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6088 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6089
rgrover1 343:6675661fa600 6090 /* Register: SPIM_ENABLE */
rgrover1 343:6675661fa600 6091 /* Description: Enable SPIM. */
rgrover1 343:6675661fa600 6092
rgrover1 343:6675661fa600 6093 /* Bits 3..0 : Enable or disable SPIM. */
rgrover1 343:6675661fa600 6094 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
rgrover1 343:6675661fa600 6095 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
rgrover1 343:6675661fa600 6096 #define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */
rgrover1 343:6675661fa600 6097 #define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */
rgrover1 343:6675661fa600 6098
rgrover1 343:6675661fa600 6099 /* Register: SPIM_RXDDATA */
rgrover1 343:6675661fa600 6100 /* Description: RXD register. */
rgrover1 343:6675661fa600 6101
rgrover1 343:6675661fa600 6102 /* Bits 7..0 : RX data received. Double buffered. */
rgrover1 343:6675661fa600 6103 #define SPIM_RXDDATA_RXD_Pos (0UL) /*!< Position of RXD field. */
rgrover1 343:6675661fa600 6104 #define SPIM_RXDDATA_RXD_Msk (0xFFUL << SPIM_RXDDATA_RXD_Pos) /*!< Bit mask of RXD field. */
rgrover1 343:6675661fa600 6105
rgrover1 343:6675661fa600 6106 /* Register: SPIM_TXDDATA */
rgrover1 343:6675661fa600 6107 /* Description: TXD register. */
rgrover1 343:6675661fa600 6108
rgrover1 343:6675661fa600 6109 /* Bits 7..0 : TX data to send. Double buffered. */
rgrover1 343:6675661fa600 6110 #define SPIM_TXDDATA_TXD_Pos (0UL) /*!< Position of TXD field. */
rgrover1 343:6675661fa600 6111 #define SPIM_TXDDATA_TXD_Msk (0xFFUL << SPIM_TXDDATA_TXD_Pos) /*!< Bit mask of TXD field. */
rgrover1 343:6675661fa600 6112
rgrover1 343:6675661fa600 6113 /* Register: SPIM_FREQUENCY */
rgrover1 343:6675661fa600 6114 /* Description: SPI frequency. */
rgrover1 343:6675661fa600 6115
rgrover1 343:6675661fa600 6116 /* Bits 31..0 : SPI master data rate. */
rgrover1 343:6675661fa600 6117 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
rgrover1 343:6675661fa600 6118 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
rgrover1 343:6675661fa600 6119 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps. */
rgrover1 343:6675661fa600 6120 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
rgrover1 343:6675661fa600 6121 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps. */
rgrover1 343:6675661fa600 6122 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps. */
rgrover1 343:6675661fa600 6123 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps. */
rgrover1 343:6675661fa600 6124 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */
rgrover1 343:6675661fa600 6125 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */
rgrover1 343:6675661fa600 6126
rgrover1 343:6675661fa600 6127 /* Register: SPIM_CONFIG */
rgrover1 343:6675661fa600 6128 /* Description: Configuration register. */
rgrover1 343:6675661fa600 6129
rgrover1 343:6675661fa600 6130 /* Bit 2 : Serial clock (SCK) polarity. */
rgrover1 343:6675661fa600 6131 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
rgrover1 343:6675661fa600 6132 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
rgrover1 343:6675661fa600 6133 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
rgrover1 343:6675661fa600 6134 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
rgrover1 343:6675661fa600 6135
rgrover1 343:6675661fa600 6136 /* Bit 1 : Serial clock (SCK) phase. */
rgrover1 343:6675661fa600 6137 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
rgrover1 343:6675661fa600 6138 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
rgrover1 343:6675661fa600 6139 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
rgrover1 343:6675661fa600 6140 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
rgrover1 343:6675661fa600 6141
rgrover1 343:6675661fa600 6142 /* Bit 0 : Bit order. */
rgrover1 343:6675661fa600 6143 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
rgrover1 343:6675661fa600 6144 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
rgrover1 343:6675661fa600 6145 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
rgrover1 343:6675661fa600 6146 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
rgrover1 343:6675661fa600 6147
rgrover1 343:6675661fa600 6148 /* Register: SPIM_ORC */
rgrover1 343:6675661fa600 6149 /* Description: Over-read character. */
rgrover1 343:6675661fa600 6150
rgrover1 343:6675661fa600 6151 /* Bits 7..0 : Over-read character. */
rgrover1 343:6675661fa600 6152 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
rgrover1 343:6675661fa600 6153 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
rgrover1 343:6675661fa600 6154
rgrover1 343:6675661fa600 6155 /* Register: SPIM_POWER */
rgrover1 343:6675661fa600 6156 /* Description: Peripheral power control. */
rgrover1 343:6675661fa600 6157
rgrover1 343:6675661fa600 6158 /* Bit 0 : Peripheral power control. */
rgrover1 343:6675661fa600 6159 #define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
rgrover1 343:6675661fa600 6160 #define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
rgrover1 343:6675661fa600 6161 #define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
rgrover1 343:6675661fa600 6162 #define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
rgrover1 343:6675661fa600 6163
rgrover1 343:6675661fa600 6164 /* Register: SPIM_RXD_PTR */
rgrover1 343:6675661fa600 6165 /* Description: Data pointer. */
rgrover1 343:6675661fa600 6166
rgrover1 343:6675661fa600 6167 /* Bits 31..0 : Data pointer. */
rgrover1 343:6675661fa600 6168 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
rgrover1 343:6675661fa600 6169 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
rgrover1 343:6675661fa600 6170
rgrover1 343:6675661fa600 6171 /* Register: SPIM_RXD_MAXCNT */
rgrover1 343:6675661fa600 6172 /* Description: Maximum number of buffer bytes to receive. */
rgrover1 343:6675661fa600 6173
rgrover1 343:6675661fa600 6174 /* Bits 7..0 : Maximum number of buffer bytes to receive. */
rgrover1 343:6675661fa600 6175 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
rgrover1 343:6675661fa600 6176 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
rgrover1 343:6675661fa600 6177
rgrover1 343:6675661fa600 6178 /* Register: SPIM_RXD_AMOUNT */
rgrover1 343:6675661fa600 6179 /* Description: Number of bytes received in the last transaction. */
rgrover1 343:6675661fa600 6180
rgrover1 343:6675661fa600 6181 /* Bits 7..0 : Number of bytes received in the last transaction. */
rgrover1 343:6675661fa600 6182 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
rgrover1 343:6675661fa600 6183 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
rgrover1 343:6675661fa600 6184
rgrover1 343:6675661fa600 6185 /* Register: SPIM_TXD_PTR */
rgrover1 343:6675661fa600 6186 /* Description: Data pointer. */
rgrover1 343:6675661fa600 6187
rgrover1 343:6675661fa600 6188 /* Bits 31..0 : Data pointer. */
rgrover1 343:6675661fa600 6189 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
rgrover1 343:6675661fa600 6190 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
rgrover1 343:6675661fa600 6191
rgrover1 343:6675661fa600 6192 /* Register: SPIM_TXD_MAXCNT */
rgrover1 343:6675661fa600 6193 /* Description: Maximum number of buffer bytes to send. */
rgrover1 343:6675661fa600 6194
rgrover1 343:6675661fa600 6195 /* Bits 7..0 : Maximum number of buffer bytes to send. */
rgrover1 343:6675661fa600 6196 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
rgrover1 343:6675661fa600 6197 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
rgrover1 343:6675661fa600 6198
rgrover1 343:6675661fa600 6199 /* Register: SPIM_TXD_AMOUNT */
rgrover1 343:6675661fa600 6200 /* Description: Number of bytes sent in the last transaction. */
rgrover1 343:6675661fa600 6201
rgrover1 343:6675661fa600 6202 /* Bits 7..0 : Number of bytes sent in the last transaction. */
rgrover1 343:6675661fa600 6203 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
rgrover1 343:6675661fa600 6204 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
rgrover1 343:6675661fa600 6205
rgrover1 343:6675661fa600 6206
rgrover1 343:6675661fa600 6207 /* Peripheral: SPIS */
rgrover1 343:6675661fa600 6208 /* Description: SPI slave 1. */
rgrover1 343:6675661fa600 6209
rgrover1 343:6675661fa600 6210 /* Register: SPIS_SHORTS */
rgrover1 343:6675661fa600 6211 /* Description: Shortcuts for SPIS. */
rgrover1 343:6675661fa600 6212
rgrover1 343:6675661fa600 6213 /* Bit 2 : Shortcut between END event and the ACQUIRE task. */
rgrover1 343:6675661fa600 6214 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
rgrover1 343:6675661fa600 6215 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
rgrover1 343:6675661fa600 6216 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 6217 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 6218
rgrover1 343:6675661fa600 6219 /* Register: SPIS_INTENSET */
rgrover1 343:6675661fa600 6220 /* Description: Interrupt enable set register. */
rgrover1 343:6675661fa600 6221
rgrover1 343:6675661fa600 6222 /* Bit 10 : Enable interrupt on ACQUIRED event. */
rgrover1 343:6675661fa600 6223 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
rgrover1 343:6675661fa600 6224 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
rgrover1 343:6675661fa600 6225 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6226 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6227 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6228
rgrover1 343:6675661fa600 6229 /* Bit 1 : Enable interrupt on END event. */
rgrover1 343:6675661fa600 6230 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
rgrover1 343:6675661fa600 6231 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
rgrover1 343:6675661fa600 6232 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6233 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6234 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6235
rgrover1 343:6675661fa600 6236 /* Register: SPIS_INTENCLR */
rgrover1 343:6675661fa600 6237 /* Description: Interrupt enable clear register. */
rgrover1 343:6675661fa600 6238
rgrover1 343:6675661fa600 6239 /* Bit 10 : Disable interrupt on ACQUIRED event. */
rgrover1 343:6675661fa600 6240 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
rgrover1 343:6675661fa600 6241 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
rgrover1 343:6675661fa600 6242 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6243 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6244 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6245
rgrover1 343:6675661fa600 6246 /* Bit 1 : Disable interrupt on END event. */
rgrover1 343:6675661fa600 6247 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
rgrover1 343:6675661fa600 6248 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
rgrover1 343:6675661fa600 6249 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6250 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6251 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6252
rgrover1 343:6675661fa600 6253 /* Register: SPIS_SEMSTAT */
rgrover1 343:6675661fa600 6254 /* Description: Semaphore status. */
rgrover1 343:6675661fa600 6255
rgrover1 343:6675661fa600 6256 /* Bits 1..0 : Semaphore status. */
rgrover1 343:6675661fa600 6257 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
rgrover1 343:6675661fa600 6258 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
rgrover1 343:6675661fa600 6259 #define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */
rgrover1 343:6675661fa600 6260 #define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */
rgrover1 343:6675661fa600 6261 #define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */
rgrover1 343:6675661fa600 6262 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */
rgrover1 343:6675661fa600 6263
rgrover1 343:6675661fa600 6264 /* Register: SPIS_STATUS */
rgrover1 343:6675661fa600 6265 /* Description: Status from last transaction. */
rgrover1 343:6675661fa600 6266
rgrover1 343:6675661fa600 6267 /* Bit 1 : RX buffer overflow detected, and prevented. */
rgrover1 343:6675661fa600 6268 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
rgrover1 343:6675661fa600 6269 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
rgrover1 343:6675661fa600 6270 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */
rgrover1 343:6675661fa600 6271 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */
rgrover1 343:6675661fa600 6272 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */
rgrover1 343:6675661fa600 6273
rgrover1 343:6675661fa600 6274 /* Bit 0 : TX buffer overread detected, and prevented. */
rgrover1 343:6675661fa600 6275 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
rgrover1 343:6675661fa600 6276 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
rgrover1 343:6675661fa600 6277 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */
rgrover1 343:6675661fa600 6278 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */
rgrover1 343:6675661fa600 6279 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */
rgrover1 343:6675661fa600 6280
rgrover1 343:6675661fa600 6281 /* Register: SPIS_ENABLE */
rgrover1 343:6675661fa600 6282 /* Description: Enable SPIS. */
rgrover1 343:6675661fa600 6283
rgrover1 343:6675661fa600 6284 /* Bits 2..0 : Enable or disable SPIS. */
rgrover1 343:6675661fa600 6285 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
rgrover1 343:6675661fa600 6286 #define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
rgrover1 343:6675661fa600 6287 #define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */
rgrover1 343:6675661fa600 6288 #define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */
rgrover1 343:6675661fa600 6289
rgrover1 343:6675661fa600 6290 /* Register: SPIS_MAXRX */
rgrover1 343:6675661fa600 6291 /* Description: Maximum number of bytes in the receive buffer. */
rgrover1 343:6675661fa600 6292
rgrover1 343:6675661fa600 6293 /* Bits 7..0 : Maximum number of bytes in the receive buffer. */
rgrover1 343:6675661fa600 6294 #define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */
rgrover1 343:6675661fa600 6295 #define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */
rgrover1 343:6675661fa600 6296
rgrover1 343:6675661fa600 6297 /* Register: SPIS_AMOUNTRX */
rgrover1 343:6675661fa600 6298 /* Description: Number of bytes received in last granted transaction. */
rgrover1 343:6675661fa600 6299
rgrover1 343:6675661fa600 6300 /* Bits 7..0 : Number of bytes received in last granted transaction. */
rgrover1 343:6675661fa600 6301 #define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */
rgrover1 343:6675661fa600 6302 #define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */
rgrover1 343:6675661fa600 6303
rgrover1 343:6675661fa600 6304 /* Register: SPIS_MAXTX */
rgrover1 343:6675661fa600 6305 /* Description: Maximum number of bytes in the transmit buffer. */
rgrover1 343:6675661fa600 6306
rgrover1 343:6675661fa600 6307 /* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
rgrover1 343:6675661fa600 6308 #define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */
rgrover1 343:6675661fa600 6309 #define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */
rgrover1 343:6675661fa600 6310
rgrover1 343:6675661fa600 6311 /* Register: SPIS_AMOUNTTX */
rgrover1 343:6675661fa600 6312 /* Description: Number of bytes transmitted in last granted transaction. */
rgrover1 343:6675661fa600 6313
rgrover1 343:6675661fa600 6314 /* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
rgrover1 343:6675661fa600 6315 #define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */
rgrover1 343:6675661fa600 6316 #define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */
rgrover1 343:6675661fa600 6317
rgrover1 343:6675661fa600 6318 /* Register: SPIS_CONFIG */
rgrover1 343:6675661fa600 6319 /* Description: Configuration register. */
rgrover1 343:6675661fa600 6320
rgrover1 343:6675661fa600 6321 /* Bit 2 : Serial clock (SCK) polarity. */
rgrover1 343:6675661fa600 6322 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
rgrover1 343:6675661fa600 6323 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
rgrover1 343:6675661fa600 6324 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
rgrover1 343:6675661fa600 6325 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
rgrover1 343:6675661fa600 6326
rgrover1 343:6675661fa600 6327 /* Bit 1 : Serial clock (SCK) phase. */
rgrover1 343:6675661fa600 6328 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
rgrover1 343:6675661fa600 6329 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
rgrover1 343:6675661fa600 6330 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
rgrover1 343:6675661fa600 6331 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
rgrover1 343:6675661fa600 6332
rgrover1 343:6675661fa600 6333 /* Bit 0 : Bit order. */
rgrover1 343:6675661fa600 6334 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
rgrover1 343:6675661fa600 6335 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
rgrover1 343:6675661fa600 6336 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
rgrover1 343:6675661fa600 6337 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
rgrover1 343:6675661fa600 6338
rgrover1 343:6675661fa600 6339 /* Register: SPIS_DEF */
rgrover1 343:6675661fa600 6340 /* Description: Default character. */
rgrover1 343:6675661fa600 6341
rgrover1 343:6675661fa600 6342 /* Bits 7..0 : Default character. */
rgrover1 343:6675661fa600 6343 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
rgrover1 343:6675661fa600 6344 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
rgrover1 343:6675661fa600 6345
rgrover1 343:6675661fa600 6346 /* Register: SPIS_ORC */
rgrover1 343:6675661fa600 6347 /* Description: Over-read character. */
rgrover1 343:6675661fa600 6348
rgrover1 343:6675661fa600 6349 /* Bits 7..0 : Over-read character. */
rgrover1 343:6675661fa600 6350 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
rgrover1 343:6675661fa600 6351 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
rgrover1 343:6675661fa600 6352
rgrover1 343:6675661fa600 6353 /* Register: SPIS_POWER */
rgrover1 343:6675661fa600 6354 /* Description: Peripheral power control. */
rgrover1 343:6675661fa600 6355
rgrover1 343:6675661fa600 6356 /* Bit 0 : Peripheral power control. */
rgrover1 343:6675661fa600 6357 #define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
rgrover1 343:6675661fa600 6358 #define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
rgrover1 343:6675661fa600 6359 #define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
rgrover1 343:6675661fa600 6360 #define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
rgrover1 343:6675661fa600 6361
rgrover1 343:6675661fa600 6362
rgrover1 343:6675661fa600 6363 /* Peripheral: TEMP */
rgrover1 343:6675661fa600 6364 /* Description: Temperature Sensor. */
rgrover1 343:6675661fa600 6365
rgrover1 343:6675661fa600 6366 /* Register: TEMP_INTENSET */
rgrover1 343:6675661fa600 6367 /* Description: Interrupt enable set register. */
rgrover1 343:6675661fa600 6368
rgrover1 343:6675661fa600 6369 /* Bit 0 : Enable interrupt on DATARDY event. */
rgrover1 343:6675661fa600 6370 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
rgrover1 343:6675661fa600 6371 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
rgrover1 343:6675661fa600 6372 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6373 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6374 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6375
rgrover1 343:6675661fa600 6376 /* Register: TEMP_INTENCLR */
rgrover1 343:6675661fa600 6377 /* Description: Interrupt enable clear register. */
rgrover1 343:6675661fa600 6378
rgrover1 343:6675661fa600 6379 /* Bit 0 : Disable interrupt on DATARDY event. */
rgrover1 343:6675661fa600 6380 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
rgrover1 343:6675661fa600 6381 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
rgrover1 343:6675661fa600 6382 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6383 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6384 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6385
rgrover1 343:6675661fa600 6386 /* Register: TEMP_POWER */
rgrover1 343:6675661fa600 6387 /* Description: Peripheral power control. */
rgrover1 343:6675661fa600 6388
rgrover1 343:6675661fa600 6389 /* Bit 0 : Peripheral power control. */
rgrover1 343:6675661fa600 6390 #define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
rgrover1 343:6675661fa600 6391 #define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
rgrover1 343:6675661fa600 6392 #define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
rgrover1 343:6675661fa600 6393 #define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
rgrover1 343:6675661fa600 6394
rgrover1 343:6675661fa600 6395
rgrover1 343:6675661fa600 6396 /* Peripheral: TIMER */
rgrover1 343:6675661fa600 6397 /* Description: Timer 0. */
rgrover1 343:6675661fa600 6398
rgrover1 343:6675661fa600 6399 /* Register: TIMER_SHORTS */
rgrover1 343:6675661fa600 6400 /* Description: Shortcuts for Timer. */
rgrover1 343:6675661fa600 6401
rgrover1 343:6675661fa600 6402 /* Bit 11 : Shortcut between CC[3] event and the STOP task. */
rgrover1 343:6675661fa600 6403 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
rgrover1 343:6675661fa600 6404 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
rgrover1 343:6675661fa600 6405 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 6406 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 6407
rgrover1 343:6675661fa600 6408 /* Bit 10 : Shortcut between CC[2] event and the STOP task. */
rgrover1 343:6675661fa600 6409 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
rgrover1 343:6675661fa600 6410 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
rgrover1 343:6675661fa600 6411 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 6412 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 6413
rgrover1 343:6675661fa600 6414 /* Bit 9 : Shortcut between CC[1] event and the STOP task. */
rgrover1 343:6675661fa600 6415 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
rgrover1 343:6675661fa600 6416 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
rgrover1 343:6675661fa600 6417 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 6418 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 6419
rgrover1 343:6675661fa600 6420 /* Bit 8 : Shortcut between CC[0] event and the STOP task. */
rgrover1 343:6675661fa600 6421 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
rgrover1 343:6675661fa600 6422 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
rgrover1 343:6675661fa600 6423 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 6424 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 6425
rgrover1 343:6675661fa600 6426 /* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
rgrover1 343:6675661fa600 6427 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
rgrover1 343:6675661fa600 6428 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
rgrover1 343:6675661fa600 6429 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 6430 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 6431
rgrover1 343:6675661fa600 6432 /* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
rgrover1 343:6675661fa600 6433 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
rgrover1 343:6675661fa600 6434 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
rgrover1 343:6675661fa600 6435 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 6436 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 6437
rgrover1 343:6675661fa600 6438 /* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
rgrover1 343:6675661fa600 6439 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
rgrover1 343:6675661fa600 6440 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
rgrover1 343:6675661fa600 6441 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 6442 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 6443
rgrover1 343:6675661fa600 6444 /* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
rgrover1 343:6675661fa600 6445 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
rgrover1 343:6675661fa600 6446 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
rgrover1 343:6675661fa600 6447 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 6448 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 6449
rgrover1 343:6675661fa600 6450 /* Register: TIMER_INTENSET */
rgrover1 343:6675661fa600 6451 /* Description: Interrupt enable set register. */
rgrover1 343:6675661fa600 6452
rgrover1 343:6675661fa600 6453 /* Bit 19 : Enable interrupt on COMPARE[3] */
rgrover1 343:6675661fa600 6454 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
rgrover1 343:6675661fa600 6455 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
rgrover1 343:6675661fa600 6456 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6457 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6458 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6459
rgrover1 343:6675661fa600 6460 /* Bit 18 : Enable interrupt on COMPARE[2] */
rgrover1 343:6675661fa600 6461 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
rgrover1 343:6675661fa600 6462 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
rgrover1 343:6675661fa600 6463 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6464 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6465 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6466
rgrover1 343:6675661fa600 6467 /* Bit 17 : Enable interrupt on COMPARE[1] */
rgrover1 343:6675661fa600 6468 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
rgrover1 343:6675661fa600 6469 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
rgrover1 343:6675661fa600 6470 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6471 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6472 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6473
rgrover1 343:6675661fa600 6474 /* Bit 16 : Enable interrupt on COMPARE[0] */
rgrover1 343:6675661fa600 6475 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
rgrover1 343:6675661fa600 6476 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
rgrover1 343:6675661fa600 6477 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6478 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6479 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6480
rgrover1 343:6675661fa600 6481 /* Register: TIMER_INTENCLR */
rgrover1 343:6675661fa600 6482 /* Description: Interrupt enable clear register. */
rgrover1 343:6675661fa600 6483
rgrover1 343:6675661fa600 6484 /* Bit 19 : Disable interrupt on COMPARE[3] */
rgrover1 343:6675661fa600 6485 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
rgrover1 343:6675661fa600 6486 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
rgrover1 343:6675661fa600 6487 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6488 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6489 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6490
rgrover1 343:6675661fa600 6491 /* Bit 18 : Disable interrupt on COMPARE[2] */
rgrover1 343:6675661fa600 6492 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
rgrover1 343:6675661fa600 6493 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
rgrover1 343:6675661fa600 6494 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6495 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6496 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6497
rgrover1 343:6675661fa600 6498 /* Bit 17 : Disable interrupt on COMPARE[1] */
rgrover1 343:6675661fa600 6499 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
rgrover1 343:6675661fa600 6500 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
rgrover1 343:6675661fa600 6501 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6502 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6503 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6504
rgrover1 343:6675661fa600 6505 /* Bit 16 : Disable interrupt on COMPARE[0] */
rgrover1 343:6675661fa600 6506 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
rgrover1 343:6675661fa600 6507 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
rgrover1 343:6675661fa600 6508 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6509 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6510 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6511
rgrover1 343:6675661fa600 6512 /* Register: TIMER_MODE */
rgrover1 343:6675661fa600 6513 /* Description: Timer Mode selection. */
rgrover1 343:6675661fa600 6514
rgrover1 343:6675661fa600 6515 /* Bit 0 : Select Normal or Counter mode. */
rgrover1 343:6675661fa600 6516 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
rgrover1 343:6675661fa600 6517 #define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
rgrover1 343:6675661fa600 6518 #define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */
rgrover1 343:6675661fa600 6519 #define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */
rgrover1 343:6675661fa600 6520
rgrover1 343:6675661fa600 6521 /* Register: TIMER_BITMODE */
rgrover1 343:6675661fa600 6522 /* Description: Sets timer behaviour. */
rgrover1 343:6675661fa600 6523
rgrover1 343:6675661fa600 6524 /* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
rgrover1 343:6675661fa600 6525 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
rgrover1 343:6675661fa600 6526 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
rgrover1 343:6675661fa600 6527 #define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */
rgrover1 343:6675661fa600 6528 #define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */
rgrover1 343:6675661fa600 6529 #define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */
rgrover1 343:6675661fa600 6530 #define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */
rgrover1 343:6675661fa600 6531
rgrover1 343:6675661fa600 6532 /* Register: TIMER_PRESCALER */
rgrover1 343:6675661fa600 6533 /* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
rgrover1 343:6675661fa600 6534
rgrover1 343:6675661fa600 6535 /* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
rgrover1 343:6675661fa600 6536 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
rgrover1 343:6675661fa600 6537 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
rgrover1 343:6675661fa600 6538
rgrover1 343:6675661fa600 6539 /* Register: TIMER_POWER */
rgrover1 343:6675661fa600 6540 /* Description: Peripheral power control. */
rgrover1 343:6675661fa600 6541
rgrover1 343:6675661fa600 6542 /* Bit 0 : Peripheral power control. */
rgrover1 343:6675661fa600 6543 #define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
rgrover1 343:6675661fa600 6544 #define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
rgrover1 343:6675661fa600 6545 #define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
rgrover1 343:6675661fa600 6546 #define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
rgrover1 343:6675661fa600 6547
rgrover1 343:6675661fa600 6548
rgrover1 343:6675661fa600 6549 /* Peripheral: TWI */
rgrover1 343:6675661fa600 6550 /* Description: Two-wire interface master 0. */
rgrover1 343:6675661fa600 6551
rgrover1 343:6675661fa600 6552 /* Register: TWI_SHORTS */
rgrover1 343:6675661fa600 6553 /* Description: Shortcuts for TWI. */
rgrover1 343:6675661fa600 6554
rgrover1 343:6675661fa600 6555 /* Bit 1 : Shortcut between BB event and the STOP task. */
rgrover1 343:6675661fa600 6556 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
rgrover1 343:6675661fa600 6557 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
rgrover1 343:6675661fa600 6558 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 6559 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 6560
rgrover1 343:6675661fa600 6561 /* Bit 0 : Shortcut between BB event and the SUSPEND task. */
rgrover1 343:6675661fa600 6562 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
rgrover1 343:6675661fa600 6563 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
rgrover1 343:6675661fa600 6564 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 6565 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 6566
rgrover1 343:6675661fa600 6567 /* Register: TWI_INTENSET */
rgrover1 343:6675661fa600 6568 /* Description: Interrupt enable set register. */
rgrover1 343:6675661fa600 6569
rgrover1 343:6675661fa600 6570 /* Bit 18 : Enable interrupt on SUSPENDED event. */
rgrover1 343:6675661fa600 6571 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
rgrover1 343:6675661fa600 6572 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
rgrover1 343:6675661fa600 6573 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6574 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6575 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6576
rgrover1 343:6675661fa600 6577 /* Bit 14 : Enable interrupt on BB event. */
rgrover1 343:6675661fa600 6578 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
rgrover1 343:6675661fa600 6579 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
rgrover1 343:6675661fa600 6580 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6581 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6582 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6583
rgrover1 343:6675661fa600 6584 /* Bit 9 : Enable interrupt on ERROR event. */
rgrover1 343:6675661fa600 6585 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
rgrover1 343:6675661fa600 6586 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
rgrover1 343:6675661fa600 6587 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6588 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6589 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6590
rgrover1 343:6675661fa600 6591 /* Bit 7 : Enable interrupt on TXDSENT event. */
rgrover1 343:6675661fa600 6592 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
rgrover1 343:6675661fa600 6593 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
rgrover1 343:6675661fa600 6594 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6595 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6596 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6597
rgrover1 343:6675661fa600 6598 /* Bit 2 : Enable interrupt on READY event. */
rgrover1 343:6675661fa600 6599 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
rgrover1 343:6675661fa600 6600 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
rgrover1 343:6675661fa600 6601 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6602 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6603 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6604
rgrover1 343:6675661fa600 6605 /* Bit 1 : Enable interrupt on STOPPED event. */
rgrover1 343:6675661fa600 6606 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
rgrover1 343:6675661fa600 6607 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
rgrover1 343:6675661fa600 6608 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6609 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6610 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6611
rgrover1 343:6675661fa600 6612 /* Register: TWI_INTENCLR */
rgrover1 343:6675661fa600 6613 /* Description: Interrupt enable clear register. */
rgrover1 343:6675661fa600 6614
rgrover1 343:6675661fa600 6615 /* Bit 18 : Disable interrupt on SUSPENDED event. */
rgrover1 343:6675661fa600 6616 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
rgrover1 343:6675661fa600 6617 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
rgrover1 343:6675661fa600 6618 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6619 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6620 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6621
rgrover1 343:6675661fa600 6622 /* Bit 14 : Disable interrupt on BB event. */
rgrover1 343:6675661fa600 6623 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
rgrover1 343:6675661fa600 6624 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
rgrover1 343:6675661fa600 6625 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6626 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6627 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6628
rgrover1 343:6675661fa600 6629 /* Bit 9 : Disable interrupt on ERROR event. */
rgrover1 343:6675661fa600 6630 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
rgrover1 343:6675661fa600 6631 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
rgrover1 343:6675661fa600 6632 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6633 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6634 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6635
rgrover1 343:6675661fa600 6636 /* Bit 7 : Disable interrupt on TXDSENT event. */
rgrover1 343:6675661fa600 6637 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
rgrover1 343:6675661fa600 6638 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
rgrover1 343:6675661fa600 6639 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6640 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6641 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6642
rgrover1 343:6675661fa600 6643 /* Bit 2 : Disable interrupt on RXDREADY event. */
rgrover1 343:6675661fa600 6644 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
rgrover1 343:6675661fa600 6645 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
rgrover1 343:6675661fa600 6646 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6647 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6648 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6649
rgrover1 343:6675661fa600 6650 /* Bit 1 : Disable interrupt on STOPPED event. */
rgrover1 343:6675661fa600 6651 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
rgrover1 343:6675661fa600 6652 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
rgrover1 343:6675661fa600 6653 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6654 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6655 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6656
rgrover1 343:6675661fa600 6657 /* Register: TWI_ERRORSRC */
rgrover1 343:6675661fa600 6658 /* Description: Two-wire error source. Write error field to 1 to clear error. */
rgrover1 343:6675661fa600 6659
rgrover1 343:6675661fa600 6660 /* Bit 2 : NACK received after sending a data byte. */
rgrover1 343:6675661fa600 6661 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
rgrover1 343:6675661fa600 6662 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
rgrover1 343:6675661fa600 6663 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */
rgrover1 343:6675661fa600 6664 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */
rgrover1 343:6675661fa600 6665 #define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */
rgrover1 343:6675661fa600 6666
rgrover1 343:6675661fa600 6667 /* Bit 1 : NACK received after sending the address. */
rgrover1 343:6675661fa600 6668 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
rgrover1 343:6675661fa600 6669 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
rgrover1 343:6675661fa600 6670 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */
rgrover1 343:6675661fa600 6671 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */
rgrover1 343:6675661fa600 6672 #define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */
rgrover1 343:6675661fa600 6673
rgrover1 343:6675661fa600 6674 /* Register: TWI_ENABLE */
rgrover1 343:6675661fa600 6675 /* Description: Enable two-wire master. */
rgrover1 343:6675661fa600 6676
rgrover1 343:6675661fa600 6677 /* Bits 2..0 : Enable or disable W2M */
rgrover1 343:6675661fa600 6678 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
rgrover1 343:6675661fa600 6679 #define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
rgrover1 343:6675661fa600 6680 #define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */
rgrover1 343:6675661fa600 6681 #define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */
rgrover1 343:6675661fa600 6682
rgrover1 343:6675661fa600 6683 /* Register: TWI_RXD */
rgrover1 343:6675661fa600 6684 /* Description: RX data register. */
rgrover1 343:6675661fa600 6685
rgrover1 343:6675661fa600 6686 /* Bits 7..0 : RX data from last transfer. */
rgrover1 343:6675661fa600 6687 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
rgrover1 343:6675661fa600 6688 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
rgrover1 343:6675661fa600 6689
rgrover1 343:6675661fa600 6690 /* Register: TWI_TXD */
rgrover1 343:6675661fa600 6691 /* Description: TX data register. */
rgrover1 343:6675661fa600 6692
rgrover1 343:6675661fa600 6693 /* Bits 7..0 : TX data for next transfer. */
rgrover1 343:6675661fa600 6694 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
rgrover1 343:6675661fa600 6695 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
rgrover1 343:6675661fa600 6696
rgrover1 343:6675661fa600 6697 /* Register: TWI_FREQUENCY */
rgrover1 343:6675661fa600 6698 /* Description: Two-wire frequency. */
rgrover1 343:6675661fa600 6699
rgrover1 343:6675661fa600 6700 /* Bits 31..0 : Two-wire master clock frequency. */
rgrover1 343:6675661fa600 6701 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
rgrover1 343:6675661fa600 6702 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
rgrover1 343:6675661fa600 6703 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */
rgrover1 343:6675661fa600 6704 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
rgrover1 343:6675661fa600 6705 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */
rgrover1 343:6675661fa600 6706
rgrover1 343:6675661fa600 6707 /* Register: TWI_ADDRESS */
rgrover1 343:6675661fa600 6708 /* Description: Address used in the two-wire transfer. */
rgrover1 343:6675661fa600 6709
rgrover1 343:6675661fa600 6710 /* Bits 6..0 : Two-wire address. */
rgrover1 343:6675661fa600 6711 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
rgrover1 343:6675661fa600 6712 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
rgrover1 343:6675661fa600 6713
rgrover1 343:6675661fa600 6714 /* Register: TWI_POWER */
rgrover1 343:6675661fa600 6715 /* Description: Peripheral power control. */
rgrover1 343:6675661fa600 6716
rgrover1 343:6675661fa600 6717 /* Bit 0 : Peripheral power control. */
rgrover1 343:6675661fa600 6718 #define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
rgrover1 343:6675661fa600 6719 #define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
rgrover1 343:6675661fa600 6720 #define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
rgrover1 343:6675661fa600 6721 #define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
rgrover1 343:6675661fa600 6722
rgrover1 343:6675661fa600 6723
rgrover1 343:6675661fa600 6724 /* Peripheral: UART */
rgrover1 343:6675661fa600 6725 /* Description: Universal Asynchronous Receiver/Transmitter. */
rgrover1 343:6675661fa600 6726
rgrover1 343:6675661fa600 6727 /* Register: UART_SHORTS */
rgrover1 343:6675661fa600 6728 /* Description: Shortcuts for UART. */
rgrover1 343:6675661fa600 6729
rgrover1 343:6675661fa600 6730 /* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
rgrover1 343:6675661fa600 6731 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
rgrover1 343:6675661fa600 6732 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
rgrover1 343:6675661fa600 6733 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 6734 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 6735
rgrover1 343:6675661fa600 6736 /* Bit 3 : Shortcut between CTS event and the STARTRX task. */
rgrover1 343:6675661fa600 6737 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
rgrover1 343:6675661fa600 6738 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
rgrover1 343:6675661fa600 6739 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */
rgrover1 343:6675661fa600 6740 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */
rgrover1 343:6675661fa600 6741
rgrover1 343:6675661fa600 6742 /* Register: UART_INTENSET */
rgrover1 343:6675661fa600 6743 /* Description: Interrupt enable set register. */
rgrover1 343:6675661fa600 6744
rgrover1 343:6675661fa600 6745 /* Bit 17 : Enable interrupt on RXTO event. */
rgrover1 343:6675661fa600 6746 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
rgrover1 343:6675661fa600 6747 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
rgrover1 343:6675661fa600 6748 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6749 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6750 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6751
rgrover1 343:6675661fa600 6752 /* Bit 9 : Enable interrupt on ERROR event. */
rgrover1 343:6675661fa600 6753 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
rgrover1 343:6675661fa600 6754 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
rgrover1 343:6675661fa600 6755 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6756 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6757 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6758
rgrover1 343:6675661fa600 6759 /* Bit 7 : Enable interrupt on TXRDY event. */
rgrover1 343:6675661fa600 6760 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
rgrover1 343:6675661fa600 6761 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
rgrover1 343:6675661fa600 6762 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6763 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6764 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6765
rgrover1 343:6675661fa600 6766 /* Bit 2 : Enable interrupt on RXRDY event. */
rgrover1 343:6675661fa600 6767 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
rgrover1 343:6675661fa600 6768 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
rgrover1 343:6675661fa600 6769 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6770 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6771 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6772
rgrover1 343:6675661fa600 6773 /* Bit 1 : Enable interrupt on NCTS event. */
rgrover1 343:6675661fa600 6774 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
rgrover1 343:6675661fa600 6775 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
rgrover1 343:6675661fa600 6776 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6777 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6778 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6779
rgrover1 343:6675661fa600 6780 /* Bit 0 : Enable interrupt on CTS event. */
rgrover1 343:6675661fa600 6781 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
rgrover1 343:6675661fa600 6782 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
rgrover1 343:6675661fa600 6783 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6784 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6785 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6786
rgrover1 343:6675661fa600 6787 /* Register: UART_INTENCLR */
rgrover1 343:6675661fa600 6788 /* Description: Interrupt enable clear register. */
rgrover1 343:6675661fa600 6789
rgrover1 343:6675661fa600 6790 /* Bit 17 : Disable interrupt on RXTO event. */
rgrover1 343:6675661fa600 6791 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
rgrover1 343:6675661fa600 6792 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
rgrover1 343:6675661fa600 6793 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6794 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6795 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6796
rgrover1 343:6675661fa600 6797 /* Bit 9 : Disable interrupt on ERROR event. */
rgrover1 343:6675661fa600 6798 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
rgrover1 343:6675661fa600 6799 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
rgrover1 343:6675661fa600 6800 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6801 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6802 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6803
rgrover1 343:6675661fa600 6804 /* Bit 7 : Disable interrupt on TXRDY event. */
rgrover1 343:6675661fa600 6805 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
rgrover1 343:6675661fa600 6806 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
rgrover1 343:6675661fa600 6807 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6808 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6809 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6810
rgrover1 343:6675661fa600 6811 /* Bit 2 : Disable interrupt on RXRDY event. */
rgrover1 343:6675661fa600 6812 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
rgrover1 343:6675661fa600 6813 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
rgrover1 343:6675661fa600 6814 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6815 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6816 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6817
rgrover1 343:6675661fa600 6818 /* Bit 1 : Disable interrupt on NCTS event. */
rgrover1 343:6675661fa600 6819 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
rgrover1 343:6675661fa600 6820 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
rgrover1 343:6675661fa600 6821 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6822 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6823 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6824
rgrover1 343:6675661fa600 6825 /* Bit 0 : Disable interrupt on CTS event. */
rgrover1 343:6675661fa600 6826 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
rgrover1 343:6675661fa600 6827 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
rgrover1 343:6675661fa600 6828 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6829 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6830 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6831
rgrover1 343:6675661fa600 6832 /* Register: UART_ERRORSRC */
rgrover1 343:6675661fa600 6833 /* Description: Error source. Write error field to 1 to clear error. */
rgrover1 343:6675661fa600 6834
rgrover1 343:6675661fa600 6835 /* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
rgrover1 343:6675661fa600 6836 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
rgrover1 343:6675661fa600 6837 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
rgrover1 343:6675661fa600 6838 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */
rgrover1 343:6675661fa600 6839 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */
rgrover1 343:6675661fa600 6840 #define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */
rgrover1 343:6675661fa600 6841
rgrover1 343:6675661fa600 6842 /* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
rgrover1 343:6675661fa600 6843 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
rgrover1 343:6675661fa600 6844 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
rgrover1 343:6675661fa600 6845 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */
rgrover1 343:6675661fa600 6846 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */
rgrover1 343:6675661fa600 6847 #define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */
rgrover1 343:6675661fa600 6848
rgrover1 343:6675661fa600 6849 /* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
rgrover1 343:6675661fa600 6850 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
rgrover1 343:6675661fa600 6851 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
rgrover1 343:6675661fa600 6852 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */
rgrover1 343:6675661fa600 6853 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */
rgrover1 343:6675661fa600 6854 #define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */
rgrover1 343:6675661fa600 6855
rgrover1 343:6675661fa600 6856 /* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
rgrover1 343:6675661fa600 6857 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
rgrover1 343:6675661fa600 6858 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
rgrover1 343:6675661fa600 6859 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
rgrover1 343:6675661fa600 6860 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
rgrover1 343:6675661fa600 6861 #define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
rgrover1 343:6675661fa600 6862
rgrover1 343:6675661fa600 6863 /* Register: UART_ENABLE */
rgrover1 343:6675661fa600 6864 /* Description: Enable UART and acquire IOs. */
rgrover1 343:6675661fa600 6865
rgrover1 343:6675661fa600 6866 /* Bits 2..0 : Enable or disable UART and acquire IOs. */
rgrover1 343:6675661fa600 6867 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
rgrover1 343:6675661fa600 6868 #define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
rgrover1 343:6675661fa600 6869 #define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */
rgrover1 343:6675661fa600 6870 #define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */
rgrover1 343:6675661fa600 6871
rgrover1 343:6675661fa600 6872 /* Register: UART_RXD */
rgrover1 343:6675661fa600 6873 /* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
rgrover1 343:6675661fa600 6874
rgrover1 343:6675661fa600 6875 /* Bits 7..0 : RX data from previous transfer. Double buffered. */
rgrover1 343:6675661fa600 6876 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
rgrover1 343:6675661fa600 6877 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
rgrover1 343:6675661fa600 6878
rgrover1 343:6675661fa600 6879 /* Register: UART_TXD */
rgrover1 343:6675661fa600 6880 /* Description: TXD register. */
rgrover1 343:6675661fa600 6881
rgrover1 343:6675661fa600 6882 /* Bits 7..0 : TX data for transfer. */
rgrover1 343:6675661fa600 6883 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
rgrover1 343:6675661fa600 6884 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
rgrover1 343:6675661fa600 6885
rgrover1 343:6675661fa600 6886 /* Register: UART_BAUDRATE */
rgrover1 343:6675661fa600 6887 /* Description: UART Baudrate. */
rgrover1 343:6675661fa600 6888
rgrover1 343:6675661fa600 6889 /* Bits 31..0 : UART baudrate. */
rgrover1 343:6675661fa600 6890 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
rgrover1 343:6675661fa600 6891 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
rgrover1 343:6675661fa600 6892 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */
rgrover1 343:6675661fa600 6893 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */
rgrover1 343:6675661fa600 6894 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */
rgrover1 343:6675661fa600 6895 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */
rgrover1 343:6675661fa600 6896 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */
rgrover1 343:6675661fa600 6897 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */
rgrover1 343:6675661fa600 6898 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */
rgrover1 343:6675661fa600 6899 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */
rgrover1 343:6675661fa600 6900 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */
rgrover1 343:6675661fa600 6901 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */
rgrover1 343:6675661fa600 6902 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */
rgrover1 343:6675661fa600 6903 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */
rgrover1 343:6675661fa600 6904 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */
rgrover1 343:6675661fa600 6905 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */
rgrover1 343:6675661fa600 6906 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /*!< 921600 baud. */
rgrover1 343:6675661fa600 6907 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */
rgrover1 343:6675661fa600 6908
rgrover1 343:6675661fa600 6909 /* Register: UART_CONFIG */
rgrover1 343:6675661fa600 6910 /* Description: Configuration of parity and hardware flow control register. */
rgrover1 343:6675661fa600 6911
rgrover1 343:6675661fa600 6912 /* Bits 3..1 : Include parity bit. */
rgrover1 343:6675661fa600 6913 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
rgrover1 343:6675661fa600 6914 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
rgrover1 343:6675661fa600 6915 #define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */
rgrover1 343:6675661fa600 6916 #define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */
rgrover1 343:6675661fa600 6917
rgrover1 343:6675661fa600 6918 /* Bit 0 : Hardware flow control. */
rgrover1 343:6675661fa600 6919 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
rgrover1 343:6675661fa600 6920 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
rgrover1 343:6675661fa600 6921 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */
rgrover1 343:6675661fa600 6922 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */
rgrover1 343:6675661fa600 6923
rgrover1 343:6675661fa600 6924 /* Register: UART_POWER */
rgrover1 343:6675661fa600 6925 /* Description: Peripheral power control. */
rgrover1 343:6675661fa600 6926
rgrover1 343:6675661fa600 6927 /* Bit 0 : Peripheral power control. */
rgrover1 343:6675661fa600 6928 #define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
rgrover1 343:6675661fa600 6929 #define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
rgrover1 343:6675661fa600 6930 #define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
rgrover1 343:6675661fa600 6931 #define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
rgrover1 343:6675661fa600 6932
rgrover1 343:6675661fa600 6933
rgrover1 343:6675661fa600 6934 /* Peripheral: UICR */
rgrover1 343:6675661fa600 6935 /* Description: User Information Configuration. */
rgrover1 343:6675661fa600 6936
rgrover1 343:6675661fa600 6937 /* Register: UICR_RBPCONF */
rgrover1 343:6675661fa600 6938 /* Description: Readback protection configuration. */
rgrover1 343:6675661fa600 6939
rgrover1 343:6675661fa600 6940 /* Bits 15..8 : Readback protect all code in the device. */
rgrover1 343:6675661fa600 6941 #define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */
rgrover1 343:6675661fa600 6942 #define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */
rgrover1 343:6675661fa600 6943 #define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */
rgrover1 343:6675661fa600 6944 #define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */
rgrover1 343:6675661fa600 6945
rgrover1 343:6675661fa600 6946 /* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
rgrover1 343:6675661fa600 6947 #define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */
rgrover1 343:6675661fa600 6948 #define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */
rgrover1 343:6675661fa600 6949 #define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */
rgrover1 343:6675661fa600 6950 #define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */
rgrover1 343:6675661fa600 6951
rgrover1 343:6675661fa600 6952 /* Register: UICR_XTALFREQ */
rgrover1 343:6675661fa600 6953 /* Description: Reset value for CLOCK XTALFREQ register. */
rgrover1 343:6675661fa600 6954
rgrover1 343:6675661fa600 6955 /* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
rgrover1 343:6675661fa600 6956 #define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
rgrover1 343:6675661fa600 6957 #define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
rgrover1 343:6675661fa600 6958 #define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */
rgrover1 343:6675661fa600 6959 #define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */
rgrover1 343:6675661fa600 6960
rgrover1 343:6675661fa600 6961 /* Register: UICR_FWID */
rgrover1 343:6675661fa600 6962 /* Description: Firmware ID. */
rgrover1 343:6675661fa600 6963
rgrover1 343:6675661fa600 6964 /* Bits 15..0 : Identification number for the firmware loaded into the chip. */
rgrover1 343:6675661fa600 6965 #define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */
rgrover1 343:6675661fa600 6966 #define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */
rgrover1 343:6675661fa600 6967
rgrover1 343:6675661fa600 6968
rgrover1 343:6675661fa600 6969 /* Peripheral: WDT */
rgrover1 343:6675661fa600 6970 /* Description: Watchdog Timer. */
rgrover1 343:6675661fa600 6971
rgrover1 343:6675661fa600 6972 /* Register: WDT_INTENSET */
rgrover1 343:6675661fa600 6973 /* Description: Interrupt enable set register. */
rgrover1 343:6675661fa600 6974
rgrover1 343:6675661fa600 6975 /* Bit 0 : Enable interrupt on TIMEOUT event. */
rgrover1 343:6675661fa600 6976 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
rgrover1 343:6675661fa600 6977 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
rgrover1 343:6675661fa600 6978 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6979 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6980 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */
rgrover1 343:6675661fa600 6981
rgrover1 343:6675661fa600 6982 /* Register: WDT_INTENCLR */
rgrover1 343:6675661fa600 6983 /* Description: Interrupt enable clear register. */
rgrover1 343:6675661fa600 6984
rgrover1 343:6675661fa600 6985 /* Bit 0 : Disable interrupt on TIMEOUT event. */
rgrover1 343:6675661fa600 6986 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
rgrover1 343:6675661fa600 6987 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
rgrover1 343:6675661fa600 6988 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
rgrover1 343:6675661fa600 6989 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
rgrover1 343:6675661fa600 6990 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */
rgrover1 343:6675661fa600 6991
rgrover1 343:6675661fa600 6992 /* Register: WDT_RUNSTATUS */
rgrover1 343:6675661fa600 6993 /* Description: Watchdog running status. */
rgrover1 343:6675661fa600 6994
rgrover1 343:6675661fa600 6995 /* Bit 0 : Watchdog running status. */
rgrover1 343:6675661fa600 6996 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
rgrover1 343:6675661fa600 6997 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
rgrover1 343:6675661fa600 6998 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */
rgrover1 343:6675661fa600 6999 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */
rgrover1 343:6675661fa600 7000
rgrover1 343:6675661fa600 7001 /* Register: WDT_REQSTATUS */
rgrover1 343:6675661fa600 7002 /* Description: Request status. */
rgrover1 343:6675661fa600 7003
rgrover1 343:6675661fa600 7004 /* Bit 7 : Request status for RR[7]. */
rgrover1 343:6675661fa600 7005 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
rgrover1 343:6675661fa600 7006 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
rgrover1 343:6675661fa600 7007 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */
rgrover1 343:6675661fa600 7008 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */
rgrover1 343:6675661fa600 7009
rgrover1 343:6675661fa600 7010 /* Bit 6 : Request status for RR[6]. */
rgrover1 343:6675661fa600 7011 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
rgrover1 343:6675661fa600 7012 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
rgrover1 343:6675661fa600 7013 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */
rgrover1 343:6675661fa600 7014 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */
rgrover1 343:6675661fa600 7015
rgrover1 343:6675661fa600 7016 /* Bit 5 : Request status for RR[5]. */
rgrover1 343:6675661fa600 7017 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
rgrover1 343:6675661fa600 7018 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
rgrover1 343:6675661fa600 7019 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */
rgrover1 343:6675661fa600 7020 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */
rgrover1 343:6675661fa600 7021
rgrover1 343:6675661fa600 7022 /* Bit 4 : Request status for RR[4]. */
rgrover1 343:6675661fa600 7023 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
rgrover1 343:6675661fa600 7024 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
rgrover1 343:6675661fa600 7025 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */
rgrover1 343:6675661fa600 7026 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */
rgrover1 343:6675661fa600 7027
rgrover1 343:6675661fa600 7028 /* Bit 3 : Request status for RR[3]. */
rgrover1 343:6675661fa600 7029 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
rgrover1 343:6675661fa600 7030 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
rgrover1 343:6675661fa600 7031 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */
rgrover1 343:6675661fa600 7032 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */
rgrover1 343:6675661fa600 7033
rgrover1 343:6675661fa600 7034 /* Bit 2 : Request status for RR[2]. */
rgrover1 343:6675661fa600 7035 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
rgrover1 343:6675661fa600 7036 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
rgrover1 343:6675661fa600 7037 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */
rgrover1 343:6675661fa600 7038 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */
rgrover1 343:6675661fa600 7039
rgrover1 343:6675661fa600 7040 /* Bit 1 : Request status for RR[1]. */
rgrover1 343:6675661fa600 7041 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
rgrover1 343:6675661fa600 7042 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
rgrover1 343:6675661fa600 7043 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */
rgrover1 343:6675661fa600 7044 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */
rgrover1 343:6675661fa600 7045
rgrover1 343:6675661fa600 7046 /* Bit 0 : Request status for RR[0]. */
rgrover1 343:6675661fa600 7047 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
rgrover1 343:6675661fa600 7048 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
rgrover1 343:6675661fa600 7049 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */
rgrover1 343:6675661fa600 7050 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */
rgrover1 343:6675661fa600 7051
rgrover1 343:6675661fa600 7052 /* Register: WDT_RREN */
rgrover1 343:6675661fa600 7053 /* Description: Reload request enable. */
rgrover1 343:6675661fa600 7054
rgrover1 343:6675661fa600 7055 /* Bit 7 : Enable or disable RR[7] register. */
rgrover1 343:6675661fa600 7056 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
rgrover1 343:6675661fa600 7057 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
rgrover1 343:6675661fa600 7058 #define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */
rgrover1 343:6675661fa600 7059 #define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */
rgrover1 343:6675661fa600 7060
rgrover1 343:6675661fa600 7061 /* Bit 6 : Enable or disable RR[6] register. */
rgrover1 343:6675661fa600 7062 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
rgrover1 343:6675661fa600 7063 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
rgrover1 343:6675661fa600 7064 #define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */
rgrover1 343:6675661fa600 7065 #define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */
rgrover1 343:6675661fa600 7066
rgrover1 343:6675661fa600 7067 /* Bit 5 : Enable or disable RR[5] register. */
rgrover1 343:6675661fa600 7068 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
rgrover1 343:6675661fa600 7069 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
rgrover1 343:6675661fa600 7070 #define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */
rgrover1 343:6675661fa600 7071 #define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */
rgrover1 343:6675661fa600 7072
rgrover1 343:6675661fa600 7073 /* Bit 4 : Enable or disable RR[4] register. */
rgrover1 343:6675661fa600 7074 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
rgrover1 343:6675661fa600 7075 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
rgrover1 343:6675661fa600 7076 #define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */
rgrover1 343:6675661fa600 7077 #define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */
rgrover1 343:6675661fa600 7078
rgrover1 343:6675661fa600 7079 /* Bit 3 : Enable or disable RR[3] register. */
rgrover1 343:6675661fa600 7080 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
rgrover1 343:6675661fa600 7081 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
rgrover1 343:6675661fa600 7082 #define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */
rgrover1 343:6675661fa600 7083 #define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */
rgrover1 343:6675661fa600 7084
rgrover1 343:6675661fa600 7085 /* Bit 2 : Enable or disable RR[2] register. */
rgrover1 343:6675661fa600 7086 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
rgrover1 343:6675661fa600 7087 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
rgrover1 343:6675661fa600 7088 #define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */
rgrover1 343:6675661fa600 7089 #define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */
rgrover1 343:6675661fa600 7090
rgrover1 343:6675661fa600 7091 /* Bit 1 : Enable or disable RR[1] register. */
rgrover1 343:6675661fa600 7092 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
rgrover1 343:6675661fa600 7093 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
rgrover1 343:6675661fa600 7094 #define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */
rgrover1 343:6675661fa600 7095 #define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */
rgrover1 343:6675661fa600 7096
rgrover1 343:6675661fa600 7097 /* Bit 0 : Enable or disable RR[0] register. */
rgrover1 343:6675661fa600 7098 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
rgrover1 343:6675661fa600 7099 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
rgrover1 343:6675661fa600 7100 #define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */
rgrover1 343:6675661fa600 7101 #define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */
rgrover1 343:6675661fa600 7102
rgrover1 343:6675661fa600 7103 /* Register: WDT_CONFIG */
rgrover1 343:6675661fa600 7104 /* Description: Configuration register. */
rgrover1 343:6675661fa600 7105
rgrover1 343:6675661fa600 7106 /* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
rgrover1 343:6675661fa600 7107 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
rgrover1 343:6675661fa600 7108 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
rgrover1 343:6675661fa600 7109 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */
rgrover1 343:6675661fa600 7110 #define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */
rgrover1 343:6675661fa600 7111
rgrover1 343:6675661fa600 7112 /* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
rgrover1 343:6675661fa600 7113 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
rgrover1 343:6675661fa600 7114 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
rgrover1 343:6675661fa600 7115 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */
rgrover1 343:6675661fa600 7116 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */
rgrover1 343:6675661fa600 7117
rgrover1 343:6675661fa600 7118 /* Register: WDT_RR */
rgrover1 343:6675661fa600 7119 /* Description: Reload requests registers. */
rgrover1 343:6675661fa600 7120
rgrover1 343:6675661fa600 7121 /* Bits 31..0 : Reload register. */
rgrover1 343:6675661fa600 7122 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
rgrover1 343:6675661fa600 7123 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
rgrover1 343:6675661fa600 7124 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */
rgrover1 343:6675661fa600 7125
rgrover1 343:6675661fa600 7126 /* Register: WDT_POWER */
rgrover1 343:6675661fa600 7127 /* Description: Peripheral power control. */
rgrover1 343:6675661fa600 7128
rgrover1 343:6675661fa600 7129 /* Bit 0 : Peripheral power control. */
rgrover1 343:6675661fa600 7130 #define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
rgrover1 343:6675661fa600 7131 #define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
rgrover1 343:6675661fa600 7132 #define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
rgrover1 343:6675661fa600 7133 #define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
rgrover1 343:6675661fa600 7134
rgrover1 343:6675661fa600 7135
rgrover1 343:6675661fa600 7136 /*lint --flb "Leave library region" */
rgrover1 343:6675661fa600 7137 #endif