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Dependencies:   mbed

EncoderCounter.cpp@2:f381fc3a8eaf, 2020-02-26 (annotated)

Committer:
wengefa1
Date:
Wed Feb 26 14:20:16 2020 +0000
Revision:
2:f381fc3a8eaf
Motor Controller added

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wengefa1 2:f381fc3a8eaf 1 /*
wengefa1 2:f381fc3a8eaf 2 * EncoderCounter.cpp
wengefa1 2:f381fc3a8eaf 3 * Copyright (c) 2020, ZHAW
wengefa1 2:f381fc3a8eaf 4 * All rights reserved.
wengefa1 2:f381fc3a8eaf 5 */
wengefa1 2:f381fc3a8eaf 6
wengefa1 2:f381fc3a8eaf 7 #include "EncoderCounter.h"
wengefa1 2:f381fc3a8eaf 8
wengefa1 2:f381fc3a8eaf 9 using namespace std;
wengefa1 2:f381fc3a8eaf 10
wengefa1 2:f381fc3a8eaf 11 /**
wengefa1 2:f381fc3a8eaf 12 * Creates and initialises the driver to read the quadrature
wengefa1 2:f381fc3a8eaf 13 * encoder counter of the STM32 microcontroller.
wengefa1 2:f381fc3a8eaf 14 * @param a the input pin for the channel A.
wengefa1 2:f381fc3a8eaf 15 * @param b the input pin for the channel B.
wengefa1 2:f381fc3a8eaf 16 */
wengefa1 2:f381fc3a8eaf 17 EncoderCounter::EncoderCounter(PinName a, PinName b) {
wengefa1 2:f381fc3a8eaf 18
wengefa1 2:f381fc3a8eaf 19 // check pins
wengefa1 2:f381fc3a8eaf 20
wengefa1 2:f381fc3a8eaf 21 if ((a == PA_15) && (b == PB_3)) {
wengefa1 2:f381fc3a8eaf 22
wengefa1 2:f381fc3a8eaf 23 // pinmap OK for TIM2 CH1 and CH2
wengefa1 2:f381fc3a8eaf 24
wengefa1 2:f381fc3a8eaf 25 TIM = TIM2;
wengefa1 2:f381fc3a8eaf 26
wengefa1 2:f381fc3a8eaf 27 // configure reset and clock control registers
wengefa1 2:f381fc3a8eaf 28
wengefa1 2:f381fc3a8eaf 29 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; // manually enable port B (port A enabled by mbed library)
wengefa1 2:f381fc3a8eaf 30
wengefa1 2:f381fc3a8eaf 31 // configure general purpose I/O registers
wengefa1 2:f381fc3a8eaf 32
wengefa1 2:f381fc3a8eaf 33 GPIOA->MODER &= ~GPIO_MODER_MODER15; // reset port A15
wengefa1 2:f381fc3a8eaf 34 GPIOA->MODER |= GPIO_MODER_MODER15_1; // set alternate mode of port A15
wengefa1 2:f381fc3a8eaf 35 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR15; // reset pull-up/pull-down on port A15
wengefa1 2:f381fc3a8eaf 36 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR15_1; // set input as pull-down
wengefa1 2:f381fc3a8eaf 37 GPIOA->AFR[1] &= ~0xF0000000; // reset alternate function of port A15
wengefa1 2:f381fc3a8eaf 38 GPIOA->AFR[1] |= 1 << 4*7; // set alternate funtion 1 of port A15
wengefa1 2:f381fc3a8eaf 39
wengefa1 2:f381fc3a8eaf 40 GPIOB->MODER &= ~GPIO_MODER_MODER3; // reset port B3
wengefa1 2:f381fc3a8eaf 41 GPIOB->MODER |= GPIO_MODER_MODER3_1; // set alternate mode of port B3
wengefa1 2:f381fc3a8eaf 42 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR3; // reset pull-up/pull-down on port B3
wengefa1 2:f381fc3a8eaf 43 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR3_1; // set input as pull-down
wengefa1 2:f381fc3a8eaf 44 GPIOB->AFR[0] &= ~(0xF << 4*3); // reset alternate function of port B3
wengefa1 2:f381fc3a8eaf 45 GPIOB->AFR[0] |= 1 << 4*3; // set alternate funtion 1 of port B3
wengefa1 2:f381fc3a8eaf 46
wengefa1 2:f381fc3a8eaf 47 // configure reset and clock control registers
wengefa1 2:f381fc3a8eaf 48
wengefa1 2:f381fc3a8eaf 49 RCC->APB1RSTR |= RCC_APB1RSTR_TIM2RST; //reset TIM2 controller
wengefa1 2:f381fc3a8eaf 50 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM2RST;
wengefa1 2:f381fc3a8eaf 51
wengefa1 2:f381fc3a8eaf 52 RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // TIM2 clock enable
wengefa1 2:f381fc3a8eaf 53
wengefa1 2:f381fc3a8eaf 54 } else if ((a == PB_4) && (b == PC_7)) {
wengefa1 2:f381fc3a8eaf 55
wengefa1 2:f381fc3a8eaf 56 // pinmap OK for TIM3 CH1 and CH2
wengefa1 2:f381fc3a8eaf 57
wengefa1 2:f381fc3a8eaf 58 TIM = TIM3;
wengefa1 2:f381fc3a8eaf 59
wengefa1 2:f381fc3a8eaf 60 // configure reset and clock control registers
wengefa1 2:f381fc3a8eaf 61
wengefa1 2:f381fc3a8eaf 62 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; // manually enable port B
wengefa1 2:f381fc3a8eaf 63 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; // manually enable port C
wengefa1 2:f381fc3a8eaf 64
wengefa1 2:f381fc3a8eaf 65 // configure general purpose I/O registers
wengefa1 2:f381fc3a8eaf 66
wengefa1 2:f381fc3a8eaf 67 GPIOB->MODER &= ~GPIO_MODER_MODER4; // reset port B4
wengefa1 2:f381fc3a8eaf 68 GPIOB->MODER |= GPIO_MODER_MODER4_1; // set alternate mode of port B4
wengefa1 2:f381fc3a8eaf 69 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR4; // reset pull-up/pull-down on port B4
wengefa1 2:f381fc3a8eaf 70 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR4_1; // set input as pull-down
wengefa1 2:f381fc3a8eaf 71 GPIOB->AFR[0] &= ~(0xF << 4*4); // reset alternate function of port B4
wengefa1 2:f381fc3a8eaf 72 GPIOB->AFR[0] |= 2 << 4*4; // set alternate funtion 2 of port B4
wengefa1 2:f381fc3a8eaf 73
wengefa1 2:f381fc3a8eaf 74 GPIOC->MODER &= ~GPIO_MODER_MODER7; // reset port C7
wengefa1 2:f381fc3a8eaf 75 GPIOC->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port C7
wengefa1 2:f381fc3a8eaf 76 GPIOC->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port C7
wengefa1 2:f381fc3a8eaf 77 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
wengefa1 2:f381fc3a8eaf 78 GPIOC->AFR[0] &= ~0xF0000000; // reset alternate function of port C7
wengefa1 2:f381fc3a8eaf 79 GPIOC->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port C7
wengefa1 2:f381fc3a8eaf 80
wengefa1 2:f381fc3a8eaf 81 // configure reset and clock control registers
wengefa1 2:f381fc3a8eaf 82
wengefa1 2:f381fc3a8eaf 83 RCC->APB1RSTR |= RCC_APB1RSTR_TIM3RST; //reset TIM3 controller
wengefa1 2:f381fc3a8eaf 84 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM3RST;
wengefa1 2:f381fc3a8eaf 85
wengefa1 2:f381fc3a8eaf 86 RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; // TIM3 clock enable
wengefa1 2:f381fc3a8eaf 87
wengefa1 2:f381fc3a8eaf 88 } else if ((a == PD_12) && (b == PD_13)) {
wengefa1 2:f381fc3a8eaf 89
wengefa1 2:f381fc3a8eaf 90 // pinmap OK for TIM4 CH1 and CH2
wengefa1 2:f381fc3a8eaf 91
wengefa1 2:f381fc3a8eaf 92 TIM = TIM4;
wengefa1 2:f381fc3a8eaf 93
wengefa1 2:f381fc3a8eaf 94 // configure reset and clock control registers
wengefa1 2:f381fc3a8eaf 95
wengefa1 2:f381fc3a8eaf 96 RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN; // manually enable port D
wengefa1 2:f381fc3a8eaf 97
wengefa1 2:f381fc3a8eaf 98 // configure general purpose I/O registers
wengefa1 2:f381fc3a8eaf 99
wengefa1 2:f381fc3a8eaf 100 GPIOD->MODER &= ~GPIO_MODER_MODER12; // reset port D12
wengefa1 2:f381fc3a8eaf 101 GPIOD->MODER |= GPIO_MODER_MODER12_1; // set alternate mode of port D12
wengefa1 2:f381fc3a8eaf 102 GPIOD->PUPDR &= ~GPIO_PUPDR_PUPDR12; // reset pull-up/pull-down on port D12
wengefa1 2:f381fc3a8eaf 103 GPIOD->PUPDR |= GPIO_PUPDR_PUPDR12_1; // set input as pull-down
wengefa1 2:f381fc3a8eaf 104 GPIOD->AFR[1] &= ~(0xF << 4*4); // reset alternate function of port D12
wengefa1 2:f381fc3a8eaf 105 GPIOD->AFR[1] |= 2 << 4*4; // set alternate funtion 2 of port D12
wengefa1 2:f381fc3a8eaf 106
wengefa1 2:f381fc3a8eaf 107 GPIOD->MODER &= ~GPIO_MODER_MODER13; // reset port D13
wengefa1 2:f381fc3a8eaf 108 GPIOD->MODER |= GPIO_MODER_MODER13_1; // set alternate mode of port D13
wengefa1 2:f381fc3a8eaf 109 GPIOD->PUPDR &= ~GPIO_PUPDR_PUPDR13; // reset pull-up/pull-down on port D13
wengefa1 2:f381fc3a8eaf 110 GPIOD->PUPDR |= GPIO_PUPDR_PUPDR13_1; // set input as pull-down
wengefa1 2:f381fc3a8eaf 111 GPIOD->AFR[1] &= ~(0xF << 4*5); // reset alternate function of port D13
wengefa1 2:f381fc3a8eaf 112 GPIOD->AFR[1] |= 2 << 4*5; // set alternate funtion 2 of port D13
wengefa1 2:f381fc3a8eaf 113
wengefa1 2:f381fc3a8eaf 114 // configure reset and clock control registers
wengefa1 2:f381fc3a8eaf 115
wengefa1 2:f381fc3a8eaf 116 RCC->APB1RSTR |= RCC_APB1RSTR_TIM4RST; //reset TIM4 controller
wengefa1 2:f381fc3a8eaf 117 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM4RST;
wengefa1 2:f381fc3a8eaf 118
wengefa1 2:f381fc3a8eaf 119 RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; // TIM4 clock enable
wengefa1 2:f381fc3a8eaf 120
wengefa1 2:f381fc3a8eaf 121 } else {
wengefa1 2:f381fc3a8eaf 122
wengefa1 2:f381fc3a8eaf 123 printf("pinmap not found for peripheral\n");
wengefa1 2:f381fc3a8eaf 124
wengefa1 2:f381fc3a8eaf 125 TIM = NULL;
wengefa1 2:f381fc3a8eaf 126 }
wengefa1 2:f381fc3a8eaf 127
wengefa1 2:f381fc3a8eaf 128 // configure general purpose timer 2, 3 or 4
wengefa1 2:f381fc3a8eaf 129
wengefa1 2:f381fc3a8eaf 130 if (TIM != NULL) {
wengefa1 2:f381fc3a8eaf 131
wengefa1 2:f381fc3a8eaf 132 TIM->CR1 = 0x0000; // counter disable
wengefa1 2:f381fc3a8eaf 133 TIM->CR2 = 0x0000; // reset master mode selection
wengefa1 2:f381fc3a8eaf 134 TIM->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; // counting on both TI1 & TI2 edges
wengefa1 2:f381fc3a8eaf 135 TIM->CCMR1 = TIM_CCMR1_CC2S_0 | TIM_CCMR1_CC1S_0;
wengefa1 2:f381fc3a8eaf 136 TIM->CCMR2 = 0x0000; // reset capture mode register 2
wengefa1 2:f381fc3a8eaf 137 TIM->CCER = TIM_CCER_CC2E | TIM_CCER_CC1E;
wengefa1 2:f381fc3a8eaf 138 TIM->CNT = 0x0000; // reset counter value
wengefa1 2:f381fc3a8eaf 139 TIM->ARR = 0xFFFF; // auto reload register
wengefa1 2:f381fc3a8eaf 140 TIM->CR1 = TIM_CR1_CEN; // counter enable
wengefa1 2:f381fc3a8eaf 141 }
wengefa1 2:f381fc3a8eaf 142 }
wengefa1 2:f381fc3a8eaf 143
wengefa1 2:f381fc3a8eaf 144 /**
wengefa1 2:f381fc3a8eaf 145 * Deletes this EncoderCounter object.
wengefa1 2:f381fc3a8eaf 146 */
wengefa1 2:f381fc3a8eaf 147 EncoderCounter::~EncoderCounter() {}
wengefa1 2:f381fc3a8eaf 148
wengefa1 2:f381fc3a8eaf 149 /**
wengefa1 2:f381fc3a8eaf 150 * Resets the counter value to zero.
wengefa1 2:f381fc3a8eaf 151 */
wengefa1 2:f381fc3a8eaf 152 void EncoderCounter::reset() {
wengefa1 2:f381fc3a8eaf 153
wengefa1 2:f381fc3a8eaf 154 TIM->CNT = 0x0000;
wengefa1 2:f381fc3a8eaf 155 }
wengefa1 2:f381fc3a8eaf 156
wengefa1 2:f381fc3a8eaf 157 /**
wengefa1 2:f381fc3a8eaf 158 * Resets the counter value to a given offset value.
wengefa1 2:f381fc3a8eaf 159 * @param offset the offset value to reset the counter to.
wengefa1 2:f381fc3a8eaf 160 */
wengefa1 2:f381fc3a8eaf 161 void EncoderCounter::reset(short offset) {
wengefa1 2:f381fc3a8eaf 162
wengefa1 2:f381fc3a8eaf 163 TIM->CNT = -offset;
wengefa1 2:f381fc3a8eaf 164 }
wengefa1 2:f381fc3a8eaf 165
wengefa1 2:f381fc3a8eaf 166 /**
wengefa1 2:f381fc3a8eaf 167 * Reads the quadrature encoder counter value.
wengefa1 2:f381fc3a8eaf 168 * @return the quadrature encoder counter as a signed 16-bit integer value.
wengefa1 2:f381fc3a8eaf 169 */
wengefa1 2:f381fc3a8eaf 170 short EncoderCounter::read() {
wengefa1 2:f381fc3a8eaf 171
wengefa1 2:f381fc3a8eaf 172 return (short)(-TIM->CNT);
wengefa1 2:f381fc3a8eaf 173 }
wengefa1 2:f381fc3a8eaf 174
wengefa1 2:f381fc3a8eaf 175 /**
wengefa1 2:f381fc3a8eaf 176 * The empty operator is a shorthand notation of the <code>read()</code> method.
wengefa1 2:f381fc3a8eaf 177 */
wengefa1 2:f381fc3a8eaf 178 EncoderCounter::operator short() {
wengefa1 2:f381fc3a8eaf 179
wengefa1 2:f381fc3a8eaf 180 return read();
wengefa1 2:f381fc3a8eaf 181 }
wengefa1 2:f381fc3a8eaf 182