David Lowe / Mbed 2 deprecated Nucleo_BSP_IHM01A1

X-CUBE-SPN1-20150128 example source code for one motor compiled under mbed. Tested OK on Nucleo F401. l6474.cpp is modified from original with defines in l6474_target_config.h to select the original behaviour (motor de-energised when halted), or new mode to continue powering with a (reduced) current in the coils (braking/position hold capability). On F401 avoid using mbed's InterruptIn on pins 10-15 (any port). Beware of other conflicts! L0 & F0 are included but untested.

Dependencies:   mbed

IHM01A1/stm32f4xx_nucleo_ihm01a1.h@6:19c1b4a04c24, 2015-10-13 (annotated)

Committer:
gregeric
Date:
Tue Oct 13 10:46:01 2015 +0000
Revision:
6:19c1b4a04c24
Parent:
0:b9444a40a999 
Ensure bridge is disabled before resetting the L6474.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gregeric 0:b9444a40a999 1 /**
gregeric 0:b9444a40a999 2 ******************************************************************************
gregeric 0:b9444a40a999 3 * @file stm32f4xx_nucleo_ihm01a1.h
gregeric 0:b9444a40a999 4 * @author IPC Rennes
gregeric 0:b9444a40a999 5 * @version V1.5.0
gregeric 0:b9444a40a999 6 * @date November 12, 2014
gregeric 0:b9444a40a999 7 * @brief Header for BSP driver for x-nucleo-ihm01a1 Nucleo extension board
gregeric 0:b9444a40a999 8 * (based on L6474)
gregeric 0:b9444a40a999 9 ******************************************************************************
gregeric 0:b9444a40a999 10 * @attention
gregeric 0:b9444a40a999 11 *
gregeric 0:b9444a40a999 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
gregeric 0:b9444a40a999 13 *
gregeric 0:b9444a40a999 14 * Redistribution and use in source and binary forms, with or without modification,
gregeric 0:b9444a40a999 15 * are permitted provided that the following conditions are met:
gregeric 0:b9444a40a999 16 * 1. Redistributions of source code must retain the above copyright notice,
gregeric 0:b9444a40a999 17 * this list of conditions and the following disclaimer.
gregeric 0:b9444a40a999 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
gregeric 0:b9444a40a999 19 * this list of conditions and the following disclaimer in the documentation
gregeric 0:b9444a40a999 20 * and/or other materials provided with the distribution.
gregeric 0:b9444a40a999 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
gregeric 0:b9444a40a999 22 * may be used to endorse or promote products derived from this software
gregeric 0:b9444a40a999 23 * without specific prior written permission.
gregeric 0:b9444a40a999 24 *
gregeric 0:b9444a40a999 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
gregeric 0:b9444a40a999 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
gregeric 0:b9444a40a999 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
gregeric 0:b9444a40a999 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
gregeric 0:b9444a40a999 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
gregeric 0:b9444a40a999 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
gregeric 0:b9444a40a999 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
gregeric 0:b9444a40a999 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
gregeric 0:b9444a40a999 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
gregeric 0:b9444a40a999 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
gregeric 0:b9444a40a999 35 *
gregeric 0:b9444a40a999 36 ******************************************************************************
gregeric 0:b9444a40a999 37 */
gregeric 0:b9444a40a999 38
gregeric 0:b9444a40a999 39 /* Define to prevent recursive inclusion -------------------------------------*/
gregeric 0:b9444a40a999 40 #ifndef __STM32F4XX_NUCLEO_IHM01A1_H
gregeric 0:b9444a40a999 41 #define __STM32F4XX_NUCLEO_IHM01A1_H
gregeric 0:b9444a40a999 42
gregeric 0:b9444a40a999 43 #ifdef __cplusplus
gregeric 0:b9444a40a999 44 extern "C" {
gregeric 0:b9444a40a999 45 #endif
gregeric 0:b9444a40a999 46
gregeric 0:b9444a40a999 47 /* Includes ------------------------------------------------------------------*/
gregeric 0:b9444a40a999 48 //mbed #include "stm32f4xx_nucleo.h"
gregeric 0:b9444a40a999 49
gregeric 0:b9444a40a999 50 /** @addtogroup BSP
gregeric 0:b9444a40a999 51 * @{
gregeric 0:b9444a40a999 52 */
gregeric 0:b9444a40a999 53
gregeric 0:b9444a40a999 54 /** @addtogroup STM32F4XX_NUCLEO_IHM01A1
gregeric 0:b9444a40a999 55 * @{
gregeric 0:b9444a40a999 56 */
gregeric 0:b9444a40a999 57
gregeric 0:b9444a40a999 58 /** @defgroup IHM01A1_Board_Private_Function_Prototypes
gregeric 0:b9444a40a999 59 * @{
gregeric 0:b9444a40a999 60 */
gregeric 0:b9444a40a999 61
gregeric 0:b9444a40a999 62 void BSP_MotorControlBoard_Delay(uint32_t delay); //Delay of the requested number of milliseconds
gregeric 0:b9444a40a999 63 void BSP_MotorControlBoard_DisableIrq(void); //Disable Irq
gregeric 0:b9444a40a999 64 void BSP_MotorControlBoard_EnableIrq(void); //Enable Irq
gregeric 0:b9444a40a999 65 void BSP_MotorControlBoard_GpioInit(uint8_t nbDevices); //Initialise GPIOs used for L6474s
gregeric 0:b9444a40a999 66 void BSP_MotorControlBoard_Pwm1SetFreq(uint16_t newFreq); //Set PWM1 frequency and start it
gregeric 0:b9444a40a999 67 void BSP_MotorControlBoard_Pwm2SetFreq(uint16_t newFreq); //Set PWM2 frequency and start it
gregeric 0:b9444a40a999 68 void BSP_MotorControlBoard_Pwm3SetFreq(uint16_t newFreq); //Set PWM3 frequency and start it
gregeric 0:b9444a40a999 69 void BSP_MotorControlBoard_PwmInit(uint8_t deviceId); //Init the PWM of the specified device
gregeric 0:b9444a40a999 70 void BSP_MotorControlBoard_PwmStop(uint8_t deviceId); //Stop the PWM of the specified device
gregeric 0:b9444a40a999 71 void BSP_MotorControlBoard_ReleaseReset(void); //Reset the L6474 reset pin
gregeric 0:b9444a40a999 72 void BSP_MotorControlBoard_Reset(void); //Set the L6474 reset pin
gregeric 0:b9444a40a999 73 void BSP_MotorControlBoard_SetDirectionGpio(uint8_t deviceId, uint8_t gpioState); //Set direction GPIO
gregeric 0:b9444a40a999 74 uint8_t BSP_MotorControlBoard_SpiInit(void); //Initialise the SPI used for L6474s
gregeric 0:b9444a40a999 75 uint8_t BSP_MotorControlBoard_SpiWriteBytes(uint8_t *pByteToTransmit, uint8_t *pReceivedByte, uint8_t nbDevices); //Write bytes to the L6474s via SPI
gregeric 0:b9444a40a999 76
gregeric 0:b9444a40a999 77 /* Exported Constants --------------------------------------------------------*/
gregeric 0:b9444a40a999 78
gregeric 0:b9444a40a999 79 /** @defgroup IHM01A1_Exported_Constants
gregeric 0:b9444a40a999 80 * @{
gregeric 0:b9444a40a999 81 */
gregeric 0:b9444a40a999 82
gregeric 0:b9444a40a999 83 /******************************************************************************/
gregeric 0:b9444a40a999 84 /* USE_STM32F4XX_NUCLEO */
gregeric 0:b9444a40a999 85 /******************************************************************************/
gregeric 0:b9444a40a999 86
gregeric 0:b9444a40a999 87 /** @defgroup Constants_For_STM32F4XX_NUCLEO
gregeric 0:b9444a40a999 88 * @{
gregeric 0:b9444a40a999 89 */
gregeric 0:b9444a40a999 90 /// Interrupt line used for L6474 FLAG
gregeric 0:b9444a40a999 91 #define EXTI_MCU_LINE_IRQn (EXTI15_10_IRQn)
gregeric 0:b9444a40a999 92
gregeric 0:b9444a40a999 93 /// Timer used for PWM1
gregeric 0:b9444a40a999 94 #define BSP_MOTOR_CONTROL_BOARD_TIMER_PWM1 (TIM3)
gregeric 0:b9444a40a999 95
gregeric 0:b9444a40a999 96 /// Timer used for PWM2
gregeric 0:b9444a40a999 97 #define BSP_MOTOR_CONTROL_BOARD_TIMER_PWM2 (TIM2)
gregeric 0:b9444a40a999 98
gregeric 0:b9444a40a999 99 /// Timer used for PWM3
gregeric 0:b9444a40a999 100 #define BSP_MOTOR_CONTROL_BOARD_TIMER_PWM3 (TIM4)
gregeric 0:b9444a40a999 101
gregeric 0:b9444a40a999 102 /// Channel Timer used for PWM1
gregeric 0:b9444a40a999 103 #define BSP_MOTOR_CONTROL_BOARD_CHAN_TIMER_PWM1 (TIM_CHANNEL_2)
gregeric 0:b9444a40a999 104
gregeric 0:b9444a40a999 105 /// Channel Timer used for PWM2
gregeric 0:b9444a40a999 106 #define BSP_MOTOR_CONTROL_BOARD_CHAN_TIMER_PWM2 (TIM_CHANNEL_2)
gregeric 0:b9444a40a999 107
gregeric 0:b9444a40a999 108 /// Channel Timer used for PWM3
gregeric 0:b9444a40a999 109 #define BSP_MOTOR_CONTROL_BOARD_CHAN_TIMER_PWM3 (TIM_CHANNEL_3)
gregeric 0:b9444a40a999 110
gregeric 0:b9444a40a999 111 /// HAL Active Channel Timer used for PWM1
gregeric 0:b9444a40a999 112 #define BSP_MOTOR_CONTROL_BOARD_HAL_ACT_CHAN_TIMER_PWM1 (HAL_TIM_ACTIVE_CHANNEL_2)
gregeric 0:b9444a40a999 113
gregeric 0:b9444a40a999 114 /// HAL Active Channel Timer used for PWM2
gregeric 0:b9444a40a999 115 #define BSP_MOTOR_CONTROL_BOARD_HAL_ACT_CHAN_TIMER_PWM2 (HAL_TIM_ACTIVE_CHANNEL_2)
gregeric 0:b9444a40a999 116
gregeric 0:b9444a40a999 117 /// HAL Active Channel Timer used for PWM3
gregeric 0:b9444a40a999 118 #define BSP_MOTOR_CONTROL_BOARD_HAL_ACT_CHAN_TIMER_PWM3 (HAL_TIM_ACTIVE_CHANNEL_3)
gregeric 0:b9444a40a999 119
gregeric 0:b9444a40a999 120 /// Timer Clock Enable for PWM1
gregeric 0:b9444a40a999 121 #define __BSP_MOTOR_CONTROL_BOARD_TIMER_PWM1_CLCK_ENABLE() __TIM3_CLK_ENABLE()
gregeric 0:b9444a40a999 122
gregeric 0:b9444a40a999 123 /// Timer Clock Enable for PWM2
gregeric 0:b9444a40a999 124 #define __BSP_MOTOR_CONTROL_BOARD_TIMER_PWM2_CLCK_ENABLE() __TIM2_CLK_ENABLE()
gregeric 0:b9444a40a999 125
gregeric 0:b9444a40a999 126 /// Timer Clock Enable for PWM1
gregeric 0:b9444a40a999 127 #define __BSP_MOTOR_CONTROL_BOARD_TIMER_PWM3_CLCK_ENABLE() __TIM4_CLK_ENABLE()
gregeric 0:b9444a40a999 128
gregeric 0:b9444a40a999 129 /// Timer Clock Disable for PWM1
gregeric 0:b9444a40a999 130 #define __BSP_MOTOR_CONTROL_BOARD_TIMER_PWM1_CLCK_DISABLE() __TIM3_CLK_DISABLE()
gregeric 0:b9444a40a999 131
gregeric 0:b9444a40a999 132 /// Timer Clock Disable for PWM2
gregeric 0:b9444a40a999 133 #define __BSP_MOTOR_CONTROL_BOARD_TIMER_PWM2_CLCK_DISABLE() __TIM2_CLK_DISABLE()
gregeric 0:b9444a40a999 134
gregeric 0:b9444a40a999 135 /// Timer Clock Disable for PWM3
gregeric 0:b9444a40a999 136 #define __BSP_MOTOR_CONTROL_BOARD_TIMER_PWM3_CLCK_DISABLE() __TIM4_CLK_DISABLE()
gregeric 0:b9444a40a999 137
gregeric 0:b9444a40a999 138 /// PWM1 global interrupt
gregeric 0:b9444a40a999 139 #define BSP_MOTOR_CONTROL_BOARD_PWM1_IRQn (TIM3_IRQn)
gregeric 0:b9444a40a999 140
gregeric 0:b9444a40a999 141 /// PWM2 global interrupt
gregeric 0:b9444a40a999 142 #define BSP_MOTOR_CONTROL_BOARD_PWM2_IRQn (TIM2_IRQn)
gregeric 0:b9444a40a999 143
gregeric 0:b9444a40a999 144 /// PWM3 global interrupt
gregeric 0:b9444a40a999 145 #define BSP_MOTOR_CONTROL_BOARD_PWM3_IRQn (TIM4_IRQn)
gregeric 0:b9444a40a999 146
gregeric 0:b9444a40a999 147 /// PWM1 GPIO alternate function
gregeric 0:b9444a40a999 148 #define BSP_MOTOR_CONTROL_BOARD_AFx_TIMx_PWM1 (GPIO_AF2_TIM3)
gregeric 0:b9444a40a999 149
gregeric 0:b9444a40a999 150 /// PWM2 GPIO alternate function
gregeric 0:b9444a40a999 151 #define BSP_MOTOR_CONTROL_BOARD_AFx_TIMx_PWM2 (GPIO_AF1_TIM2)
gregeric 0:b9444a40a999 152
gregeric 0:b9444a40a999 153 #ifndef BSP_MOTOR_CONTROL_BOARD_USE_SPI2
gregeric 0:b9444a40a999 154 /// SPI SCK AF
gregeric 0:b9444a40a999 155 #define SPIx_SCK_AF (GPIO_AF5_SPI1)
gregeric 0:b9444a40a999 156 #else /* #ifndef BSP_MOTOR_CONTROL_BOARD_USE_SPI2 */
gregeric 0:b9444a40a999 157 /// SPI SCK AF
gregeric 0:b9444a40a999 158 #define SPIx_SCK_AF (GPIO_AF5_SPI2)
gregeric 0:b9444a40a999 159 #endif /* #ifndef BSP_MOTOR_CONTROL_BOARD_USE_SPI2 */
gregeric 0:b9444a40a999 160
gregeric 0:b9444a40a999 161 /// PWM1 frequency rescaler (1 for HW PWM, 2 for SW PWM)
gregeric 0:b9444a40a999 162 #define BSP_MOTOR_CONTROL_BOARD_PWM1_FREQ_RESCALER (1)
gregeric 0:b9444a40a999 163 /// PWM2 frequency rescaler (1 for HW PWM, 2 for SW PWM)
gregeric 0:b9444a40a999 164 #define BSP_MOTOR_CONTROL_BOARD_PWM2_FREQ_RESCALER (1)
gregeric 0:b9444a40a999 165 /// PWM3 frequency rescaler (1 for HW PWM, 2 for SW PWM)
gregeric 0:b9444a40a999 166 #define BSP_MOTOR_CONTROL_BOARD_PWM3_FREQ_RESCALER (2)
gregeric 0:b9444a40a999 167
gregeric 0:b9444a40a999 168 /**
gregeric 0:b9444a40a999 169 * @}
gregeric 0:b9444a40a999 170 */
gregeric 0:b9444a40a999 171
gregeric 0:b9444a40a999 172 /******************************************************************************/
gregeric 0:b9444a40a999 173 /* Independent plateform definitions */
gregeric 0:b9444a40a999 174 /******************************************************************************/
gregeric 0:b9444a40a999 175
gregeric 0:b9444a40a999 176 /** @defgroup Constants_For_All_Nucleo_Platforms
gregeric 0:b9444a40a999 177 * @{
gregeric 0:b9444a40a999 178 */
gregeric 0:b9444a40a999 179
gregeric 0:b9444a40a999 180 /// GPIO Pin used for the L6474 flag pin
gregeric 0:b9444a40a999 181 #define BSP_MOTOR_CONTROL_BOARD_FLAG_PIN (GPIO_PIN_10)
gregeric 0:b9444a40a999 182 /// GPIO port used for the L6474 flag pin
gregeric 0:b9444a40a999 183 #define BSP_MOTOR_CONTROL_BOARD_FLAG_PORT (GPIOA)
gregeric 0:b9444a40a999 184
gregeric 0:b9444a40a999 185 /// GPIO Pin used for the L6474 step clock pin of device 0
gregeric 0:b9444a40a999 186 #define BSP_MOTOR_CONTROL_BOARD_PWM_1_PIN (GPIO_PIN_7)
gregeric 0:b9444a40a999 187 /// GPIO Port used for the L6474 step clock pin of device 0
gregeric 0:b9444a40a999 188 #define BSP_MOTOR_CONTROL_BOARD_PWM_1_PORT (GPIOC)
gregeric 0:b9444a40a999 189
gregeric 0:b9444a40a999 190 /// GPIO Pin used for the L6474 step clock pin of device 1
gregeric 0:b9444a40a999 191 #define BSP_MOTOR_CONTROL_BOARD_PWM_2_PIN (GPIO_PIN_3)
gregeric 0:b9444a40a999 192 /// GPIO port used for the L6474 step clock pin of device 1
gregeric 0:b9444a40a999 193 #define BSP_MOTOR_CONTROL_BOARD_PWM_2_PORT (GPIOB)
gregeric 0:b9444a40a999 194
gregeric 0:b9444a40a999 195 /// GPIO Pin used for the L6474 step clock pin of device 2
gregeric 0:b9444a40a999 196 #define BSP_MOTOR_CONTROL_BOARD_PWM_3_PIN (GPIO_PIN_10)
gregeric 0:b9444a40a999 197 /// GPIO port used for the L6474 step clock pin of device 2
gregeric 0:b9444a40a999 198 #define BSP_MOTOR_CONTROL_BOARD_PWM_3_PORT (GPIOB)
gregeric 0:b9444a40a999 199
gregeric 0:b9444a40a999 200 /// GPIO Pin used for the L6474 direction pin of device 0
gregeric 0:b9444a40a999 201 #define BSP_MOTOR_CONTROL_BOARD_DIR_1_PIN (GPIO_PIN_8)
gregeric 0:b9444a40a999 202 /// GPIO port used for the L6474 direction pin of device 0
gregeric 0:b9444a40a999 203 #define BSP_MOTOR_CONTROL_BOARD_DIR_1_PORT (GPIOA)
gregeric 0:b9444a40a999 204
gregeric 0:b9444a40a999 205 /// GPIO Pin used for the L6474 direction pin of device 1
gregeric 0:b9444a40a999 206 #define BSP_MOTOR_CONTROL_BOARD_DIR_2_PIN (GPIO_PIN_5)
gregeric 0:b9444a40a999 207 /// GPIO port used for the L6474 direction pin of device 1
gregeric 0:b9444a40a999 208 #define BSP_MOTOR_CONTROL_BOARD_DIR_2_PORT (GPIOB)
gregeric 0:b9444a40a999 209
gregeric 0:b9444a40a999 210 /// GPIO Pin used for the L6474 direction pin of device 2
gregeric 0:b9444a40a999 211 #define BSP_MOTOR_CONTROL_BOARD_DIR_3_PIN (GPIO_PIN_4)
gregeric 0:b9444a40a999 212 /// GPIO port used for the L6474 direction pin of device 2
gregeric 0:b9444a40a999 213 #define BSP_MOTOR_CONTROL_BOARD_DIR_3_PORT (GPIOB)
gregeric 0:b9444a40a999 214
gregeric 0:b9444a40a999 215 /// GPIO Pin used for the L6474 reset pin
gregeric 0:b9444a40a999 216 #define BSP_MOTOR_CONTROL_BOARD_RESET_PIN (GPIO_PIN_9)
gregeric 0:b9444a40a999 217 /// GPIO port used for the L6474 reset pin
gregeric 0:b9444a40a999 218 #define BSP_MOTOR_CONTROL_BOARD_RESET_PORT (GPIOA)
gregeric 0:b9444a40a999 219
gregeric 0:b9444a40a999 220 /// GPIO Pin used for the L6474 SPI chip select pin
gregeric 0:b9444a40a999 221 #define BSP_MOTOR_CONTROL_BOARD_CS_PIN (GPIO_PIN_6)
gregeric 0:b9444a40a999 222 /// GPIO port used for the L6474 SPI chip select pin
gregeric 0:b9444a40a999 223 #define BSP_MOTOR_CONTROL_BOARD_CS_PORT (GPIOB)
gregeric 0:b9444a40a999 224
gregeric 0:b9444a40a999 225 /* Definition for SPIx clock resources */
gregeric 0:b9444a40a999 226
gregeric 0:b9444a40a999 227 #ifndef BSP_MOTOR_CONTROL_BOARD_USE_SPI2
gregeric 0:b9444a40a999 228 /* Default SPI is SPI1 */
gregeric 0:b9444a40a999 229
gregeric 0:b9444a40a999 230 /// Used SPI
gregeric 0:b9444a40a999 231 #define SPIx (SPI1)
gregeric 0:b9444a40a999 232
gregeric 0:b9444a40a999 233 /// SPI clock enable
gregeric 0:b9444a40a999 234 #define SPIx_CLK_ENABLE() __SPI1_CLK_ENABLE()
gregeric 0:b9444a40a999 235
gregeric 0:b9444a40a999 236 /// SPI SCK enable
gregeric 0:b9444a40a999 237 #define SPIx_SCK_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE()
gregeric 0:b9444a40a999 238
gregeric 0:b9444a40a999 239 /// SPI MISO enable
gregeric 0:b9444a40a999 240 #define SPIx_MISO_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE()
gregeric 0:b9444a40a999 241
gregeric 0:b9444a40a999 242 /// SPI MOSI enable
gregeric 0:b9444a40a999 243 #define SPIx_MOSI_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE()
gregeric 0:b9444a40a999 244
gregeric 0:b9444a40a999 245 /// SPI Force reset
gregeric 0:b9444a40a999 246 #define SPIx_FORCE_RESET() __SPI1_FORCE_RESET()
gregeric 0:b9444a40a999 247
gregeric 0:b9444a40a999 248 /// SPI Release reset
gregeric 0:b9444a40a999 249 #define SPIx_RELEASE_RESET() __SPI1_RELEASE_RESET()
gregeric 0:b9444a40a999 250
gregeric 0:b9444a40a999 251 /// SPI SCK pin
gregeric 0:b9444a40a999 252 #define SPIx_SCK_PIN (GPIO_PIN_5)
gregeric 0:b9444a40a999 253
gregeric 0:b9444a40a999 254 /// SPI SCK port
gregeric 0:b9444a40a999 255 #define SPIx_SCK_GPIO_PORT (GPIOA)
gregeric 0:b9444a40a999 256
gregeric 0:b9444a40a999 257
gregeric 0:b9444a40a999 258 /// SPI MISO pin
gregeric 0:b9444a40a999 259 #define SPIx_MISO_PIN (GPIO_PIN_6)
gregeric 0:b9444a40a999 260
gregeric 0:b9444a40a999 261 /// SPI MISO port
gregeric 0:b9444a40a999 262 #define SPIx_MISO_GPIO_PORT (GPIOA)
gregeric 0:b9444a40a999 263
gregeric 0:b9444a40a999 264 /// SPI MOSI pin
gregeric 0:b9444a40a999 265 #define SPIx_MOSI_PIN (GPIO_PIN_7)
gregeric 0:b9444a40a999 266
gregeric 0:b9444a40a999 267 /// SPI MOSI port
gregeric 0:b9444a40a999 268 #define SPIx_MOSI_GPIO_PORT (GPIOA)
gregeric 0:b9444a40a999 269
gregeric 0:b9444a40a999 270 #else /* USE SPI2 */
gregeric 0:b9444a40a999 271
gregeric 0:b9444a40a999 272 /// Used SPI
gregeric 0:b9444a40a999 273 #define SPIx (SPI2)
gregeric 0:b9444a40a999 274
gregeric 0:b9444a40a999 275 /// SPI clock enable
gregeric 0:b9444a40a999 276 #define SPIx_CLK_ENABLE() __SPI2_CLK_ENABLE()
gregeric 0:b9444a40a999 277
gregeric 0:b9444a40a999 278 /// SPI SCK enable
gregeric 0:b9444a40a999 279 #define SPIx_SCK_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE()
gregeric 0:b9444a40a999 280
gregeric 0:b9444a40a999 281 /// SPI MISO enable
gregeric 0:b9444a40a999 282 #define SPIx_MISO_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE()
gregeric 0:b9444a40a999 283
gregeric 0:b9444a40a999 284 /// SPI MOSI enable
gregeric 0:b9444a40a999 285 #define SPIx_MOSI_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE()
gregeric 0:b9444a40a999 286
gregeric 0:b9444a40a999 287 /// SPI Force reset
gregeric 0:b9444a40a999 288 #define SPIx_FORCE_RESET() __SPI2_FORCE_RESET()
gregeric 0:b9444a40a999 289
gregeric 0:b9444a40a999 290 /// SPI Release reset
gregeric 0:b9444a40a999 291 #define SPIx_RELEASE_RESET() __SPI2_RELEASE_RESET()
gregeric 0:b9444a40a999 292
gregeric 0:b9444a40a999 293 /// SPI SCK pin
gregeric 0:b9444a40a999 294 #define SPIx_SCK_PIN (GPIO_PIN_13)
gregeric 0:b9444a40a999 295
gregeric 0:b9444a40a999 296 /// SPI SCK port
gregeric 0:b9444a40a999 297 #define SPIx_SCK_GPIO_PORT (GPIOB)
gregeric 0:b9444a40a999 298
gregeric 0:b9444a40a999 299 /// SPI MISO pin
gregeric 0:b9444a40a999 300 #define SPIx_MISO_PIN (GPIO_PIN_14)
gregeric 0:b9444a40a999 301
gregeric 0:b9444a40a999 302 /// SPI MISO port
gregeric 0:b9444a40a999 303 #define SPIx_MISO_GPIO_PORT (GPIOB)
gregeric 0:b9444a40a999 304
gregeric 0:b9444a40a999 305 /// SPI MISO AF
gregeric 0:b9444a40a999 306 #define SPIx_MISO_AF (SPIx_SCK_AF)
gregeric 0:b9444a40a999 307
gregeric 0:b9444a40a999 308 /// SPI MOSI pin
gregeric 0:b9444a40a999 309 #define SPIx_MOSI_PIN (GPIO_PIN_15)
gregeric 0:b9444a40a999 310
gregeric 0:b9444a40a999 311 /// SPI MOSI port
gregeric 0:b9444a40a999 312 #define SPIx_MOSI_GPIO_PORT (GPIOB)
gregeric 0:b9444a40a999 313
gregeric 0:b9444a40a999 314 #endif
gregeric 0:b9444a40a999 315
gregeric 0:b9444a40a999 316 /// SPI MISO AF
gregeric 0:b9444a40a999 317 #define SPIx_MISO_AF (SPIx_SCK_AF)
gregeric 0:b9444a40a999 318
gregeric 0:b9444a40a999 319 /// SPI MOSI AF
gregeric 0:b9444a40a999 320 #define SPIx_MOSI_AF (SPIx_SCK_AF)
gregeric 0:b9444a40a999 321
gregeric 0:b9444a40a999 322 /**
gregeric 0:b9444a40a999 323 * @}
gregeric 0:b9444a40a999 324 */
gregeric 0:b9444a40a999 325
gregeric 0:b9444a40a999 326 /**
gregeric 0:b9444a40a999 327 * @}
gregeric 0:b9444a40a999 328 */
gregeric 0:b9444a40a999 329
gregeric 0:b9444a40a999 330 #ifdef __cplusplus
gregeric 0:b9444a40a999 331 }
gregeric 0:b9444a40a999 332 #endif
gregeric 0:b9444a40a999 333
gregeric 0:b9444a40a999 334 #endif /* __STM32F4XX_NUCLEO_IHM01A1_H */
gregeric 0:b9444a40a999 335
gregeric 0:b9444a40a999 336 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/