green rosh / Mbed 2 deprecated BAE_FRDMTESIN2

i2c working

Dependencies:   mbed-rtos mbed

Fork of BAE_FRDMTESIN2 by Seeker of Truth ,

beacon.cpp@10:ed6d3b8d1d56, 2014-12-16 (annotated)

Committer:
greenroshks
Date:
Tue Dec 16 07:44:54 2014 +0000
Revision:
10:ed6d3b8d1d56
Parent:
0:8b0d43fe6c05 
working

Who changed what in which revision?

UserRevisionLine numberNew contents of line
greenroshks 0:8b0d43fe6c05 1 //switch off the sync!!!!!!!
greenroshks 0:8b0d43fe6c05 2 //switch off the preamble!!!!!!!
greenroshks 0:8b0d43fe6c05 3 /*for crc in tx:
greenroshks 0:8b0d43fe6c05 4 regIrq2(0x28) :
greenroshks 0:8b0d43fe6c05 5
greenroshks 0:8b0d43fe6c05 6 regpacketconfig 1(0x37) :
greenroshks 0:8b0d43fe6c05 7 set crc detection/calc. on : | 0x10
greenroshks 0:8b0d43fe6c05 8 crcautoclearoff : | 0x08
greenroshks 0:8b0d43fe6c05 9
greenroshks 0:8b0d43fe6c05 10 for data whitening : regpacketconfig 1(0x37) :| 0x40
greenroshks 0:8b0d43fe6c05 11 for
greenroshks 0:8b0d43fe6c05 12
greenroshks 0:8b0d43fe6c05 13
greenroshks 0:8b0d43fe6c05 14
greenroshks 0:8b0d43fe6c05 15 */
greenroshks 0:8b0d43fe6c05 16 // 6CC000 for 435 MHz
greenroshks 0:8b0d43fe6c05 17 //set all values as FF for checking on spectrum analyzer
greenroshks 0:8b0d43fe6c05 18 #include "beacon.h"
greenroshks 0:8b0d43fe6c05 19 #include "HK.h"
greenroshks 0:8b0d43fe6c05 20 Serial chavan(USBTX, USBRX); // tx, rx
greenroshks 0:8b0d43fe6c05 21 SPI spi(PTD6,PTD7,PTD5); // mosi, miso, sclk
greenroshks 0:8b0d43fe6c05 22 DigitalOut cs_bar(D5); //slave select or chip select
greenroshks 0:8b0d43fe6c05 23 //InterruptIn button(p9);
greenroshks 0:8b0d43fe6c05 24 //#define TIMES 16
greenroshks 0:8b0d43fe6c05 25 //Timer t;
greenroshks 0:8b0d43fe6c05 26
greenroshks 0:8b0d43fe6c05 27 /*void interrupt_func()
greenroshks 0:8b0d43fe6c05 28 {
greenroshks 0:8b0d43fe6c05 29 chavan.printf("INTERRUPT_FUNC TRIGGERED\n wait for 3 secs\n");
greenroshks 0:8b0d43fe6c05 30 wait(3);
greenroshks 0:8b0d43fe6c05 31
greenroshks 0:8b0d43fe6c05 32 }*/
greenroshks 0:8b0d43fe6c05 33
greenroshks 0:8b0d43fe6c05 34 extern ShortBeacy Shortbeacon;
greenroshks 0:8b0d43fe6c05 35 void writereg(uint8_t reg,uint8_t val)
greenroshks 0:8b0d43fe6c05 36 {
greenroshks 0:8b0d43fe6c05 37 cs_bar = 0;
greenroshks 0:8b0d43fe6c05 38 spi.write(reg | 0x80);
greenroshks 0:8b0d43fe6c05 39 spi.write(val);
greenroshks 0:8b0d43fe6c05 40 cs_bar = 1;
greenroshks 0:8b0d43fe6c05 41 }
greenroshks 0:8b0d43fe6c05 42 uint8_t readreg(uint8_t reg)
greenroshks 0:8b0d43fe6c05 43 {
greenroshks 0:8b0d43fe6c05 44 uint8_t val;
greenroshks 0:8b0d43fe6c05 45 cs_bar = 0;
greenroshks 0:8b0d43fe6c05 46 spi.write(reg & ~0x80);
greenroshks 0:8b0d43fe6c05 47 val = spi.write(0);
greenroshks 0:8b0d43fe6c05 48 cs_bar = 1;
greenroshks 0:8b0d43fe6c05 49 return val;
greenroshks 0:8b0d43fe6c05 50 }
greenroshks 0:8b0d43fe6c05 51
greenroshks 0:8b0d43fe6c05 52 void FUNC_BEA() {
greenroshks 0:8b0d43fe6c05 53
greenroshks 0:8b0d43fe6c05 54 //button.rise(&interrupt_func); //interrupt enabled ( rising edge of pin 9)
greenroshks 0:8b0d43fe6c05 55 printf("\nBeacon function entered\n");
greenroshks 0:8b0d43fe6c05 56 wait(0.02); //takes 10 ms for POR event + 10ms for safety
greenroshks 0:8b0d43fe6c05 57
greenroshks 0:8b0d43fe6c05 58 uint8_t byte_counter = 0;
greenroshks 0:8b0d43fe6c05 59
greenroshks 0:8b0d43fe6c05 60 /*struct Short_beacon{
greenroshks 0:8b0d43fe6c05 61 uint8_t Voltage[1];
greenroshks 0:8b0d43fe6c05 62 uint8_t AngularSpeed[2];
greenroshks 0:8b0d43fe6c05 63 uint8_t SubsystemStatus[1];
greenroshks 0:8b0d43fe6c05 64 uint8_t Temp[3];
greenroshks 0:8b0d43fe6c05 65 uint8_t ErrorFlag[1];
greenroshks 0:8b0d43fe6c05 66 }Shortbeacon = { {0x22}, {0x22, 0x33} , {0x00},{0x00,0x00,0x00}, {0xFE} };
greenroshks 0:8b0d43fe6c05 67 */
greenroshks 0:8b0d43fe6c05 68 //filling hk data
greenroshks 0:8b0d43fe6c05 69 //ShortBeacon Shortbeacon;
greenroshks 0:8b0d43fe6c05 70 uint8_t short_beacon[] = { 0xAB, 0x8A, 0xE2, 0xBB, 0xB8, 0xA2, 0x8E,Shortbeacon.Voltage[0],Shortbeacon.AngularSpeed[0], Shortbeacon.AngularSpeed[1],Shortbeacon.SubsystemStatus[0],Shortbeacon.Temp[0],Shortbeacon.Temp[1],Shortbeacon.Temp[2],Shortbeacon.ErrorFlag[0]};
greenroshks 0:8b0d43fe6c05 71
greenroshks 0:8b0d43fe6c05 72 //mask
greenroshks 0:8b0d43fe6c05 73 //uint8_t mask[] = {0x80, 0x40, 0x20,0x10,0x8,0x4,0x2,0x1};
greenroshks 0:8b0d43fe6c05 74
greenroshks 0:8b0d43fe6c05 75 for(int i = 0; i < 15 ; i++)
greenroshks 0:8b0d43fe6c05 76 {
greenroshks 0:8b0d43fe6c05 77 chavan.printf("0x%X\n",(short_beacon[i]));
greenroshks 0:8b0d43fe6c05 78 }
greenroshks 0:8b0d43fe6c05 79
greenroshks 0:8b0d43fe6c05 80 spi.format(8,0);
greenroshks 0:8b0d43fe6c05 81 spi.frequency(10000000); //10MHz SCLK frequency(its max for rfm69hcw)
greenroshks 0:8b0d43fe6c05 82 cs_bar = 1; // Chip must be deselected
greenroshks 0:8b0d43fe6c05 83
greenroshks 0:8b0d43fe6c05 84 //initialization
greenroshks 0:8b0d43fe6c05 85 //Common configuration registers
greenroshks 0:8b0d43fe6c05 86 writereg(0x01,0x04); //sequencer on,standby mode
greenroshks 0:8b0d43fe6c05 87 writereg(0x02,0x08); //packet-mode used , ook modultion , no dc-shaping
greenroshks 0:8b0d43fe6c05 88 writereg(0x03,0x68); //1200bps datarate
greenroshks 0:8b0d43fe6c05 89 writereg(0x04,0x2B); //1200bps datarate
greenroshks 0:8b0d43fe6c05 90 writereg(0x07,0x6C); //Frequency MSB
greenroshks 0:8b0d43fe6c05 91 writereg(0x08,0xC0); //Frequency MID
greenroshks 0:8b0d43fe6c05 92 writereg(0x09,0x00); //Frequency LSB ....6C C0 00 for 435 MHZ
greenroshks 0:8b0d43fe6c05 93
greenroshks 0:8b0d43fe6c05 94 //Transmitter registers
greenroshks 0:8b0d43fe6c05 95 // RegPaLevel(default +13 dBm)
greenroshks 0:8b0d43fe6c05 96
greenroshks 0:8b0d43fe6c05 97 //IRQ and Pin Mapping Registers
greenroshks 0:8b0d43fe6c05 98 //no DIO mapped yet
greenroshks 0:8b0d43fe6c05 99 //regirq1(0x27): modeready (8th bit) will be checked for interrupts
greenroshks 0:8b0d43fe6c05 100 //regIrq2(0x28): fifothresh (5th bit) ,packetsent(3rd bit) will be checked for interrupts
greenroshks 0:8b0d43fe6c05 101
greenroshks 0:8b0d43fe6c05 102 //Packet Engine Registers
greenroshks 0:8b0d43fe6c05 103 writereg(0x2C,0x00); //set preamble
greenroshks 0:8b0d43fe6c05 104 writereg(0x2D,0x0A); //set preamble
greenroshks 0:8b0d43fe6c05 105 writereg(0x2E,0x80); //sync off
greenroshks 0:8b0d43fe6c05 106 writereg(0x2F,0x5E); //sync word 1
greenroshks 0:8b0d43fe6c05 107 writereg(0x37,0x08 | 0x40);// | 0x10); //packetconfig1, 0x40 for data whitening (only for testing)
greenroshks 0:8b0d43fe6c05 108 writereg(0x38,0x00); //payload length = 0 ... unlimited payload mode
greenroshks 0:8b0d43fe6c05 109 writereg(0x3C,0xB0); //fifothresh = 48 because we want it cleared once its 40!!!!
greenroshks 0:8b0d43fe6c05 110 //Initialization complete
greenroshks 0:8b0d43fe6c05 111
greenroshks 0:8b0d43fe6c05 112 //while(chavan.getc() == 't'){
greenroshks 0:8b0d43fe6c05 113 //t.start();
greenroshks 0:8b0d43fe6c05 114 //Filling Data into FIFO 64 BYTES : eff.32 bits = 4bytes //fread
greenroshks 0:8b0d43fe6c05 115 cs_bar = 0;
greenroshks 0:8b0d43fe6c05 116 spi.write(0x80);//fifo write access
greenroshks 0:8b0d43fe6c05 117 for(byte_counter=0 ; byte_counter<4; byte_counter++)
greenroshks 0:8b0d43fe6c05 118 {
greenroshks 0:8b0d43fe6c05 119 for(int i=7; i>=0 ; i--)
greenroshks 0:8b0d43fe6c05 120 {
greenroshks 0:8b0d43fe6c05 121 if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!=0)
greenroshks 0:8b0d43fe6c05 122 //if((short_beacon[byte_counter] & mask[i]) != 0)
greenroshks 0:8b0d43fe6c05 123 {
greenroshks 0:8b0d43fe6c05 124 spi.write(0xFF);
greenroshks 0:8b0d43fe6c05 125 spi.write(0xFF);
greenroshks 0:8b0d43fe6c05 126 }
greenroshks 0:8b0d43fe6c05 127 else
greenroshks 0:8b0d43fe6c05 128 {
greenroshks 0:8b0d43fe6c05 129 spi.write(0x00);
greenroshks 0:8b0d43fe6c05 130 spi.write(0x00);
greenroshks 0:8b0d43fe6c05 131 }
greenroshks 0:8b0d43fe6c05 132 }
greenroshks 0:8b0d43fe6c05 133 }
greenroshks 0:8b0d43fe6c05 134 cs_bar = 1; //cs_bar
greenroshks 0:8b0d43fe6c05 135
greenroshks 0:8b0d43fe6c05 136 //Check for fifoThresh
greenroshks 0:8b0d43fe6c05 137 printf("\nfor loop executed\n");
greenroshks 0:8b0d43fe6c05 138 while((readreg(0x28) & 0x20) != 0x20);
greenroshks 0:8b0d43fe6c05 139 printf("\nwhile loop executed\n");
greenroshks 0:8b0d43fe6c05 140 //Highpower settings
greenroshks 0:8b0d43fe6c05 141 writereg(0x11,0x7F); //RegPalevel (20db) //~
greenroshks 0:8b0d43fe6c05 142 writereg(0x13,0x0F); //RegOCP
greenroshks 0:8b0d43fe6c05 143 writereg(0x5A,0x5D); //RegTestPa1
greenroshks 0:8b0d43fe6c05 144 writereg(0x5C,0x7C); //RegTestPa2
greenroshks 0:8b0d43fe6c05 145
greenroshks 0:8b0d43fe6c05 146 //Set to Tx mode
greenroshks 0:8b0d43fe6c05 147 writereg(0x01,0x0C);
greenroshks 0:8b0d43fe6c05 148
greenroshks 0:8b0d43fe6c05 149 printf("\npre 2nd while loop\n");
greenroshks 0:8b0d43fe6c05 150 //Check for fifoThresh
greenroshks 0:8b0d43fe6c05 151 while((readreg(0x28) & 0x20) != 0x00);
greenroshks 0:8b0d43fe6c05 152 printf("\n2nd while loop executed\n");
greenroshks 0:8b0d43fe6c05 153 while(byte_counter!=15){
greenroshks 0:8b0d43fe6c05 154
greenroshks 0:8b0d43fe6c05 155 //writing again
greenroshks 0:8b0d43fe6c05 156 cs_bar = 0;
greenroshks 0:8b0d43fe6c05 157 spi.write(0x80);
greenroshks 0:8b0d43fe6c05 158 for(int i=7; i>=0 ;i--)
greenroshks 0:8b0d43fe6c05 159 {
greenroshks 0:8b0d43fe6c05 160 if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!=0)
greenroshks 0:8b0d43fe6c05 161 //if((short_beacon[byte_counter] & mask[i]) != 0)
greenroshks 0:8b0d43fe6c05 162 {
greenroshks 0:8b0d43fe6c05 163 spi.write(0xFF);
greenroshks 0:8b0d43fe6c05 164 spi.write(0xFF);
greenroshks 0:8b0d43fe6c05 165 }
greenroshks 0:8b0d43fe6c05 166 else
greenroshks 0:8b0d43fe6c05 167 {
greenroshks 0:8b0d43fe6c05 168 spi.write(0x00);
greenroshks 0:8b0d43fe6c05 169 spi.write(0x00);
greenroshks 0:8b0d43fe6c05 170 }
greenroshks 0:8b0d43fe6c05 171 }
greenroshks 0:8b0d43fe6c05 172 cs_bar = 1;
greenroshks 0:8b0d43fe6c05 173 byte_counter++;
greenroshks 0:8b0d43fe6c05 174
greenroshks 0:8b0d43fe6c05 175 //Check for fifoThresh
greenroshks 0:8b0d43fe6c05 176 while((readreg(0x28) & 0x20) != 0x00);
greenroshks 0:8b0d43fe6c05 177 }
greenroshks 0:8b0d43fe6c05 178 printf("\n3rd big while loop executed\n");
greenroshks 0:8b0d43fe6c05 179 //wait for packet sent bit to fire
greenroshks 0:8b0d43fe6c05 180 while((readreg(0x28) & 0x08) != 0x08);
greenroshks 0:8b0d43fe6c05 181 printf("\n4th while loop executed\n");
greenroshks 0:8b0d43fe6c05 182 //chavan.printf("packet sent!!! \n");
greenroshks 0:8b0d43fe6c05 183
greenroshks 0:8b0d43fe6c05 184 //Switch back to Standby Mode
greenroshks 0:8b0d43fe6c05 185 writereg(0x01,0x04);
greenroshks 0:8b0d43fe6c05 186
greenroshks 0:8b0d43fe6c05 187 //Lowpowermode
greenroshks 0:8b0d43fe6c05 188 writereg(0x11,0x9F); //RegPalevel (13db)
greenroshks 0:8b0d43fe6c05 189 writereg(0x13,0x1A); //RegOCP
greenroshks 0:8b0d43fe6c05 190 writereg(0x5A,0x55); //RegTestPa1(setting PA_BOOST on RFIO)
greenroshks 0:8b0d43fe6c05 191 writereg(0x5C,0x70); //RegTestPa2(setting PA_BOOST on RFIO)
greenroshks 0:8b0d43fe6c05 192
greenroshks 0:8b0d43fe6c05 193 //wait for modeready
greenroshks 0:8b0d43fe6c05 194 while((readreg(0x27)&0x80)!=0x80);
greenroshks 0:8b0d43fe6c05 195
greenroshks 0:8b0d43fe6c05 196 //t.stop();
greenroshks 0:8b0d43fe6c05 197 //chavan.printf(" time taken to init + transmit = %f \n", t.read()) ;
greenroshks 0:8b0d43fe6c05 198 //}
greenroshks 0:8b0d43fe6c05 199 printf("\nBeacon function exiting\n");
greenroshks 0:8b0d43fe6c05 200 }