George Roussos / BLE_iBeacon_Exercise

Birkbeck College Mobile and Ubiquitous Computing IoT Lab Exercise 2

Dependencies:   BLE_API_Native_blog

mbed/TARGET_NRF51822/core_cm4_simd.h@0:e8fdba0ed044, 2015-03-07 (annotated)

Committer:
gkroussos
Date:
Sat Mar 07 16:34:53 2015 +0000
Revision:
0:e8fdba0ed044
MUC IoT Workshop v1.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gkroussos 0:e8fdba0ed044 1 /**************************************************************************//**
gkroussos 0:e8fdba0ed044 2 * @file core_cm4_simd.h
gkroussos 0:e8fdba0ed044 3 * @brief CMSIS Cortex-M4 SIMD Header File
gkroussos 0:e8fdba0ed044 4 * @version V3.20
gkroussos 0:e8fdba0ed044 5 * @date 25. February 2013
gkroussos 0:e8fdba0ed044 6 *
gkroussos 0:e8fdba0ed044 7 * @note
gkroussos 0:e8fdba0ed044 8 *
gkroussos 0:e8fdba0ed044 9 ******************************************************************************/
gkroussos 0:e8fdba0ed044 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
gkroussos 0:e8fdba0ed044 11
gkroussos 0:e8fdba0ed044 12 All rights reserved.
gkroussos 0:e8fdba0ed044 13 Redistribution and use in source and binary forms, with or without
gkroussos 0:e8fdba0ed044 14 modification, are permitted provided that the following conditions are met:
gkroussos 0:e8fdba0ed044 15 - Redistributions of source code must retain the above copyright
gkroussos 0:e8fdba0ed044 16 notice, this list of conditions and the following disclaimer.
gkroussos 0:e8fdba0ed044 17 - Redistributions in binary form must reproduce the above copyright
gkroussos 0:e8fdba0ed044 18 notice, this list of conditions and the following disclaimer in the
gkroussos 0:e8fdba0ed044 19 documentation and/or other materials provided with the distribution.
gkroussos 0:e8fdba0ed044 20 - Neither the name of ARM nor the names of its contributors may be used
gkroussos 0:e8fdba0ed044 21 to endorse or promote products derived from this software without
gkroussos 0:e8fdba0ed044 22 specific prior written permission.
gkroussos 0:e8fdba0ed044 23 *
gkroussos 0:e8fdba0ed044 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
gkroussos 0:e8fdba0ed044 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
gkroussos 0:e8fdba0ed044 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
gkroussos 0:e8fdba0ed044 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
gkroussos 0:e8fdba0ed044 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
gkroussos 0:e8fdba0ed044 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
gkroussos 0:e8fdba0ed044 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
gkroussos 0:e8fdba0ed044 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
gkroussos 0:e8fdba0ed044 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
gkroussos 0:e8fdba0ed044 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
gkroussos 0:e8fdba0ed044 34 POSSIBILITY OF SUCH DAMAGE.
gkroussos 0:e8fdba0ed044 35 ---------------------------------------------------------------------------*/
gkroussos 0:e8fdba0ed044 36
gkroussos 0:e8fdba0ed044 37
gkroussos 0:e8fdba0ed044 38 #ifdef __cplusplus
gkroussos 0:e8fdba0ed044 39 extern "C" {
gkroussos 0:e8fdba0ed044 40 #endif
gkroussos 0:e8fdba0ed044 41
gkroussos 0:e8fdba0ed044 42 #ifndef __CORE_CM4_SIMD_H
gkroussos 0:e8fdba0ed044 43 #define __CORE_CM4_SIMD_H
gkroussos 0:e8fdba0ed044 44
gkroussos 0:e8fdba0ed044 45
gkroussos 0:e8fdba0ed044 46 /*******************************************************************************
gkroussos 0:e8fdba0ed044 47 * Hardware Abstraction Layer
gkroussos 0:e8fdba0ed044 48 ******************************************************************************/
gkroussos 0:e8fdba0ed044 49
gkroussos 0:e8fdba0ed044 50
gkroussos 0:e8fdba0ed044 51 /* ################### Compiler specific Intrinsics ########################### */
gkroussos 0:e8fdba0ed044 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
gkroussos 0:e8fdba0ed044 53 Access to dedicated SIMD instructions
gkroussos 0:e8fdba0ed044 54 @{
gkroussos 0:e8fdba0ed044 55 */
gkroussos 0:e8fdba0ed044 56
gkroussos 0:e8fdba0ed044 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
gkroussos 0:e8fdba0ed044 58 /* ARM armcc specific functions */
gkroussos 0:e8fdba0ed044 59
gkroussos 0:e8fdba0ed044 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
gkroussos 0:e8fdba0ed044 61 #define __SADD8 __sadd8
gkroussos 0:e8fdba0ed044 62 #define __QADD8 __qadd8
gkroussos 0:e8fdba0ed044 63 #define __SHADD8 __shadd8
gkroussos 0:e8fdba0ed044 64 #define __UADD8 __uadd8
gkroussos 0:e8fdba0ed044 65 #define __UQADD8 __uqadd8
gkroussos 0:e8fdba0ed044 66 #define __UHADD8 __uhadd8
gkroussos 0:e8fdba0ed044 67 #define __SSUB8 __ssub8
gkroussos 0:e8fdba0ed044 68 #define __QSUB8 __qsub8
gkroussos 0:e8fdba0ed044 69 #define __SHSUB8 __shsub8
gkroussos 0:e8fdba0ed044 70 #define __USUB8 __usub8
gkroussos 0:e8fdba0ed044 71 #define __UQSUB8 __uqsub8
gkroussos 0:e8fdba0ed044 72 #define __UHSUB8 __uhsub8
gkroussos 0:e8fdba0ed044 73 #define __SADD16 __sadd16
gkroussos 0:e8fdba0ed044 74 #define __QADD16 __qadd16
gkroussos 0:e8fdba0ed044 75 #define __SHADD16 __shadd16
gkroussos 0:e8fdba0ed044 76 #define __UADD16 __uadd16
gkroussos 0:e8fdba0ed044 77 #define __UQADD16 __uqadd16
gkroussos 0:e8fdba0ed044 78 #define __UHADD16 __uhadd16
gkroussos 0:e8fdba0ed044 79 #define __SSUB16 __ssub16
gkroussos 0:e8fdba0ed044 80 #define __QSUB16 __qsub16
gkroussos 0:e8fdba0ed044 81 #define __SHSUB16 __shsub16
gkroussos 0:e8fdba0ed044 82 #define __USUB16 __usub16
gkroussos 0:e8fdba0ed044 83 #define __UQSUB16 __uqsub16
gkroussos 0:e8fdba0ed044 84 #define __UHSUB16 __uhsub16
gkroussos 0:e8fdba0ed044 85 #define __SASX __sasx
gkroussos 0:e8fdba0ed044 86 #define __QASX __qasx
gkroussos 0:e8fdba0ed044 87 #define __SHASX __shasx
gkroussos 0:e8fdba0ed044 88 #define __UASX __uasx
gkroussos 0:e8fdba0ed044 89 #define __UQASX __uqasx
gkroussos 0:e8fdba0ed044 90 #define __UHASX __uhasx
gkroussos 0:e8fdba0ed044 91 #define __SSAX __ssax
gkroussos 0:e8fdba0ed044 92 #define __QSAX __qsax
gkroussos 0:e8fdba0ed044 93 #define __SHSAX __shsax
gkroussos 0:e8fdba0ed044 94 #define __USAX __usax
gkroussos 0:e8fdba0ed044 95 #define __UQSAX __uqsax
gkroussos 0:e8fdba0ed044 96 #define __UHSAX __uhsax
gkroussos 0:e8fdba0ed044 97 #define __USAD8 __usad8
gkroussos 0:e8fdba0ed044 98 #define __USADA8 __usada8
gkroussos 0:e8fdba0ed044 99 #define __SSAT16 __ssat16
gkroussos 0:e8fdba0ed044 100 #define __USAT16 __usat16
gkroussos 0:e8fdba0ed044 101 #define __UXTB16 __uxtb16
gkroussos 0:e8fdba0ed044 102 #define __UXTAB16 __uxtab16
gkroussos 0:e8fdba0ed044 103 #define __SXTB16 __sxtb16
gkroussos 0:e8fdba0ed044 104 #define __SXTAB16 __sxtab16
gkroussos 0:e8fdba0ed044 105 #define __SMUAD __smuad
gkroussos 0:e8fdba0ed044 106 #define __SMUADX __smuadx
gkroussos 0:e8fdba0ed044 107 #define __SMLAD __smlad
gkroussos 0:e8fdba0ed044 108 #define __SMLADX __smladx
gkroussos 0:e8fdba0ed044 109 #define __SMLALD __smlald
gkroussos 0:e8fdba0ed044 110 #define __SMLALDX __smlaldx
gkroussos 0:e8fdba0ed044 111 #define __SMUSD __smusd
gkroussos 0:e8fdba0ed044 112 #define __SMUSDX __smusdx
gkroussos 0:e8fdba0ed044 113 #define __SMLSD __smlsd
gkroussos 0:e8fdba0ed044 114 #define __SMLSDX __smlsdx
gkroussos 0:e8fdba0ed044 115 #define __SMLSLD __smlsld
gkroussos 0:e8fdba0ed044 116 #define __SMLSLDX __smlsldx
gkroussos 0:e8fdba0ed044 117 #define __SEL __sel
gkroussos 0:e8fdba0ed044 118 #define __QADD __qadd
gkroussos 0:e8fdba0ed044 119 #define __QSUB __qsub
gkroussos 0:e8fdba0ed044 120
gkroussos 0:e8fdba0ed044 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
gkroussos 0:e8fdba0ed044 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
gkroussos 0:e8fdba0ed044 123
gkroussos 0:e8fdba0ed044 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
gkroussos 0:e8fdba0ed044 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
gkroussos 0:e8fdba0ed044 126
gkroussos 0:e8fdba0ed044 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
gkroussos 0:e8fdba0ed044 128 ((int64_t)(ARG3) << 32) ) >> 32))
gkroussos 0:e8fdba0ed044 129
gkroussos 0:e8fdba0ed044 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
gkroussos 0:e8fdba0ed044 131
gkroussos 0:e8fdba0ed044 132
gkroussos 0:e8fdba0ed044 133
gkroussos 0:e8fdba0ed044 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
gkroussos 0:e8fdba0ed044 135 /* IAR iccarm specific functions */
gkroussos 0:e8fdba0ed044 136
gkroussos 0:e8fdba0ed044 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
gkroussos 0:e8fdba0ed044 138 #include <cmsis_iar.h>
gkroussos 0:e8fdba0ed044 139
gkroussos 0:e8fdba0ed044 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
gkroussos 0:e8fdba0ed044 141
gkroussos 0:e8fdba0ed044 142
gkroussos 0:e8fdba0ed044 143
gkroussos 0:e8fdba0ed044 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
gkroussos 0:e8fdba0ed044 145 /* TI CCS specific functions */
gkroussos 0:e8fdba0ed044 146
gkroussos 0:e8fdba0ed044 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
gkroussos 0:e8fdba0ed044 148 #include <cmsis_ccs.h>
gkroussos 0:e8fdba0ed044 149
gkroussos 0:e8fdba0ed044 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
gkroussos 0:e8fdba0ed044 151
gkroussos 0:e8fdba0ed044 152
gkroussos 0:e8fdba0ed044 153
gkroussos 0:e8fdba0ed044 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
gkroussos 0:e8fdba0ed044 155 /* GNU gcc specific functions */
gkroussos 0:e8fdba0ed044 156
gkroussos 0:e8fdba0ed044 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
gkroussos 0:e8fdba0ed044 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 159 {
gkroussos 0:e8fdba0ed044 160 uint32_t result;
gkroussos 0:e8fdba0ed044 161
gkroussos 0:e8fdba0ed044 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 163 return(result);
gkroussos 0:e8fdba0ed044 164 }
gkroussos 0:e8fdba0ed044 165
gkroussos 0:e8fdba0ed044 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 167 {
gkroussos 0:e8fdba0ed044 168 uint32_t result;
gkroussos 0:e8fdba0ed044 169
gkroussos 0:e8fdba0ed044 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 171 return(result);
gkroussos 0:e8fdba0ed044 172 }
gkroussos 0:e8fdba0ed044 173
gkroussos 0:e8fdba0ed044 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 175 {
gkroussos 0:e8fdba0ed044 176 uint32_t result;
gkroussos 0:e8fdba0ed044 177
gkroussos 0:e8fdba0ed044 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 179 return(result);
gkroussos 0:e8fdba0ed044 180 }
gkroussos 0:e8fdba0ed044 181
gkroussos 0:e8fdba0ed044 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 183 {
gkroussos 0:e8fdba0ed044 184 uint32_t result;
gkroussos 0:e8fdba0ed044 185
gkroussos 0:e8fdba0ed044 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 187 return(result);
gkroussos 0:e8fdba0ed044 188 }
gkroussos 0:e8fdba0ed044 189
gkroussos 0:e8fdba0ed044 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 191 {
gkroussos 0:e8fdba0ed044 192 uint32_t result;
gkroussos 0:e8fdba0ed044 193
gkroussos 0:e8fdba0ed044 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 195 return(result);
gkroussos 0:e8fdba0ed044 196 }
gkroussos 0:e8fdba0ed044 197
gkroussos 0:e8fdba0ed044 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 199 {
gkroussos 0:e8fdba0ed044 200 uint32_t result;
gkroussos 0:e8fdba0ed044 201
gkroussos 0:e8fdba0ed044 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 203 return(result);
gkroussos 0:e8fdba0ed044 204 }
gkroussos 0:e8fdba0ed044 205
gkroussos 0:e8fdba0ed044 206
gkroussos 0:e8fdba0ed044 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 208 {
gkroussos 0:e8fdba0ed044 209 uint32_t result;
gkroussos 0:e8fdba0ed044 210
gkroussos 0:e8fdba0ed044 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 212 return(result);
gkroussos 0:e8fdba0ed044 213 }
gkroussos 0:e8fdba0ed044 214
gkroussos 0:e8fdba0ed044 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 216 {
gkroussos 0:e8fdba0ed044 217 uint32_t result;
gkroussos 0:e8fdba0ed044 218
gkroussos 0:e8fdba0ed044 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 220 return(result);
gkroussos 0:e8fdba0ed044 221 }
gkroussos 0:e8fdba0ed044 222
gkroussos 0:e8fdba0ed044 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 224 {
gkroussos 0:e8fdba0ed044 225 uint32_t result;
gkroussos 0:e8fdba0ed044 226
gkroussos 0:e8fdba0ed044 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 228 return(result);
gkroussos 0:e8fdba0ed044 229 }
gkroussos 0:e8fdba0ed044 230
gkroussos 0:e8fdba0ed044 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 232 {
gkroussos 0:e8fdba0ed044 233 uint32_t result;
gkroussos 0:e8fdba0ed044 234
gkroussos 0:e8fdba0ed044 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 236 return(result);
gkroussos 0:e8fdba0ed044 237 }
gkroussos 0:e8fdba0ed044 238
gkroussos 0:e8fdba0ed044 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 240 {
gkroussos 0:e8fdba0ed044 241 uint32_t result;
gkroussos 0:e8fdba0ed044 242
gkroussos 0:e8fdba0ed044 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 244 return(result);
gkroussos 0:e8fdba0ed044 245 }
gkroussos 0:e8fdba0ed044 246
gkroussos 0:e8fdba0ed044 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 248 {
gkroussos 0:e8fdba0ed044 249 uint32_t result;
gkroussos 0:e8fdba0ed044 250
gkroussos 0:e8fdba0ed044 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 252 return(result);
gkroussos 0:e8fdba0ed044 253 }
gkroussos 0:e8fdba0ed044 254
gkroussos 0:e8fdba0ed044 255
gkroussos 0:e8fdba0ed044 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 257 {
gkroussos 0:e8fdba0ed044 258 uint32_t result;
gkroussos 0:e8fdba0ed044 259
gkroussos 0:e8fdba0ed044 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 261 return(result);
gkroussos 0:e8fdba0ed044 262 }
gkroussos 0:e8fdba0ed044 263
gkroussos 0:e8fdba0ed044 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 265 {
gkroussos 0:e8fdba0ed044 266 uint32_t result;
gkroussos 0:e8fdba0ed044 267
gkroussos 0:e8fdba0ed044 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 269 return(result);
gkroussos 0:e8fdba0ed044 270 }
gkroussos 0:e8fdba0ed044 271
gkroussos 0:e8fdba0ed044 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 273 {
gkroussos 0:e8fdba0ed044 274 uint32_t result;
gkroussos 0:e8fdba0ed044 275
gkroussos 0:e8fdba0ed044 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 277 return(result);
gkroussos 0:e8fdba0ed044 278 }
gkroussos 0:e8fdba0ed044 279
gkroussos 0:e8fdba0ed044 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 281 {
gkroussos 0:e8fdba0ed044 282 uint32_t result;
gkroussos 0:e8fdba0ed044 283
gkroussos 0:e8fdba0ed044 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 285 return(result);
gkroussos 0:e8fdba0ed044 286 }
gkroussos 0:e8fdba0ed044 287
gkroussos 0:e8fdba0ed044 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 289 {
gkroussos 0:e8fdba0ed044 290 uint32_t result;
gkroussos 0:e8fdba0ed044 291
gkroussos 0:e8fdba0ed044 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 293 return(result);
gkroussos 0:e8fdba0ed044 294 }
gkroussos 0:e8fdba0ed044 295
gkroussos 0:e8fdba0ed044 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 297 {
gkroussos 0:e8fdba0ed044 298 uint32_t result;
gkroussos 0:e8fdba0ed044 299
gkroussos 0:e8fdba0ed044 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 301 return(result);
gkroussos 0:e8fdba0ed044 302 }
gkroussos 0:e8fdba0ed044 303
gkroussos 0:e8fdba0ed044 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 305 {
gkroussos 0:e8fdba0ed044 306 uint32_t result;
gkroussos 0:e8fdba0ed044 307
gkroussos 0:e8fdba0ed044 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 309 return(result);
gkroussos 0:e8fdba0ed044 310 }
gkroussos 0:e8fdba0ed044 311
gkroussos 0:e8fdba0ed044 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 313 {
gkroussos 0:e8fdba0ed044 314 uint32_t result;
gkroussos 0:e8fdba0ed044 315
gkroussos 0:e8fdba0ed044 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 317 return(result);
gkroussos 0:e8fdba0ed044 318 }
gkroussos 0:e8fdba0ed044 319
gkroussos 0:e8fdba0ed044 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 321 {
gkroussos 0:e8fdba0ed044 322 uint32_t result;
gkroussos 0:e8fdba0ed044 323
gkroussos 0:e8fdba0ed044 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 325 return(result);
gkroussos 0:e8fdba0ed044 326 }
gkroussos 0:e8fdba0ed044 327
gkroussos 0:e8fdba0ed044 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 329 {
gkroussos 0:e8fdba0ed044 330 uint32_t result;
gkroussos 0:e8fdba0ed044 331
gkroussos 0:e8fdba0ed044 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 333 return(result);
gkroussos 0:e8fdba0ed044 334 }
gkroussos 0:e8fdba0ed044 335
gkroussos 0:e8fdba0ed044 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 337 {
gkroussos 0:e8fdba0ed044 338 uint32_t result;
gkroussos 0:e8fdba0ed044 339
gkroussos 0:e8fdba0ed044 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 341 return(result);
gkroussos 0:e8fdba0ed044 342 }
gkroussos 0:e8fdba0ed044 343
gkroussos 0:e8fdba0ed044 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 345 {
gkroussos 0:e8fdba0ed044 346 uint32_t result;
gkroussos 0:e8fdba0ed044 347
gkroussos 0:e8fdba0ed044 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 349 return(result);
gkroussos 0:e8fdba0ed044 350 }
gkroussos 0:e8fdba0ed044 351
gkroussos 0:e8fdba0ed044 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 353 {
gkroussos 0:e8fdba0ed044 354 uint32_t result;
gkroussos 0:e8fdba0ed044 355
gkroussos 0:e8fdba0ed044 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 357 return(result);
gkroussos 0:e8fdba0ed044 358 }
gkroussos 0:e8fdba0ed044 359
gkroussos 0:e8fdba0ed044 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 361 {
gkroussos 0:e8fdba0ed044 362 uint32_t result;
gkroussos 0:e8fdba0ed044 363
gkroussos 0:e8fdba0ed044 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 365 return(result);
gkroussos 0:e8fdba0ed044 366 }
gkroussos 0:e8fdba0ed044 367
gkroussos 0:e8fdba0ed044 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 369 {
gkroussos 0:e8fdba0ed044 370 uint32_t result;
gkroussos 0:e8fdba0ed044 371
gkroussos 0:e8fdba0ed044 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 373 return(result);
gkroussos 0:e8fdba0ed044 374 }
gkroussos 0:e8fdba0ed044 375
gkroussos 0:e8fdba0ed044 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 377 {
gkroussos 0:e8fdba0ed044 378 uint32_t result;
gkroussos 0:e8fdba0ed044 379
gkroussos 0:e8fdba0ed044 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 381 return(result);
gkroussos 0:e8fdba0ed044 382 }
gkroussos 0:e8fdba0ed044 383
gkroussos 0:e8fdba0ed044 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 385 {
gkroussos 0:e8fdba0ed044 386 uint32_t result;
gkroussos 0:e8fdba0ed044 387
gkroussos 0:e8fdba0ed044 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 389 return(result);
gkroussos 0:e8fdba0ed044 390 }
gkroussos 0:e8fdba0ed044 391
gkroussos 0:e8fdba0ed044 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 393 {
gkroussos 0:e8fdba0ed044 394 uint32_t result;
gkroussos 0:e8fdba0ed044 395
gkroussos 0:e8fdba0ed044 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 397 return(result);
gkroussos 0:e8fdba0ed044 398 }
gkroussos 0:e8fdba0ed044 399
gkroussos 0:e8fdba0ed044 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 401 {
gkroussos 0:e8fdba0ed044 402 uint32_t result;
gkroussos 0:e8fdba0ed044 403
gkroussos 0:e8fdba0ed044 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 405 return(result);
gkroussos 0:e8fdba0ed044 406 }
gkroussos 0:e8fdba0ed044 407
gkroussos 0:e8fdba0ed044 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 409 {
gkroussos 0:e8fdba0ed044 410 uint32_t result;
gkroussos 0:e8fdba0ed044 411
gkroussos 0:e8fdba0ed044 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 413 return(result);
gkroussos 0:e8fdba0ed044 414 }
gkroussos 0:e8fdba0ed044 415
gkroussos 0:e8fdba0ed044 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 417 {
gkroussos 0:e8fdba0ed044 418 uint32_t result;
gkroussos 0:e8fdba0ed044 419
gkroussos 0:e8fdba0ed044 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 421 return(result);
gkroussos 0:e8fdba0ed044 422 }
gkroussos 0:e8fdba0ed044 423
gkroussos 0:e8fdba0ed044 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 425 {
gkroussos 0:e8fdba0ed044 426 uint32_t result;
gkroussos 0:e8fdba0ed044 427
gkroussos 0:e8fdba0ed044 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 429 return(result);
gkroussos 0:e8fdba0ed044 430 }
gkroussos 0:e8fdba0ed044 431
gkroussos 0:e8fdba0ed044 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 433 {
gkroussos 0:e8fdba0ed044 434 uint32_t result;
gkroussos 0:e8fdba0ed044 435
gkroussos 0:e8fdba0ed044 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 437 return(result);
gkroussos 0:e8fdba0ed044 438 }
gkroussos 0:e8fdba0ed044 439
gkroussos 0:e8fdba0ed044 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 441 {
gkroussos 0:e8fdba0ed044 442 uint32_t result;
gkroussos 0:e8fdba0ed044 443
gkroussos 0:e8fdba0ed044 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 445 return(result);
gkroussos 0:e8fdba0ed044 446 }
gkroussos 0:e8fdba0ed044 447
gkroussos 0:e8fdba0ed044 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 449 {
gkroussos 0:e8fdba0ed044 450 uint32_t result;
gkroussos 0:e8fdba0ed044 451
gkroussos 0:e8fdba0ed044 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 453 return(result);
gkroussos 0:e8fdba0ed044 454 }
gkroussos 0:e8fdba0ed044 455
gkroussos 0:e8fdba0ed044 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
gkroussos 0:e8fdba0ed044 457 {
gkroussos 0:e8fdba0ed044 458 uint32_t result;
gkroussos 0:e8fdba0ed044 459
gkroussos 0:e8fdba0ed044 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
gkroussos 0:e8fdba0ed044 461 return(result);
gkroussos 0:e8fdba0ed044 462 }
gkroussos 0:e8fdba0ed044 463
gkroussos 0:e8fdba0ed044 464 #define __SSAT16(ARG1,ARG2) \
gkroussos 0:e8fdba0ed044 465 ({ \
gkroussos 0:e8fdba0ed044 466 uint32_t __RES, __ARG1 = (ARG1); \
gkroussos 0:e8fdba0ed044 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
gkroussos 0:e8fdba0ed044 468 __RES; \
gkroussos 0:e8fdba0ed044 469 })
gkroussos 0:e8fdba0ed044 470
gkroussos 0:e8fdba0ed044 471 #define __USAT16(ARG1,ARG2) \
gkroussos 0:e8fdba0ed044 472 ({ \
gkroussos 0:e8fdba0ed044 473 uint32_t __RES, __ARG1 = (ARG1); \
gkroussos 0:e8fdba0ed044 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
gkroussos 0:e8fdba0ed044 475 __RES; \
gkroussos 0:e8fdba0ed044 476 })
gkroussos 0:e8fdba0ed044 477
gkroussos 0:e8fdba0ed044 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
gkroussos 0:e8fdba0ed044 479 {
gkroussos 0:e8fdba0ed044 480 uint32_t result;
gkroussos 0:e8fdba0ed044 481
gkroussos 0:e8fdba0ed044 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
gkroussos 0:e8fdba0ed044 483 return(result);
gkroussos 0:e8fdba0ed044 484 }
gkroussos 0:e8fdba0ed044 485
gkroussos 0:e8fdba0ed044 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 487 {
gkroussos 0:e8fdba0ed044 488 uint32_t result;
gkroussos 0:e8fdba0ed044 489
gkroussos 0:e8fdba0ed044 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 491 return(result);
gkroussos 0:e8fdba0ed044 492 }
gkroussos 0:e8fdba0ed044 493
gkroussos 0:e8fdba0ed044 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
gkroussos 0:e8fdba0ed044 495 {
gkroussos 0:e8fdba0ed044 496 uint32_t result;
gkroussos 0:e8fdba0ed044 497
gkroussos 0:e8fdba0ed044 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
gkroussos 0:e8fdba0ed044 499 return(result);
gkroussos 0:e8fdba0ed044 500 }
gkroussos 0:e8fdba0ed044 501
gkroussos 0:e8fdba0ed044 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 503 {
gkroussos 0:e8fdba0ed044 504 uint32_t result;
gkroussos 0:e8fdba0ed044 505
gkroussos 0:e8fdba0ed044 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 507 return(result);
gkroussos 0:e8fdba0ed044 508 }
gkroussos 0:e8fdba0ed044 509
gkroussos 0:e8fdba0ed044 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 511 {
gkroussos 0:e8fdba0ed044 512 uint32_t result;
gkroussos 0:e8fdba0ed044 513
gkroussos 0:e8fdba0ed044 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 515 return(result);
gkroussos 0:e8fdba0ed044 516 }
gkroussos 0:e8fdba0ed044 517
gkroussos 0:e8fdba0ed044 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 519 {
gkroussos 0:e8fdba0ed044 520 uint32_t result;
gkroussos 0:e8fdba0ed044 521
gkroussos 0:e8fdba0ed044 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 523 return(result);
gkroussos 0:e8fdba0ed044 524 }
gkroussos 0:e8fdba0ed044 525
gkroussos 0:e8fdba0ed044 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
gkroussos 0:e8fdba0ed044 527 {
gkroussos 0:e8fdba0ed044 528 uint32_t result;
gkroussos 0:e8fdba0ed044 529
gkroussos 0:e8fdba0ed044 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
gkroussos 0:e8fdba0ed044 531 return(result);
gkroussos 0:e8fdba0ed044 532 }
gkroussos 0:e8fdba0ed044 533
gkroussos 0:e8fdba0ed044 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
gkroussos 0:e8fdba0ed044 535 {
gkroussos 0:e8fdba0ed044 536 uint32_t result;
gkroussos 0:e8fdba0ed044 537
gkroussos 0:e8fdba0ed044 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
gkroussos 0:e8fdba0ed044 539 return(result);
gkroussos 0:e8fdba0ed044 540 }
gkroussos 0:e8fdba0ed044 541
gkroussos 0:e8fdba0ed044 542 #define __SMLALD(ARG1,ARG2,ARG3) \
gkroussos 0:e8fdba0ed044 543 ({ \
gkroussos 0:e8fdba0ed044 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
gkroussos 0:e8fdba0ed044 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
gkroussos 0:e8fdba0ed044 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
gkroussos 0:e8fdba0ed044 547 })
gkroussos 0:e8fdba0ed044 548
gkroussos 0:e8fdba0ed044 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
gkroussos 0:e8fdba0ed044 550 ({ \
gkroussos 0:e8fdba0ed044 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
gkroussos 0:e8fdba0ed044 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
gkroussos 0:e8fdba0ed044 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
gkroussos 0:e8fdba0ed044 554 })
gkroussos 0:e8fdba0ed044 555
gkroussos 0:e8fdba0ed044 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 557 {
gkroussos 0:e8fdba0ed044 558 uint32_t result;
gkroussos 0:e8fdba0ed044 559
gkroussos 0:e8fdba0ed044 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 561 return(result);
gkroussos 0:e8fdba0ed044 562 }
gkroussos 0:e8fdba0ed044 563
gkroussos 0:e8fdba0ed044 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 565 {
gkroussos 0:e8fdba0ed044 566 uint32_t result;
gkroussos 0:e8fdba0ed044 567
gkroussos 0:e8fdba0ed044 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 569 return(result);
gkroussos 0:e8fdba0ed044 570 }
gkroussos 0:e8fdba0ed044 571
gkroussos 0:e8fdba0ed044 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
gkroussos 0:e8fdba0ed044 573 {
gkroussos 0:e8fdba0ed044 574 uint32_t result;
gkroussos 0:e8fdba0ed044 575
gkroussos 0:e8fdba0ed044 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
gkroussos 0:e8fdba0ed044 577 return(result);
gkroussos 0:e8fdba0ed044 578 }
gkroussos 0:e8fdba0ed044 579
gkroussos 0:e8fdba0ed044 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
gkroussos 0:e8fdba0ed044 581 {
gkroussos 0:e8fdba0ed044 582 uint32_t result;
gkroussos 0:e8fdba0ed044 583
gkroussos 0:e8fdba0ed044 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
gkroussos 0:e8fdba0ed044 585 return(result);
gkroussos 0:e8fdba0ed044 586 }
gkroussos 0:e8fdba0ed044 587
gkroussos 0:e8fdba0ed044 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
gkroussos 0:e8fdba0ed044 589 ({ \
gkroussos 0:e8fdba0ed044 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
gkroussos 0:e8fdba0ed044 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
gkroussos 0:e8fdba0ed044 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
gkroussos 0:e8fdba0ed044 593 })
gkroussos 0:e8fdba0ed044 594
gkroussos 0:e8fdba0ed044 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
gkroussos 0:e8fdba0ed044 596 ({ \
gkroussos 0:e8fdba0ed044 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
gkroussos 0:e8fdba0ed044 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
gkroussos 0:e8fdba0ed044 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
gkroussos 0:e8fdba0ed044 600 })
gkroussos 0:e8fdba0ed044 601
gkroussos 0:e8fdba0ed044 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 603 {
gkroussos 0:e8fdba0ed044 604 uint32_t result;
gkroussos 0:e8fdba0ed044 605
gkroussos 0:e8fdba0ed044 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 607 return(result);
gkroussos 0:e8fdba0ed044 608 }
gkroussos 0:e8fdba0ed044 609
gkroussos 0:e8fdba0ed044 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 611 {
gkroussos 0:e8fdba0ed044 612 uint32_t result;
gkroussos 0:e8fdba0ed044 613
gkroussos 0:e8fdba0ed044 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 615 return(result);
gkroussos 0:e8fdba0ed044 616 }
gkroussos 0:e8fdba0ed044 617
gkroussos 0:e8fdba0ed044 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
gkroussos 0:e8fdba0ed044 619 {
gkroussos 0:e8fdba0ed044 620 uint32_t result;
gkroussos 0:e8fdba0ed044 621
gkroussos 0:e8fdba0ed044 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:e8fdba0ed044 623 return(result);
gkroussos 0:e8fdba0ed044 624 }
gkroussos 0:e8fdba0ed044 625
gkroussos 0:e8fdba0ed044 626 #define __PKHBT(ARG1,ARG2,ARG3) \
gkroussos 0:e8fdba0ed044 627 ({ \
gkroussos 0:e8fdba0ed044 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
gkroussos 0:e8fdba0ed044 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
gkroussos 0:e8fdba0ed044 630 __RES; \
gkroussos 0:e8fdba0ed044 631 })
gkroussos 0:e8fdba0ed044 632
gkroussos 0:e8fdba0ed044 633 #define __PKHTB(ARG1,ARG2,ARG3) \
gkroussos 0:e8fdba0ed044 634 ({ \
gkroussos 0:e8fdba0ed044 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
gkroussos 0:e8fdba0ed044 636 if (ARG3 == 0) \
gkroussos 0:e8fdba0ed044 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
gkroussos 0:e8fdba0ed044 638 else \
gkroussos 0:e8fdba0ed044 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
gkroussos 0:e8fdba0ed044 640 __RES; \
gkroussos 0:e8fdba0ed044 641 })
gkroussos 0:e8fdba0ed044 642
gkroussos 0:e8fdba0ed044 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
gkroussos 0:e8fdba0ed044 644 {
gkroussos 0:e8fdba0ed044 645 int32_t result;
gkroussos 0:e8fdba0ed044 646
gkroussos 0:e8fdba0ed044 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
gkroussos 0:e8fdba0ed044 648 return(result);
gkroussos 0:e8fdba0ed044 649 }
gkroussos 0:e8fdba0ed044 650
gkroussos 0:e8fdba0ed044 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
gkroussos 0:e8fdba0ed044 652
gkroussos 0:e8fdba0ed044 653
gkroussos 0:e8fdba0ed044 654
gkroussos 0:e8fdba0ed044 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
gkroussos 0:e8fdba0ed044 656 /* TASKING carm specific functions */
gkroussos 0:e8fdba0ed044 657
gkroussos 0:e8fdba0ed044 658
gkroussos 0:e8fdba0ed044 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
gkroussos 0:e8fdba0ed044 660 /* not yet supported */
gkroussos 0:e8fdba0ed044 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
gkroussos 0:e8fdba0ed044 662
gkroussos 0:e8fdba0ed044 663
gkroussos 0:e8fdba0ed044 664 #endif
gkroussos 0:e8fdba0ed044 665
gkroussos 0:e8fdba0ed044 666 /*@} end of group CMSIS_SIMD_intrinsics */
gkroussos 0:e8fdba0ed044 667
gkroussos 0:e8fdba0ed044 668
gkroussos 0:e8fdba0ed044 669 #endif /* __CORE_CM4_SIMD_H */
gkroussos 0:e8fdba0ed044 670
gkroussos 0:e8fdba0ed044 671 #ifdef __cplusplus
gkroussos 0:e8fdba0ed044 672 }
gkroussos 0:e8fdba0ed044 673 #endif