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Birkbeck College Mobile and Ubiquitous Computing IoT Lab Exercise 2

mbed/TARGET_NRF51822/core_cm3.h@0:e8fdba0ed044, 2015-03-07 (annotated)

Committer:: gkroussos
Date:: Sat Mar 07 16:34:53 2015 +0000
Revision:: 0:e8fdba0ed044

MUC IoT Workshop v1.0

Who changed what in which revision?

User	Revision	Line number	New contents of line
gkroussos	0:e8fdba0ed044	1	/************************************************************************//
gkroussos	0:e8fdba0ed044	2	* @file core_cm3.h
gkroussos	0:e8fdba0ed044	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
gkroussos	0:e8fdba0ed044	4	* @version V3.20
gkroussos	0:e8fdba0ed044	5	* @date 25. February 2013
gkroussos	0:e8fdba0ed044	6	*
gkroussos	0:e8fdba0ed044	7	* @note
gkroussos	0:e8fdba0ed044	8	*
gkroussos	0:e8fdba0ed044	9	******************************************************************************/
gkroussos	0:e8fdba0ed044	10	/* Copyright (c) 2009 - 2013 ARM LIMITED
gkroussos	0:e8fdba0ed044	11
gkroussos	0:e8fdba0ed044	12	All rights reserved.
gkroussos	0:e8fdba0ed044	13	Redistribution and use in source and binary forms, with or without
gkroussos	0:e8fdba0ed044	14	modification, are permitted provided that the following conditions are met:
gkroussos	0:e8fdba0ed044	15	- Redistributions of source code must retain the above copyright
gkroussos	0:e8fdba0ed044	16	notice, this list of conditions and the following disclaimer.
gkroussos	0:e8fdba0ed044	17	- Redistributions in binary form must reproduce the above copyright
gkroussos	0:e8fdba0ed044	18	notice, this list of conditions and the following disclaimer in the
gkroussos	0:e8fdba0ed044	19	documentation and/or other materials provided with the distribution.
gkroussos	0:e8fdba0ed044	20	- Neither the name of ARM nor the names of its contributors may be used
gkroussos	0:e8fdba0ed044	21	to endorse or promote products derived from this software without
gkroussos	0:e8fdba0ed044	22	specific prior written permission.
gkroussos	0:e8fdba0ed044	23	*
gkroussos	0:e8fdba0ed044	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
gkroussos	0:e8fdba0ed044	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
gkroussos	0:e8fdba0ed044	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
gkroussos	0:e8fdba0ed044	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
gkroussos	0:e8fdba0ed044	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
gkroussos	0:e8fdba0ed044	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
gkroussos	0:e8fdba0ed044	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
gkroussos	0:e8fdba0ed044	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
gkroussos	0:e8fdba0ed044	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
gkroussos	0:e8fdba0ed044	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
gkroussos	0:e8fdba0ed044	34	POSSIBILITY OF SUCH DAMAGE.
gkroussos	0:e8fdba0ed044	35	---------------------------------------------------------------------------*/
gkroussos	0:e8fdba0ed044	36
gkroussos	0:e8fdba0ed044	37
gkroussos	0:e8fdba0ed044	38	#if defined ( __ICCARM__ )
gkroussos	0:e8fdba0ed044	39	#pragma system_include /* treat file as system include file for MISRA check */
gkroussos	0:e8fdba0ed044	40	#endif
gkroussos	0:e8fdba0ed044	41
gkroussos	0:e8fdba0ed044	42	#ifdef __cplusplus
gkroussos	0:e8fdba0ed044	43	extern "C" {
gkroussos	0:e8fdba0ed044	44	#endif
gkroussos	0:e8fdba0ed044	45
gkroussos	0:e8fdba0ed044	46	#ifndef __CORE_CM3_H_GENERIC
gkroussos	0:e8fdba0ed044	47	#define __CORE_CM3_H_GENERIC
gkroussos	0:e8fdba0ed044	48
gkroussos	0:e8fdba0ed044	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
gkroussos	0:e8fdba0ed044	50	CMSIS violates the following MISRA-C:2004 rules:
gkroussos	0:e8fdba0ed044	51
gkroussos	0:e8fdba0ed044	52	\li Required Rule 8.5, object/function definition in header file.<br>
gkroussos	0:e8fdba0ed044	53	Function definitions in header files are used to allow 'inlining'.
gkroussos	0:e8fdba0ed044	54
gkroussos	0:e8fdba0ed044	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
gkroussos	0:e8fdba0ed044	56	Unions are used for effective representation of core registers.
gkroussos	0:e8fdba0ed044	57
gkroussos	0:e8fdba0ed044	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
gkroussos	0:e8fdba0ed044	59	Function-like macros are used to allow more efficient code.
gkroussos	0:e8fdba0ed044	60	*/
gkroussos	0:e8fdba0ed044	61
gkroussos	0:e8fdba0ed044	62
gkroussos	0:e8fdba0ed044	63	/*******************************************************************************
gkroussos	0:e8fdba0ed044	64	* CMSIS definitions
gkroussos	0:e8fdba0ed044	65	******************************************************************************/
gkroussos	0:e8fdba0ed044	66	/** \ingroup Cortex_M3
gkroussos	0:e8fdba0ed044	67	@{
gkroussos	0:e8fdba0ed044	68	*/
gkroussos	0:e8fdba0ed044	69
gkroussos	0:e8fdba0ed044	70	/* CMSIS CM3 definitions */
gkroussos	0:e8fdba0ed044	71	#define __CM3_CMSIS_VERSION_MAIN (0x03) /!< [31:16] CMSIS HAL main version /
gkroussos	0:e8fdba0ed044	72	#define __CM3_CMSIS_VERSION_SUB (0x20) /!< [15:0] CMSIS HAL sub version /
gkroussos	0:e8fdba0ed044	73	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| \
gkroussos	0:e8fdba0ed044	74	__CM3_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
gkroussos	0:e8fdba0ed044	75
gkroussos	0:e8fdba0ed044	76	#define __CORTEX_M (0x03) /!< Cortex-M Core /
gkroussos	0:e8fdba0ed044	77
gkroussos	0:e8fdba0ed044	78
gkroussos	0:e8fdba0ed044	79	#if defined ( __CC_ARM )
gkroussos	0:e8fdba0ed044	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
gkroussos	0:e8fdba0ed044	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
gkroussos	0:e8fdba0ed044	82	#define __STATIC_INLINE static __inline
gkroussos	0:e8fdba0ed044	83
gkroussos	0:e8fdba0ed044	84	#elif defined ( __ICCARM__ )
gkroussos	0:e8fdba0ed044	85	#define __ASM __asm /!< asm keyword for IAR Compiler /
gkroussos	0:e8fdba0ed044	86	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
gkroussos	0:e8fdba0ed044	87	#define __STATIC_INLINE static inline
gkroussos	0:e8fdba0ed044	88
gkroussos	0:e8fdba0ed044	89	#elif defined ( __TMS470__ )
gkroussos	0:e8fdba0ed044	90	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
gkroussos	0:e8fdba0ed044	91	#define __STATIC_INLINE static inline
gkroussos	0:e8fdba0ed044	92
gkroussos	0:e8fdba0ed044	93	#elif defined ( __GNUC__ )
gkroussos	0:e8fdba0ed044	94	#define __ASM __asm /!< asm keyword for GNU Compiler /
gkroussos	0:e8fdba0ed044	95	#define __INLINE inline /!< inline keyword for GNU Compiler /
gkroussos	0:e8fdba0ed044	96	#define __STATIC_INLINE static inline
gkroussos	0:e8fdba0ed044	97
gkroussos	0:e8fdba0ed044	98	#elif defined ( __TASKING__ )
gkroussos	0:e8fdba0ed044	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
gkroussos	0:e8fdba0ed044	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
gkroussos	0:e8fdba0ed044	101	#define __STATIC_INLINE static inline
gkroussos	0:e8fdba0ed044	102
gkroussos	0:e8fdba0ed044	103	#endif
gkroussos	0:e8fdba0ed044	104
gkroussos	0:e8fdba0ed044	105	/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
gkroussos	0:e8fdba0ed044	106	*/
gkroussos	0:e8fdba0ed044	107	#define __FPU_USED 0
gkroussos	0:e8fdba0ed044	108
gkroussos	0:e8fdba0ed044	109	#if defined ( __CC_ARM )
gkroussos	0:e8fdba0ed044	110	#if defined __TARGET_FPU_VFP
gkroussos	0:e8fdba0ed044	111	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gkroussos	0:e8fdba0ed044	112	#endif
gkroussos	0:e8fdba0ed044	113
gkroussos	0:e8fdba0ed044	114	#elif defined ( __ICCARM__ )
gkroussos	0:e8fdba0ed044	115	#if defined __ARMVFP__
gkroussos	0:e8fdba0ed044	116	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gkroussos	0:e8fdba0ed044	117	#endif
gkroussos	0:e8fdba0ed044	118
gkroussos	0:e8fdba0ed044	119	#elif defined ( __TMS470__ )
gkroussos	0:e8fdba0ed044	120	#if defined __TI__VFP_SUPPORT____
gkroussos	0:e8fdba0ed044	121	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gkroussos	0:e8fdba0ed044	122	#endif
gkroussos	0:e8fdba0ed044	123
gkroussos	0:e8fdba0ed044	124	#elif defined ( __GNUC__ )
gkroussos	0:e8fdba0ed044	125	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
gkroussos	0:e8fdba0ed044	126	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gkroussos	0:e8fdba0ed044	127	#endif
gkroussos	0:e8fdba0ed044	128
gkroussos	0:e8fdba0ed044	129	#elif defined ( __TASKING__ )
gkroussos	0:e8fdba0ed044	130	#if defined __FPU_VFP__
gkroussos	0:e8fdba0ed044	131	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gkroussos	0:e8fdba0ed044	132	#endif
gkroussos	0:e8fdba0ed044	133	#endif
gkroussos	0:e8fdba0ed044	134
gkroussos	0:e8fdba0ed044	135	#include <stdint.h> /* standard types definitions */
gkroussos	0:e8fdba0ed044	136	#include <core_cmInstr.h> /* Core Instruction Access */
gkroussos	0:e8fdba0ed044	137	#include <core_cmFunc.h> /* Core Function Access */
gkroussos	0:e8fdba0ed044	138
gkroussos	0:e8fdba0ed044	139	#endif /* __CORE_CM3_H_GENERIC */
gkroussos	0:e8fdba0ed044	140
gkroussos	0:e8fdba0ed044	141	#ifndef __CMSIS_GENERIC
gkroussos	0:e8fdba0ed044	142
gkroussos	0:e8fdba0ed044	143	#ifndef __CORE_CM3_H_DEPENDANT
gkroussos	0:e8fdba0ed044	144	#define __CORE_CM3_H_DEPENDANT
gkroussos	0:e8fdba0ed044	145
gkroussos	0:e8fdba0ed044	146	/* check device defines and use defaults */
gkroussos	0:e8fdba0ed044	147	#if defined __CHECK_DEVICE_DEFINES
gkroussos	0:e8fdba0ed044	148	#ifndef __CM3_REV
gkroussos	0:e8fdba0ed044	149	#define __CM3_REV 0x0200
gkroussos	0:e8fdba0ed044	150	#warning "__CM3_REV not defined in device header file; using default!"
gkroussos	0:e8fdba0ed044	151	#endif
gkroussos	0:e8fdba0ed044	152
gkroussos	0:e8fdba0ed044	153	#ifndef __MPU_PRESENT
gkroussos	0:e8fdba0ed044	154	#define __MPU_PRESENT 0
gkroussos	0:e8fdba0ed044	155	#warning "__MPU_PRESENT not defined in device header file; using default!"
gkroussos	0:e8fdba0ed044	156	#endif
gkroussos	0:e8fdba0ed044	157
gkroussos	0:e8fdba0ed044	158	#ifndef __NVIC_PRIO_BITS
gkroussos	0:e8fdba0ed044	159	#define __NVIC_PRIO_BITS 4
gkroussos	0:e8fdba0ed044	160	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
gkroussos	0:e8fdba0ed044	161	#endif
gkroussos	0:e8fdba0ed044	162
gkroussos	0:e8fdba0ed044	163	#ifndef __Vendor_SysTickConfig
gkroussos	0:e8fdba0ed044	164	#define __Vendor_SysTickConfig 0
gkroussos	0:e8fdba0ed044	165	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
gkroussos	0:e8fdba0ed044	166	#endif
gkroussos	0:e8fdba0ed044	167	#endif
gkroussos	0:e8fdba0ed044	168
gkroussos	0:e8fdba0ed044	169	/* IO definitions (access restrictions to peripheral registers) */
gkroussos	0:e8fdba0ed044	170	/**
gkroussos	0:e8fdba0ed044	171	\defgroup CMSIS_glob_defs CMSIS Global Defines
gkroussos	0:e8fdba0ed044	172
gkroussos	0:e8fdba0ed044	173	<strong>IO Type Qualifiers</strong> are used
gkroussos	0:e8fdba0ed044	174	\li to specify the access to peripheral variables.
gkroussos	0:e8fdba0ed044	175	\li for automatic generation of peripheral register debug information.
gkroussos	0:e8fdba0ed044	176	*/
gkroussos	0:e8fdba0ed044	177	#ifdef __cplusplus
gkroussos	0:e8fdba0ed044	178	#define __I volatile /!< Defines 'read only' permissions /
gkroussos	0:e8fdba0ed044	179	#else
gkroussos	0:e8fdba0ed044	180	#define __I volatile const /!< Defines 'read only' permissions /
gkroussos	0:e8fdba0ed044	181	#endif
gkroussos	0:e8fdba0ed044	182	#define __O volatile /!< Defines 'write only' permissions /
gkroussos	0:e8fdba0ed044	183	#define __IO volatile /!< Defines 'read / write' permissions /
gkroussos	0:e8fdba0ed044	184
gkroussos	0:e8fdba0ed044	185	/@} end of group Cortex_M3 /
gkroussos	0:e8fdba0ed044	186
gkroussos	0:e8fdba0ed044	187
gkroussos	0:e8fdba0ed044	188
gkroussos	0:e8fdba0ed044	189	/*******************************************************************************
gkroussos	0:e8fdba0ed044	190	* Register Abstraction
gkroussos	0:e8fdba0ed044	191	Core Register contain:
gkroussos	0:e8fdba0ed044	192	- Core Register
gkroussos	0:e8fdba0ed044	193	- Core NVIC Register
gkroussos	0:e8fdba0ed044	194	- Core SCB Register
gkroussos	0:e8fdba0ed044	195	- Core SysTick Register
gkroussos	0:e8fdba0ed044	196	- Core Debug Register
gkroussos	0:e8fdba0ed044	197	- Core MPU Register
gkroussos	0:e8fdba0ed044	198	******************************************************************************/
gkroussos	0:e8fdba0ed044	199	/** \defgroup CMSIS_core_register Defines and Type Definitions
gkroussos	0:e8fdba0ed044	200	\brief Type definitions and defines for Cortex-M processor based devices.
gkroussos	0:e8fdba0ed044	201	*/
gkroussos	0:e8fdba0ed044	202
gkroussos	0:e8fdba0ed044	203	/** \ingroup CMSIS_core_register
gkroussos	0:e8fdba0ed044	204	\defgroup CMSIS_CORE Status and Control Registers
gkroussos	0:e8fdba0ed044	205	\brief Core Register type definitions.
gkroussos	0:e8fdba0ed044	206	@{
gkroussos	0:e8fdba0ed044	207	*/
gkroussos	0:e8fdba0ed044	208
gkroussos	0:e8fdba0ed044	209	/** \brief Union type to access the Application Program Status Register (APSR).
gkroussos	0:e8fdba0ed044	210	*/
gkroussos	0:e8fdba0ed044	211	typedef union
gkroussos	0:e8fdba0ed044	212	{
gkroussos	0:e8fdba0ed044	213	struct
gkroussos	0:e8fdba0ed044	214	{
gkroussos	0:e8fdba0ed044	215	#if (__CORTEX_M != 0x04)
gkroussos	0:e8fdba0ed044	216	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
gkroussos	0:e8fdba0ed044	217	#else
gkroussos	0:e8fdba0ed044	218	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
gkroussos	0:e8fdba0ed044	219	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
gkroussos	0:e8fdba0ed044	220	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
gkroussos	0:e8fdba0ed044	221	#endif
gkroussos	0:e8fdba0ed044	222	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
gkroussos	0:e8fdba0ed044	223	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
gkroussos	0:e8fdba0ed044	224	uint32_t C:1; /!< bit: 29 Carry condition code flag /
gkroussos	0:e8fdba0ed044	225	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
gkroussos	0:e8fdba0ed044	226	uint32_t N:1; /!< bit: 31 Negative condition code flag /
gkroussos	0:e8fdba0ed044	227	} b; /!< Structure used for bit access /
gkroussos	0:e8fdba0ed044	228	uint32_t w; /!< Type used for word access /
gkroussos	0:e8fdba0ed044	229	} APSR_Type;
gkroussos	0:e8fdba0ed044	230
gkroussos	0:e8fdba0ed044	231
gkroussos	0:e8fdba0ed044	232	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
gkroussos	0:e8fdba0ed044	233	*/
gkroussos	0:e8fdba0ed044	234	typedef union
gkroussos	0:e8fdba0ed044	235	{
gkroussos	0:e8fdba0ed044	236	struct
gkroussos	0:e8fdba0ed044	237	{
gkroussos	0:e8fdba0ed044	238	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
gkroussos	0:e8fdba0ed044	239	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
gkroussos	0:e8fdba0ed044	240	} b; /!< Structure used for bit access /
gkroussos	0:e8fdba0ed044	241	uint32_t w; /!< Type used for word access /
gkroussos	0:e8fdba0ed044	242	} IPSR_Type;
gkroussos	0:e8fdba0ed044	243
gkroussos	0:e8fdba0ed044	244
gkroussos	0:e8fdba0ed044	245	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
gkroussos	0:e8fdba0ed044	246	*/
gkroussos	0:e8fdba0ed044	247	typedef union
gkroussos	0:e8fdba0ed044	248	{
gkroussos	0:e8fdba0ed044	249	struct
gkroussos	0:e8fdba0ed044	250	{
gkroussos	0:e8fdba0ed044	251	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
gkroussos	0:e8fdba0ed044	252	#if (__CORTEX_M != 0x04)
gkroussos	0:e8fdba0ed044	253	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
gkroussos	0:e8fdba0ed044	254	#else
gkroussos	0:e8fdba0ed044	255	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
gkroussos	0:e8fdba0ed044	256	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
gkroussos	0:e8fdba0ed044	257	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
gkroussos	0:e8fdba0ed044	258	#endif
gkroussos	0:e8fdba0ed044	259	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
gkroussos	0:e8fdba0ed044	260	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
gkroussos	0:e8fdba0ed044	261	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
gkroussos	0:e8fdba0ed044	262	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
gkroussos	0:e8fdba0ed044	263	uint32_t C:1; /!< bit: 29 Carry condition code flag /
gkroussos	0:e8fdba0ed044	264	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
gkroussos	0:e8fdba0ed044	265	uint32_t N:1; /!< bit: 31 Negative condition code flag /
gkroussos	0:e8fdba0ed044	266	} b; /!< Structure used for bit access /
gkroussos	0:e8fdba0ed044	267	uint32_t w; /!< Type used for word access /
gkroussos	0:e8fdba0ed044	268	} xPSR_Type;
gkroussos	0:e8fdba0ed044	269
gkroussos	0:e8fdba0ed044	270
gkroussos	0:e8fdba0ed044	271	/** \brief Union type to access the Control Registers (CONTROL).
gkroussos	0:e8fdba0ed044	272	*/
gkroussos	0:e8fdba0ed044	273	typedef union
gkroussos	0:e8fdba0ed044	274	{
gkroussos	0:e8fdba0ed044	275	struct
gkroussos	0:e8fdba0ed044	276	{
gkroussos	0:e8fdba0ed044	277	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
gkroussos	0:e8fdba0ed044	278	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
gkroussos	0:e8fdba0ed044	279	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
gkroussos	0:e8fdba0ed044	280	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
gkroussos	0:e8fdba0ed044	281	} b; /!< Structure used for bit access /
gkroussos	0:e8fdba0ed044	282	uint32_t w; /!< Type used for word access /
gkroussos	0:e8fdba0ed044	283	} CONTROL_Type;
gkroussos	0:e8fdba0ed044	284
gkroussos	0:e8fdba0ed044	285	/@} end of group CMSIS_CORE /
gkroussos	0:e8fdba0ed044	286
gkroussos	0:e8fdba0ed044	287
gkroussos	0:e8fdba0ed044	288	/** \ingroup CMSIS_core_register
gkroussos	0:e8fdba0ed044	289	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
gkroussos	0:e8fdba0ed044	290	\brief Type definitions for the NVIC Registers
gkroussos	0:e8fdba0ed044	291	@{
gkroussos	0:e8fdba0ed044	292	*/
gkroussos	0:e8fdba0ed044	293
gkroussos	0:e8fdba0ed044	294	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
gkroussos	0:e8fdba0ed044	295	*/
gkroussos	0:e8fdba0ed044	296	typedef struct
gkroussos	0:e8fdba0ed044	297	{
gkroussos	0:e8fdba0ed044	298	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
gkroussos	0:e8fdba0ed044	299	uint32_t RESERVED0[24];
gkroussos	0:e8fdba0ed044	300	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
gkroussos	0:e8fdba0ed044	301	uint32_t RSERVED1[24];
gkroussos	0:e8fdba0ed044	302	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
gkroussos	0:e8fdba0ed044	303	uint32_t RESERVED2[24];
gkroussos	0:e8fdba0ed044	304	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
gkroussos	0:e8fdba0ed044	305	uint32_t RESERVED3[24];
gkroussos	0:e8fdba0ed044	306	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
gkroussos	0:e8fdba0ed044	307	uint32_t RESERVED4[56];
gkroussos	0:e8fdba0ed044	308	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
gkroussos	0:e8fdba0ed044	309	uint32_t RESERVED5[644];
gkroussos	0:e8fdba0ed044	310	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
gkroussos	0:e8fdba0ed044	311	} NVIC_Type;
gkroussos	0:e8fdba0ed044	312
gkroussos	0:e8fdba0ed044	313	/* Software Triggered Interrupt Register Definitions */
gkroussos	0:e8fdba0ed044	314	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
gkroussos	0:e8fdba0ed044	315	#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /!< STIR: INTLINESNUM Mask /
gkroussos	0:e8fdba0ed044	316
gkroussos	0:e8fdba0ed044	317	/@} end of group CMSIS_NVIC /
gkroussos	0:e8fdba0ed044	318
gkroussos	0:e8fdba0ed044	319
gkroussos	0:e8fdba0ed044	320	/** \ingroup CMSIS_core_register
gkroussos	0:e8fdba0ed044	321	\defgroup CMSIS_SCB System Control Block (SCB)
gkroussos	0:e8fdba0ed044	322	\brief Type definitions for the System Control Block Registers
gkroussos	0:e8fdba0ed044	323	@{
gkroussos	0:e8fdba0ed044	324	*/
gkroussos	0:e8fdba0ed044	325
gkroussos	0:e8fdba0ed044	326	/** \brief Structure type to access the System Control Block (SCB).
gkroussos	0:e8fdba0ed044	327	*/
gkroussos	0:e8fdba0ed044	328	typedef struct
gkroussos	0:e8fdba0ed044	329	{
gkroussos	0:e8fdba0ed044	330	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
gkroussos	0:e8fdba0ed044	331	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
gkroussos	0:e8fdba0ed044	332	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
gkroussos	0:e8fdba0ed044	333	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
gkroussos	0:e8fdba0ed044	334	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
gkroussos	0:e8fdba0ed044	335	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
gkroussos	0:e8fdba0ed044	336	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
gkroussos	0:e8fdba0ed044	337	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
gkroussos	0:e8fdba0ed044	338	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
gkroussos	0:e8fdba0ed044	339	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
gkroussos	0:e8fdba0ed044	340	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
gkroussos	0:e8fdba0ed044	341	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
gkroussos	0:e8fdba0ed044	342	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
gkroussos	0:e8fdba0ed044	343	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
gkroussos	0:e8fdba0ed044	344	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
gkroussos	0:e8fdba0ed044	345	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
gkroussos	0:e8fdba0ed044	346	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
gkroussos	0:e8fdba0ed044	347	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
gkroussos	0:e8fdba0ed044	348	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
gkroussos	0:e8fdba0ed044	349	uint32_t RESERVED0[5];
gkroussos	0:e8fdba0ed044	350	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
gkroussos	0:e8fdba0ed044	351	} SCB_Type;
gkroussos	0:e8fdba0ed044	352
gkroussos	0:e8fdba0ed044	353	/* SCB CPUID Register Definitions */
gkroussos	0:e8fdba0ed044	354	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
gkroussos	0:e8fdba0ed044	355	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
gkroussos	0:e8fdba0ed044	356
gkroussos	0:e8fdba0ed044	357	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
gkroussos	0:e8fdba0ed044	358	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
gkroussos	0:e8fdba0ed044	359
gkroussos	0:e8fdba0ed044	360	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
gkroussos	0:e8fdba0ed044	361	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
gkroussos	0:e8fdba0ed044	362
gkroussos	0:e8fdba0ed044	363	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
gkroussos	0:e8fdba0ed044	364	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
gkroussos	0:e8fdba0ed044	365
gkroussos	0:e8fdba0ed044	366	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
gkroussos	0:e8fdba0ed044	367	#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /!< SCB CPUID: REVISION Mask /
gkroussos	0:e8fdba0ed044	368
gkroussos	0:e8fdba0ed044	369	/* SCB Interrupt Control State Register Definitions */
gkroussos	0:e8fdba0ed044	370	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
gkroussos	0:e8fdba0ed044	371	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
gkroussos	0:e8fdba0ed044	372
gkroussos	0:e8fdba0ed044	373	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
gkroussos	0:e8fdba0ed044	374	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
gkroussos	0:e8fdba0ed044	375
gkroussos	0:e8fdba0ed044	376	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
gkroussos	0:e8fdba0ed044	377	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
gkroussos	0:e8fdba0ed044	378
gkroussos	0:e8fdba0ed044	379	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
gkroussos	0:e8fdba0ed044	380	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
gkroussos	0:e8fdba0ed044	381
gkroussos	0:e8fdba0ed044	382	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
gkroussos	0:e8fdba0ed044	383	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
gkroussos	0:e8fdba0ed044	384
gkroussos	0:e8fdba0ed044	385	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
gkroussos	0:e8fdba0ed044	386	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
gkroussos	0:e8fdba0ed044	387
gkroussos	0:e8fdba0ed044	388	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
gkroussos	0:e8fdba0ed044	389	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
gkroussos	0:e8fdba0ed044	390
gkroussos	0:e8fdba0ed044	391	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
gkroussos	0:e8fdba0ed044	392	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
gkroussos	0:e8fdba0ed044	393
gkroussos	0:e8fdba0ed044	394	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
gkroussos	0:e8fdba0ed044	395	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
gkroussos	0:e8fdba0ed044	396
gkroussos	0:e8fdba0ed044	397	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
gkroussos	0:e8fdba0ed044	398	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /!< SCB ICSR: VECTACTIVE Mask /
gkroussos	0:e8fdba0ed044	399
gkroussos	0:e8fdba0ed044	400	/* SCB Vector Table Offset Register Definitions */
gkroussos	0:e8fdba0ed044	401	#if (__CM3_REV < 0x0201) /* core r2p1 */
gkroussos	0:e8fdba0ed044	402	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
gkroussos	0:e8fdba0ed044	403	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
gkroussos	0:e8fdba0ed044	404
gkroussos	0:e8fdba0ed044	405	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
gkroussos	0:e8fdba0ed044	406	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
gkroussos	0:e8fdba0ed044	407	#else
gkroussos	0:e8fdba0ed044	408	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
gkroussos	0:e8fdba0ed044	409	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
gkroussos	0:e8fdba0ed044	410	#endif
gkroussos	0:e8fdba0ed044	411
gkroussos	0:e8fdba0ed044	412	/* SCB Application Interrupt and Reset Control Register Definitions */
gkroussos	0:e8fdba0ed044	413	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
gkroussos	0:e8fdba0ed044	414	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
gkroussos	0:e8fdba0ed044	415
gkroussos	0:e8fdba0ed044	416	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
gkroussos	0:e8fdba0ed044	417	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
gkroussos	0:e8fdba0ed044	418
gkroussos	0:e8fdba0ed044	419	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
gkroussos	0:e8fdba0ed044	420	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
gkroussos	0:e8fdba0ed044	421
gkroussos	0:e8fdba0ed044	422	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
gkroussos	0:e8fdba0ed044	423	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
gkroussos	0:e8fdba0ed044	424
gkroussos	0:e8fdba0ed044	425	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
gkroussos	0:e8fdba0ed044	426	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
gkroussos	0:e8fdba0ed044	427
gkroussos	0:e8fdba0ed044	428	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
gkroussos	0:e8fdba0ed044	429	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
gkroussos	0:e8fdba0ed044	430
gkroussos	0:e8fdba0ed044	431	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
gkroussos	0:e8fdba0ed044	432	#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /!< SCB AIRCR: VECTRESET Mask /
gkroussos	0:e8fdba0ed044	433
gkroussos	0:e8fdba0ed044	434	/* SCB System Control Register Definitions */
gkroussos	0:e8fdba0ed044	435	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
gkroussos	0:e8fdba0ed044	436	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
gkroussos	0:e8fdba0ed044	437
gkroussos	0:e8fdba0ed044	438	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
gkroussos	0:e8fdba0ed044	439	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
gkroussos	0:e8fdba0ed044	440
gkroussos	0:e8fdba0ed044	441	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
gkroussos	0:e8fdba0ed044	442	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
gkroussos	0:e8fdba0ed044	443
gkroussos	0:e8fdba0ed044	444	/* SCB Configuration Control Register Definitions */
gkroussos	0:e8fdba0ed044	445	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
gkroussos	0:e8fdba0ed044	446	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
gkroussos	0:e8fdba0ed044	447
gkroussos	0:e8fdba0ed044	448	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
gkroussos	0:e8fdba0ed044	449	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
gkroussos	0:e8fdba0ed044	450
gkroussos	0:e8fdba0ed044	451	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
gkroussos	0:e8fdba0ed044	452	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
gkroussos	0:e8fdba0ed044	453
gkroussos	0:e8fdba0ed044	454	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
gkroussos	0:e8fdba0ed044	455	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
gkroussos	0:e8fdba0ed044	456
gkroussos	0:e8fdba0ed044	457	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
gkroussos	0:e8fdba0ed044	458	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
gkroussos	0:e8fdba0ed044	459
gkroussos	0:e8fdba0ed044	460	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
gkroussos	0:e8fdba0ed044	461	#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /!< SCB CCR: NONBASETHRDENA Mask /
gkroussos	0:e8fdba0ed044	462
gkroussos	0:e8fdba0ed044	463	/* SCB System Handler Control and State Register Definitions */
gkroussos	0:e8fdba0ed044	464	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
gkroussos	0:e8fdba0ed044	465	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
gkroussos	0:e8fdba0ed044	466
gkroussos	0:e8fdba0ed044	467	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
gkroussos	0:e8fdba0ed044	468	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
gkroussos	0:e8fdba0ed044	469
gkroussos	0:e8fdba0ed044	470	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
gkroussos	0:e8fdba0ed044	471	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
gkroussos	0:e8fdba0ed044	472
gkroussos	0:e8fdba0ed044	473	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
gkroussos	0:e8fdba0ed044	474	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
gkroussos	0:e8fdba0ed044	475
gkroussos	0:e8fdba0ed044	476	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
gkroussos	0:e8fdba0ed044	477	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
gkroussos	0:e8fdba0ed044	478
gkroussos	0:e8fdba0ed044	479	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
gkroussos	0:e8fdba0ed044	480	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
gkroussos	0:e8fdba0ed044	481
gkroussos	0:e8fdba0ed044	482	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
gkroussos	0:e8fdba0ed044	483	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
gkroussos	0:e8fdba0ed044	484
gkroussos	0:e8fdba0ed044	485	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
gkroussos	0:e8fdba0ed044	486	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
gkroussos	0:e8fdba0ed044	487
gkroussos	0:e8fdba0ed044	488	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
gkroussos	0:e8fdba0ed044	489	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
gkroussos	0:e8fdba0ed044	490
gkroussos	0:e8fdba0ed044	491	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
gkroussos	0:e8fdba0ed044	492	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
gkroussos	0:e8fdba0ed044	493
gkroussos	0:e8fdba0ed044	494	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
gkroussos	0:e8fdba0ed044	495	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
gkroussos	0:e8fdba0ed044	496
gkroussos	0:e8fdba0ed044	497	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
gkroussos	0:e8fdba0ed044	498	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
gkroussos	0:e8fdba0ed044	499
gkroussos	0:e8fdba0ed044	500	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
gkroussos	0:e8fdba0ed044	501	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
gkroussos	0:e8fdba0ed044	502
gkroussos	0:e8fdba0ed044	503	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
gkroussos	0:e8fdba0ed044	504	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /!< SCB SHCSR: MEMFAULTACT Mask /
gkroussos	0:e8fdba0ed044	505
gkroussos	0:e8fdba0ed044	506	/* SCB Configurable Fault Status Registers Definitions */
gkroussos	0:e8fdba0ed044	507	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
gkroussos	0:e8fdba0ed044	508	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
gkroussos	0:e8fdba0ed044	509
gkroussos	0:e8fdba0ed044	510	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
gkroussos	0:e8fdba0ed044	511	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
gkroussos	0:e8fdba0ed044	512
gkroussos	0:e8fdba0ed044	513	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
gkroussos	0:e8fdba0ed044	514	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
gkroussos	0:e8fdba0ed044	515
gkroussos	0:e8fdba0ed044	516	/* SCB Hard Fault Status Registers Definitions */
gkroussos	0:e8fdba0ed044	517	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
gkroussos	0:e8fdba0ed044	518	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
gkroussos	0:e8fdba0ed044	519
gkroussos	0:e8fdba0ed044	520	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
gkroussos	0:e8fdba0ed044	521	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
gkroussos	0:e8fdba0ed044	522
gkroussos	0:e8fdba0ed044	523	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
gkroussos	0:e8fdba0ed044	524	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
gkroussos	0:e8fdba0ed044	525
gkroussos	0:e8fdba0ed044	526	/* SCB Debug Fault Status Register Definitions */
gkroussos	0:e8fdba0ed044	527	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
gkroussos	0:e8fdba0ed044	528	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
gkroussos	0:e8fdba0ed044	529
gkroussos	0:e8fdba0ed044	530	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
gkroussos	0:e8fdba0ed044	531	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
gkroussos	0:e8fdba0ed044	532
gkroussos	0:e8fdba0ed044	533	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
gkroussos	0:e8fdba0ed044	534	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
gkroussos	0:e8fdba0ed044	535
gkroussos	0:e8fdba0ed044	536	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
gkroussos	0:e8fdba0ed044	537	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
gkroussos	0:e8fdba0ed044	538
gkroussos	0:e8fdba0ed044	539	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
gkroussos	0:e8fdba0ed044	540	#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /!< SCB DFSR: HALTED Mask /
gkroussos	0:e8fdba0ed044	541
gkroussos	0:e8fdba0ed044	542	/@} end of group CMSIS_SCB /
gkroussos	0:e8fdba0ed044	543
gkroussos	0:e8fdba0ed044	544
gkroussos	0:e8fdba0ed044	545	/** \ingroup CMSIS_core_register
gkroussos	0:e8fdba0ed044	546	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
gkroussos	0:e8fdba0ed044	547	\brief Type definitions for the System Control and ID Register not in the SCB
gkroussos	0:e8fdba0ed044	548	@{
gkroussos	0:e8fdba0ed044	549	*/
gkroussos	0:e8fdba0ed044	550
gkroussos	0:e8fdba0ed044	551	/** \brief Structure type to access the System Control and ID Register not in the SCB.
gkroussos	0:e8fdba0ed044	552	*/
gkroussos	0:e8fdba0ed044	553	typedef struct
gkroussos	0:e8fdba0ed044	554	{
gkroussos	0:e8fdba0ed044	555	uint32_t RESERVED0[1];
gkroussos	0:e8fdba0ed044	556	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
gkroussos	0:e8fdba0ed044	557	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
gkroussos	0:e8fdba0ed044	558	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
gkroussos	0:e8fdba0ed044	559	#else
gkroussos	0:e8fdba0ed044	560	uint32_t RESERVED1[1];
gkroussos	0:e8fdba0ed044	561	#endif
gkroussos	0:e8fdba0ed044	562	} SCnSCB_Type;
gkroussos	0:e8fdba0ed044	563
gkroussos	0:e8fdba0ed044	564	/* Interrupt Controller Type Register Definitions */
gkroussos	0:e8fdba0ed044	565	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
gkroussos	0:e8fdba0ed044	566	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /!< ICTR: INTLINESNUM Mask /
gkroussos	0:e8fdba0ed044	567
gkroussos	0:e8fdba0ed044	568	/* Auxiliary Control Register Definitions */
gkroussos	0:e8fdba0ed044	569
gkroussos	0:e8fdba0ed044	570	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
gkroussos	0:e8fdba0ed044	571	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
gkroussos	0:e8fdba0ed044	572
gkroussos	0:e8fdba0ed044	573	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
gkroussos	0:e8fdba0ed044	574	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
gkroussos	0:e8fdba0ed044	575
gkroussos	0:e8fdba0ed044	576	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
gkroussos	0:e8fdba0ed044	577	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /!< ACTLR: DISMCYCINT Mask /
gkroussos	0:e8fdba0ed044	578
gkroussos	0:e8fdba0ed044	579	/@} end of group CMSIS_SCnotSCB /
gkroussos	0:e8fdba0ed044	580
gkroussos	0:e8fdba0ed044	581
gkroussos	0:e8fdba0ed044	582	/** \ingroup CMSIS_core_register
gkroussos	0:e8fdba0ed044	583	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
gkroussos	0:e8fdba0ed044	584	\brief Type definitions for the System Timer Registers.
gkroussos	0:e8fdba0ed044	585	@{
gkroussos	0:e8fdba0ed044	586	*/
gkroussos	0:e8fdba0ed044	587
gkroussos	0:e8fdba0ed044	588	/** \brief Structure type to access the System Timer (SysTick).
gkroussos	0:e8fdba0ed044	589	*/
gkroussos	0:e8fdba0ed044	590	typedef struct
gkroussos	0:e8fdba0ed044	591	{
gkroussos	0:e8fdba0ed044	592	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
gkroussos	0:e8fdba0ed044	593	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
gkroussos	0:e8fdba0ed044	594	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
gkroussos	0:e8fdba0ed044	595	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
gkroussos	0:e8fdba0ed044	596	} SysTick_Type;
gkroussos	0:e8fdba0ed044	597
gkroussos	0:e8fdba0ed044	598	/* SysTick Control / Status Register Definitions */
gkroussos	0:e8fdba0ed044	599	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
gkroussos	0:e8fdba0ed044	600	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
gkroussos	0:e8fdba0ed044	601
gkroussos	0:e8fdba0ed044	602	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
gkroussos	0:e8fdba0ed044	603	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
gkroussos	0:e8fdba0ed044	604
gkroussos	0:e8fdba0ed044	605	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
gkroussos	0:e8fdba0ed044	606	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
gkroussos	0:e8fdba0ed044	607
gkroussos	0:e8fdba0ed044	608	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
gkroussos	0:e8fdba0ed044	609	#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /!< SysTick CTRL: ENABLE Mask /
gkroussos	0:e8fdba0ed044	610
gkroussos	0:e8fdba0ed044	611	/* SysTick Reload Register Definitions */
gkroussos	0:e8fdba0ed044	612	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
gkroussos	0:e8fdba0ed044	613	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /!< SysTick LOAD: RELOAD Mask /
gkroussos	0:e8fdba0ed044	614
gkroussos	0:e8fdba0ed044	615	/* SysTick Current Register Definitions */
gkroussos	0:e8fdba0ed044	616	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
gkroussos	0:e8fdba0ed044	617	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick VAL: CURRENT Mask /
gkroussos	0:e8fdba0ed044	618
gkroussos	0:e8fdba0ed044	619	/* SysTick Calibration Register Definitions */
gkroussos	0:e8fdba0ed044	620	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
gkroussos	0:e8fdba0ed044	621	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
gkroussos	0:e8fdba0ed044	622
gkroussos	0:e8fdba0ed044	623	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
gkroussos	0:e8fdba0ed044	624	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
gkroussos	0:e8fdba0ed044	625
gkroussos	0:e8fdba0ed044	626	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
gkroussos	0:e8fdba0ed044	627	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick CALIB: TENMS Mask /
gkroussos	0:e8fdba0ed044	628
gkroussos	0:e8fdba0ed044	629	/@} end of group CMSIS_SysTick /
gkroussos	0:e8fdba0ed044	630
gkroussos	0:e8fdba0ed044	631
gkroussos	0:e8fdba0ed044	632	/** \ingroup CMSIS_core_register
gkroussos	0:e8fdba0ed044	633	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
gkroussos	0:e8fdba0ed044	634	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
gkroussos	0:e8fdba0ed044	635	@{
gkroussos	0:e8fdba0ed044	636	*/
gkroussos	0:e8fdba0ed044	637
gkroussos	0:e8fdba0ed044	638	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
gkroussos	0:e8fdba0ed044	639	*/
gkroussos	0:e8fdba0ed044	640	typedef struct
gkroussos	0:e8fdba0ed044	641	{
gkroussos	0:e8fdba0ed044	642	__O union
gkroussos	0:e8fdba0ed044	643	{
gkroussos	0:e8fdba0ed044	644	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
gkroussos	0:e8fdba0ed044	645	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
gkroussos	0:e8fdba0ed044	646	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
gkroussos	0:e8fdba0ed044	647	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
gkroussos	0:e8fdba0ed044	648	uint32_t RESERVED0[864];
gkroussos	0:e8fdba0ed044	649	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
gkroussos	0:e8fdba0ed044	650	uint32_t RESERVED1[15];
gkroussos	0:e8fdba0ed044	651	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
gkroussos	0:e8fdba0ed044	652	uint32_t RESERVED2[15];
gkroussos	0:e8fdba0ed044	653	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
gkroussos	0:e8fdba0ed044	654	uint32_t RESERVED3[29];
gkroussos	0:e8fdba0ed044	655	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
gkroussos	0:e8fdba0ed044	656	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
gkroussos	0:e8fdba0ed044	657	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
gkroussos	0:e8fdba0ed044	658	uint32_t RESERVED4[43];
gkroussos	0:e8fdba0ed044	659	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
gkroussos	0:e8fdba0ed044	660	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
gkroussos	0:e8fdba0ed044	661	uint32_t RESERVED5[6];
gkroussos	0:e8fdba0ed044	662	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
gkroussos	0:e8fdba0ed044	663	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
gkroussos	0:e8fdba0ed044	664	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
gkroussos	0:e8fdba0ed044	665	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
gkroussos	0:e8fdba0ed044	666	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
gkroussos	0:e8fdba0ed044	667	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
gkroussos	0:e8fdba0ed044	668	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
gkroussos	0:e8fdba0ed044	669	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
gkroussos	0:e8fdba0ed044	670	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
gkroussos	0:e8fdba0ed044	671	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
gkroussos	0:e8fdba0ed044	672	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
gkroussos	0:e8fdba0ed044	673	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
gkroussos	0:e8fdba0ed044	674	} ITM_Type;
gkroussos	0:e8fdba0ed044	675
gkroussos	0:e8fdba0ed044	676	/* ITM Trace Privilege Register Definitions */
gkroussos	0:e8fdba0ed044	677	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
gkroussos	0:e8fdba0ed044	678	#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /!< ITM TPR: PRIVMASK Mask /
gkroussos	0:e8fdba0ed044	679
gkroussos	0:e8fdba0ed044	680	/* ITM Trace Control Register Definitions */
gkroussos	0:e8fdba0ed044	681	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
gkroussos	0:e8fdba0ed044	682	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
gkroussos	0:e8fdba0ed044	683
gkroussos	0:e8fdba0ed044	684	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
gkroussos	0:e8fdba0ed044	685	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
gkroussos	0:e8fdba0ed044	686
gkroussos	0:e8fdba0ed044	687	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
gkroussos	0:e8fdba0ed044	688	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
gkroussos	0:e8fdba0ed044	689
gkroussos	0:e8fdba0ed044	690	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
gkroussos	0:e8fdba0ed044	691	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
gkroussos	0:e8fdba0ed044	692
gkroussos	0:e8fdba0ed044	693	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
gkroussos	0:e8fdba0ed044	694	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
gkroussos	0:e8fdba0ed044	695
gkroussos	0:e8fdba0ed044	696	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
gkroussos	0:e8fdba0ed044	697	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
gkroussos	0:e8fdba0ed044	698
gkroussos	0:e8fdba0ed044	699	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
gkroussos	0:e8fdba0ed044	700	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
gkroussos	0:e8fdba0ed044	701
gkroussos	0:e8fdba0ed044	702	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
gkroussos	0:e8fdba0ed044	703	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
gkroussos	0:e8fdba0ed044	704
gkroussos	0:e8fdba0ed044	705	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
gkroussos	0:e8fdba0ed044	706	#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /!< ITM TCR: ITM Enable bit Mask /
gkroussos	0:e8fdba0ed044	707
gkroussos	0:e8fdba0ed044	708	/* ITM Integration Write Register Definitions */
gkroussos	0:e8fdba0ed044	709	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
gkroussos	0:e8fdba0ed044	710	#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /!< ITM IWR: ATVALIDM Mask /
gkroussos	0:e8fdba0ed044	711
gkroussos	0:e8fdba0ed044	712	/* ITM Integration Read Register Definitions */
gkroussos	0:e8fdba0ed044	713	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
gkroussos	0:e8fdba0ed044	714	#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /!< ITM IRR: ATREADYM Mask /
gkroussos	0:e8fdba0ed044	715
gkroussos	0:e8fdba0ed044	716	/* ITM Integration Mode Control Register Definitions */
gkroussos	0:e8fdba0ed044	717	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
gkroussos	0:e8fdba0ed044	718	#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /!< ITM IMCR: INTEGRATION Mask /
gkroussos	0:e8fdba0ed044	719
gkroussos	0:e8fdba0ed044	720	/* ITM Lock Status Register Definitions */
gkroussos	0:e8fdba0ed044	721	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
gkroussos	0:e8fdba0ed044	722	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
gkroussos	0:e8fdba0ed044	723
gkroussos	0:e8fdba0ed044	724	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
gkroussos	0:e8fdba0ed044	725	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
gkroussos	0:e8fdba0ed044	726
gkroussos	0:e8fdba0ed044	727	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
gkroussos	0:e8fdba0ed044	728	#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /!< ITM LSR: Present Mask /
gkroussos	0:e8fdba0ed044	729
gkroussos	0:e8fdba0ed044	730	/@}/ /* end of group CMSIS_ITM */
gkroussos	0:e8fdba0ed044	731
gkroussos	0:e8fdba0ed044	732
gkroussos	0:e8fdba0ed044	733	/** \ingroup CMSIS_core_register
gkroussos	0:e8fdba0ed044	734	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
gkroussos	0:e8fdba0ed044	735	\brief Type definitions for the Data Watchpoint and Trace (DWT)
gkroussos	0:e8fdba0ed044	736	@{
gkroussos	0:e8fdba0ed044	737	*/
gkroussos	0:e8fdba0ed044	738
gkroussos	0:e8fdba0ed044	739	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
gkroussos	0:e8fdba0ed044	740	*/
gkroussos	0:e8fdba0ed044	741	typedef struct
gkroussos	0:e8fdba0ed044	742	{
gkroussos	0:e8fdba0ed044	743	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
gkroussos	0:e8fdba0ed044	744	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
gkroussos	0:e8fdba0ed044	745	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
gkroussos	0:e8fdba0ed044	746	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
gkroussos	0:e8fdba0ed044	747	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
gkroussos	0:e8fdba0ed044	748	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
gkroussos	0:e8fdba0ed044	749	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
gkroussos	0:e8fdba0ed044	750	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
gkroussos	0:e8fdba0ed044	751	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
gkroussos	0:e8fdba0ed044	752	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
gkroussos	0:e8fdba0ed044	753	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
gkroussos	0:e8fdba0ed044	754	uint32_t RESERVED0[1];
gkroussos	0:e8fdba0ed044	755	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
gkroussos	0:e8fdba0ed044	756	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
gkroussos	0:e8fdba0ed044	757	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
gkroussos	0:e8fdba0ed044	758	uint32_t RESERVED1[1];
gkroussos	0:e8fdba0ed044	759	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
gkroussos	0:e8fdba0ed044	760	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
gkroussos	0:e8fdba0ed044	761	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
gkroussos	0:e8fdba0ed044	762	uint32_t RESERVED2[1];
gkroussos	0:e8fdba0ed044	763	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
gkroussos	0:e8fdba0ed044	764	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
gkroussos	0:e8fdba0ed044	765	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
gkroussos	0:e8fdba0ed044	766	} DWT_Type;
gkroussos	0:e8fdba0ed044	767
gkroussos	0:e8fdba0ed044	768	/* DWT Control Register Definitions */
gkroussos	0:e8fdba0ed044	769	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
gkroussos	0:e8fdba0ed044	770	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
gkroussos	0:e8fdba0ed044	771
gkroussos	0:e8fdba0ed044	772	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
gkroussos	0:e8fdba0ed044	773	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
gkroussos	0:e8fdba0ed044	774
gkroussos	0:e8fdba0ed044	775	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
gkroussos	0:e8fdba0ed044	776	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
gkroussos	0:e8fdba0ed044	777
gkroussos	0:e8fdba0ed044	778	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
gkroussos	0:e8fdba0ed044	779	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
gkroussos	0:e8fdba0ed044	780
gkroussos	0:e8fdba0ed044	781	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
gkroussos	0:e8fdba0ed044	782	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
gkroussos	0:e8fdba0ed044	783
gkroussos	0:e8fdba0ed044	784	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
gkroussos	0:e8fdba0ed044	785	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
gkroussos	0:e8fdba0ed044	786
gkroussos	0:e8fdba0ed044	787	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
gkroussos	0:e8fdba0ed044	788	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
gkroussos	0:e8fdba0ed044	789
gkroussos	0:e8fdba0ed044	790	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
gkroussos	0:e8fdba0ed044	791	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
gkroussos	0:e8fdba0ed044	792
gkroussos	0:e8fdba0ed044	793	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
gkroussos	0:e8fdba0ed044	794	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
gkroussos	0:e8fdba0ed044	795
gkroussos	0:e8fdba0ed044	796	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
gkroussos	0:e8fdba0ed044	797	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
gkroussos	0:e8fdba0ed044	798
gkroussos	0:e8fdba0ed044	799	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
gkroussos	0:e8fdba0ed044	800	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
gkroussos	0:e8fdba0ed044	801
gkroussos	0:e8fdba0ed044	802	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
gkroussos	0:e8fdba0ed044	803	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
gkroussos	0:e8fdba0ed044	804
gkroussos	0:e8fdba0ed044	805	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
gkroussos	0:e8fdba0ed044	806	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
gkroussos	0:e8fdba0ed044	807
gkroussos	0:e8fdba0ed044	808	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
gkroussos	0:e8fdba0ed044	809	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
gkroussos	0:e8fdba0ed044	810
gkroussos	0:e8fdba0ed044	811	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
gkroussos	0:e8fdba0ed044	812	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
gkroussos	0:e8fdba0ed044	813
gkroussos	0:e8fdba0ed044	814	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
gkroussos	0:e8fdba0ed044	815	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
gkroussos	0:e8fdba0ed044	816
gkroussos	0:e8fdba0ed044	817	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
gkroussos	0:e8fdba0ed044	818	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
gkroussos	0:e8fdba0ed044	819
gkroussos	0:e8fdba0ed044	820	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
gkroussos	0:e8fdba0ed044	821	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /!< DWT CTRL: CYCCNTENA Mask /
gkroussos	0:e8fdba0ed044	822
gkroussos	0:e8fdba0ed044	823	/* DWT CPI Count Register Definitions */
gkroussos	0:e8fdba0ed044	824	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
gkroussos	0:e8fdba0ed044	825	#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /!< DWT CPICNT: CPICNT Mask /
gkroussos	0:e8fdba0ed044	826
gkroussos	0:e8fdba0ed044	827	/* DWT Exception Overhead Count Register Definitions */
gkroussos	0:e8fdba0ed044	828	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
gkroussos	0:e8fdba0ed044	829	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /!< DWT EXCCNT: EXCCNT Mask /
gkroussos	0:e8fdba0ed044	830
gkroussos	0:e8fdba0ed044	831	/* DWT Sleep Count Register Definitions */
gkroussos	0:e8fdba0ed044	832	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
gkroussos	0:e8fdba0ed044	833	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /!< DWT SLEEPCNT: SLEEPCNT Mask /
gkroussos	0:e8fdba0ed044	834
gkroussos	0:e8fdba0ed044	835	/* DWT LSU Count Register Definitions */
gkroussos	0:e8fdba0ed044	836	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
gkroussos	0:e8fdba0ed044	837	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /!< DWT LSUCNT: LSUCNT Mask /
gkroussos	0:e8fdba0ed044	838
gkroussos	0:e8fdba0ed044	839	/* DWT Folded-instruction Count Register Definitions */
gkroussos	0:e8fdba0ed044	840	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
gkroussos	0:e8fdba0ed044	841	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /!< DWT FOLDCNT: FOLDCNT Mask /
gkroussos	0:e8fdba0ed044	842
gkroussos	0:e8fdba0ed044	843	/* DWT Comparator Mask Register Definitions */
gkroussos	0:e8fdba0ed044	844	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
gkroussos	0:e8fdba0ed044	845	#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /!< DWT MASK: MASK Mask /
gkroussos	0:e8fdba0ed044	846
gkroussos	0:e8fdba0ed044	847	/* DWT Comparator Function Register Definitions */
gkroussos	0:e8fdba0ed044	848	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
gkroussos	0:e8fdba0ed044	849	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
gkroussos	0:e8fdba0ed044	850
gkroussos	0:e8fdba0ed044	851	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
gkroussos	0:e8fdba0ed044	852	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
gkroussos	0:e8fdba0ed044	853
gkroussos	0:e8fdba0ed044	854	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
gkroussos	0:e8fdba0ed044	855	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
gkroussos	0:e8fdba0ed044	856
gkroussos	0:e8fdba0ed044	857	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
gkroussos	0:e8fdba0ed044	858	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
gkroussos	0:e8fdba0ed044	859
gkroussos	0:e8fdba0ed044	860	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
gkroussos	0:e8fdba0ed044	861	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
gkroussos	0:e8fdba0ed044	862
gkroussos	0:e8fdba0ed044	863	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
gkroussos	0:e8fdba0ed044	864	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
gkroussos	0:e8fdba0ed044	865
gkroussos	0:e8fdba0ed044	866	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
gkroussos	0:e8fdba0ed044	867	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
gkroussos	0:e8fdba0ed044	868
gkroussos	0:e8fdba0ed044	869	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
gkroussos	0:e8fdba0ed044	870	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
gkroussos	0:e8fdba0ed044	871
gkroussos	0:e8fdba0ed044	872	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
gkroussos	0:e8fdba0ed044	873	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /!< DWT FUNCTION: FUNCTION Mask /
gkroussos	0:e8fdba0ed044	874
gkroussos	0:e8fdba0ed044	875	/@}/ /* end of group CMSIS_DWT */
gkroussos	0:e8fdba0ed044	876
gkroussos	0:e8fdba0ed044	877
gkroussos	0:e8fdba0ed044	878	/** \ingroup CMSIS_core_register
gkroussos	0:e8fdba0ed044	879	\defgroup CMSIS_TPI Trace Port Interface (TPI)
gkroussos	0:e8fdba0ed044	880	\brief Type definitions for the Trace Port Interface (TPI)
gkroussos	0:e8fdba0ed044	881	@{
gkroussos	0:e8fdba0ed044	882	*/
gkroussos	0:e8fdba0ed044	883
gkroussos	0:e8fdba0ed044	884	/** \brief Structure type to access the Trace Port Interface Register (TPI).
gkroussos	0:e8fdba0ed044	885	*/
gkroussos	0:e8fdba0ed044	886	typedef struct
gkroussos	0:e8fdba0ed044	887	{
gkroussos	0:e8fdba0ed044	888	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
gkroussos	0:e8fdba0ed044	889	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
gkroussos	0:e8fdba0ed044	890	uint32_t RESERVED0[2];
gkroussos	0:e8fdba0ed044	891	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
gkroussos	0:e8fdba0ed044	892	uint32_t RESERVED1[55];
gkroussos	0:e8fdba0ed044	893	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
gkroussos	0:e8fdba0ed044	894	uint32_t RESERVED2[131];
gkroussos	0:e8fdba0ed044	895	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
gkroussos	0:e8fdba0ed044	896	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
gkroussos	0:e8fdba0ed044	897	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
gkroussos	0:e8fdba0ed044	898	uint32_t RESERVED3[759];
gkroussos	0:e8fdba0ed044	899	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
gkroussos	0:e8fdba0ed044	900	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
gkroussos	0:e8fdba0ed044	901	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
gkroussos	0:e8fdba0ed044	902	uint32_t RESERVED4[1];
gkroussos	0:e8fdba0ed044	903	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
gkroussos	0:e8fdba0ed044	904	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
gkroussos	0:e8fdba0ed044	905	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
gkroussos	0:e8fdba0ed044	906	uint32_t RESERVED5[39];
gkroussos	0:e8fdba0ed044	907	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
gkroussos	0:e8fdba0ed044	908	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
gkroussos	0:e8fdba0ed044	909	uint32_t RESERVED7[8];
gkroussos	0:e8fdba0ed044	910	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
gkroussos	0:e8fdba0ed044	911	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
gkroussos	0:e8fdba0ed044	912	} TPI_Type;
gkroussos	0:e8fdba0ed044	913
gkroussos	0:e8fdba0ed044	914	/* TPI Asynchronous Clock Prescaler Register Definitions */
gkroussos	0:e8fdba0ed044	915	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
gkroussos	0:e8fdba0ed044	916	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /!< TPI ACPR: PRESCALER Mask /
gkroussos	0:e8fdba0ed044	917
gkroussos	0:e8fdba0ed044	918	/* TPI Selected Pin Protocol Register Definitions */
gkroussos	0:e8fdba0ed044	919	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
gkroussos	0:e8fdba0ed044	920	#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /!< TPI SPPR: TXMODE Mask /
gkroussos	0:e8fdba0ed044	921
gkroussos	0:e8fdba0ed044	922	/* TPI Formatter and Flush Status Register Definitions */
gkroussos	0:e8fdba0ed044	923	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
gkroussos	0:e8fdba0ed044	924	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
gkroussos	0:e8fdba0ed044	925
gkroussos	0:e8fdba0ed044	926	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
gkroussos	0:e8fdba0ed044	927	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
gkroussos	0:e8fdba0ed044	928
gkroussos	0:e8fdba0ed044	929	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
gkroussos	0:e8fdba0ed044	930	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
gkroussos	0:e8fdba0ed044	931
gkroussos	0:e8fdba0ed044	932	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
gkroussos	0:e8fdba0ed044	933	#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /!< TPI FFSR: FlInProg Mask /
gkroussos	0:e8fdba0ed044	934
gkroussos	0:e8fdba0ed044	935	/* TPI Formatter and Flush Control Register Definitions */
gkroussos	0:e8fdba0ed044	936	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
gkroussos	0:e8fdba0ed044	937	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
gkroussos	0:e8fdba0ed044	938
gkroussos	0:e8fdba0ed044	939	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
gkroussos	0:e8fdba0ed044	940	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
gkroussos	0:e8fdba0ed044	941
gkroussos	0:e8fdba0ed044	942	/* TPI TRIGGER Register Definitions */
gkroussos	0:e8fdba0ed044	943	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
gkroussos	0:e8fdba0ed044	944	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /!< TPI TRIGGER: TRIGGER Mask /
gkroussos	0:e8fdba0ed044	945
gkroussos	0:e8fdba0ed044	946	/* TPI Integration ETM Data Register Definitions (FIFO0) */
gkroussos	0:e8fdba0ed044	947	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
gkroussos	0:e8fdba0ed044	948	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
gkroussos	0:e8fdba0ed044	949
gkroussos	0:e8fdba0ed044	950	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
gkroussos	0:e8fdba0ed044	951	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
gkroussos	0:e8fdba0ed044	952
gkroussos	0:e8fdba0ed044	953	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
gkroussos	0:e8fdba0ed044	954	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
gkroussos	0:e8fdba0ed044	955
gkroussos	0:e8fdba0ed044	956	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
gkroussos	0:e8fdba0ed044	957	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
gkroussos	0:e8fdba0ed044	958
gkroussos	0:e8fdba0ed044	959	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
gkroussos	0:e8fdba0ed044	960	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
gkroussos	0:e8fdba0ed044	961
gkroussos	0:e8fdba0ed044	962	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
gkroussos	0:e8fdba0ed044	963	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
gkroussos	0:e8fdba0ed044	964
gkroussos	0:e8fdba0ed044	965	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
gkroussos	0:e8fdba0ed044	966	#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /!< TPI FIFO0: ETM0 Mask /
gkroussos	0:e8fdba0ed044	967
gkroussos	0:e8fdba0ed044	968	/* TPI ITATBCTR2 Register Definitions */
gkroussos	0:e8fdba0ed044	969	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
gkroussos	0:e8fdba0ed044	970	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /!< TPI ITATBCTR2: ATREADY Mask /
gkroussos	0:e8fdba0ed044	971
gkroussos	0:e8fdba0ed044	972	/* TPI Integration ITM Data Register Definitions (FIFO1) */
gkroussos	0:e8fdba0ed044	973	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
gkroussos	0:e8fdba0ed044	974	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
gkroussos	0:e8fdba0ed044	975
gkroussos	0:e8fdba0ed044	976	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
gkroussos	0:e8fdba0ed044	977	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
gkroussos	0:e8fdba0ed044	978
gkroussos	0:e8fdba0ed044	979	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
gkroussos	0:e8fdba0ed044	980	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
gkroussos	0:e8fdba0ed044	981
gkroussos	0:e8fdba0ed044	982	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
gkroussos	0:e8fdba0ed044	983	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
gkroussos	0:e8fdba0ed044	984
gkroussos	0:e8fdba0ed044	985	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
gkroussos	0:e8fdba0ed044	986	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
gkroussos	0:e8fdba0ed044	987
gkroussos	0:e8fdba0ed044	988	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
gkroussos	0:e8fdba0ed044	989	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
gkroussos	0:e8fdba0ed044	990
gkroussos	0:e8fdba0ed044	991	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
gkroussos	0:e8fdba0ed044	992	#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /!< TPI FIFO1: ITM0 Mask /
gkroussos	0:e8fdba0ed044	993
gkroussos	0:e8fdba0ed044	994	/* TPI ITATBCTR0 Register Definitions */
gkroussos	0:e8fdba0ed044	995	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
gkroussos	0:e8fdba0ed044	996	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /!< TPI ITATBCTR0: ATREADY Mask /
gkroussos	0:e8fdba0ed044	997
gkroussos	0:e8fdba0ed044	998	/* TPI Integration Mode Control Register Definitions */
gkroussos	0:e8fdba0ed044	999	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
gkroussos	0:e8fdba0ed044	1000	#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /!< TPI ITCTRL: Mode Mask /
gkroussos	0:e8fdba0ed044	1001
gkroussos	0:e8fdba0ed044	1002	/* TPI DEVID Register Definitions */
gkroussos	0:e8fdba0ed044	1003	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
gkroussos	0:e8fdba0ed044	1004	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
gkroussos	0:e8fdba0ed044	1005
gkroussos	0:e8fdba0ed044	1006	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
gkroussos	0:e8fdba0ed044	1007	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
gkroussos	0:e8fdba0ed044	1008
gkroussos	0:e8fdba0ed044	1009	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
gkroussos	0:e8fdba0ed044	1010	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
gkroussos	0:e8fdba0ed044	1011
gkroussos	0:e8fdba0ed044	1012	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
gkroussos	0:e8fdba0ed044	1013	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
gkroussos	0:e8fdba0ed044	1014
gkroussos	0:e8fdba0ed044	1015	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
gkroussos	0:e8fdba0ed044	1016	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
gkroussos	0:e8fdba0ed044	1017
gkroussos	0:e8fdba0ed044	1018	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
gkroussos	0:e8fdba0ed044	1019	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /!< TPI DEVID: NrTraceInput Mask /
gkroussos	0:e8fdba0ed044	1020
gkroussos	0:e8fdba0ed044	1021	/* TPI DEVTYPE Register Definitions */
gkroussos	0:e8fdba0ed044	1022	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
gkroussos	0:e8fdba0ed044	1023	#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /!< TPI DEVTYPE: SubType Mask /
gkroussos	0:e8fdba0ed044	1024
gkroussos	0:e8fdba0ed044	1025	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
gkroussos	0:e8fdba0ed044	1026	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
gkroussos	0:e8fdba0ed044	1027
gkroussos	0:e8fdba0ed044	1028	/@}/ /* end of group CMSIS_TPI */
gkroussos	0:e8fdba0ed044	1029
gkroussos	0:e8fdba0ed044	1030
gkroussos	0:e8fdba0ed044	1031	#if (__MPU_PRESENT == 1)
gkroussos	0:e8fdba0ed044	1032	/** \ingroup CMSIS_core_register
gkroussos	0:e8fdba0ed044	1033	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
gkroussos	0:e8fdba0ed044	1034	\brief Type definitions for the Memory Protection Unit (MPU)
gkroussos	0:e8fdba0ed044	1035	@{
gkroussos	0:e8fdba0ed044	1036	*/
gkroussos	0:e8fdba0ed044	1037
gkroussos	0:e8fdba0ed044	1038	/** \brief Structure type to access the Memory Protection Unit (MPU).
gkroussos	0:e8fdba0ed044	1039	*/
gkroussos	0:e8fdba0ed044	1040	typedef struct
gkroussos	0:e8fdba0ed044	1041	{
gkroussos	0:e8fdba0ed044	1042	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
gkroussos	0:e8fdba0ed044	1043	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
gkroussos	0:e8fdba0ed044	1044	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
gkroussos	0:e8fdba0ed044	1045	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
gkroussos	0:e8fdba0ed044	1046	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
gkroussos	0:e8fdba0ed044	1047	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
gkroussos	0:e8fdba0ed044	1048	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
gkroussos	0:e8fdba0ed044	1049	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
gkroussos	0:e8fdba0ed044	1050	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
gkroussos	0:e8fdba0ed044	1051	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
gkroussos	0:e8fdba0ed044	1052	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
gkroussos	0:e8fdba0ed044	1053	} MPU_Type;
gkroussos	0:e8fdba0ed044	1054
gkroussos	0:e8fdba0ed044	1055	/* MPU Type Register */
gkroussos	0:e8fdba0ed044	1056	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
gkroussos	0:e8fdba0ed044	1057	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
gkroussos	0:e8fdba0ed044	1058
gkroussos	0:e8fdba0ed044	1059	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
gkroussos	0:e8fdba0ed044	1060	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
gkroussos	0:e8fdba0ed044	1061
gkroussos	0:e8fdba0ed044	1062	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
gkroussos	0:e8fdba0ed044	1063	#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /!< MPU TYPE: SEPARATE Mask /
gkroussos	0:e8fdba0ed044	1064
gkroussos	0:e8fdba0ed044	1065	/* MPU Control Register */
gkroussos	0:e8fdba0ed044	1066	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
gkroussos	0:e8fdba0ed044	1067	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
gkroussos	0:e8fdba0ed044	1068
gkroussos	0:e8fdba0ed044	1069	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
gkroussos	0:e8fdba0ed044	1070	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
gkroussos	0:e8fdba0ed044	1071
gkroussos	0:e8fdba0ed044	1072	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
gkroussos	0:e8fdba0ed044	1073	#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /!< MPU CTRL: ENABLE Mask /
gkroussos	0:e8fdba0ed044	1074
gkroussos	0:e8fdba0ed044	1075	/* MPU Region Number Register */
gkroussos	0:e8fdba0ed044	1076	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
gkroussos	0:e8fdba0ed044	1077	#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /!< MPU RNR: REGION Mask /
gkroussos	0:e8fdba0ed044	1078
gkroussos	0:e8fdba0ed044	1079	/* MPU Region Base Address Register */
gkroussos	0:e8fdba0ed044	1080	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
gkroussos	0:e8fdba0ed044	1081	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
gkroussos	0:e8fdba0ed044	1082
gkroussos	0:e8fdba0ed044	1083	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
gkroussos	0:e8fdba0ed044	1084	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
gkroussos	0:e8fdba0ed044	1085
gkroussos	0:e8fdba0ed044	1086	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
gkroussos	0:e8fdba0ed044	1087	#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /!< MPU RBAR: REGION Mask /
gkroussos	0:e8fdba0ed044	1088
gkroussos	0:e8fdba0ed044	1089	/* MPU Region Attribute and Size Register */
gkroussos	0:e8fdba0ed044	1090	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
gkroussos	0:e8fdba0ed044	1091	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
gkroussos	0:e8fdba0ed044	1092
gkroussos	0:e8fdba0ed044	1093	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
gkroussos	0:e8fdba0ed044	1094	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
gkroussos	0:e8fdba0ed044	1095
gkroussos	0:e8fdba0ed044	1096	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
gkroussos	0:e8fdba0ed044	1097	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
gkroussos	0:e8fdba0ed044	1098
gkroussos	0:e8fdba0ed044	1099	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
gkroussos	0:e8fdba0ed044	1100	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
gkroussos	0:e8fdba0ed044	1101
gkroussos	0:e8fdba0ed044	1102	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
gkroussos	0:e8fdba0ed044	1103	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
gkroussos	0:e8fdba0ed044	1104
gkroussos	0:e8fdba0ed044	1105	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
gkroussos	0:e8fdba0ed044	1106	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
gkroussos	0:e8fdba0ed044	1107
gkroussos	0:e8fdba0ed044	1108	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
gkroussos	0:e8fdba0ed044	1109	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
gkroussos	0:e8fdba0ed044	1110
gkroussos	0:e8fdba0ed044	1111	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
gkroussos	0:e8fdba0ed044	1112	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
gkroussos	0:e8fdba0ed044	1113
gkroussos	0:e8fdba0ed044	1114	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
gkroussos	0:e8fdba0ed044	1115	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
gkroussos	0:e8fdba0ed044	1116
gkroussos	0:e8fdba0ed044	1117	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
gkroussos	0:e8fdba0ed044	1118	#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /!< MPU RASR: Region enable bit Disable Mask /
gkroussos	0:e8fdba0ed044	1119
gkroussos	0:e8fdba0ed044	1120	/@} end of group CMSIS_MPU /
gkroussos	0:e8fdba0ed044	1121	#endif
gkroussos	0:e8fdba0ed044	1122
gkroussos	0:e8fdba0ed044	1123
gkroussos	0:e8fdba0ed044	1124	/** \ingroup CMSIS_core_register
gkroussos	0:e8fdba0ed044	1125	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
gkroussos	0:e8fdba0ed044	1126	\brief Type definitions for the Core Debug Registers
gkroussos	0:e8fdba0ed044	1127	@{
gkroussos	0:e8fdba0ed044	1128	*/
gkroussos	0:e8fdba0ed044	1129
gkroussos	0:e8fdba0ed044	1130	/** \brief Structure type to access the Core Debug Register (CoreDebug).
gkroussos	0:e8fdba0ed044	1131	*/
gkroussos	0:e8fdba0ed044	1132	typedef struct
gkroussos	0:e8fdba0ed044	1133	{
gkroussos	0:e8fdba0ed044	1134	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
gkroussos	0:e8fdba0ed044	1135	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
gkroussos	0:e8fdba0ed044	1136	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
gkroussos	0:e8fdba0ed044	1137	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
gkroussos	0:e8fdba0ed044	1138	} CoreDebug_Type;
gkroussos	0:e8fdba0ed044	1139
gkroussos	0:e8fdba0ed044	1140	/* Debug Halting Control and Status Register */
gkroussos	0:e8fdba0ed044	1141	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
gkroussos	0:e8fdba0ed044	1142	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
gkroussos	0:e8fdba0ed044	1143
gkroussos	0:e8fdba0ed044	1144	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
gkroussos	0:e8fdba0ed044	1145	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
gkroussos	0:e8fdba0ed044	1146
gkroussos	0:e8fdba0ed044	1147	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
gkroussos	0:e8fdba0ed044	1148	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
gkroussos	0:e8fdba0ed044	1149
gkroussos	0:e8fdba0ed044	1150	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
gkroussos	0:e8fdba0ed044	1151	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
gkroussos	0:e8fdba0ed044	1152
gkroussos	0:e8fdba0ed044	1153	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
gkroussos	0:e8fdba0ed044	1154	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
gkroussos	0:e8fdba0ed044	1155
gkroussos	0:e8fdba0ed044	1156	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
gkroussos	0:e8fdba0ed044	1157	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
gkroussos	0:e8fdba0ed044	1158
gkroussos	0:e8fdba0ed044	1159	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
gkroussos	0:e8fdba0ed044	1160	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
gkroussos	0:e8fdba0ed044	1161
gkroussos	0:e8fdba0ed044	1162	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
gkroussos	0:e8fdba0ed044	1163	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
gkroussos	0:e8fdba0ed044	1164
gkroussos	0:e8fdba0ed044	1165	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
gkroussos	0:e8fdba0ed044	1166	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
gkroussos	0:e8fdba0ed044	1167
gkroussos	0:e8fdba0ed044	1168	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
gkroussos	0:e8fdba0ed044	1169	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
gkroussos	0:e8fdba0ed044	1170
gkroussos	0:e8fdba0ed044	1171	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
gkroussos	0:e8fdba0ed044	1172	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
gkroussos	0:e8fdba0ed044	1173
gkroussos	0:e8fdba0ed044	1174	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
gkroussos	0:e8fdba0ed044	1175	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
gkroussos	0:e8fdba0ed044	1176
gkroussos	0:e8fdba0ed044	1177	/* Debug Core Register Selector Register */
gkroussos	0:e8fdba0ed044	1178	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
gkroussos	0:e8fdba0ed044	1179	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
gkroussos	0:e8fdba0ed044	1180
gkroussos	0:e8fdba0ed044	1181	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
gkroussos	0:e8fdba0ed044	1182	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /!< CoreDebug DCRSR: REGSEL Mask /
gkroussos	0:e8fdba0ed044	1183
gkroussos	0:e8fdba0ed044	1184	/* Debug Exception and Monitor Control Register */
gkroussos	0:e8fdba0ed044	1185	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
gkroussos	0:e8fdba0ed044	1186	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
gkroussos	0:e8fdba0ed044	1187
gkroussos	0:e8fdba0ed044	1188	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
gkroussos	0:e8fdba0ed044	1189	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
gkroussos	0:e8fdba0ed044	1190
gkroussos	0:e8fdba0ed044	1191	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
gkroussos	0:e8fdba0ed044	1192	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
gkroussos	0:e8fdba0ed044	1193
gkroussos	0:e8fdba0ed044	1194	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
gkroussos	0:e8fdba0ed044	1195	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
gkroussos	0:e8fdba0ed044	1196
gkroussos	0:e8fdba0ed044	1197	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
gkroussos	0:e8fdba0ed044	1198	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
gkroussos	0:e8fdba0ed044	1199
gkroussos	0:e8fdba0ed044	1200	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
gkroussos	0:e8fdba0ed044	1201	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
gkroussos	0:e8fdba0ed044	1202
gkroussos	0:e8fdba0ed044	1203	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
gkroussos	0:e8fdba0ed044	1204	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
gkroussos	0:e8fdba0ed044	1205
gkroussos	0:e8fdba0ed044	1206	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
gkroussos	0:e8fdba0ed044	1207	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
gkroussos	0:e8fdba0ed044	1208
gkroussos	0:e8fdba0ed044	1209	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
gkroussos	0:e8fdba0ed044	1210	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
gkroussos	0:e8fdba0ed044	1211
gkroussos	0:e8fdba0ed044	1212	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
gkroussos	0:e8fdba0ed044	1213	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
gkroussos	0:e8fdba0ed044	1214
gkroussos	0:e8fdba0ed044	1215	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
gkroussos	0:e8fdba0ed044	1216	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
gkroussos	0:e8fdba0ed044	1217
gkroussos	0:e8fdba0ed044	1218	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
gkroussos	0:e8fdba0ed044	1219	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
gkroussos	0:e8fdba0ed044	1220
gkroussos	0:e8fdba0ed044	1221	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
gkroussos	0:e8fdba0ed044	1222	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /!< CoreDebug DEMCR: VC_CORERESET Mask /
gkroussos	0:e8fdba0ed044	1223
gkroussos	0:e8fdba0ed044	1224	/@} end of group CMSIS_CoreDebug /
gkroussos	0:e8fdba0ed044	1225
gkroussos	0:e8fdba0ed044	1226
gkroussos	0:e8fdba0ed044	1227	/** \ingroup CMSIS_core_register
gkroussos	0:e8fdba0ed044	1228	\defgroup CMSIS_core_base Core Definitions
gkroussos	0:e8fdba0ed044	1229	\brief Definitions for base addresses, unions, and structures.
gkroussos	0:e8fdba0ed044	1230	@{
gkroussos	0:e8fdba0ed044	1231	*/
gkroussos	0:e8fdba0ed044	1232
gkroussos	0:e8fdba0ed044	1233	/* Memory mapping of Cortex-M3 Hardware */
gkroussos	0:e8fdba0ed044	1234	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
gkroussos	0:e8fdba0ed044	1235	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
gkroussos	0:e8fdba0ed044	1236	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
gkroussos	0:e8fdba0ed044	1237	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
gkroussos	0:e8fdba0ed044	1238	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
gkroussos	0:e8fdba0ed044	1239	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
gkroussos	0:e8fdba0ed044	1240	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
gkroussos	0:e8fdba0ed044	1241	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
gkroussos	0:e8fdba0ed044	1242
gkroussos	0:e8fdba0ed044	1243	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
gkroussos	0:e8fdba0ed044	1244	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
gkroussos	0:e8fdba0ed044	1245	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
gkroussos	0:e8fdba0ed044	1246	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
gkroussos	0:e8fdba0ed044	1247	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
gkroussos	0:e8fdba0ed044	1248	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
gkroussos	0:e8fdba0ed044	1249	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
gkroussos	0:e8fdba0ed044	1250	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
gkroussos	0:e8fdba0ed044	1251
gkroussos	0:e8fdba0ed044	1252	#if (__MPU_PRESENT == 1)
gkroussos	0:e8fdba0ed044	1253	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
gkroussos	0:e8fdba0ed044	1254	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
gkroussos	0:e8fdba0ed044	1255	#endif
gkroussos	0:e8fdba0ed044	1256
gkroussos	0:e8fdba0ed044	1257	/@} /
gkroussos	0:e8fdba0ed044	1258
gkroussos	0:e8fdba0ed044	1259
gkroussos	0:e8fdba0ed044	1260
gkroussos	0:e8fdba0ed044	1261	/*******************************************************************************
gkroussos	0:e8fdba0ed044	1262	* Hardware Abstraction Layer
gkroussos	0:e8fdba0ed044	1263	Core Function Interface contains:
gkroussos	0:e8fdba0ed044	1264	- Core NVIC Functions
gkroussos	0:e8fdba0ed044	1265	- Core SysTick Functions
gkroussos	0:e8fdba0ed044	1266	- Core Debug Functions
gkroussos	0:e8fdba0ed044	1267	- Core Register Access Functions
gkroussos	0:e8fdba0ed044	1268	******************************************************************************/
gkroussos	0:e8fdba0ed044	1269	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
gkroussos	0:e8fdba0ed044	1270	*/
gkroussos	0:e8fdba0ed044	1271
gkroussos	0:e8fdba0ed044	1272
gkroussos	0:e8fdba0ed044	1273
gkroussos	0:e8fdba0ed044	1274	/* ########################## NVIC functions #################################### */
gkroussos	0:e8fdba0ed044	1275	/** \ingroup CMSIS_Core_FunctionInterface
gkroussos	0:e8fdba0ed044	1276	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
gkroussos	0:e8fdba0ed044	1277	\brief Functions that manage interrupts and exceptions via the NVIC.
gkroussos	0:e8fdba0ed044	1278	@{
gkroussos	0:e8fdba0ed044	1279	*/
gkroussos	0:e8fdba0ed044	1280
gkroussos	0:e8fdba0ed044	1281	/** \brief Set Priority Grouping
gkroussos	0:e8fdba0ed044	1282
gkroussos	0:e8fdba0ed044	1283	The function sets the priority grouping field using the required unlock sequence.
gkroussos	0:e8fdba0ed044	1284	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
gkroussos	0:e8fdba0ed044	1285	Only values from 0..7 are used.
gkroussos	0:e8fdba0ed044	1286	In case of a conflict between priority grouping and available
gkroussos	0:e8fdba0ed044	1287	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
gkroussos	0:e8fdba0ed044	1288
gkroussos	0:e8fdba0ed044	1289	\param [in] PriorityGroup Priority grouping field.
gkroussos	0:e8fdba0ed044	1290	*/
gkroussos	0:e8fdba0ed044	1291	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
gkroussos	0:e8fdba0ed044	1292	{
gkroussos	0:e8fdba0ed044	1293	uint32_t reg_value;
gkroussos	0:e8fdba0ed044	1294	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
gkroussos	0:e8fdba0ed044	1295
gkroussos	0:e8fdba0ed044	1296	reg_value = SCB->AIRCR; /* read old register configuration */
gkroussos	0:e8fdba0ed044	1297	reg_value &= ~(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
gkroussos	0:e8fdba0ed044	1298	reg_value = (reg_value \|
gkroussos	0:e8fdba0ed044	1299	((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
gkroussos	0:e8fdba0ed044	1300	(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
gkroussos	0:e8fdba0ed044	1301	SCB->AIRCR = reg_value;
gkroussos	0:e8fdba0ed044	1302	}
gkroussos	0:e8fdba0ed044	1303
gkroussos	0:e8fdba0ed044	1304
gkroussos	0:e8fdba0ed044	1305	/** \brief Get Priority Grouping
gkroussos	0:e8fdba0ed044	1306
gkroussos	0:e8fdba0ed044	1307	The function reads the priority grouping field from the NVIC Interrupt Controller.
gkroussos	0:e8fdba0ed044	1308
gkroussos	0:e8fdba0ed044	1309	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
gkroussos	0:e8fdba0ed044	1310	*/
gkroussos	0:e8fdba0ed044	1311	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
gkroussos	0:e8fdba0ed044	1312	{
gkroussos	0:e8fdba0ed044	1313	return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
gkroussos	0:e8fdba0ed044	1314	}
gkroussos	0:e8fdba0ed044	1315
gkroussos	0:e8fdba0ed044	1316
gkroussos	0:e8fdba0ed044	1317	/** \brief Enable External Interrupt
gkroussos	0:e8fdba0ed044	1318
gkroussos	0:e8fdba0ed044	1319	The function enables a device-specific interrupt in the NVIC interrupt controller.
gkroussos	0:e8fdba0ed044	1320
gkroussos	0:e8fdba0ed044	1321	\param [in] IRQn External interrupt number. Value cannot be negative.
gkroussos	0:e8fdba0ed044	1322	*/
gkroussos	0:e8fdba0ed044	1323	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
gkroussos	0:e8fdba0ed044	1324	{
gkroussos	0:e8fdba0ed044	1325	NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
gkroussos	0:e8fdba0ed044	1326	}
gkroussos	0:e8fdba0ed044	1327
gkroussos	0:e8fdba0ed044	1328
gkroussos	0:e8fdba0ed044	1329	/** \brief Disable External Interrupt
gkroussos	0:e8fdba0ed044	1330
gkroussos	0:e8fdba0ed044	1331	The function disables a device-specific interrupt in the NVIC interrupt controller.
gkroussos	0:e8fdba0ed044	1332
gkroussos	0:e8fdba0ed044	1333	\param [in] IRQn External interrupt number. Value cannot be negative.
gkroussos	0:e8fdba0ed044	1334	*/
gkroussos	0:e8fdba0ed044	1335	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
gkroussos	0:e8fdba0ed044	1336	{
gkroussos	0:e8fdba0ed044	1337	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
gkroussos	0:e8fdba0ed044	1338	}
gkroussos	0:e8fdba0ed044	1339
gkroussos	0:e8fdba0ed044	1340
gkroussos	0:e8fdba0ed044	1341	/** \brief Get Pending Interrupt
gkroussos	0:e8fdba0ed044	1342
gkroussos	0:e8fdba0ed044	1343	The function reads the pending register in the NVIC and returns the pending bit
gkroussos	0:e8fdba0ed044	1344	for the specified interrupt.
gkroussos	0:e8fdba0ed044	1345
gkroussos	0:e8fdba0ed044	1346	\param [in] IRQn Interrupt number.
gkroussos	0:e8fdba0ed044	1347
gkroussos	0:e8fdba0ed044	1348	\return 0 Interrupt status is not pending.
gkroussos	0:e8fdba0ed044	1349	\return 1 Interrupt status is pending.
gkroussos	0:e8fdba0ed044	1350	*/
gkroussos	0:e8fdba0ed044	1351	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
gkroussos	0:e8fdba0ed044	1352	{
gkroussos	0:e8fdba0ed044	1353	return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
gkroussos	0:e8fdba0ed044	1354	}
gkroussos	0:e8fdba0ed044	1355
gkroussos	0:e8fdba0ed044	1356
gkroussos	0:e8fdba0ed044	1357	/** \brief Set Pending Interrupt
gkroussos	0:e8fdba0ed044	1358
gkroussos	0:e8fdba0ed044	1359	The function sets the pending bit of an external interrupt.
gkroussos	0:e8fdba0ed044	1360
gkroussos	0:e8fdba0ed044	1361	\param [in] IRQn Interrupt number. Value cannot be negative.
gkroussos	0:e8fdba0ed044	1362	*/
gkroussos	0:e8fdba0ed044	1363	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
gkroussos	0:e8fdba0ed044	1364	{
gkroussos	0:e8fdba0ed044	1365	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
gkroussos	0:e8fdba0ed044	1366	}
gkroussos	0:e8fdba0ed044	1367
gkroussos	0:e8fdba0ed044	1368
gkroussos	0:e8fdba0ed044	1369	/** \brief Clear Pending Interrupt
gkroussos	0:e8fdba0ed044	1370
gkroussos	0:e8fdba0ed044	1371	The function clears the pending bit of an external interrupt.
gkroussos	0:e8fdba0ed044	1372
gkroussos	0:e8fdba0ed044	1373	\param [in] IRQn External interrupt number. Value cannot be negative.
gkroussos	0:e8fdba0ed044	1374	*/
gkroussos	0:e8fdba0ed044	1375	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
gkroussos	0:e8fdba0ed044	1376	{
gkroussos	0:e8fdba0ed044	1377	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
gkroussos	0:e8fdba0ed044	1378	}
gkroussos	0:e8fdba0ed044	1379
gkroussos	0:e8fdba0ed044	1380
gkroussos	0:e8fdba0ed044	1381	/** \brief Get Active Interrupt
gkroussos	0:e8fdba0ed044	1382
gkroussos	0:e8fdba0ed044	1383	The function reads the active register in NVIC and returns the active bit.
gkroussos	0:e8fdba0ed044	1384
gkroussos	0:e8fdba0ed044	1385	\param [in] IRQn Interrupt number.
gkroussos	0:e8fdba0ed044	1386
gkroussos	0:e8fdba0ed044	1387	\return 0 Interrupt status is not active.
gkroussos	0:e8fdba0ed044	1388	\return 1 Interrupt status is active.
gkroussos	0:e8fdba0ed044	1389	*/
gkroussos	0:e8fdba0ed044	1390	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
gkroussos	0:e8fdba0ed044	1391	{
gkroussos	0:e8fdba0ed044	1392	return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
gkroussos	0:e8fdba0ed044	1393	}
gkroussos	0:e8fdba0ed044	1394
gkroussos	0:e8fdba0ed044	1395
gkroussos	0:e8fdba0ed044	1396	/** \brief Set Interrupt Priority
gkroussos	0:e8fdba0ed044	1397
gkroussos	0:e8fdba0ed044	1398	The function sets the priority of an interrupt.
gkroussos	0:e8fdba0ed044	1399
gkroussos	0:e8fdba0ed044	1400	\note The priority cannot be set for every core interrupt.
gkroussos	0:e8fdba0ed044	1401
gkroussos	0:e8fdba0ed044	1402	\param [in] IRQn Interrupt number.
gkroussos	0:e8fdba0ed044	1403	\param [in] priority Priority to set.
gkroussos	0:e8fdba0ed044	1404	*/
gkroussos	0:e8fdba0ed044	1405	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
gkroussos	0:e8fdba0ed044	1406	{
gkroussos	0:e8fdba0ed044	1407	if(IRQn < 0) {
gkroussos	0:e8fdba0ed044	1408	SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
gkroussos	0:e8fdba0ed044	1409	else {
gkroussos	0:e8fdba0ed044	1410	NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
gkroussos	0:e8fdba0ed044	1411	}
gkroussos	0:e8fdba0ed044	1412
gkroussos	0:e8fdba0ed044	1413
gkroussos	0:e8fdba0ed044	1414	/** \brief Get Interrupt Priority
gkroussos	0:e8fdba0ed044	1415
gkroussos	0:e8fdba0ed044	1416	The function reads the priority of an interrupt. The interrupt
gkroussos	0:e8fdba0ed044	1417	number can be positive to specify an external (device specific)
gkroussos	0:e8fdba0ed044	1418	interrupt, or negative to specify an internal (core) interrupt.
gkroussos	0:e8fdba0ed044	1419
gkroussos	0:e8fdba0ed044	1420
gkroussos	0:e8fdba0ed044	1421	\param [in] IRQn Interrupt number.
gkroussos	0:e8fdba0ed044	1422	\return Interrupt Priority. Value is aligned automatically to the implemented
gkroussos	0:e8fdba0ed044	1423	priority bits of the microcontroller.
gkroussos	0:e8fdba0ed044	1424	*/
gkroussos	0:e8fdba0ed044	1425	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
gkroussos	0:e8fdba0ed044	1426	{
gkroussos	0:e8fdba0ed044	1427
gkroussos	0:e8fdba0ed044	1428	if(IRQn < 0) {
gkroussos	0:e8fdba0ed044	1429	return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
gkroussos	0:e8fdba0ed044	1430	else {
gkroussos	0:e8fdba0ed044	1431	return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
gkroussos	0:e8fdba0ed044	1432	}
gkroussos	0:e8fdba0ed044	1433
gkroussos	0:e8fdba0ed044	1434
gkroussos	0:e8fdba0ed044	1435	/** \brief Encode Priority
gkroussos	0:e8fdba0ed044	1436
gkroussos	0:e8fdba0ed044	1437	The function encodes the priority for an interrupt with the given priority group,
gkroussos	0:e8fdba0ed044	1438	preemptive priority value, and subpriority value.
gkroussos	0:e8fdba0ed044	1439	In case of a conflict between priority grouping and available
gkroussos	0:e8fdba0ed044	1440	priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
gkroussos	0:e8fdba0ed044	1441
gkroussos	0:e8fdba0ed044	1442	\param [in] PriorityGroup Used priority group.
gkroussos	0:e8fdba0ed044	1443	\param [in] PreemptPriority Preemptive priority value (starting from 0).
gkroussos	0:e8fdba0ed044	1444	\param [in] SubPriority Subpriority value (starting from 0).
gkroussos	0:e8fdba0ed044	1445	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
gkroussos	0:e8fdba0ed044	1446	*/
gkroussos	0:e8fdba0ed044	1447	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
gkroussos	0:e8fdba0ed044	1448	{
gkroussos	0:e8fdba0ed044	1449	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
gkroussos	0:e8fdba0ed044	1450	uint32_t PreemptPriorityBits;
gkroussos	0:e8fdba0ed044	1451	uint32_t SubPriorityBits;
gkroussos	0:e8fdba0ed044	1452
gkroussos	0:e8fdba0ed044	1453	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
gkroussos	0:e8fdba0ed044	1454	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
gkroussos	0:e8fdba0ed044	1455
gkroussos	0:e8fdba0ed044	1456	return (
gkroussos	0:e8fdba0ed044	1457	((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) \|
gkroussos	0:e8fdba0ed044	1458	((SubPriority & ((1 << (SubPriorityBits )) - 1)))
gkroussos	0:e8fdba0ed044	1459	);
gkroussos	0:e8fdba0ed044	1460	}
gkroussos	0:e8fdba0ed044	1461
gkroussos	0:e8fdba0ed044	1462
gkroussos	0:e8fdba0ed044	1463	/** \brief Decode Priority
gkroussos	0:e8fdba0ed044	1464
gkroussos	0:e8fdba0ed044	1465	The function decodes an interrupt priority value with a given priority group to
gkroussos	0:e8fdba0ed044	1466	preemptive priority value and subpriority value.
gkroussos	0:e8fdba0ed044	1467	In case of a conflict between priority grouping and available
gkroussos	0:e8fdba0ed044	1468	priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
gkroussos	0:e8fdba0ed044	1469
gkroussos	0:e8fdba0ed044	1470	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
gkroussos	0:e8fdba0ed044	1471	\param [in] PriorityGroup Used priority group.
gkroussos	0:e8fdba0ed044	1472	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
gkroussos	0:e8fdba0ed044	1473	\param [out] pSubPriority Subpriority value (starting from 0).
gkroussos	0:e8fdba0ed044	1474	*/
gkroussos	0:e8fdba0ed044	1475	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
gkroussos	0:e8fdba0ed044	1476	{
gkroussos	0:e8fdba0ed044	1477	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
gkroussos	0:e8fdba0ed044	1478	uint32_t PreemptPriorityBits;
gkroussos	0:e8fdba0ed044	1479	uint32_t SubPriorityBits;
gkroussos	0:e8fdba0ed044	1480
gkroussos	0:e8fdba0ed044	1481	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
gkroussos	0:e8fdba0ed044	1482	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
gkroussos	0:e8fdba0ed044	1483
gkroussos	0:e8fdba0ed044	1484	*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
gkroussos	0:e8fdba0ed044	1485	*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
gkroussos	0:e8fdba0ed044	1486	}
gkroussos	0:e8fdba0ed044	1487
gkroussos	0:e8fdba0ed044	1488
gkroussos	0:e8fdba0ed044	1489	/** \brief System Reset
gkroussos	0:e8fdba0ed044	1490
gkroussos	0:e8fdba0ed044	1491	The function initiates a system reset request to reset the MCU.
gkroussos	0:e8fdba0ed044	1492	*/
gkroussos	0:e8fdba0ed044	1493	__STATIC_INLINE void NVIC_SystemReset(void)
gkroussos	0:e8fdba0ed044	1494	{
gkroussos	0:e8fdba0ed044	1495	__DSB(); /* Ensure all outstanding memory accesses included
gkroussos	0:e8fdba0ed044	1496	buffered write are completed before reset */
gkroussos	0:e8fdba0ed044	1497	SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
gkroussos	0:e8fdba0ed044	1498	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
gkroussos	0:e8fdba0ed044	1499	SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
gkroussos	0:e8fdba0ed044	1500	__DSB(); /* Ensure completion of memory access */
gkroussos	0:e8fdba0ed044	1501	while(1); /* wait until reset */
gkroussos	0:e8fdba0ed044	1502	}
gkroussos	0:e8fdba0ed044	1503
gkroussos	0:e8fdba0ed044	1504	/@} end of CMSIS_Core_NVICFunctions /
gkroussos	0:e8fdba0ed044	1505
gkroussos	0:e8fdba0ed044	1506
gkroussos	0:e8fdba0ed044	1507
gkroussos	0:e8fdba0ed044	1508	/* ################################## SysTick function ############################################ */
gkroussos	0:e8fdba0ed044	1509	/** \ingroup CMSIS_Core_FunctionInterface
gkroussos	0:e8fdba0ed044	1510	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
gkroussos	0:e8fdba0ed044	1511	\brief Functions that configure the System.
gkroussos	0:e8fdba0ed044	1512	@{
gkroussos	0:e8fdba0ed044	1513	*/
gkroussos	0:e8fdba0ed044	1514
gkroussos	0:e8fdba0ed044	1515	#if (__Vendor_SysTickConfig == 0)
gkroussos	0:e8fdba0ed044	1516
gkroussos	0:e8fdba0ed044	1517	/** \brief System Tick Configuration
gkroussos	0:e8fdba0ed044	1518
gkroussos	0:e8fdba0ed044	1519	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
gkroussos	0:e8fdba0ed044	1520	Counter is in free running mode to generate periodic interrupts.
gkroussos	0:e8fdba0ed044	1521
gkroussos	0:e8fdba0ed044	1522	\param [in] ticks Number of ticks between two interrupts.
gkroussos	0:e8fdba0ed044	1523
gkroussos	0:e8fdba0ed044	1524	\return 0 Function succeeded.
gkroussos	0:e8fdba0ed044	1525	\return 1 Function failed.
gkroussos	0:e8fdba0ed044	1526
gkroussos	0:e8fdba0ed044	1527	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
gkroussos	0:e8fdba0ed044	1528	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
gkroussos	0:e8fdba0ed044	1529	must contain a vendor-specific implementation of this function.
gkroussos	0:e8fdba0ed044	1530
gkroussos	0:e8fdba0ed044	1531	*/
gkroussos	0:e8fdba0ed044	1532	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
gkroussos	0:e8fdba0ed044	1533	{
gkroussos	0:e8fdba0ed044	1534	if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
gkroussos	0:e8fdba0ed044	1535
gkroussos	0:e8fdba0ed044	1536	SysTick->LOAD = ticks - 1; /* set reload register */
gkroussos	0:e8fdba0ed044	1537	NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
gkroussos	0:e8fdba0ed044	1538	SysTick->VAL = 0; /* Load the SysTick Counter Value */
gkroussos	0:e8fdba0ed044	1539	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
gkroussos	0:e8fdba0ed044	1540	SysTick_CTRL_TICKINT_Msk \|
gkroussos	0:e8fdba0ed044	1541	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
gkroussos	0:e8fdba0ed044	1542	return (0); /* Function successful */
gkroussos	0:e8fdba0ed044	1543	}
gkroussos	0:e8fdba0ed044	1544
gkroussos	0:e8fdba0ed044	1545	#endif
gkroussos	0:e8fdba0ed044	1546
gkroussos	0:e8fdba0ed044	1547	/@} end of CMSIS_Core_SysTickFunctions /
gkroussos	0:e8fdba0ed044	1548
gkroussos	0:e8fdba0ed044	1549
gkroussos	0:e8fdba0ed044	1550
gkroussos	0:e8fdba0ed044	1551	/* ##################################### Debug In/Output function ########################################### */
gkroussos	0:e8fdba0ed044	1552	/** \ingroup CMSIS_Core_FunctionInterface
gkroussos	0:e8fdba0ed044	1553	\defgroup CMSIS_core_DebugFunctions ITM Functions
gkroussos	0:e8fdba0ed044	1554	\brief Functions that access the ITM debug interface.
gkroussos	0:e8fdba0ed044	1555	@{
gkroussos	0:e8fdba0ed044	1556	*/
gkroussos	0:e8fdba0ed044	1557
gkroussos	0:e8fdba0ed044	1558	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
gkroussos	0:e8fdba0ed044	1559	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
gkroussos	0:e8fdba0ed044	1560
gkroussos	0:e8fdba0ed044	1561
gkroussos	0:e8fdba0ed044	1562	/** \brief ITM Send Character
gkroussos	0:e8fdba0ed044	1563
gkroussos	0:e8fdba0ed044	1564	The function transmits a character via the ITM channel 0, and
gkroussos	0:e8fdba0ed044	1565	\li Just returns when no debugger is connected that has booked the output.
gkroussos	0:e8fdba0ed044	1566	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
gkroussos	0:e8fdba0ed044	1567
gkroussos	0:e8fdba0ed044	1568	\param [in] ch Character to transmit.
gkroussos	0:e8fdba0ed044	1569
gkroussos	0:e8fdba0ed044	1570	\returns Character to transmit.
gkroussos	0:e8fdba0ed044	1571	*/
gkroussos	0:e8fdba0ed044	1572	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
gkroussos	0:e8fdba0ed044	1573	{
gkroussos	0:e8fdba0ed044	1574	if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
gkroussos	0:e8fdba0ed044	1575	(ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
gkroussos	0:e8fdba0ed044	1576	{
gkroussos	0:e8fdba0ed044	1577	while (ITM->PORT[0].u32 == 0);
gkroussos	0:e8fdba0ed044	1578	ITM->PORT[0].u8 = (uint8_t) ch;
gkroussos	0:e8fdba0ed044	1579	}
gkroussos	0:e8fdba0ed044	1580	return (ch);
gkroussos	0:e8fdba0ed044	1581	}
gkroussos	0:e8fdba0ed044	1582
gkroussos	0:e8fdba0ed044	1583
gkroussos	0:e8fdba0ed044	1584	/** \brief ITM Receive Character
gkroussos	0:e8fdba0ed044	1585
gkroussos	0:e8fdba0ed044	1586	The function inputs a character via the external variable \ref ITM_RxBuffer.
gkroussos	0:e8fdba0ed044	1587
gkroussos	0:e8fdba0ed044	1588	\return Received character.
gkroussos	0:e8fdba0ed044	1589	\return -1 No character pending.
gkroussos	0:e8fdba0ed044	1590	*/
gkroussos	0:e8fdba0ed044	1591	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
gkroussos	0:e8fdba0ed044	1592	int32_t ch = -1; /* no character available */
gkroussos	0:e8fdba0ed044	1593
gkroussos	0:e8fdba0ed044	1594	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
gkroussos	0:e8fdba0ed044	1595	ch = ITM_RxBuffer;
gkroussos	0:e8fdba0ed044	1596	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
gkroussos	0:e8fdba0ed044	1597	}
gkroussos	0:e8fdba0ed044	1598
gkroussos	0:e8fdba0ed044	1599	return (ch);
gkroussos	0:e8fdba0ed044	1600	}
gkroussos	0:e8fdba0ed044	1601
gkroussos	0:e8fdba0ed044	1602
gkroussos	0:e8fdba0ed044	1603	/** \brief ITM Check Character
gkroussos	0:e8fdba0ed044	1604
gkroussos	0:e8fdba0ed044	1605	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
gkroussos	0:e8fdba0ed044	1606
gkroussos	0:e8fdba0ed044	1607	\return 0 No character available.
gkroussos	0:e8fdba0ed044	1608	\return 1 Character available.
gkroussos	0:e8fdba0ed044	1609	*/
gkroussos	0:e8fdba0ed044	1610	__STATIC_INLINE int32_t ITM_CheckChar (void) {
gkroussos	0:e8fdba0ed044	1611
gkroussos	0:e8fdba0ed044	1612	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
gkroussos	0:e8fdba0ed044	1613	return (0); /* no character available */
gkroussos	0:e8fdba0ed044	1614	} else {
gkroussos	0:e8fdba0ed044	1615	return (1); /* character available */
gkroussos	0:e8fdba0ed044	1616	}
gkroussos	0:e8fdba0ed044	1617	}
gkroussos	0:e8fdba0ed044	1618
gkroussos	0:e8fdba0ed044	1619	/@} end of CMSIS_core_DebugFunctions /
gkroussos	0:e8fdba0ed044	1620
gkroussos	0:e8fdba0ed044	1621	#endif /* __CORE_CM3_H_DEPENDANT */
gkroussos	0:e8fdba0ed044	1622
gkroussos	0:e8fdba0ed044	1623	#endif /* __CMSIS_GENERIC */
gkroussos	0:e8fdba0ed044	1624
gkroussos	0:e8fdba0ed044	1625	#ifdef __cplusplus
gkroussos	0:e8fdba0ed044	1626	}
gkroussos	0:e8fdba0ed044	1627	#endif

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Type:	Program
Created:	07 Mar 2015
Imports:	47
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	4

The code in this repository is Apache licensed.

mbed/TARGET_NRF51822/core_cm3.h@0:e8fdba0ed044, 2015-03-07 (annotated)

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