George Roussos
BLE Temperature Service Mobile and Ubiquitous Computing Module Birkbeck College
mbed/TARGET_NRF51822/nrf_soc.h@0:dd0fea342ad2, 2015-03-08 (annotated)
- Committer:
- gkroussos
- Date:
- Sun Mar 08 19:42:20 2015 +0000
- Revision:
- 0:dd0fea342ad2
BLE Temperature Service ; Mobile and Ubiquitous Computing Module; Birkbeck College
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| gkroussos | 0:dd0fea342ad2 | 1 | /* Copyright (c) 2011 Nordic Semiconductor. All Rights Reserved. |
| gkroussos | 0:dd0fea342ad2 | 2 | * |
| gkroussos | 0:dd0fea342ad2 | 3 | * The information contained herein is confidential property of Nordic Semiconductor. The use, |
| gkroussos | 0:dd0fea342ad2 | 4 | * copying, transfer or disclosure of such information is prohibited except by express written |
| gkroussos | 0:dd0fea342ad2 | 5 | * agreement with Nordic Semiconductor. |
| gkroussos | 0:dd0fea342ad2 | 6 | * |
| gkroussos | 0:dd0fea342ad2 | 7 | */ |
| gkroussos | 0:dd0fea342ad2 | 8 | |
| gkroussos | 0:dd0fea342ad2 | 9 | /** |
| gkroussos | 0:dd0fea342ad2 | 10 | @defgroup nrf_soc_api SoC Library API |
| gkroussos | 0:dd0fea342ad2 | 11 | @{ |
| gkroussos | 0:dd0fea342ad2 | 12 | |
| gkroussos | 0:dd0fea342ad2 | 13 | @brief APIs for the SoC library. |
| gkroussos | 0:dd0fea342ad2 | 14 | |
| gkroussos | 0:dd0fea342ad2 | 15 | */ |
| gkroussos | 0:dd0fea342ad2 | 16 | |
| gkroussos | 0:dd0fea342ad2 | 17 | #ifndef NRF_SOC_H__ |
| gkroussos | 0:dd0fea342ad2 | 18 | #define NRF_SOC_H__ |
| gkroussos | 0:dd0fea342ad2 | 19 | |
| gkroussos | 0:dd0fea342ad2 | 20 | #include <stdint.h> |
| gkroussos | 0:dd0fea342ad2 | 21 | #include <stdbool.h> |
| gkroussos | 0:dd0fea342ad2 | 22 | #include "nrf_svc.h" |
| gkroussos | 0:dd0fea342ad2 | 23 | #include "nrf51.h" |
| gkroussos | 0:dd0fea342ad2 | 24 | #include "nrf51_bitfields.h" |
| gkroussos | 0:dd0fea342ad2 | 25 | #include "nrf_error_soc.h" |
| gkroussos | 0:dd0fea342ad2 | 26 | |
| gkroussos | 0:dd0fea342ad2 | 27 | /** @addtogroup NRF_SOC_DEFINES Defines |
| gkroussos | 0:dd0fea342ad2 | 28 | * @{ */ |
| gkroussos | 0:dd0fea342ad2 | 29 | |
| gkroussos | 0:dd0fea342ad2 | 30 | /**@brief The number of the lowest SVC number reserved for the SoC library. */ |
| gkroussos | 0:dd0fea342ad2 | 31 | #define SOC_SVC_BASE 0x20 |
| gkroussos | 0:dd0fea342ad2 | 32 | |
| gkroussos | 0:dd0fea342ad2 | 33 | /**@brief Guranteed time for application to process radio inactive notification. */ |
| gkroussos | 0:dd0fea342ad2 | 34 | #define NRF_RADIO_NOTIFICATION_INACTIVE_GUARANTEED_TIME_US (62) |
| gkroussos | 0:dd0fea342ad2 | 35 | |
| gkroussos | 0:dd0fea342ad2 | 36 | #define SOC_ECB_KEY_LENGTH (16) /**< ECB key length. */ |
| gkroussos | 0:dd0fea342ad2 | 37 | #define SOC_ECB_CLEARTEXT_LENGTH (16) /**< ECB cleartext length. */ |
| gkroussos | 0:dd0fea342ad2 | 38 | #define SOC_ECB_CIPHERTEXT_LENGTH (SOC_ECB_CLEARTEXT_LENGTH) /**< ECB ciphertext length. */ |
| gkroussos | 0:dd0fea342ad2 | 39 | |
| gkroussos | 0:dd0fea342ad2 | 40 | #define SD_EVT_IRQn (SWI2_IRQn) /**< SoftDevice Event IRQ number. Used for both protocol events and SoC events. */ |
| gkroussos | 0:dd0fea342ad2 | 41 | #define SD_EVT_IRQHandler (SWI2_IRQHandler) /**< SoftDevice Event IRQ handler. Used for both protocol events and SoC events. */ |
| gkroussos | 0:dd0fea342ad2 | 42 | #define RADIO_NOTIFICATION_IRQn (SWI1_IRQn) /**< The radio notification IRQ number. */ |
| gkroussos | 0:dd0fea342ad2 | 43 | #define RADIO_NOTIFICATION_IRQHandler (SWI1_IRQHandler) /**< The radio notification IRQ handler. */ |
| gkroussos | 0:dd0fea342ad2 | 44 | |
| gkroussos | 0:dd0fea342ad2 | 45 | /** @} */ |
| gkroussos | 0:dd0fea342ad2 | 46 | |
| gkroussos | 0:dd0fea342ad2 | 47 | /** @addtogroup NRF_SOC_TYPES Types |
| gkroussos | 0:dd0fea342ad2 | 48 | * @{ */ |
| gkroussos | 0:dd0fea342ad2 | 49 | |
| gkroussos | 0:dd0fea342ad2 | 50 | /**@brief The SVC numbers used by the SVC functions in the SoC library. */ |
| gkroussos | 0:dd0fea342ad2 | 51 | enum NRF_SOC_SVCS |
| gkroussos | 0:dd0fea342ad2 | 52 | { |
| gkroussos | 0:dd0fea342ad2 | 53 | SD_MUTEX_NEW = SOC_SVC_BASE, |
| gkroussos | 0:dd0fea342ad2 | 54 | SD_MUTEX_ACQUIRE, |
| gkroussos | 0:dd0fea342ad2 | 55 | SD_MUTEX_RELEASE, |
| gkroussos | 0:dd0fea342ad2 | 56 | SD_NVIC_ENABLEIRQ, |
| gkroussos | 0:dd0fea342ad2 | 57 | SD_NVIC_DISABLEIRQ, |
| gkroussos | 0:dd0fea342ad2 | 58 | SD_NVIC_GETPENDINGIRQ, |
| gkroussos | 0:dd0fea342ad2 | 59 | SD_NVIC_SETPENDINGIRQ, |
| gkroussos | 0:dd0fea342ad2 | 60 | SD_NVIC_CLEARPENDINGIRQ, |
| gkroussos | 0:dd0fea342ad2 | 61 | SD_NVIC_SETPRIORITY, |
| gkroussos | 0:dd0fea342ad2 | 62 | SD_NVIC_GETPRIORITY, |
| gkroussos | 0:dd0fea342ad2 | 63 | SD_NVIC_SYSTEMRESET, |
| gkroussos | 0:dd0fea342ad2 | 64 | SD_NVIC_CRITICAL_REGION_ENTER, |
| gkroussos | 0:dd0fea342ad2 | 65 | SD_NVIC_CRITICAL_REGION_EXIT, |
| gkroussos | 0:dd0fea342ad2 | 66 | SD_RAND_APPLICATION_POOL_CAPACITY, |
| gkroussos | 0:dd0fea342ad2 | 67 | SD_RAND_APPLICATION_BYTES_AVAILABLE, |
| gkroussos | 0:dd0fea342ad2 | 68 | SD_RAND_APPLICATION_GET_VECTOR, |
| gkroussos | 0:dd0fea342ad2 | 69 | SD_POWER_MODE_SET, |
| gkroussos | 0:dd0fea342ad2 | 70 | SD_POWER_SYSTEM_OFF, |
| gkroussos | 0:dd0fea342ad2 | 71 | SD_POWER_RESET_REASON_GET, |
| gkroussos | 0:dd0fea342ad2 | 72 | SD_POWER_RESET_REASON_CLR, |
| gkroussos | 0:dd0fea342ad2 | 73 | SD_POWER_POF_ENABLE, |
| gkroussos | 0:dd0fea342ad2 | 74 | SD_POWER_POF_THRESHOLD_SET, |
| gkroussos | 0:dd0fea342ad2 | 75 | SD_POWER_RAMON_SET, |
| gkroussos | 0:dd0fea342ad2 | 76 | SD_POWER_RAMON_CLR, |
| gkroussos | 0:dd0fea342ad2 | 77 | SD_POWER_RAMON_GET, |
| gkroussos | 0:dd0fea342ad2 | 78 | SD_POWER_GPREGRET_SET, |
| gkroussos | 0:dd0fea342ad2 | 79 | SD_POWER_GPREGRET_CLR, |
| gkroussos | 0:dd0fea342ad2 | 80 | SD_POWER_GPREGRET_GET, |
| gkroussos | 0:dd0fea342ad2 | 81 | SD_POWER_DCDC_MODE_SET, |
| gkroussos | 0:dd0fea342ad2 | 82 | SD_APP_EVT_WAIT, |
| gkroussos | 0:dd0fea342ad2 | 83 | SD_CLOCK_HFCLK_REQUEST, |
| gkroussos | 0:dd0fea342ad2 | 84 | SD_CLOCK_HFCLK_RELEASE, |
| gkroussos | 0:dd0fea342ad2 | 85 | SD_CLOCK_HFCLK_IS_RUNNING, |
| gkroussos | 0:dd0fea342ad2 | 86 | SD_PPI_CHANNEL_ENABLE_GET, |
| gkroussos | 0:dd0fea342ad2 | 87 | SD_PPI_CHANNEL_ENABLE_SET, |
| gkroussos | 0:dd0fea342ad2 | 88 | SD_PPI_CHANNEL_ENABLE_CLR, |
| gkroussos | 0:dd0fea342ad2 | 89 | SD_PPI_CHANNEL_ASSIGN, |
| gkroussos | 0:dd0fea342ad2 | 90 | SD_PPI_GROUP_TASK_ENABLE, |
| gkroussos | 0:dd0fea342ad2 | 91 | SD_PPI_GROUP_TASK_DISABLE, |
| gkroussos | 0:dd0fea342ad2 | 92 | SD_PPI_GROUP_ASSIGN, |
| gkroussos | 0:dd0fea342ad2 | 93 | SD_PPI_GROUP_GET, |
| gkroussos | 0:dd0fea342ad2 | 94 | SD_RADIO_NOTIFICATION_CFG_SET, |
| gkroussos | 0:dd0fea342ad2 | 95 | SD_ECB_BLOCK_ENCRYPT, |
| gkroussos | 0:dd0fea342ad2 | 96 | SD_RESERVED1, |
| gkroussos | 0:dd0fea342ad2 | 97 | SD_RESERVED2, |
| gkroussos | 0:dd0fea342ad2 | 98 | SD_RESERVED3, |
| gkroussos | 0:dd0fea342ad2 | 99 | SD_EVT_GET, |
| gkroussos | 0:dd0fea342ad2 | 100 | SD_TEMP_GET, |
| gkroussos | 0:dd0fea342ad2 | 101 | SD_FLASH_ERASE_PAGE, |
| gkroussos | 0:dd0fea342ad2 | 102 | SD_FLASH_WRITE, |
| gkroussos | 0:dd0fea342ad2 | 103 | SD_FLASH_PROTECT, |
| gkroussos | 0:dd0fea342ad2 | 104 | SVC_SOC_LAST |
| gkroussos | 0:dd0fea342ad2 | 105 | }; |
| gkroussos | 0:dd0fea342ad2 | 106 | |
| gkroussos | 0:dd0fea342ad2 | 107 | /**@brief Possible values of a ::nrf_mutex_t. */ |
| gkroussos | 0:dd0fea342ad2 | 108 | enum NRF_MUTEX_VALUES |
| gkroussos | 0:dd0fea342ad2 | 109 | { |
| gkroussos | 0:dd0fea342ad2 | 110 | NRF_MUTEX_FREE, |
| gkroussos | 0:dd0fea342ad2 | 111 | NRF_MUTEX_TAKEN |
| gkroussos | 0:dd0fea342ad2 | 112 | }; |
| gkroussos | 0:dd0fea342ad2 | 113 | |
| gkroussos | 0:dd0fea342ad2 | 114 | /**@brief Possible values of ::nrf_app_irq_priority_t. */ |
| gkroussos | 0:dd0fea342ad2 | 115 | enum NRF_APP_PRIORITIES |
| gkroussos | 0:dd0fea342ad2 | 116 | { |
| gkroussos | 0:dd0fea342ad2 | 117 | NRF_APP_PRIORITY_HIGH = 1, |
| gkroussos | 0:dd0fea342ad2 | 118 | NRF_APP_PRIORITY_LOW = 3 |
| gkroussos | 0:dd0fea342ad2 | 119 | }; |
| gkroussos | 0:dd0fea342ad2 | 120 | |
| gkroussos | 0:dd0fea342ad2 | 121 | /**@brief Possible values of ::nrf_power_mode_t. */ |
| gkroussos | 0:dd0fea342ad2 | 122 | enum NRF_POWER_MODES |
| gkroussos | 0:dd0fea342ad2 | 123 | { |
| gkroussos | 0:dd0fea342ad2 | 124 | NRF_POWER_MODE_CONSTLAT, /**< Constant latency mode. See power management in the reference manual. */ |
| gkroussos | 0:dd0fea342ad2 | 125 | NRF_POWER_MODE_LOWPWR /**< Low power mode. See power management in the reference manual. */ |
| gkroussos | 0:dd0fea342ad2 | 126 | }; |
| gkroussos | 0:dd0fea342ad2 | 127 | |
| gkroussos | 0:dd0fea342ad2 | 128 | |
| gkroussos | 0:dd0fea342ad2 | 129 | /**@brief Possible values of ::nrf_power_failure_threshold_t */ |
| gkroussos | 0:dd0fea342ad2 | 130 | enum NRF_POWER_THRESHOLDS |
| gkroussos | 0:dd0fea342ad2 | 131 | { |
| gkroussos | 0:dd0fea342ad2 | 132 | NRF_POWER_THRESHOLD_V21, /**< 2.1 Volts power failure threshold. */ |
| gkroussos | 0:dd0fea342ad2 | 133 | NRF_POWER_THRESHOLD_V23, /**< 2.3 Volts power failure threshold. */ |
| gkroussos | 0:dd0fea342ad2 | 134 | NRF_POWER_THRESHOLD_V25, /**< 2.5 Volts power failure threshold. */ |
| gkroussos | 0:dd0fea342ad2 | 135 | NRF_POWER_THRESHOLD_V27 /**< 2.7 Volts power failure threshold. */ |
| gkroussos | 0:dd0fea342ad2 | 136 | }; |
| gkroussos | 0:dd0fea342ad2 | 137 | |
| gkroussos | 0:dd0fea342ad2 | 138 | |
| gkroussos | 0:dd0fea342ad2 | 139 | /**@brief Possible values of ::nrf_power_dcdc_mode_t. */ |
| gkroussos | 0:dd0fea342ad2 | 140 | enum NRF_POWER_DCDC_MODES |
| gkroussos | 0:dd0fea342ad2 | 141 | { |
| gkroussos | 0:dd0fea342ad2 | 142 | NRF_POWER_DCDC_MODE_OFF, /**< The DCDC is always off. */ |
| gkroussos | 0:dd0fea342ad2 | 143 | NRF_POWER_DCDC_MODE_ON, /**< The DCDC is always on. */ |
| gkroussos | 0:dd0fea342ad2 | 144 | NRF_POWER_DCDC_MODE_AUTOMATIC /**< The DCDC is automatically managed. */ |
| gkroussos | 0:dd0fea342ad2 | 145 | }; |
| gkroussos | 0:dd0fea342ad2 | 146 | |
| gkroussos | 0:dd0fea342ad2 | 147 | /**@brief Possible values of ::nrf_radio_notification_distance_t. */ |
| gkroussos | 0:dd0fea342ad2 | 148 | enum NRF_RADIO_NOTIFICATION_DISTANCES |
| gkroussos | 0:dd0fea342ad2 | 149 | { |
| gkroussos | 0:dd0fea342ad2 | 150 | NRF_RADIO_NOTIFICATION_DISTANCE_NONE = 0, /**< The event does not have a notification. */ |
| gkroussos | 0:dd0fea342ad2 | 151 | NRF_RADIO_NOTIFICATION_DISTANCE_800US, /**< The distance from the active notification to start of radio activity. */ |
| gkroussos | 0:dd0fea342ad2 | 152 | NRF_RADIO_NOTIFICATION_DISTANCE_1740US, /**< The distance from the active notification to start of radio activity. */ |
| gkroussos | 0:dd0fea342ad2 | 153 | NRF_RADIO_NOTIFICATION_DISTANCE_2680US, /**< The distance from the active notification to start of radio activity. */ |
| gkroussos | 0:dd0fea342ad2 | 154 | NRF_RADIO_NOTIFICATION_DISTANCE_3620US, /**< The distance from the active notification to start of radio activity. */ |
| gkroussos | 0:dd0fea342ad2 | 155 | NRF_RADIO_NOTIFICATION_DISTANCE_4560US, /**< The distance from the active notification to start of radio activity. */ |
| gkroussos | 0:dd0fea342ad2 | 156 | NRF_RADIO_NOTIFICATION_DISTANCE_5500US /**< The distance from the active notification to start of radio activity. */ |
| gkroussos | 0:dd0fea342ad2 | 157 | }; |
| gkroussos | 0:dd0fea342ad2 | 158 | |
| gkroussos | 0:dd0fea342ad2 | 159 | |
| gkroussos | 0:dd0fea342ad2 | 160 | /**@brief Possible values of ::nrf_radio_notification_type_t. */ |
| gkroussos | 0:dd0fea342ad2 | 161 | enum NRF_RADIO_NOTIFICATION_TYPES |
| gkroussos | 0:dd0fea342ad2 | 162 | { |
| gkroussos | 0:dd0fea342ad2 | 163 | NRF_RADIO_NOTIFICATION_TYPE_NONE = 0, /**< The event does not have a radio notification signal. */ |
| gkroussos | 0:dd0fea342ad2 | 164 | NRF_RADIO_NOTIFICATION_TYPE_INT_ON_ACTIVE, /**< Using interrupt for notification when the radio will be enabled. */ |
| gkroussos | 0:dd0fea342ad2 | 165 | NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE, /**< Using interrupt for notification when the radio has been disabled. */ |
| gkroussos | 0:dd0fea342ad2 | 166 | NRF_RADIO_NOTIFICATION_TYPE_INT_ON_BOTH, /**< Using interrupt for notification both when the radio will be enabled and disabled. */ |
| gkroussos | 0:dd0fea342ad2 | 167 | }; |
| gkroussos | 0:dd0fea342ad2 | 168 | |
| gkroussos | 0:dd0fea342ad2 | 169 | /**@brief SoC Events. */ |
| gkroussos | 0:dd0fea342ad2 | 170 | enum NRF_SOC_EVTS |
| gkroussos | 0:dd0fea342ad2 | 171 | { |
| gkroussos | 0:dd0fea342ad2 | 172 | NRF_EVT_HFCLKSTARTED, /**< Event indicating that the HFCLK has started. */ |
| gkroussos | 0:dd0fea342ad2 | 173 | NRF_EVT_POWER_FAILURE_WARNING, /**< Event indicating that a power failure warning has occurred. */ |
| gkroussos | 0:dd0fea342ad2 | 174 | NRF_EVT_FLASH_OPERATION_SUCCESS, /**< Event indicating that the ongoing flash operation has completed successfully. */ |
| gkroussos | 0:dd0fea342ad2 | 175 | NRF_EVT_FLASH_OPERATION_ERROR, /**< Event indicating that the ongoing flash operation has timed out with an error. */ |
| gkroussos | 0:dd0fea342ad2 | 176 | NRF_EVT_RESERVED1, |
| gkroussos | 0:dd0fea342ad2 | 177 | NRF_EVT_RESERVED2, |
| gkroussos | 0:dd0fea342ad2 | 178 | NRF_EVT_RESERVED3, |
| gkroussos | 0:dd0fea342ad2 | 179 | NRF_EVT_RESERVED4, |
| gkroussos | 0:dd0fea342ad2 | 180 | NRF_EVT_RESERVED5, |
| gkroussos | 0:dd0fea342ad2 | 181 | NRF_EVT_NUMBER_OF_EVTS |
| gkroussos | 0:dd0fea342ad2 | 182 | }; |
| gkroussos | 0:dd0fea342ad2 | 183 | |
| gkroussos | 0:dd0fea342ad2 | 184 | /** @} */ |
| gkroussos | 0:dd0fea342ad2 | 185 | |
| gkroussos | 0:dd0fea342ad2 | 186 | /** @addtogroup NRF_SOC_TYPES Types |
| gkroussos | 0:dd0fea342ad2 | 187 | * @{ */ |
| gkroussos | 0:dd0fea342ad2 | 188 | |
| gkroussos | 0:dd0fea342ad2 | 189 | /**@brief Represents a mutex for use with the nrf_mutex functions. |
| gkroussos | 0:dd0fea342ad2 | 190 | * @note Accessing the value directly is not safe, use the mutex functions! |
| gkroussos | 0:dd0fea342ad2 | 191 | */ |
| gkroussos | 0:dd0fea342ad2 | 192 | typedef volatile uint8_t nrf_mutex_t; |
| gkroussos | 0:dd0fea342ad2 | 193 | |
| gkroussos | 0:dd0fea342ad2 | 194 | /**@brief The interrupt priorities available to the application while the softdevice is active. */ |
| gkroussos | 0:dd0fea342ad2 | 195 | typedef uint8_t nrf_app_irq_priority_t; |
| gkroussos | 0:dd0fea342ad2 | 196 | |
| gkroussos | 0:dd0fea342ad2 | 197 | /**@brief Represents a power mode, used in power mode functions */ |
| gkroussos | 0:dd0fea342ad2 | 198 | typedef uint8_t nrf_power_mode_t; |
| gkroussos | 0:dd0fea342ad2 | 199 | |
| gkroussos | 0:dd0fea342ad2 | 200 | /**@brief Represents a power failure threshold value. */ |
| gkroussos | 0:dd0fea342ad2 | 201 | typedef uint8_t nrf_power_failure_threshold_t; |
| gkroussos | 0:dd0fea342ad2 | 202 | |
| gkroussos | 0:dd0fea342ad2 | 203 | /**@brief Represents a DCDC mode value. */ |
| gkroussos | 0:dd0fea342ad2 | 204 | typedef uint32_t nrf_power_dcdc_mode_t; |
| gkroussos | 0:dd0fea342ad2 | 205 | |
| gkroussos | 0:dd0fea342ad2 | 206 | /**@brief Radio notification distances. */ |
| gkroussos | 0:dd0fea342ad2 | 207 | typedef uint8_t nrf_radio_notification_distance_t; |
| gkroussos | 0:dd0fea342ad2 | 208 | |
| gkroussos | 0:dd0fea342ad2 | 209 | /**@brief Radio notification types. */ |
| gkroussos | 0:dd0fea342ad2 | 210 | typedef uint8_t nrf_radio_notification_type_t; |
| gkroussos | 0:dd0fea342ad2 | 211 | |
| gkroussos | 0:dd0fea342ad2 | 212 | |
| gkroussos | 0:dd0fea342ad2 | 213 | /**@brief AES ECB data structure */ |
| gkroussos | 0:dd0fea342ad2 | 214 | typedef struct |
| gkroussos | 0:dd0fea342ad2 | 215 | { |
| gkroussos | 0:dd0fea342ad2 | 216 | uint8_t key[SOC_ECB_KEY_LENGTH]; /**< Encryption key. */ |
| gkroussos | 0:dd0fea342ad2 | 217 | uint8_t cleartext[SOC_ECB_CLEARTEXT_LENGTH]; /**< Clear Text data. */ |
| gkroussos | 0:dd0fea342ad2 | 218 | uint8_t ciphertext[SOC_ECB_CIPHERTEXT_LENGTH]; /**< Cipher Text data. */ |
| gkroussos | 0:dd0fea342ad2 | 219 | } nrf_ecb_hal_data_t; |
| gkroussos | 0:dd0fea342ad2 | 220 | |
| gkroussos | 0:dd0fea342ad2 | 221 | /** @} */ |
| gkroussos | 0:dd0fea342ad2 | 222 | |
| gkroussos | 0:dd0fea342ad2 | 223 | /** @addtogroup NRF_SOC_FUNCTIONS Functions |
| gkroussos | 0:dd0fea342ad2 | 224 | * @{ */ |
| gkroussos | 0:dd0fea342ad2 | 225 | |
| gkroussos | 0:dd0fea342ad2 | 226 | /**@brief Initialize a mutex. |
| gkroussos | 0:dd0fea342ad2 | 227 | * |
| gkroussos | 0:dd0fea342ad2 | 228 | * @param[in] p_mutex Pointer to the mutex to initialize. |
| gkroussos | 0:dd0fea342ad2 | 229 | * |
| gkroussos | 0:dd0fea342ad2 | 230 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 231 | */ |
| gkroussos | 0:dd0fea342ad2 | 232 | SVCALL(SD_MUTEX_NEW, uint32_t, sd_mutex_new(nrf_mutex_t * p_mutex)); |
| gkroussos | 0:dd0fea342ad2 | 233 | |
| gkroussos | 0:dd0fea342ad2 | 234 | /**@brief Attempt to acquire a mutex. |
| gkroussos | 0:dd0fea342ad2 | 235 | * |
| gkroussos | 0:dd0fea342ad2 | 236 | * @param[in] p_mutex Pointer to the mutex to acquire. |
| gkroussos | 0:dd0fea342ad2 | 237 | * |
| gkroussos | 0:dd0fea342ad2 | 238 | * @retval ::NRF_SUCCESS The mutex was successfully acquired. |
| gkroussos | 0:dd0fea342ad2 | 239 | * @retval ::NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN The mutex could not be acquired. |
| gkroussos | 0:dd0fea342ad2 | 240 | */ |
| gkroussos | 0:dd0fea342ad2 | 241 | SVCALL(SD_MUTEX_ACQUIRE, uint32_t, sd_mutex_acquire(nrf_mutex_t * p_mutex)); |
| gkroussos | 0:dd0fea342ad2 | 242 | |
| gkroussos | 0:dd0fea342ad2 | 243 | /**@brief Release a mutex. |
| gkroussos | 0:dd0fea342ad2 | 244 | * |
| gkroussos | 0:dd0fea342ad2 | 245 | * @param[in] p_mutex Pointer to the mutex to release. |
| gkroussos | 0:dd0fea342ad2 | 246 | * |
| gkroussos | 0:dd0fea342ad2 | 247 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 248 | */ |
| gkroussos | 0:dd0fea342ad2 | 249 | SVCALL(SD_MUTEX_RELEASE, uint32_t, sd_mutex_release(nrf_mutex_t * p_mutex)); |
| gkroussos | 0:dd0fea342ad2 | 250 | |
| gkroussos | 0:dd0fea342ad2 | 251 | /**@brief Enable External Interrupt. |
| gkroussos | 0:dd0fea342ad2 | 252 | * @note Corresponds to NVIC_EnableIRQ in CMSIS. |
| gkroussos | 0:dd0fea342ad2 | 253 | * |
| gkroussos | 0:dd0fea342ad2 | 254 | * @pre{IRQn is valid and not reserved by the stack} |
| gkroussos | 0:dd0fea342ad2 | 255 | * |
| gkroussos | 0:dd0fea342ad2 | 256 | * @param[in] IRQn See the NVIC_EnableIRQ documentation in CMSIS. |
| gkroussos | 0:dd0fea342ad2 | 257 | * |
| gkroussos | 0:dd0fea342ad2 | 258 | * @retval ::NRF_SUCCESS The interrupt was enabled. |
| gkroussos | 0:dd0fea342ad2 | 259 | * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application. |
| gkroussos | 0:dd0fea342ad2 | 260 | * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt has a priority not available for the application. |
| gkroussos | 0:dd0fea342ad2 | 261 | */ |
| gkroussos | 0:dd0fea342ad2 | 262 | SVCALL(SD_NVIC_ENABLEIRQ, uint32_t, sd_nvic_EnableIRQ(IRQn_Type IRQn)); |
| gkroussos | 0:dd0fea342ad2 | 263 | |
| gkroussos | 0:dd0fea342ad2 | 264 | /**@brief Disable External Interrupt. |
| gkroussos | 0:dd0fea342ad2 | 265 | * @note Corresponds to NVIC_DisableIRQ in CMSIS. |
| gkroussos | 0:dd0fea342ad2 | 266 | * |
| gkroussos | 0:dd0fea342ad2 | 267 | * @pre{IRQn is valid and not reserved by the stack} |
| gkroussos | 0:dd0fea342ad2 | 268 | * |
| gkroussos | 0:dd0fea342ad2 | 269 | * @param[in] IRQn See the NVIC_DisableIRQ documentation in CMSIS |
| gkroussos | 0:dd0fea342ad2 | 270 | * |
| gkroussos | 0:dd0fea342ad2 | 271 | * @retval ::NRF_SUCCESS The interrupt was disabled. |
| gkroussos | 0:dd0fea342ad2 | 272 | * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application. |
| gkroussos | 0:dd0fea342ad2 | 273 | */ |
| gkroussos | 0:dd0fea342ad2 | 274 | SVCALL(SD_NVIC_DISABLEIRQ, uint32_t, sd_nvic_DisableIRQ(IRQn_Type IRQn)); |
| gkroussos | 0:dd0fea342ad2 | 275 | |
| gkroussos | 0:dd0fea342ad2 | 276 | /**@brief Get Pending Interrupt. |
| gkroussos | 0:dd0fea342ad2 | 277 | * @note Corresponds to NVIC_GetPendingIRQ in CMSIS. |
| gkroussos | 0:dd0fea342ad2 | 278 | * |
| gkroussos | 0:dd0fea342ad2 | 279 | * @pre{IRQn is valid and not reserved by the stack} |
| gkroussos | 0:dd0fea342ad2 | 280 | * |
| gkroussos | 0:dd0fea342ad2 | 281 | * @param[in] IRQn See the NVIC_GetPendingIRQ documentation in CMSIS. |
| gkroussos | 0:dd0fea342ad2 | 282 | * @param[out] p_pending_irq Return value from NVIC_GetPendingIRQ. |
| gkroussos | 0:dd0fea342ad2 | 283 | * |
| gkroussos | 0:dd0fea342ad2 | 284 | * @retval ::NRF_SUCCESS The interrupt is available for the application. |
| gkroussos | 0:dd0fea342ad2 | 285 | * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. |
| gkroussos | 0:dd0fea342ad2 | 286 | */ |
| gkroussos | 0:dd0fea342ad2 | 287 | SVCALL(SD_NVIC_GETPENDINGIRQ, uint32_t, sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq)); |
| gkroussos | 0:dd0fea342ad2 | 288 | |
| gkroussos | 0:dd0fea342ad2 | 289 | /**@brief Set Pending Interrupt. |
| gkroussos | 0:dd0fea342ad2 | 290 | * @note Corresponds to NVIC_SetPendingIRQ in CMSIS. |
| gkroussos | 0:dd0fea342ad2 | 291 | * |
| gkroussos | 0:dd0fea342ad2 | 292 | * @pre{IRQn is valid and not reserved by the stack} |
| gkroussos | 0:dd0fea342ad2 | 293 | * |
| gkroussos | 0:dd0fea342ad2 | 294 | * @param[in] IRQn See the NVIC_SetPendingIRQ documentation in CMSIS. |
| gkroussos | 0:dd0fea342ad2 | 295 | * |
| gkroussos | 0:dd0fea342ad2 | 296 | * @retval ::NRF_SUCCESS The interrupt is set pending. |
| gkroussos | 0:dd0fea342ad2 | 297 | * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. |
| gkroussos | 0:dd0fea342ad2 | 298 | */ |
| gkroussos | 0:dd0fea342ad2 | 299 | SVCALL(SD_NVIC_SETPENDINGIRQ, uint32_t, sd_nvic_SetPendingIRQ(IRQn_Type IRQn)); |
| gkroussos | 0:dd0fea342ad2 | 300 | |
| gkroussos | 0:dd0fea342ad2 | 301 | /**@brief Clear Pending Interrupt. |
| gkroussos | 0:dd0fea342ad2 | 302 | * @note Corresponds to NVIC_ClearPendingIRQ in CMSIS. |
| gkroussos | 0:dd0fea342ad2 | 303 | * |
| gkroussos | 0:dd0fea342ad2 | 304 | * @pre{IRQn is valid and not reserved by the stack} |
| gkroussos | 0:dd0fea342ad2 | 305 | * |
| gkroussos | 0:dd0fea342ad2 | 306 | * @param[in] IRQn See the NVIC_ClearPendingIRQ documentation in CMSIS. |
| gkroussos | 0:dd0fea342ad2 | 307 | * |
| gkroussos | 0:dd0fea342ad2 | 308 | * @retval ::NRF_SUCCESS The interrupt pending flag is cleared. |
| gkroussos | 0:dd0fea342ad2 | 309 | * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. |
| gkroussos | 0:dd0fea342ad2 | 310 | */ |
| gkroussos | 0:dd0fea342ad2 | 311 | SVCALL(SD_NVIC_CLEARPENDINGIRQ, uint32_t, sd_nvic_ClearPendingIRQ(IRQn_Type IRQn)); |
| gkroussos | 0:dd0fea342ad2 | 312 | |
| gkroussos | 0:dd0fea342ad2 | 313 | /**@brief Set Interrupt Priority. |
| gkroussos | 0:dd0fea342ad2 | 314 | * @note Corresponds to NVIC_SetPriority in CMSIS. |
| gkroussos | 0:dd0fea342ad2 | 315 | * |
| gkroussos | 0:dd0fea342ad2 | 316 | * @pre{IRQn is valid and not reserved by the stack} |
| gkroussos | 0:dd0fea342ad2 | 317 | * @pre{priority is valid and not reserved by the stack} |
| gkroussos | 0:dd0fea342ad2 | 318 | * |
| gkroussos | 0:dd0fea342ad2 | 319 | * @param[in] IRQn See the NVIC_SetPriority documentation in CMSIS. |
| gkroussos | 0:dd0fea342ad2 | 320 | * @param[in] priority A valid IRQ priority for use by the application. |
| gkroussos | 0:dd0fea342ad2 | 321 | * |
| gkroussos | 0:dd0fea342ad2 | 322 | * @retval ::NRF_SUCCESS The interrupt and priority level is available for the application. |
| gkroussos | 0:dd0fea342ad2 | 323 | * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. |
| gkroussos | 0:dd0fea342ad2 | 324 | * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt priority is not available for the application. |
| gkroussos | 0:dd0fea342ad2 | 325 | */ |
| gkroussos | 0:dd0fea342ad2 | 326 | SVCALL(SD_NVIC_SETPRIORITY, uint32_t, sd_nvic_SetPriority(IRQn_Type IRQn, nrf_app_irq_priority_t priority)); |
| gkroussos | 0:dd0fea342ad2 | 327 | |
| gkroussos | 0:dd0fea342ad2 | 328 | /**@brief Get Interrupt Priority. |
| gkroussos | 0:dd0fea342ad2 | 329 | * @note Corresponds to NVIC_GetPriority in CMSIS. |
| gkroussos | 0:dd0fea342ad2 | 330 | * |
| gkroussos | 0:dd0fea342ad2 | 331 | * @pre{IRQn is valid and not reserved by the stack} |
| gkroussos | 0:dd0fea342ad2 | 332 | * |
| gkroussos | 0:dd0fea342ad2 | 333 | * @param[in] IRQn See the NVIC_GetPriority documentation in CMSIS. |
| gkroussos | 0:dd0fea342ad2 | 334 | * @param[out] p_priority Return value from NVIC_GetPriority. |
| gkroussos | 0:dd0fea342ad2 | 335 | * |
| gkroussos | 0:dd0fea342ad2 | 336 | * @retval ::NRF_SUCCESS The interrupt priority is returned in p_priority. |
| gkroussos | 0:dd0fea342ad2 | 337 | * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE - IRQn is not available for the application. |
| gkroussos | 0:dd0fea342ad2 | 338 | */ |
| gkroussos | 0:dd0fea342ad2 | 339 | SVCALL(SD_NVIC_GETPRIORITY, uint32_t, sd_nvic_GetPriority(IRQn_Type IRQn, nrf_app_irq_priority_t * p_priority)); |
| gkroussos | 0:dd0fea342ad2 | 340 | |
| gkroussos | 0:dd0fea342ad2 | 341 | /**@brief System Reset. |
| gkroussos | 0:dd0fea342ad2 | 342 | * @note Corresponds to NVIC_SystemReset in CMSIS. |
| gkroussos | 0:dd0fea342ad2 | 343 | * |
| gkroussos | 0:dd0fea342ad2 | 344 | * @retval ::NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN |
| gkroussos | 0:dd0fea342ad2 | 345 | */ |
| gkroussos | 0:dd0fea342ad2 | 346 | SVCALL(SD_NVIC_SYSTEMRESET, uint32_t, sd_nvic_SystemReset(void)); |
| gkroussos | 0:dd0fea342ad2 | 347 | |
| gkroussos | 0:dd0fea342ad2 | 348 | /**@brief Enters critical region. |
| gkroussos | 0:dd0fea342ad2 | 349 | * |
| gkroussos | 0:dd0fea342ad2 | 350 | * @post Application interrupts will be disabled. |
| gkroussos | 0:dd0fea342ad2 | 351 | * @sa sd_nvic_critical_region_exit |
| gkroussos | 0:dd0fea342ad2 | 352 | * |
| gkroussos | 0:dd0fea342ad2 | 353 | * @param[out] p_is_nested_critical_region 1: If in a nested critical region. |
| gkroussos | 0:dd0fea342ad2 | 354 | * 0: Otherwise. |
| gkroussos | 0:dd0fea342ad2 | 355 | * |
| gkroussos | 0:dd0fea342ad2 | 356 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 357 | */ |
| gkroussos | 0:dd0fea342ad2 | 358 | SVCALL(SD_NVIC_CRITICAL_REGION_ENTER, uint32_t, sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region)); |
| gkroussos | 0:dd0fea342ad2 | 359 | |
| gkroussos | 0:dd0fea342ad2 | 360 | /**@brief Exit critical region. |
| gkroussos | 0:dd0fea342ad2 | 361 | * |
| gkroussos | 0:dd0fea342ad2 | 362 | * @pre Application has entered a critical region using ::sd_nvic_critical_region_enter. |
| gkroussos | 0:dd0fea342ad2 | 363 | * @post If not in a nested critical region, the application interrupts will restored to the state before ::sd_nvic_critical_region_enter was called. |
| gkroussos | 0:dd0fea342ad2 | 364 | * |
| gkroussos | 0:dd0fea342ad2 | 365 | * @param[in] is_nested_critical_region If this is set to 1, the critical region won't be exited. @sa sd_nvic_critical_region_enter. |
| gkroussos | 0:dd0fea342ad2 | 366 | * |
| gkroussos | 0:dd0fea342ad2 | 367 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 368 | */ |
| gkroussos | 0:dd0fea342ad2 | 369 | SVCALL(SD_NVIC_CRITICAL_REGION_EXIT, uint32_t, sd_nvic_critical_region_exit(uint8_t is_nested_critical_region)); |
| gkroussos | 0:dd0fea342ad2 | 370 | |
| gkroussos | 0:dd0fea342ad2 | 371 | /**@brief Query the capacity of the application random pool. |
| gkroussos | 0:dd0fea342ad2 | 372 | * |
| gkroussos | 0:dd0fea342ad2 | 373 | * @param[out] p_pool_capacity The capacity of the pool. |
| gkroussos | 0:dd0fea342ad2 | 374 | * |
| gkroussos | 0:dd0fea342ad2 | 375 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 376 | */ |
| gkroussos | 0:dd0fea342ad2 | 377 | SVCALL(SD_RAND_APPLICATION_POOL_CAPACITY, uint32_t, sd_rand_application_pool_capacity_get(uint8_t * p_pool_capacity)); |
| gkroussos | 0:dd0fea342ad2 | 378 | |
| gkroussos | 0:dd0fea342ad2 | 379 | /**@brief Get number of random bytes available to the application. |
| gkroussos | 0:dd0fea342ad2 | 380 | * |
| gkroussos | 0:dd0fea342ad2 | 381 | * @param[out] p_bytes_available The number of bytes currently available in the pool. |
| gkroussos | 0:dd0fea342ad2 | 382 | * |
| gkroussos | 0:dd0fea342ad2 | 383 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 384 | */ |
| gkroussos | 0:dd0fea342ad2 | 385 | SVCALL(SD_RAND_APPLICATION_BYTES_AVAILABLE, uint32_t, sd_rand_application_bytes_available_get(uint8_t * p_bytes_available)); |
| gkroussos | 0:dd0fea342ad2 | 386 | |
| gkroussos | 0:dd0fea342ad2 | 387 | /**@brief Get random bytes from the application pool. |
| gkroussos | 0:dd0fea342ad2 | 388 | |
| gkroussos | 0:dd0fea342ad2 | 389 | @param[out] p_buff Pointer to unit8_t buffer for storing the bytes. |
| gkroussos | 0:dd0fea342ad2 | 390 | @param[in] length Number of bytes to take from pool and place in p_buff. |
| gkroussos | 0:dd0fea342ad2 | 391 | |
| gkroussos | 0:dd0fea342ad2 | 392 | @retval ::NRF_SUCCESS The requested bytes were written to p_buff. |
| gkroussos | 0:dd0fea342ad2 | 393 | @retval ::NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES No bytes were written to the buffer, because there were not enough bytes available. |
| gkroussos | 0:dd0fea342ad2 | 394 | */ |
| gkroussos | 0:dd0fea342ad2 | 395 | SVCALL(SD_RAND_APPLICATION_GET_VECTOR, uint32_t, sd_rand_application_vector_get(uint8_t * p_buff, uint8_t length)); |
| gkroussos | 0:dd0fea342ad2 | 396 | |
| gkroussos | 0:dd0fea342ad2 | 397 | /**@brief Gets the reset reason register. |
| gkroussos | 0:dd0fea342ad2 | 398 | * |
| gkroussos | 0:dd0fea342ad2 | 399 | * @param[out] p_reset_reason Contents of the NRF_POWER->RESETREAS register. |
| gkroussos | 0:dd0fea342ad2 | 400 | * |
| gkroussos | 0:dd0fea342ad2 | 401 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 402 | */ |
| gkroussos | 0:dd0fea342ad2 | 403 | SVCALL(SD_POWER_RESET_REASON_GET, uint32_t, sd_power_reset_reason_get(uint32_t * p_reset_reason)); |
| gkroussos | 0:dd0fea342ad2 | 404 | |
| gkroussos | 0:dd0fea342ad2 | 405 | /**@brief Clears the bits of the reset reason register. |
| gkroussos | 0:dd0fea342ad2 | 406 | * |
| gkroussos | 0:dd0fea342ad2 | 407 | * @param[in] reset_reason_clr_msk Contains the bits to clear from the reset reason register. |
| gkroussos | 0:dd0fea342ad2 | 408 | * |
| gkroussos | 0:dd0fea342ad2 | 409 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 410 | */ |
| gkroussos | 0:dd0fea342ad2 | 411 | SVCALL(SD_POWER_RESET_REASON_CLR, uint32_t, sd_power_reset_reason_clr(uint32_t reset_reason_clr_msk)); |
| gkroussos | 0:dd0fea342ad2 | 412 | |
| gkroussos | 0:dd0fea342ad2 | 413 | /**@brief Sets the power mode when in CPU sleep. |
| gkroussos | 0:dd0fea342ad2 | 414 | * |
| gkroussos | 0:dd0fea342ad2 | 415 | * @param[in] power_mode The power mode to use when in CPU sleep. @sa sd_app_evt_wait |
| gkroussos | 0:dd0fea342ad2 | 416 | * |
| gkroussos | 0:dd0fea342ad2 | 417 | * @retval ::NRF_SUCCESS The power mode was set. |
| gkroussos | 0:dd0fea342ad2 | 418 | * @retval ::NRF_ERROR_SOC_POWER_MODE_UNKNOWN The power mode was unknown. |
| gkroussos | 0:dd0fea342ad2 | 419 | */ |
| gkroussos | 0:dd0fea342ad2 | 420 | SVCALL(SD_POWER_MODE_SET, uint32_t, sd_power_mode_set(nrf_power_mode_t power_mode)); |
| gkroussos | 0:dd0fea342ad2 | 421 | |
| gkroussos | 0:dd0fea342ad2 | 422 | /**@brief Puts the chip in System OFF mode. |
| gkroussos | 0:dd0fea342ad2 | 423 | * |
| gkroussos | 0:dd0fea342ad2 | 424 | * @retval ::NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN |
| gkroussos | 0:dd0fea342ad2 | 425 | */ |
| gkroussos | 0:dd0fea342ad2 | 426 | SVCALL(SD_POWER_SYSTEM_OFF, uint32_t, sd_power_system_off(void)); |
| gkroussos | 0:dd0fea342ad2 | 427 | |
| gkroussos | 0:dd0fea342ad2 | 428 | /**@brief Enables or disables the power-fail comparator. |
| gkroussos | 0:dd0fea342ad2 | 429 | * |
| gkroussos | 0:dd0fea342ad2 | 430 | * Enabling this will give a softdevice event (NRF_EVT_POWER_FAILURE_WARNING) when the power failure warning occurs. |
| gkroussos | 0:dd0fea342ad2 | 431 | * The event can be retrieved with sd_evt_get(); |
| gkroussos | 0:dd0fea342ad2 | 432 | * |
| gkroussos | 0:dd0fea342ad2 | 433 | * @param[in] pof_enable True if the power-fail comparator should be enabled, false if it should be disabled. |
| gkroussos | 0:dd0fea342ad2 | 434 | * |
| gkroussos | 0:dd0fea342ad2 | 435 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 436 | */ |
| gkroussos | 0:dd0fea342ad2 | 437 | SVCALL(SD_POWER_POF_ENABLE, uint32_t, sd_power_pof_enable(uint8_t pof_enable)); |
| gkroussos | 0:dd0fea342ad2 | 438 | |
| gkroussos | 0:dd0fea342ad2 | 439 | /**@brief Sets the power-fail threshold value. |
| gkroussos | 0:dd0fea342ad2 | 440 | * |
| gkroussos | 0:dd0fea342ad2 | 441 | * @param[in] threshold The power-fail threshold value to use. |
| gkroussos | 0:dd0fea342ad2 | 442 | * |
| gkroussos | 0:dd0fea342ad2 | 443 | * @retval ::NRF_SUCCESS The power failure threshold was set. |
| gkroussos | 0:dd0fea342ad2 | 444 | * @retval ::NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN The power failure threshold is unknown. |
| gkroussos | 0:dd0fea342ad2 | 445 | */ |
| gkroussos | 0:dd0fea342ad2 | 446 | SVCALL(SD_POWER_POF_THRESHOLD_SET, uint32_t, sd_power_pof_threshold_set(nrf_power_failure_threshold_t threshold)); |
| gkroussos | 0:dd0fea342ad2 | 447 | |
| gkroussos | 0:dd0fea342ad2 | 448 | /**@brief Sets bits in the NRF_POWER->RAMON register. |
| gkroussos | 0:dd0fea342ad2 | 449 | * |
| gkroussos | 0:dd0fea342ad2 | 450 | * @param[in] ramon Contains the bits needed to be set in the NRF_POWER->RAMON register. |
| gkroussos | 0:dd0fea342ad2 | 451 | * |
| gkroussos | 0:dd0fea342ad2 | 452 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 453 | */ |
| gkroussos | 0:dd0fea342ad2 | 454 | SVCALL(SD_POWER_RAMON_SET, uint32_t, sd_power_ramon_set(uint32_t ramon)); |
| gkroussos | 0:dd0fea342ad2 | 455 | |
| gkroussos | 0:dd0fea342ad2 | 456 | /** @brief Clears bits in the NRF_POWER->RAMON register. |
| gkroussos | 0:dd0fea342ad2 | 457 | * |
| gkroussos | 0:dd0fea342ad2 | 458 | * @param ramon Contains the bits needed to be cleared in the NRF_POWER->RAMON register. |
| gkroussos | 0:dd0fea342ad2 | 459 | * |
| gkroussos | 0:dd0fea342ad2 | 460 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 461 | */ |
| gkroussos | 0:dd0fea342ad2 | 462 | SVCALL(SD_POWER_RAMON_CLR, uint32_t, sd_power_ramon_clr(uint32_t ramon)); |
| gkroussos | 0:dd0fea342ad2 | 463 | |
| gkroussos | 0:dd0fea342ad2 | 464 | /**@brief Get contents of NRF_POWER->RAMON register, indicates power status of ram blocks. |
| gkroussos | 0:dd0fea342ad2 | 465 | * |
| gkroussos | 0:dd0fea342ad2 | 466 | * @param[out] p_ramon Content of NRF_POWER->RAMON register. |
| gkroussos | 0:dd0fea342ad2 | 467 | * |
| gkroussos | 0:dd0fea342ad2 | 468 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 469 | */ |
| gkroussos | 0:dd0fea342ad2 | 470 | SVCALL(SD_POWER_RAMON_GET, uint32_t, sd_power_ramon_get(uint32_t * p_ramon)); |
| gkroussos | 0:dd0fea342ad2 | 471 | |
| gkroussos | 0:dd0fea342ad2 | 472 | /**@brief Set bits in the NRF_POWER->GPREGRET register. |
| gkroussos | 0:dd0fea342ad2 | 473 | * |
| gkroussos | 0:dd0fea342ad2 | 474 | * @param[in] gpregret_msk Bits to be set in the GPREGRET register. |
| gkroussos | 0:dd0fea342ad2 | 475 | * |
| gkroussos | 0:dd0fea342ad2 | 476 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 477 | */ |
| gkroussos | 0:dd0fea342ad2 | 478 | SVCALL(SD_POWER_GPREGRET_SET, uint32_t, sd_power_gpregret_set(uint32_t gpregret_msk)); |
| gkroussos | 0:dd0fea342ad2 | 479 | |
| gkroussos | 0:dd0fea342ad2 | 480 | /**@brief Clear bits in the NRF_POWER->GPREGRET register. |
| gkroussos | 0:dd0fea342ad2 | 481 | * |
| gkroussos | 0:dd0fea342ad2 | 482 | * @param[in] gpregret_msk Bits to be clear in the GPREGRET register. |
| gkroussos | 0:dd0fea342ad2 | 483 | * |
| gkroussos | 0:dd0fea342ad2 | 484 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 485 | */ |
| gkroussos | 0:dd0fea342ad2 | 486 | SVCALL(SD_POWER_GPREGRET_CLR, uint32_t, sd_power_gpregret_clr(uint32_t gpregret_msk)); |
| gkroussos | 0:dd0fea342ad2 | 487 | |
| gkroussos | 0:dd0fea342ad2 | 488 | /**@brief Get contents of the NRF_POWER->GPREGRET register. |
| gkroussos | 0:dd0fea342ad2 | 489 | * |
| gkroussos | 0:dd0fea342ad2 | 490 | * @param[out] p_gpregret Contents of the GPREGRET register. |
| gkroussos | 0:dd0fea342ad2 | 491 | * |
| gkroussos | 0:dd0fea342ad2 | 492 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 493 | */ |
| gkroussos | 0:dd0fea342ad2 | 494 | SVCALL(SD_POWER_GPREGRET_GET, uint32_t, sd_power_gpregret_get(uint32_t *p_gpregret)); |
| gkroussos | 0:dd0fea342ad2 | 495 | |
| gkroussos | 0:dd0fea342ad2 | 496 | /**@brief Sets the DCDC mode. |
| gkroussos | 0:dd0fea342ad2 | 497 | * |
| gkroussos | 0:dd0fea342ad2 | 498 | * Depending on the internal state of the SoftDevice, the mode change may not happen immediately. |
| gkroussos | 0:dd0fea342ad2 | 499 | * The DCDC mode switch will be blocked when occurring in close proximity to radio transmissions. When |
| gkroussos | 0:dd0fea342ad2 | 500 | * the radio transmission is done, the last mode will be used. |
| gkroussos | 0:dd0fea342ad2 | 501 | * |
| gkroussos | 0:dd0fea342ad2 | 502 | * @param[in] dcdc_mode The mode of the DCDC. |
| gkroussos | 0:dd0fea342ad2 | 503 | * |
| gkroussos | 0:dd0fea342ad2 | 504 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 505 | * @retval ::NRF_ERROR_INVALID_PARAM The DCDC mode is invalid. |
| gkroussos | 0:dd0fea342ad2 | 506 | */ |
| gkroussos | 0:dd0fea342ad2 | 507 | SVCALL(SD_POWER_DCDC_MODE_SET, uint32_t, sd_power_dcdc_mode_set(nrf_power_dcdc_mode_t dcdc_mode)); |
| gkroussos | 0:dd0fea342ad2 | 508 | |
| gkroussos | 0:dd0fea342ad2 | 509 | /**@brief Request the high frequency crystal oscillator. |
| gkroussos | 0:dd0fea342ad2 | 510 | * |
| gkroussos | 0:dd0fea342ad2 | 511 | * Will start the high frequency crystal oscillator, the startup time of the crystal varies |
| gkroussos | 0:dd0fea342ad2 | 512 | * and the ::sd_clock_hfclk_is_running function can be polled to check if it has started. |
| gkroussos | 0:dd0fea342ad2 | 513 | * |
| gkroussos | 0:dd0fea342ad2 | 514 | * @see sd_clock_hfclk_is_running |
| gkroussos | 0:dd0fea342ad2 | 515 | * @see sd_clock_hfclk_release |
| gkroussos | 0:dd0fea342ad2 | 516 | * |
| gkroussos | 0:dd0fea342ad2 | 517 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 518 | */ |
| gkroussos | 0:dd0fea342ad2 | 519 | SVCALL(SD_CLOCK_HFCLK_REQUEST, uint32_t, sd_clock_hfclk_request(void)); |
| gkroussos | 0:dd0fea342ad2 | 520 | |
| gkroussos | 0:dd0fea342ad2 | 521 | /**@brief Releases the high frequency crystal oscillator. |
| gkroussos | 0:dd0fea342ad2 | 522 | * |
| gkroussos | 0:dd0fea342ad2 | 523 | * Will stop the high frequency crystal oscillator, this happens immediately. |
| gkroussos | 0:dd0fea342ad2 | 524 | * |
| gkroussos | 0:dd0fea342ad2 | 525 | * @see sd_clock_hfclk_is_running |
| gkroussos | 0:dd0fea342ad2 | 526 | * @see sd_clock_hfclk_request |
| gkroussos | 0:dd0fea342ad2 | 527 | * |
| gkroussos | 0:dd0fea342ad2 | 528 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 529 | */ |
| gkroussos | 0:dd0fea342ad2 | 530 | SVCALL(SD_CLOCK_HFCLK_RELEASE, uint32_t, sd_clock_hfclk_release(void)); |
| gkroussos | 0:dd0fea342ad2 | 531 | |
| gkroussos | 0:dd0fea342ad2 | 532 | /**@brief Checks if the high frequency crystal oscillator is running. |
| gkroussos | 0:dd0fea342ad2 | 533 | * |
| gkroussos | 0:dd0fea342ad2 | 534 | * @see sd_clock_hfclk_request |
| gkroussos | 0:dd0fea342ad2 | 535 | * @see sd_clock_hfclk_release |
| gkroussos | 0:dd0fea342ad2 | 536 | * |
| gkroussos | 0:dd0fea342ad2 | 537 | * @param[out] p_is_running 1 if the external crystal oscillator is running, 0 if not. |
| gkroussos | 0:dd0fea342ad2 | 538 | * |
| gkroussos | 0:dd0fea342ad2 | 539 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 540 | */ |
| gkroussos | 0:dd0fea342ad2 | 541 | SVCALL(SD_CLOCK_HFCLK_IS_RUNNING, uint32_t, sd_clock_hfclk_is_running(uint32_t * p_is_running)); |
| gkroussos | 0:dd0fea342ad2 | 542 | |
| gkroussos | 0:dd0fea342ad2 | 543 | /**@brief Waits for an application event. |
| gkroussos | 0:dd0fea342ad2 | 544 | * |
| gkroussos | 0:dd0fea342ad2 | 545 | * An application event is either an application interrupt or a pended interrupt when the |
| gkroussos | 0:dd0fea342ad2 | 546 | * interrupt is disabled. When the interrupt is enabled it will be taken immediately since |
| gkroussos | 0:dd0fea342ad2 | 547 | * this function will wait in thread mode, then the execution will return in the application's |
| gkroussos | 0:dd0fea342ad2 | 548 | * main thread. When an interrupt is disabled and gets pended it will return to the application's |
| gkroussos | 0:dd0fea342ad2 | 549 | * thread main. The application must ensure that the pended flag is cleared using |
| gkroussos | 0:dd0fea342ad2 | 550 | * ::sd_nvic_ClearPendingIRQ in order to sleep using this function. This is only necessary for |
| gkroussos | 0:dd0fea342ad2 | 551 | * disabled interrupts, as the interrupt handler will clear the pending flag automatically for |
| gkroussos | 0:dd0fea342ad2 | 552 | * enabled interrupts. |
| gkroussos | 0:dd0fea342ad2 | 553 | * |
| gkroussos | 0:dd0fea342ad2 | 554 | * In order to wake up from disabled interrupts, the SEVONPEND flag has to be set in the Cortex-M0 |
| gkroussos | 0:dd0fea342ad2 | 555 | * System Control Register (SCR). @sa CMSIS_SCB |
| gkroussos | 0:dd0fea342ad2 | 556 | * |
| gkroussos | 0:dd0fea342ad2 | 557 | * @note If an application interrupt has happened since the last time sd_app_evt_wait was |
| gkroussos | 0:dd0fea342ad2 | 558 | * called this function will return immediately and not go to sleep. This is to avoid race |
| gkroussos | 0:dd0fea342ad2 | 559 | * conditions that can occur when a flag is updated in the interrupt handler and processed |
| gkroussos | 0:dd0fea342ad2 | 560 | * in the main loop. |
| gkroussos | 0:dd0fea342ad2 | 561 | * |
| gkroussos | 0:dd0fea342ad2 | 562 | * @post An application interrupt has happened or a interrupt pending flag is set. |
| gkroussos | 0:dd0fea342ad2 | 563 | * |
| gkroussos | 0:dd0fea342ad2 | 564 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 565 | */ |
| gkroussos | 0:dd0fea342ad2 | 566 | SVCALL(SD_APP_EVT_WAIT, uint32_t, sd_app_evt_wait(void)); |
| gkroussos | 0:dd0fea342ad2 | 567 | |
| gkroussos | 0:dd0fea342ad2 | 568 | /**@brief Get PPI channel enable register contents. |
| gkroussos | 0:dd0fea342ad2 | 569 | * |
| gkroussos | 0:dd0fea342ad2 | 570 | * @param[out] p_channel_enable The contents of the PPI CHEN register. |
| gkroussos | 0:dd0fea342ad2 | 571 | * |
| gkroussos | 0:dd0fea342ad2 | 572 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 573 | */ |
| gkroussos | 0:dd0fea342ad2 | 574 | SVCALL(SD_PPI_CHANNEL_ENABLE_GET, uint32_t, sd_ppi_channel_enable_get(uint32_t * p_channel_enable)); |
| gkroussos | 0:dd0fea342ad2 | 575 | |
| gkroussos | 0:dd0fea342ad2 | 576 | /**@brief Set PPI channel enable register. |
| gkroussos | 0:dd0fea342ad2 | 577 | * |
| gkroussos | 0:dd0fea342ad2 | 578 | * @param[in] channel_enable_set_msk Mask containing the bits to set in the PPI CHEN register. |
| gkroussos | 0:dd0fea342ad2 | 579 | * |
| gkroussos | 0:dd0fea342ad2 | 580 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 581 | */ |
| gkroussos | 0:dd0fea342ad2 | 582 | SVCALL(SD_PPI_CHANNEL_ENABLE_SET, uint32_t, sd_ppi_channel_enable_set(uint32_t channel_enable_set_msk)); |
| gkroussos | 0:dd0fea342ad2 | 583 | |
| gkroussos | 0:dd0fea342ad2 | 584 | /**@brief Clear PPI channel enable register. |
| gkroussos | 0:dd0fea342ad2 | 585 | * |
| gkroussos | 0:dd0fea342ad2 | 586 | * @param[in] channel_enable_clr_msk Mask containing the bits to clear in the PPI CHEN register. |
| gkroussos | 0:dd0fea342ad2 | 587 | * |
| gkroussos | 0:dd0fea342ad2 | 588 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 589 | */ |
| gkroussos | 0:dd0fea342ad2 | 590 | SVCALL(SD_PPI_CHANNEL_ENABLE_CLR, uint32_t, sd_ppi_channel_enable_clr(uint32_t channel_enable_clr_msk)); |
| gkroussos | 0:dd0fea342ad2 | 591 | |
| gkroussos | 0:dd0fea342ad2 | 592 | /**@brief Assign endpoints to a PPI channel. |
| gkroussos | 0:dd0fea342ad2 | 593 | * |
| gkroussos | 0:dd0fea342ad2 | 594 | * @param[in] channel_num Number of the PPI channel to assign. |
| gkroussos | 0:dd0fea342ad2 | 595 | * @param[in] evt_endpoint Event endpoint of the PPI channel. |
| gkroussos | 0:dd0fea342ad2 | 596 | * @param[in] task_endpoint Task endpoint of the PPI channel. |
| gkroussos | 0:dd0fea342ad2 | 597 | * |
| gkroussos | 0:dd0fea342ad2 | 598 | * @retval ::NRF_ERROR_SOC_PPI_INVALID_CHANNEL The channel number is invalid. |
| gkroussos | 0:dd0fea342ad2 | 599 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 600 | */ |
| gkroussos | 0:dd0fea342ad2 | 601 | SVCALL(SD_PPI_CHANNEL_ASSIGN, uint32_t, sd_ppi_channel_assign(uint8_t channel_num, const volatile void * evt_endpoint, const volatile void * task_endpoint)); |
| gkroussos | 0:dd0fea342ad2 | 602 | |
| gkroussos | 0:dd0fea342ad2 | 603 | /**@brief Task to enable a channel group. |
| gkroussos | 0:dd0fea342ad2 | 604 | * |
| gkroussos | 0:dd0fea342ad2 | 605 | * @param[in] group_num Number of the channel group. |
| gkroussos | 0:dd0fea342ad2 | 606 | * |
| gkroussos | 0:dd0fea342ad2 | 607 | * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid |
| gkroussos | 0:dd0fea342ad2 | 608 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 609 | */ |
| gkroussos | 0:dd0fea342ad2 | 610 | SVCALL(SD_PPI_GROUP_TASK_ENABLE, uint32_t, sd_ppi_group_task_enable(uint8_t group_num)); |
| gkroussos | 0:dd0fea342ad2 | 611 | |
| gkroussos | 0:dd0fea342ad2 | 612 | /**@brief Task to disable a channel group. |
| gkroussos | 0:dd0fea342ad2 | 613 | * |
| gkroussos | 0:dd0fea342ad2 | 614 | * @param[in] group_num Number of the PPI group. |
| gkroussos | 0:dd0fea342ad2 | 615 | * |
| gkroussos | 0:dd0fea342ad2 | 616 | * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid. |
| gkroussos | 0:dd0fea342ad2 | 617 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 618 | */ |
| gkroussos | 0:dd0fea342ad2 | 619 | SVCALL(SD_PPI_GROUP_TASK_DISABLE, uint32_t, sd_ppi_group_task_disable(uint8_t group_num)); |
| gkroussos | 0:dd0fea342ad2 | 620 | |
| gkroussos | 0:dd0fea342ad2 | 621 | /**@brief Assign PPI channels to a channel group. |
| gkroussos | 0:dd0fea342ad2 | 622 | * |
| gkroussos | 0:dd0fea342ad2 | 623 | * @param[in] group_num Number of the channel group. |
| gkroussos | 0:dd0fea342ad2 | 624 | * @param[in] channel_msk Mask of the channels to assign to the group. |
| gkroussos | 0:dd0fea342ad2 | 625 | * |
| gkroussos | 0:dd0fea342ad2 | 626 | * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid. |
| gkroussos | 0:dd0fea342ad2 | 627 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 628 | */ |
| gkroussos | 0:dd0fea342ad2 | 629 | SVCALL(SD_PPI_GROUP_ASSIGN, uint32_t, sd_ppi_group_assign(uint8_t group_num, uint32_t channel_msk)); |
| gkroussos | 0:dd0fea342ad2 | 630 | |
| gkroussos | 0:dd0fea342ad2 | 631 | /**@brief Gets the PPI channels of a channel group. |
| gkroussos | 0:dd0fea342ad2 | 632 | * |
| gkroussos | 0:dd0fea342ad2 | 633 | * @param[in] group_num Number of the channel group. |
| gkroussos | 0:dd0fea342ad2 | 634 | * @param[out] p_channel_msk Mask of the channels assigned to the group. |
| gkroussos | 0:dd0fea342ad2 | 635 | * |
| gkroussos | 0:dd0fea342ad2 | 636 | * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid. |
| gkroussos | 0:dd0fea342ad2 | 637 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 638 | */ |
| gkroussos | 0:dd0fea342ad2 | 639 | SVCALL(SD_PPI_GROUP_GET, uint32_t, sd_ppi_group_get(uint8_t group_num, uint32_t * p_channel_msk)); |
| gkroussos | 0:dd0fea342ad2 | 640 | |
| gkroussos | 0:dd0fea342ad2 | 641 | /**@brief Configures the Radio Notification signal. |
| gkroussos | 0:dd0fea342ad2 | 642 | * |
| gkroussos | 0:dd0fea342ad2 | 643 | * @note |
| gkroussos | 0:dd0fea342ad2 | 644 | * - The notification signal latency depends on the interrupt priority settings of SWI used |
| gkroussos | 0:dd0fea342ad2 | 645 | * for notification signal. |
| gkroussos | 0:dd0fea342ad2 | 646 | * - In the period between the ACTIVE signal and the start of the Radio Event, the SoftDevice |
| gkroussos | 0:dd0fea342ad2 | 647 | * will interrupt the application to do Radio Event preparation. |
| gkroussos | 0:dd0fea342ad2 | 648 | * - Using the Radio Notification feature may limit the bandwidth, as the SoftDevice may have |
| gkroussos | 0:dd0fea342ad2 | 649 | * to shorten the connection events to have time for the Radio Notification signals. |
| gkroussos | 0:dd0fea342ad2 | 650 | * |
| gkroussos | 0:dd0fea342ad2 | 651 | * @param[in] type Type of notification signal. |
| gkroussos | 0:dd0fea342ad2 | 652 | * @ref NRF_RADIO_NOTIFICATION_TYPE_NONE shall be used to turn off radio |
| gkroussos | 0:dd0fea342ad2 | 653 | * notification. Using @ref NRF_RADIO_NOTIFICATION_DISTANCE_NONE is |
| gkroussos | 0:dd0fea342ad2 | 654 | * recommended (but not required) to be used with |
| gkroussos | 0:dd0fea342ad2 | 655 | * @ref NRF_RADIO_NOTIFICATION_TYPE_NONE. |
| gkroussos | 0:dd0fea342ad2 | 656 | * |
| gkroussos | 0:dd0fea342ad2 | 657 | * @param[in] distance Distance between the notification signal and start of radio activity. |
| gkroussos | 0:dd0fea342ad2 | 658 | * This parameter is ignored when @ref NRF_RADIO_NOTIFICATION_TYPE_NONE or |
| gkroussos | 0:dd0fea342ad2 | 659 | * @ref NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE is used. |
| gkroussos | 0:dd0fea342ad2 | 660 | * |
| gkroussos | 0:dd0fea342ad2 | 661 | * @retval ::NRF_ERROR_INVALID_PARAM The group number is invalid. |
| gkroussos | 0:dd0fea342ad2 | 662 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 663 | */ |
| gkroussos | 0:dd0fea342ad2 | 664 | SVCALL(SD_RADIO_NOTIFICATION_CFG_SET, uint32_t, sd_radio_notification_cfg_set(nrf_radio_notification_type_t type, nrf_radio_notification_distance_t distance)); |
| gkroussos | 0:dd0fea342ad2 | 665 | |
| gkroussos | 0:dd0fea342ad2 | 666 | /**@brief Encrypts a block according to the specified parameters. |
| gkroussos | 0:dd0fea342ad2 | 667 | * |
| gkroussos | 0:dd0fea342ad2 | 668 | * 128-bit AES encryption. |
| gkroussos | 0:dd0fea342ad2 | 669 | * |
| gkroussos | 0:dd0fea342ad2 | 670 | * @param[in, out] p_ecb_data Pointer to the ECB parameters' struct (two input |
| gkroussos | 0:dd0fea342ad2 | 671 | * parameters and one output parameter). |
| gkroussos | 0:dd0fea342ad2 | 672 | * |
| gkroussos | 0:dd0fea342ad2 | 673 | * @retval ::NRF_SUCCESS |
| gkroussos | 0:dd0fea342ad2 | 674 | */ |
| gkroussos | 0:dd0fea342ad2 | 675 | SVCALL(SD_ECB_BLOCK_ENCRYPT, uint32_t, sd_ecb_block_encrypt(nrf_ecb_hal_data_t * p_ecb_data)); |
| gkroussos | 0:dd0fea342ad2 | 676 | |
| gkroussos | 0:dd0fea342ad2 | 677 | /**@brief Gets any pending events generated by the SoC API. |
| gkroussos | 0:dd0fea342ad2 | 678 | * |
| gkroussos | 0:dd0fea342ad2 | 679 | * The application should keep calling this function to get events, until ::NRF_ERROR_NOT_FOUND is returned. |
| gkroussos | 0:dd0fea342ad2 | 680 | * |
| gkroussos | 0:dd0fea342ad2 | 681 | * @param[out] p_evt_id Set to one of the values in @ref NRF_SOC_EVTS, if any events are pending. |
| gkroussos | 0:dd0fea342ad2 | 682 | * |
| gkroussos | 0:dd0fea342ad2 | 683 | * @retval ::NRF_SUCCESS An event was pending. The event id is written in the p_evt_id parameter. |
| gkroussos | 0:dd0fea342ad2 | 684 | * @retval ::NRF_ERROR_NOT_FOUND No pending events. |
| gkroussos | 0:dd0fea342ad2 | 685 | */ |
| gkroussos | 0:dd0fea342ad2 | 686 | SVCALL(SD_EVT_GET, uint32_t, sd_evt_get(uint32_t * p_evt_id)); |
| gkroussos | 0:dd0fea342ad2 | 687 | |
| gkroussos | 0:dd0fea342ad2 | 688 | /**@brief Get the temperature measured on the chip |
| gkroussos | 0:dd0fea342ad2 | 689 | * |
| gkroussos | 0:dd0fea342ad2 | 690 | * This function will block until the temperature measurement is done. |
| gkroussos | 0:dd0fea342ad2 | 691 | * It takes around 50us from call to return. |
| gkroussos | 0:dd0fea342ad2 | 692 | * |
| gkroussos | 0:dd0fea342ad2 | 693 | * @note Pan #28 in PAN-028 v 1.6 "Negative measured values are not represented correctly" is corrected by this function. |
| gkroussos | 0:dd0fea342ad2 | 694 | * |
| gkroussos | 0:dd0fea342ad2 | 695 | * @param[out] p_temp Result of temperature measurement. Die temperature in 0.25 degrees celsius. |
| gkroussos | 0:dd0fea342ad2 | 696 | * |
| gkroussos | 0:dd0fea342ad2 | 697 | * @retval ::NRF_SUCCESS A temperature measurement was done, and the temperature was written to temp |
| gkroussos | 0:dd0fea342ad2 | 698 | */ |
| gkroussos | 0:dd0fea342ad2 | 699 | SVCALL(SD_TEMP_GET, uint32_t, sd_temp_get(int32_t * p_temp)); |
| gkroussos | 0:dd0fea342ad2 | 700 | |
| gkroussos | 0:dd0fea342ad2 | 701 | /**@brief Flash Write |
| gkroussos | 0:dd0fea342ad2 | 702 | * |
| gkroussos | 0:dd0fea342ad2 | 703 | * Commands to write a buffer to flash |
| gkroussos | 0:dd0fea342ad2 | 704 | * |
| gkroussos | 0:dd0fea342ad2 | 705 | * This call initiates the flash access command, and its completion will be communicated to the |
| gkroussos | 0:dd0fea342ad2 | 706 | * application with exactly one of the following events: |
| gkroussos | 0:dd0fea342ad2 | 707 | * - NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed. |
| gkroussos | 0:dd0fea342ad2 | 708 | * - NRF_EVT_FLASH_OPERATION_ERROR - The command could not be started. |
| gkroussos | 0:dd0fea342ad2 | 709 | * |
| gkroussos | 0:dd0fea342ad2 | 710 | * @note |
| gkroussos | 0:dd0fea342ad2 | 711 | * - This call takes control over the radio and the CPU during flash erase and write to make sure that |
| gkroussos | 0:dd0fea342ad2 | 712 | * they will not interfere with the flash access. This means that all interrupts will be blocked |
| gkroussos | 0:dd0fea342ad2 | 713 | * for a predictable time (depending on the NVMC specification in nRF51 Series Reference Manual |
| gkroussos | 0:dd0fea342ad2 | 714 | * and the command parameters). |
| gkroussos | 0:dd0fea342ad2 | 715 | * |
| gkroussos | 0:dd0fea342ad2 | 716 | * |
| gkroussos | 0:dd0fea342ad2 | 717 | * @param[in] p_dst Pointer to start of flash location to be written. |
| gkroussos | 0:dd0fea342ad2 | 718 | * @param[in] p_src Pointer to buffer with data to be written |
| gkroussos | 0:dd0fea342ad2 | 719 | * @param[in] size Number of 32-bit words to write. Maximum size is 256 32bit words. |
| gkroussos | 0:dd0fea342ad2 | 720 | * |
| gkroussos | 0:dd0fea342ad2 | 721 | * @retval ::NRF_ERROR_INVALID_ADDR Tried to write to a non existing flash address, or p_dst or p_src was unaligned. |
| gkroussos | 0:dd0fea342ad2 | 722 | * @retval ::NRF_ERROR_BUSY The previous command has not yet completed. |
| gkroussos | 0:dd0fea342ad2 | 723 | * @retval ::NRF_ERROR_INVALID_LENGTH Size was 0, or more than 256 words. |
| gkroussos | 0:dd0fea342ad2 | 724 | * @retval ::NRF_ERROR_FORBIDDEN Tried to write to or read from protected location. |
| gkroussos | 0:dd0fea342ad2 | 725 | * @retval ::NRF_SUCCESS The command was accepted. |
| gkroussos | 0:dd0fea342ad2 | 726 | */ |
| gkroussos | 0:dd0fea342ad2 | 727 | SVCALL(SD_FLASH_WRITE, uint32_t, sd_flash_write(uint32_t * const p_dst, uint32_t const * const p_src, uint32_t size)); |
| gkroussos | 0:dd0fea342ad2 | 728 | |
| gkroussos | 0:dd0fea342ad2 | 729 | |
| gkroussos | 0:dd0fea342ad2 | 730 | /**@brief Flash Erase page |
| gkroussos | 0:dd0fea342ad2 | 731 | * |
| gkroussos | 0:dd0fea342ad2 | 732 | * Commands to erase a flash page |
| gkroussos | 0:dd0fea342ad2 | 733 | * |
| gkroussos | 0:dd0fea342ad2 | 734 | * This call initiates the flash access command, and its completion will be communicated to the |
| gkroussos | 0:dd0fea342ad2 | 735 | * application with exactly one of the following events: |
| gkroussos | 0:dd0fea342ad2 | 736 | * - NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed. |
| gkroussos | 0:dd0fea342ad2 | 737 | * - NRF_EVT_FLASH_OPERATION_ERROR - The command could not be started. |
| gkroussos | 0:dd0fea342ad2 | 738 | * |
| gkroussos | 0:dd0fea342ad2 | 739 | * @note |
| gkroussos | 0:dd0fea342ad2 | 740 | * - This call takes control over the radio and the CPU during flash erase and write to make sure that |
| gkroussos | 0:dd0fea342ad2 | 741 | * they will not interfere with the flash access. This means that all interrupts will be blocked |
| gkroussos | 0:dd0fea342ad2 | 742 | * for a predictable time (depending on the NVMC specification in nRF51 Series Reference Manual |
| gkroussos | 0:dd0fea342ad2 | 743 | * and the command parameters). |
| gkroussos | 0:dd0fea342ad2 | 744 | * |
| gkroussos | 0:dd0fea342ad2 | 745 | * |
| gkroussos | 0:dd0fea342ad2 | 746 | * @param[in] page_number Pagenumber of the page to erase |
| gkroussos | 0:dd0fea342ad2 | 747 | * @retval ::NRF_ERROR_INTERNAL If a new session could not be opened due to an internal error. |
| gkroussos | 0:dd0fea342ad2 | 748 | * @retval ::NRF_ERROR_INVALID_ADDR Tried to erase to a non existing flash page. |
| gkroussos | 0:dd0fea342ad2 | 749 | * @retval ::NRF_ERROR_BUSY The previous command has not yet completed. |
| gkroussos | 0:dd0fea342ad2 | 750 | * @retval ::NRF_ERROR_FORBIDDEN Tried to erase a protected page. |
| gkroussos | 0:dd0fea342ad2 | 751 | * @retval ::NRF_SUCCESS The command was accepted. |
| gkroussos | 0:dd0fea342ad2 | 752 | */ |
| gkroussos | 0:dd0fea342ad2 | 753 | SVCALL(SD_FLASH_ERASE_PAGE, uint32_t, sd_flash_page_erase(uint32_t page_number)); |
| gkroussos | 0:dd0fea342ad2 | 754 | |
| gkroussos | 0:dd0fea342ad2 | 755 | |
| gkroussos | 0:dd0fea342ad2 | 756 | /**@brief Flash Protection set |
| gkroussos | 0:dd0fea342ad2 | 757 | * |
| gkroussos | 0:dd0fea342ad2 | 758 | * Commands to set the flash protection registers PROTENSETx |
| gkroussos | 0:dd0fea342ad2 | 759 | * |
| gkroussos | 0:dd0fea342ad2 | 760 | * @note To read the values in PROTENSETx you can read them directly. They are only write-protected. |
| gkroussos | 0:dd0fea342ad2 | 761 | * |
| gkroussos | 0:dd0fea342ad2 | 762 | * @param[in] protenset0 Value to be written to PROTENSET0 |
| gkroussos | 0:dd0fea342ad2 | 763 | * @param[in] protenset1 Value to be written to PROTENSET1 |
| gkroussos | 0:dd0fea342ad2 | 764 | * |
| gkroussos | 0:dd0fea342ad2 | 765 | * @retval ::NRF_ERROR_FORBIDDEN Tried to protect the SoftDevice |
| gkroussos | 0:dd0fea342ad2 | 766 | * @retval ::NRF_SUCCESS Values successfully written to PROTENSETx |
| gkroussos | 0:dd0fea342ad2 | 767 | */ |
| gkroussos | 0:dd0fea342ad2 | 768 | SVCALL(SD_FLASH_PROTECT, uint32_t, sd_flash_protect(uint32_t protenset0, uint32_t protenset1)); |
| gkroussos | 0:dd0fea342ad2 | 769 | |
| gkroussos | 0:dd0fea342ad2 | 770 | |
| gkroussos | 0:dd0fea342ad2 | 771 | /** @} */ |
| gkroussos | 0:dd0fea342ad2 | 772 | |
| gkroussos | 0:dd0fea342ad2 | 773 | #endif // NRF_SOC_H__ |
| gkroussos | 0:dd0fea342ad2 | 774 | |
| gkroussos | 0:dd0fea342ad2 | 775 | /** |
| gkroussos | 0:dd0fea342ad2 | 776 | @} |
| gkroussos | 0:dd0fea342ad2 | 777 | */ |