Mike Moore / mmSPI-2

This is an involuntary fork, created because the repository would not update mmSPI. SPI library used to communicate with an altera development board attached to four zigbee-header pins.

Dependents:   Embedded_RTOS_Project

Fork of mmSPI by Mike Moore

mmSPI.h@9:0551307e3b15, 2013-08-17 (annotated)

Committer:
gatedClock
Date:
Sat Aug 17 18:50:54 2013 +0000
Revision:
9:0551307e3b15
Parent:
8:e2d8bbc3e659
Child:
12:a1b7ce9c1d64
toward cpu clock toggle test.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gatedClock 2:bebcf53b72dc 1 #ifndef mmSPI_H // include guard.
gatedClock 2:bebcf53b72dc 2 #define mmSPI_H // include guard.
gatedClock 0:fb42c5acf810 3 /*----------------------------------------------//------------------------------
gatedClock 0:fb42c5acf810 4 student : m-moore
gatedClock 0:fb42c5acf810 5 class : external SPI interface
gatedClock 0:fb42c5acf810 6 directory : mmSPI
gatedClock 0:fb42c5acf810 7 file : mmSPI.h
gatedClock 1:15706d15d123 8 ----description---------------------------------//------------------------------
gatedClock 1:15706d15d123 9 ----notes---------------------------------------//------------------------------
gatedClock 1:15706d15d123 10 1. the SPI interface pins are routed to the zigbee header.
gatedClock 0:fb42c5acf810 11 ------------------------------------------------//----------------------------*/
gatedClock 0:fb42c5acf810 12 #include "mbed.h" // standard mbed.org class.
gatedClock 1:15706d15d123 13 //---defines------------------------------------//------------------------------
gatedClock 8:e2d8bbc3e659 14 #define mmSPI_MOSI p29 // SPI interface pin.
gatedClock 8:e2d8bbc3e659 15 #define mmSPI_MISO p30 // SPI interface pin.
gatedClock 8:e2d8bbc3e659 16 #define mmSPI_SCLK p9 // SPI interface pin.
gatedClock 8:e2d8bbc3e659 17 #define mmCPU_CLK p10 // soft CPU system clock.
gatedClock 0:fb42c5acf810 18 /*----------------------------------------------//------------------------------
gatedClock 0:fb42c5acf810 19 ------------------------------------------------//----------------------------*/
gatedClock 2:bebcf53b72dc 20
gatedClock 0:fb42c5acf810 21 //==============================================//==============================
gatedClock 0:fb42c5acf810 22 class mmSPI
gatedClock 0:fb42c5acf810 23 {
gatedClock 0:fb42c5acf810 24 public:
gatedClock 0:fb42c5acf810 25 mmSPI(); // constructor.
gatedClock 0:fb42c5acf810 26 ~mmSPI(); // destructor.
gatedClock 3:de99451ab3c0 27 void allocations(); // object allocations.
gatedClock 4:aa1fe8707bef 28 void setSPIfrequency(float); // set SPI clock frequency.
gatedClock 6:b480fc4e87e5 29
gatedClock 6:b480fc4e87e5 30 // byte transceive.
gatedClock 6:b480fc4e87e5 31 void transceive_byte(char *cReceive, char *cSend);
gatedClock 7:b3e8b537d5c2 32
gatedClock 7:b3e8b537d5c2 33 // byte-array transceive.
gatedClock 7:b3e8b537d5c2 34 void transceive_vector(char *cReceive, char *cSend, char cNumBytes);
gatedClock 9:0551307e3b15 35
gatedClock 9:0551307e3b15 36 void test_toggle_cpu_clock(); // cpu clock toggle test.
gatedClock 0:fb42c5acf810 37 private:
gatedClock 2:bebcf53b72dc 38
gatedClock 3:de99451ab3c0 39 DigitalOut * pMOSI; // SPI pin.
gatedClock 3:de99451ab3c0 40 DigitalOut * pMISO; // SPI pin.
gatedClock 3:de99451ab3c0 41 DigitalOut * pSCLK; // SPI pin.
gatedClock 8:e2d8bbc3e659 42 DigitalOut * pCPUclk; // soft cpu clock.
gatedClock 4:aa1fe8707bef 43 float fSPIfreq; // SPI clock frequency.
gatedClock 4:aa1fe8707bef 44 float fSPIquarterP; // SPI quarter period.
gatedClock 5:b14dcaae260e 45 char cLoop01; // loop index.
gatedClock 7:b3e8b537d5c2 46 char cLoop02; // loop index.
gatedClock 3:de99451ab3c0 47
gatedClock 2:bebcf53b72dc 48
gatedClock 2:bebcf53b72dc 49
gatedClock 0:fb42c5acf810 50 };
gatedClock 2:bebcf53b72dc 51 //----------------------------------------------//------------------------------
gatedClock 2:bebcf53b72dc 52 #endif // include guard.