Mike Moore
This is an involuntary fork, created because the repository would not update mmSPI. SPI library used to communicate with an altera development board attached to four zigbee-header pins.
Dependents: Embedded_RTOS_Project
Fork of
mmSPI
by 
Mike Moore
Diff: mmSPI.cpp
- Revision:
- 31:ea7b25e494b5
- Parent:
- 30:331c7c7d8bc1
- Child:
- 32:5a5d9525c6c4
--- a/mmSPI.cpp Sun Aug 25 06:30:47 2013 +0000
+++ b/mmSPI.cpp Sun Aug 25 20:12:32 2013 +0000
@@ -70,7 +70,9 @@
//----------------------------------------------//------------------------------
// transceive a character array.
// MSB out/in first.
- void mmSPI::transceive_vector(void)
+ // normal inputs: [1,1,1,0]
+ // CPUstep input : [0,0,1,1]
+ void mmSPI::transceive_vector(char cPreCPU, char cPreSPI, char cScan, char cPostCPU)
{
int dClear;
int dIndex;
@@ -80,46 +82,69 @@
int dMisoBitIndex;
dIndex = (dNumBytes * 8) - 1;
- dMosiByteIndex = dIndex / 8;
- dMosiBitIndex = dIndex % 8;
+ dMosiByteIndex = dIndex / 8;
+ dMosiBitIndex = dIndex % 8;
for (dClear = 0; dClear < dNumBytes; dClear++) pcReceive[dClear] = 0;
-
- *pCPUclk = 1; // pulse the CPU clock.
- wait(fSPIquarterP);
- wait(fSPIquarterP);
- *pCPUclk = 0;
- wait(fSPIquarterP);
- wait(fSPIquarterP);
+ if (cPreCPU) // if pre-CPU clock.
+ {
+ *pCPUclk = 1; // pulse the CPU clock.
+ wait(fSPIquarterP);
+ wait(fSPIquarterP);
+ *pCPUclk = 0;
+ wait(fSPIquarterP);
+ wait(fSPIquarterP);
+ } // if pre-CPU clock.
- *pSCLK = 1; // pulse the SPI clock for parallel load.
- wait(fSPIquarterP);
- wait(fSPIquarterP);
- *pSCLK = 0;
+ if (cPreSPI) // if pre-SPI pulse.
+ {
+ *pSCLK = 1; // pulse the SPI clock for parallel load.
+ wait(fSPIquarterP);
+ wait(fSPIquarterP);
+ *pSCLK = 0;
+ } // if pre-SPI pulse.
+
+ if (cScan) // if cScan.
+ {
// pre-assert MOSI.
- *pMOSI = ((pcSend[dMosiByteIndex]) >> dMosiBitIndex) & 1;
- wait(fSPIquarterP);
- wait(fSPIquarterP);
+ *pMOSI = ((pcSend[dMosiByteIndex]) >> dMosiBitIndex) & 1;
+ wait(fSPIquarterP);
+ wait(fSPIquarterP);
- for (dIndex = (dNumBytes * 8) - 1; dIndex >= 0; dIndex--)
+ for (dIndex = (dNumBytes * 8) - 1; dIndex >= 0; dIndex--)
+ {
+ dMisoByteIndex = dIndex / 8;
+ dMisoBitIndex = dIndex % 8;
+ pcReceive[dMisoByteIndex] = pcReceive[dMisoByteIndex] | (*pMISO << dMisoBitIndex);
+ *pSCLK = 1;
+ wait(fSPIquarterP);
+ wait(fSPIquarterP);
+ *pSCLK = 0;
+ if (dIndex < 0) dIndex = 0;
+ dMosiByteIndex = (dIndex - 1) / 8;
+ dMosiBitIndex = (dIndex - 1) % 8;
+ *pMOSI = ((pcSend[dMosiByteIndex]) >> dMosiBitIndex) & 1;
+ wait(fSPIquarterP);
+ wait(fSPIquarterP);
+ }
+ } // if cScan.
+
+ if (cPostCPU) // if post-CPU pulse.
{
- dMisoByteIndex = dIndex / 8;
- dMisoBitIndex = dIndex % 8;
- pcReceive[dMisoByteIndex] = pcReceive[dMisoByteIndex] | (*pMISO << dMisoBitIndex);
- *pSCLK = 1;
+ *pCPUclk = 1; // pulse the CPU clock.
+ wait(fSPIquarterP);
+ wait(fSPIquarterP);
+ *pCPUclk = 0;
+ wait(fSPIquarterP);
+ wait(fSPIquarterP);
+
+ *pSCLK = 1; // clear-out the SPI parallel-load enable.
wait(fSPIquarterP);
wait(fSPIquarterP);
- *pSCLK = 0;
-
- if (dIndex < 0) dIndex = 0;
- dMosiByteIndex = (dIndex - 1) / 8;
- dMosiBitIndex = (dIndex - 1) % 8;
- *pMOSI = ((pcSend[dMosiByteIndex]) >> dMosiBitIndex) & 1;
- wait(fSPIquarterP);
- wait(fSPIquarterP);
- }
+ *pSCLK = 0;
+ } // if post-CPU pulse.
}
//----------------------------------------------//------------------------------
// cRegister -> CPU_register
@@ -144,7 +169,7 @@
pcSend[1] = ((cRegister & 0x07) << 2) | 0xA0;
pcSend[0] = cValue & 0xFF; // immediate value to i.w.
- transceive_vector(); // transmit command.
+ transceive_vector(1,1,1,0); // transmit command.
clear_transmit_vector(); // clear transmit vector.
}
@@ -166,7 +191,7 @@
pcSend[7] = 0x02; // suppress cpu operation.
- transceive_vector(); // snap & scan-out reg contents.
+ transceive_vector(1,1,1,0); // snap & scan-out reg contents.
return (pcReceive[6 - cRegister]); // return the particular reg value.
}
@@ -182,12 +207,12 @@
pcSend[7] = 0x02; // mbed sends command.
pcSend[1] = 0x02; // write-enable high.
pcSend[0] = 0x00; // remainder of instruction.
- transceive_vector();
+ transceive_vector(1,1,1,0);
pcSend[7] = 0x02; // mbed sends command.
pcSend[1] = 0x00; // write-enable low.
pcSend[0] = 0x00; // remainder of instruction.
- transceive_vector();
+ transceive_vector(1,1,1,0);
clear_transmit_vector(); // clear transmit vector.
}
@@ -206,17 +231,16 @@
pcSend[7] = 0x02; // mbed sends command.
pcSend[1] = 0xC8; // R2 <- MM[R3]
pcSend[0] = 0x00;
- transceive_vector(); // send command.
+ transceive_vector(1,1,1,0); // send command.
pcSend[7] = 0x02; // mbed sends command.
pcSend[1] = 0xC4; // R1 <- MM[R3]
pcSend[0] = 0x00;
- transceive_vector(); // send command.
+ transceive_vector(1,1,1,0); // send command.
cHData = read_register(0x02); // obtain MM high-data-byte.
cLData = read_register(0x01); // obtain MM low-data-byte.
-
-
+
udMemoryContent = (cHData << 8) + cLData; // build the memory word.
clear_transmit_vector(); // clear transmit vector.
@@ -226,12 +250,11 @@
//----------------------------------------------//------------------------------
void mmSPI::step(void) // step the CPU.
{
- *pCPUclk = 1; // pulse the CPU clock.
- wait(fSPIquarterP);
- wait(fSPIquarterP);
- *pCPUclk = 0;
- wait(fSPIquarterP);
- wait(fSPIquarterP);
+ clear_transmit_vector(); // clear transmit vector.
+ transceive_vector(0,0,1,0); // enable CPU mode.
+ transceive_vector(0,0,0,1); // advance CPU, clear shadow-load.
+ pcSend[7] = 0x02; // ready to disable CPU mode.
+ transceive_vector(0,0,1,0); // disable CPU mode.
}
//----------------------------------------------//------------------------------
void mmSPI::clear_transmit_vector(void) // fill transmit buffer with 0.