Diff: mmRTL/scan_16.txt

Revision:

3:659ffc90b59e

Child:

7:d1aca9ccbab8

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/scan_16.txt	Sun Sep 01 02:53:39 2013 +0000
@@ -0,0 +1,74 @@
+/*----------------------------------copyright---------------------------------*/
+//  licensed for personal and academic use.
+//  commercial use must be approved by the account-holder of
+//  gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+    module scan_16              // shadow register.
+        (
+         oParallel,             // parallel-output data.
+         iParallel,             // parallel-input  data.
+     oSerial,               // serial-output data.
+     iSerial,               // serial-input data.
+     iLoadEnable,               // parallel-load-enable.
+     iShiftEnable,              // serial-shift-enable.
+     iResetN,               // synchronous reset*.
+     iClk                   // module clock.
+        );
+/*--------------------------------description-----------------------------------
+    a 16-bit parallel shift-register.
+-------------------------------------notes--------------------------------------
+    shifting is LSB->MSB.
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+    output  [15:0]  oParallel;      // parallel-output data.
+    input   [15:0]  iParallel;      // parallel-input  data.
+    output          oSerial;        // serial-output data.
+    input           iSerial;        // serial-input data.
+    input           iLoadEnable;        // parallel-load-enable.
+    input           iShiftEnable;       // serial-shift-enable.
+    input           iResetN;        // synchronous reset*.
+    input           iClk;           // module clock.
+/*-----------------------------------wires------------------------------------*/
+    wire    [15:0]  oParallel;      // parallel-output data.
+    wire    [15:0]  iParallel;      // parallel-input  data.
+    wire    [15:0]  wParallelIn;        // select the parallel input.
+    wire            oSerial;        // serial-output data.
+    wire            iSerial;        // serial-input data.
+    wire            iLoadEnable;        // parallel-load-enable.
+    wire            iShiftEnable;       // serial-shift-enable.
+    wire            iResetN;        // synchronous reset*.
+    wire            iClk;           // module clock.
+/*---------------------------------registers----------------------------------*/
+        reg     [15:0]  rRegister;      // the register.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+/*-----------------------------------logic------------------------------------*/
+    always @ (posedge iClk or negedge iResetN)
+    begin
+           if (!iResetN)     rRegister[15:0] <= 16'h0000;
+      else if (iLoadEnable)  rRegister[15:0] <= iParallel[15:0];
+      else if (iShiftEnable) rRegister[15:0] <= {rRegister[14:0], iSerial};
+      else                   rRegister[15:0] <= rRegister[15:0];
+    end
+
+    assign oParallel[15:0] = rRegister[15:0];       // propagate parallel-out.
+    assign oSerial   = rRegister[15];   // propagate serial-out.
+/*-------------------------------*/endmodule/*--------------------------------*/
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