File content as of revision 5:4409ff66b434:

/*----------------------------------copyright---------------------------------*/
//      licensed for personal and academic use.
//      commercial use must be approved by the account-holder of
//      gated.clock@gmail.com
/*-----------------------------------module-----------------------------------*/
        module mux8x16
        (
          iDin15,                               // data-input 15.
          iDin14,                               // data-input 14.
          iDin13,                               // data-input 13.
          iDin12,                               // data-input 12.
          iDin11,                               // data-input 11.
          iDin10,                               // data-input 10.
          iDin9,                                // data-input 9.
          iDin8,                                // data-input 8.
          iDin7,                                // data-input 7.
          iDin6,                                // data-input 6.
          iDin5,                                // data-input 5.
          iDin4,                                // data-input 4.
          iDin3,                                // data-input 3.
          iDin2,                                // data-input 2.
          iDin1,                                // data-input 1.
          iDin0,                                // data-input 0.
          iSel,                                 // multiplexor select.
          oDout                                 // data-out.
        );
/*--------------------------------description-----------------------------------
        a 8-bit-wide, 16-selection multiplexor.
-------------------------------------notes--------------------------------------
------------------------------------defines-----------------------------------*/
/*-----------------------------------ports------------------------------------*/
        input   [ 7:0]  iDin15;                 // data-input 15.
        input   [ 7:0]  iDin14;                 // data-input 14.
        input   [ 7:0]  iDin13;                 // data-input 13.
        input   [ 7:0]  iDin12;                 // data-input 12.
        input   [ 7:0]  iDin11;                 // data-input 11.
        input   [ 7:0]  iDin10;                 // data-input 10.
        input   [ 7:0]  iDin9;                  // data-input 9.
        input   [ 7:0]  iDin8;                  // data-input 8.
        input   [ 7:0]  iDin7;                  // data-input 7.
        input   [ 7:0]  iDin6;                  // data-input 6.
        input   [ 7:0]  iDin5;                  // data-input 5.
        input   [ 7:0]  iDin4;                  // data-input 4.
        input   [ 7:0]  iDin3;                  // data-input 3.
        input   [ 7:0]  iDin2;                  // data-input 2.
        input   [ 7:0]  iDin1;                  // data-input 1.
        input   [ 7:0]  iDin0;                  // data-input 0.
        input   [ 3:0]  iSel;                   // multiplexor select.
        output  [ 7:0]  oDout;                  // data-out.
/*-----------------------------------wires------------------------------------*/
        wire    [ 7:0]  iDin15;                 // data-input 15.
        wire    [ 7:0]  iDin14;                 // data-input 14.
        wire    [ 7:0]  iDin13;                 // data-input 13.
        wire    [ 7:0]  iDin12;                 // data-input 12.
        wire    [ 7:0]  iDin11;                 // data-input 11.
        wire    [ 7:0]  iDin10;                 // data-input 10.
        wire    [ 7:0]  iDin9;                  // data-input 9.
        wire    [ 7:0]  iDin8;                  // data-input 8.
        wire    [ 7:0]  iDin7;                  // data-input 7.
        wire    [ 7:0]  iDin6;                  // data-input 6.
        wire    [ 7:0]  iDin5;                  // data-input 5.
        wire    [ 7:0]  iDin4;                  // data-input 4.
        wire    [ 7:0]  iDin3;                  // data-input 3.
        wire    [ 7:0]  iDin2;                  // data-input 2.
        wire    [ 7:0]  iDin1;                  // data-input 1.
        wire    [ 7:0]  iDin0;                  // data-input 0.
        wire    [ 3:0]  iSel;                   // multiplexor select.
        wire    [ 7:0]  oDout;                  // data-out.
/*---------------------------------registers----------------------------------*/
        reg     [ 7:0]  rDout;                  // output register.
/*---------------------------------variables----------------------------------*/
/*---------------------------------parameters---------------------------------*/
/*-----------------------------------clocks-----------------------------------*/
/*---------------------------------instances----------------------------------*/
/*-----------------------------------logic------------------------------------*/

        always @ (iDin15 or iDin14 or iDin13 or iDin12 or
                  iDin11 or iDin10 or iDin9  or iDin8  or
                  iDin7  or iDin6  or iDin5  or iDin4  or
                  iDin3  or iDin2  or iDin1  or iDin0  or iSel)
        case (iSel)
        15 : rDout = iDin15;
        14 : rDout = iDin14;
        13 : rDout = iDin13;
        12 : rDout = iDin12;
        11 : rDout = iDin11;
        10 : rDout = iDin10;
         9 : rDout = iDin9;
         8 : rDout = iDin8;
         7 : rDout = iDin7;
         6 : rDout = iDin6;
         5 : rDout = iDin5;
         4 : rDout = iDin4;
         3 : rDout = iDin3;
         2 : rDout = iDin2;
         1 : rDout = iDin1;
         0 : rDout = iDin0;
        endcase

        assign oDout = rDout;                   // propagate output.
/*-------------------------------*/endmodule/*--------------------------------*/