Mike Moore
embedded RTOS class project.
Dependencies: C12832_lcd USBDevice mbed-rtos mbed mmSPI_RTOS watchdog_RTOS
Fork of
RTOS_project_fork_01
by 
Mike Moore
Diff: mmRTL/reg_08.txt
- Revision:
- 0:8e898e1270d6
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/reg_08.txt Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,128 @@
+/*----------------------------------copyright---------------------------------*/
+// licensed for personal and academic use.
+// commercial use must be approved by the account-holder of
+// gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+ module reg_08
+ (
+ oParallel, // parallel-output data.
+ iParallel7, // parallel-input data.
+ iParallel6, // parallel-input data.
+ iParallel5, // parallel-input data.
+ iParallel4, // parallel-input data.
+ iParallel3, // parallel-input data.
+ iParallel2, // parallel-input data.
+ iParallel1, // parallel-input data.
+ iParallel0, // parallel-input data.
+ iSel, // select the parallel input.
+ oSerial, // serial-output data.
+ iSerial, // serial-input data.
+ iLoadEnable, // parallel-load-enable.
+ iShiftEnable, // serial-shift-enable.
+ iResetN, // synchronous reset*.
+ iClk // module clock.
+ );
+/*--------------------------------description-----------------------------------
+ an 8-bit parallel shift-register with 8 selectable input buses.
+-------------------------------------notes--------------------------------------
+ shifting is LSB->MSB.
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+ output [ 7:0] oParallel; // parallel-output data.
+ input [ 7:0] iParallel7; // parallel-input data.
+ input [ 7:0] iParallel6; // parallel-input data.
+ input [ 7:0] iParallel5; // parallel-input data.
+ input [ 7:0] iParallel4; // parallel-input data.
+ input [ 7:0] iParallel3; // parallel-input data.
+ input [ 7:0] iParallel2; // parallel-input data.
+ input [ 7:0] iParallel1; // parallel-input data.
+ input [ 7:0] iParallel0; // parallel-input data.
+ input [ 2:0] iSel; // select the parallel input.
+ output oSerial; // serial-output data.
+ input iSerial; // serial-input data.
+ input iLoadEnable; // parallel-load-enable.
+ input iShiftEnable; // serial-shift-enable.
+ input iResetN; // synchronous reset*.
+ input iClk; // module clock.
+/*-----------------------------------wires------------------------------------*/
+ wire [ 7:0] oParallel; // parallel-output data.
+ wire [ 7:0] iParallel7; // parallel-input data.
+ wire [ 7:0] iParallel6; // parallel-input data.
+ wire [ 7:0] iParallel5; // parallel-input data.
+ wire [ 7:0] iParallel4; // parallel-input data.
+ wire [ 7:0] iParallel3; // parallel-input data.
+ wire [ 7:0] iParallel2; // parallel-input data.
+ wire [ 7:0] iParallel1; // parallel-input data.
+ wire [ 7:0] iParallel0; // parallel-input data.
+ wire [ 2:0] iSel; // select the parallel input.
+ wire [ 7:0] wParallelIn; // select the parallel input.
+ wire oSerial; // serial-output data.
+ wire iSerial; // serial-input data.
+ wire iLoadEnable; // parallel-load-enable.
+ wire iShiftEnable; // serial-shift-enable.
+ wire iResetN; // synchronous reset*.
+ wire iClk; // module clock.
+/*---------------------------------registers----------------------------------*/
+ reg [ 7:0] rRegister; // the register.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+ mux8x8 U01_mux8x8 // data-input selection.
+ (
+ .iDin7(iParallel7),
+ .iDin6(iParallel6),
+ .iDin5(iParallel5),
+ .iDin4(iParallel4),
+ .iDin3(iParallel3),
+ .iDin2(iParallel2),
+ .iDin1(iParallel1),
+ .iDin0(iParallel0),
+ .iSel (iSel),
+ .oDout(wParallelIn)
+ );
+/*-----------------------------------logic------------------------------------*/
+ always @ (posedge iClk or negedge iResetN)
+ begin
+ if (!iResetN) rRegister <= 8'h00;
+ else if (iLoadEnable) rRegister <= wParallelIn;
+ else if (iShiftEnable) rRegister <= {rRegister[6:0], iSerial};
+ else rRegister <= rRegister;
+ end
+
+ assign oParallel = rRegister; // propagate parallel-out.
+ assign oSerial = rRegister[7]; // propagate serial-out.
+/*-------------------------------*/endmodule/*--------------------------------*/
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