Mike Moore / Mbed 2 deprecated RTOS_project_fork_02

embedded RTOS class project.

Dependencies:   C12832_lcd USBDevice mbed-rtos mbed mmSPI_RTOS watchdog_RTOS

Fork of RTOS_project_fork_01 by Mike Moore

mmRTL/mux8x8.txt@0:8e898e1270d6, 2013-09-17 (annotated)

Committer:
gatedClock
Date:
Tue Sep 17 19:42:49 2013 +0000
Revision:
0:8e898e1270d6
title.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gatedClock 0:8e898e1270d6 1 /*----------------------------------copyright---------------------------------*/
gatedClock 0:8e898e1270d6 2 // licensed for personal and academic use.
gatedClock 0:8e898e1270d6 3 // commercial use must be approved by the account-holder of
gatedClock 0:8e898e1270d6 4 // gated.clock@gmail.com
gatedClock 0:8e898e1270d6 5 /*-----------------------------------module-----------------------------------*/
gatedClock 0:8e898e1270d6 6 module mux8x8
gatedClock 0:8e898e1270d6 7 (
gatedClock 0:8e898e1270d6 8 iDin7, // data-input 7.
gatedClock 0:8e898e1270d6 9 iDin6, // data-input 6.
gatedClock 0:8e898e1270d6 10 iDin5, // data-input 5.
gatedClock 0:8e898e1270d6 11 iDin4, // data-input 4.
gatedClock 0:8e898e1270d6 12 iDin3, // data-input 3.
gatedClock 0:8e898e1270d6 13 iDin2, // data-input 2.
gatedClock 0:8e898e1270d6 14 iDin1, // data-input 1.
gatedClock 0:8e898e1270d6 15 iDin0, // data-input 0.
gatedClock 0:8e898e1270d6 16 iSel, // multiplexor select.
gatedClock 0:8e898e1270d6 17 oDout // data-out.
gatedClock 0:8e898e1270d6 18 );
gatedClock 0:8e898e1270d6 19 /*--------------------------------description-----------------------------------
gatedClock 0:8e898e1270d6 20 an 8-bit-wide, 8-selection multiplexor.
gatedClock 0:8e898e1270d6 21 -------------------------------------notes--------------------------------------
gatedClock 0:8e898e1270d6 22 ------------------------------------defines-----------------------------------*/
gatedClock 0:8e898e1270d6 23 /*-----------------------------------ports------------------------------------*/
gatedClock 0:8e898e1270d6 24 input [ 7:0] iDin7; // data-input 7.
gatedClock 0:8e898e1270d6 25 input [ 7:0] iDin6; // data-input 6.
gatedClock 0:8e898e1270d6 26 input [ 7:0] iDin5; // data-input 5.
gatedClock 0:8e898e1270d6 27 input [ 7:0] iDin4; // data-input 4.
gatedClock 0:8e898e1270d6 28 input [ 7:0] iDin3; // data-input 3.
gatedClock 0:8e898e1270d6 29 input [ 7:0] iDin2; // data-input 2.
gatedClock 0:8e898e1270d6 30 input [ 7:0] iDin1; // data-input 1.
gatedClock 0:8e898e1270d6 31 input [ 7:0] iDin0; // data-input 0.
gatedClock 0:8e898e1270d6 32 input [ 2:0] iSel; // multiplexor select.
gatedClock 0:8e898e1270d6 33 output [ 7:0] oDout; // data-out.
gatedClock 0:8e898e1270d6 34 /*-----------------------------------wires------------------------------------*/
gatedClock 0:8e898e1270d6 35 wire [ 7:0] iDin7; // data-input 7.
gatedClock 0:8e898e1270d6 36 wire [ 7:0] iDin6; // data-input 6.
gatedClock 0:8e898e1270d6 37 wire [ 7:0] iDin5; // data-input 5.
gatedClock 0:8e898e1270d6 38 wire [ 7:0] iDin4; // data-input 4.
gatedClock 0:8e898e1270d6 39 wire [ 7:0] iDin3; // data-input 3.
gatedClock 0:8e898e1270d6 40 wire [ 7:0] iDin2; // data-input 2.
gatedClock 0:8e898e1270d6 41 wire [ 7:0] iDin1; // data-input 1.
gatedClock 0:8e898e1270d6 42 wire [ 7:0] iDin0; // data-input 0.
gatedClock 0:8e898e1270d6 43 wire [ 2:0] iSel; // multiplexor select.
gatedClock 0:8e898e1270d6 44 wire [ 7:0] oDout; // data-out.
gatedClock 0:8e898e1270d6 45 /*---------------------------------registers----------------------------------*/
gatedClock 0:8e898e1270d6 46 reg [ 7:0] rDout; // output register.
gatedClock 0:8e898e1270d6 47 /*---------------------------------variables----------------------------------*/
gatedClock 0:8e898e1270d6 48 /*---------------------------------parameters---------------------------------*/
gatedClock 0:8e898e1270d6 49 /*-----------------------------------clocks-----------------------------------*/
gatedClock 0:8e898e1270d6 50 /*---------------------------------instances----------------------------------*/
gatedClock 0:8e898e1270d6 51 /*-----------------------------------logic------------------------------------*/
gatedClock 0:8e898e1270d6 52 always @ (iDin7 or iDin6 or iDin5 or iDin4 or
gatedClock 0:8e898e1270d6 53 iDin3 or iDin2 or iDin1 or iDin0 or iSel)
gatedClock 0:8e898e1270d6 54 case (iSel)
gatedClock 0:8e898e1270d6 55 7 : rDout = iDin7;
gatedClock 0:8e898e1270d6 56 6 : rDout = iDin6;
gatedClock 0:8e898e1270d6 57 5 : rDout = iDin5;
gatedClock 0:8e898e1270d6 58 4 : rDout = iDin4;
gatedClock 0:8e898e1270d6 59 3 : rDout = iDin3;
gatedClock 0:8e898e1270d6 60 2 : rDout = iDin2;
gatedClock 0:8e898e1270d6 61 1 : rDout = iDin1;
gatedClock 0:8e898e1270d6 62 0 : rDout = iDin0;
gatedClock 0:8e898e1270d6 63 endcase
gatedClock 0:8e898e1270d6 64
gatedClock 0:8e898e1270d6 65 assign oDout = rDout; // propagate output.
gatedClock 0:8e898e1270d6 66 /*-------------------------------*/endmodule/*--------------------------------*/
gatedClock 0:8e898e1270d6 67
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