Mike Moore / Mbed 2 deprecated RTOS_project_fork_02

embedded RTOS class project.

Dependencies:   C12832_lcd USBDevice mbed-rtos mbed mmSPI_RTOS watchdog_RTOS

Fork of RTOS_project_fork_01 by Mike Moore

mmRTL/cpu.txt@5:4409ff66b434, 2013-09-18 (annotated)

Committer:
gatedClock
Date:
Wed Sep 18 14:58:03 2013 +0000
Revision:
5:4409ff66b434
Parent:
0:8e898e1270d6 
test results.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gatedClock 0:8e898e1270d6 1 /*----------------------------------copyright---//----------------------------*/
gatedClock 0:8e898e1270d6 2 // licensed for personal and academic use.
gatedClock 0:8e898e1270d6 3 // commercial use must be approved by the account-holder of
gatedClock 0:8e898e1270d6 4 // gated.clock@gmail.com
gatedClock 0:8e898e1270d6 5 /*-----------------------------------module-----//----------------------------*/
gatedClock 0:8e898e1270d6 6 module cpu
gatedClock 0:8e898e1270d6 7 (
gatedClock 0:8e898e1270d6 8 iMOSI,
gatedClock 0:8e898e1270d6 9 oMISO,
gatedClock 0:8e898e1270d6 10 iSPIclk,
gatedClock 0:8e898e1270d6 11 iCPUclk,
gatedClock 0:8e898e1270d6 12 iKEY,
gatedClock 0:8e898e1270d6 13 iSW,
gatedClock 0:8e898e1270d6 14 oLEDR,
gatedClock 0:8e898e1270d6 15 oLEDG,
gatedClock 0:8e898e1270d6 16 oDummyLoad
gatedClock 0:8e898e1270d6 17 );
gatedClock 0:8e898e1270d6 18 /*--------------------------------description---//------------------------------
gatedClock 0:8e898e1270d6 19 the demonstration cpu datapath.
gatedClock 0:8e898e1270d6 20
gatedClock 0:8e898e1270d6 21 the CPU consists of
gatedClock 0:8e898e1270d6 22 R0 - 8-bit register and accumulator.
gatedClock 0:8e898e1270d6 23 R1 - 8-bit register and main-memory address register.
gatedClock 0:8e898e1270d6 24 R2 - 8-bit register and main-memory high data byte.
gatedClock 0:8e898e1270d6 25 R3 - 8-bit register and main-memory low data byte.
gatedClock 0:8e898e1270d6 26 PC - 8-bit program counter.
gatedClock 0:8e898e1270d6 27 IR - 16-bit instruction register.
gatedClock 0:8e898e1270d6 28 ID - combinatorial instruction decoder.
gatedClock 0:8e898e1270d6 29 MM - 16-bit-wide x 256-address Main Memory.
gatedClock 0:8e898e1270d6 30
gatedClock 0:8e898e1270d6 31 the instruction words is sixteen bits long, and is comprised of
gatedClock 0:8e898e1270d6 32 <15:13> = source resource.
gatedClock 0:8e898e1270d6 33 <12:10> = destination resource.
gatedClock 0:8e898e1270d6 34 < 9> = write-enable.
gatedClock 0:8e898e1270d6 35 < 8> = program-counter-enable.
gatedClock 0:8e898e1270d6 36 < 7: 0> = immediate data.
gatedClock 0:8e898e1270d6 37
gatedClock 0:8e898e1270d6 38 the registers (U00 through U05) have a iSel input which define the source.
gatedClock 0:8e898e1270d6 39 the instruction decoder (U06) enables the loading of the destinations.
gatedClock 0:8e898e1270d6 40
gatedClock 0:8e898e1270d6 41 the SPI shadow registers (U19-U25) monitor the CPU state, and can
gatedClock 0:8e898e1270d6 42 control the CPU state by asserting U19's bits 1 and 2.
gatedClock 0:8e898e1270d6 43
gatedClock 0:8e898e1270d6 44 U08 provides a shadow register load-enable pulse which
gatedClock 0:8e898e1270d6 45 begins at the falling edge of a CPU clock and ends at
gatedClock 0:8e898e1270d6 46 the falling edge of the next SPI clock, allowing the shadow
gatedClock 0:8e898e1270d6 47 registers the ability to capture the state of the CPU.
gatedClock 0:8e898e1270d6 48
gatedClock 0:8e898e1270d6 49 U30 routes internal nets out to the green LED bank according
gatedClock 0:8e898e1270d6 50 to the setting of switches SW<3:0>.
gatedClock 0:8e898e1270d6 51
gatedClock 0:8e898e1270d6 52 -------------------------------------notes------//------------------------------
gatedClock 0:8e898e1270d6 53
gatedClock 0:8e898e1270d6 54 fpga board pin assignments.
gatedClock 0:8e898e1270d6 55
gatedClock 0:8e898e1270d6 56
gatedClock 0:8e898e1270d6 57 project:
gatedClock 0:8e898e1270d6 58 MOSI P17
gatedClock 0:8e898e1270d6 59 MISO D15
gatedClock 0:8e898e1270d6 60 SPIclk E20
gatedClock 0:8e898e1270d6 61 CPUclk E14
gatedClock 0:8e898e1270d6 62
gatedClock 0:8e898e1270d6 63
gatedClock 0:8e898e1270d6 64 key3 T21
gatedClock 0:8e898e1270d6 65 key2 T22
gatedClock 0:8e898e1270d6 66 key1 R21
gatedClock 0:8e898e1270d6 67 key0 R22 iRstn
gatedClock 0:8e898e1270d6 68
gatedClock 0:8e898e1270d6 69 sw9 L2
gatedClock 0:8e898e1270d6 70 sw8 M1
gatedClock 0:8e898e1270d6 71 sw7 M2
gatedClock 0:8e898e1270d6 72 sw6 U11
gatedClock 0:8e898e1270d6 73 sw5 U12
gatedClock 0:8e898e1270d6 74 sw4 W12
gatedClock 0:8e898e1270d6 75 sw3 V12
gatedClock 0:8e898e1270d6 76 sw2 M22
gatedClock 0:8e898e1270d6 77 sw1 L21
gatedClock 0:8e898e1270d6 78 sw0 L22
gatedClock 0:8e898e1270d6 79
gatedClock 0:8e898e1270d6 80 ledr9 R17
gatedClock 0:8e898e1270d6 81 ledr8 R18
gatedClock 0:8e898e1270d6 82 ledr7 U18
gatedClock 0:8e898e1270d6 83 ledr6 Y18
gatedClock 0:8e898e1270d6 84 ledr5 V19
gatedClock 0:8e898e1270d6 85 ledr4 T18
gatedClock 0:8e898e1270d6 86 ledr3 Y19
gatedClock 0:8e898e1270d6 87 ledr2 U19
gatedClock 0:8e898e1270d6 88 ledr1 R19
gatedClock 0:8e898e1270d6 89 ledr0 R20
gatedClock 0:8e898e1270d6 90
gatedClock 0:8e898e1270d6 91 ledg7 Y21
gatedClock 0:8e898e1270d6 92 ledg6 Y22
gatedClock 0:8e898e1270d6 93 ledg5 W21
gatedClock 0:8e898e1270d6 94 ledg4 W22
gatedClock 0:8e898e1270d6 95 ledg3 V21
gatedClock 0:8e898e1270d6 96 ledg2 V22
gatedClock 0:8e898e1270d6 97 ledg1 U21
gatedClock 0:8e898e1270d6 98 ledg0 U22
gatedClock 0:8e898e1270d6 99 ------------------------------------defines-----//----------------------------*/
gatedClock 0:8e898e1270d6 100 /*-----------------------------------ports------//----------------------------*/
gatedClock 0:8e898e1270d6 101 input iMOSI; // SPI input.
gatedClock 0:8e898e1270d6 102 output oMISO; // SPI output.
gatedClock 0:8e898e1270d6 103 input iSPIclk; // SPI clock.
gatedClock 0:8e898e1270d6 104 input iCPUclk; // CPU clock.
gatedClock 0:8e898e1270d6 105 input [ 3:0] iKEY; // keypress.
gatedClock 0:8e898e1270d6 106 input [ 9:0] iSW; // slide-switches.
gatedClock 0:8e898e1270d6 107 output [ 9:0] oLEDR; // red LED bank.
gatedClock 0:8e898e1270d6 108 output [ 7:0] oLEDG; // green LED bank.
gatedClock 0:8e898e1270d6 109 output oDummyLoad; // anti-optimization.
gatedClock 0:8e898e1270d6 110 /*-----------------------------------wires------//----------------------------*/
gatedClock 0:8e898e1270d6 111 wire iMOSI; // SPI input.
gatedClock 0:8e898e1270d6 112 wire oMISO; // SPI output.
gatedClock 0:8e898e1270d6 113 wire iSPIclk; // SPI clock.
gatedClock 0:8e898e1270d6 114 wire iCPUclk; // CPU clock.
gatedClock 0:8e898e1270d6 115 wire [ 3:0] iKEY; // keypress.
gatedClock 0:8e898e1270d6 116 wire [ 9:0] iSW; // slide-switches.
gatedClock 0:8e898e1270d6 117 wire [ 9:0] oLEDR; // red LED bank.
gatedClock 0:8e898e1270d6 118 wire [ 7:0] oLEDG; // green LED bank.
gatedClock 0:8e898e1270d6 119
gatedClock 0:8e898e1270d6 120 wire wCEPC; // program counter count-enable.
gatedClock 0:8e898e1270d6 121 wire [15:0] wIR; // instruction register.
gatedClock 0:8e898e1270d6 122 wire wLEIR; // instruction register load-enable.
gatedClock 0:8e898e1270d6 123 wire wLEPC; // program counter load-enable.
gatedClock 0:8e898e1270d6 124 wire wLER0; // R0 load-enable.
gatedClock 0:8e898e1270d6 125 wire wLER1; // R1 load-enable.
gatedClock 0:8e898e1270d6 126 wire wLER2; // R2 load-enable.
gatedClock 0:8e898e1270d6 127 wire wLER3; // R3 load-enable.
gatedClock 0:8e898e1270d6 128 wire [15:0] wMMD; // main-memory data-out.
gatedClock 0:8e898e1270d6 129 wire [15:0] wMMI; // main-memory instruction-out.
gatedClock 0:8e898e1270d6 130 wire [ 7:0] wPC; // program-counter.
gatedClock 0:8e898e1270d6 131 wire [ 7:0] wR0; // R0.
gatedClock 0:8e898e1270d6 132 wire [ 7:0] wR1; // R1.
gatedClock 0:8e898e1270d6 133 wire [ 7:0] wR2; // R2.
gatedClock 0:8e898e1270d6 134 wire [ 7:0] wR3; // R3.
gatedClock 0:8e898e1270d6 135 wire wRstn; // system reset.
gatedClock 0:8e898e1270d6 136 wire [ 2:0] wSel; // common data-in selector.
gatedClock 0:8e898e1270d6 137 wire [ 7:0] wShadow0; // R0 shadow register.
gatedClock 0:8e898e1270d6 138 wire [ 7:0] wShadow1; // R1 shadow register.
gatedClock 0:8e898e1270d6 139 wire [ 7:0] wShadow2; // R2 shadow register.
gatedClock 0:8e898e1270d6 140 wire [ 7:0] wShadow3; // R3 shadow register.
gatedClock 0:8e898e1270d6 141 wire [15:0] wShadowIR; // instruction register shadow.
gatedClock 0:8e898e1270d6 142 wire [ 7:0] wShadowPC; // program counter shadow.
gatedClock 0:8e898e1270d6 143 wire wSIR; // instruction register shadow shift-up.
gatedClock 0:8e898e1270d6 144 wire wSPC; // program counter shadow shift-up.
gatedClock 0:8e898e1270d6 145 wire wSR0; // R0 shadow shift-up.
gatedClock 0:8e898e1270d6 146 wire wSR1; // R1 shadow shift-up.
gatedClock 0:8e898e1270d6 147 wire wSR2; // R2 shadow shift-up.
gatedClock 0:8e898e1270d6 148 wire wSR3; // R3 shadow shift-up.
gatedClock 0:8e898e1270d6 149 wire wWE; // write-enable pulse.
gatedClock 0:8e898e1270d6 150 wire [ 7:0] wImmediate; // immediate data.
gatedClock 0:8e898e1270d6 151 wire [ 7:0] wSpiControl; // from spi control register.
gatedClock 0:8e898e1270d6 152 wire wSquelch; // from spi control register.
gatedClock 0:8e898e1270d6 153 wire wBypassIR; // from spi control register.
gatedClock 0:8e898e1270d6 154 wire wLoadShadows; // shadow registers parallel load.
gatedClock 0:8e898e1270d6 155
gatedClock 0:8e898e1270d6 156 // not currently used.
gatedClock 0:8e898e1270d6 157 wire [ 7:0] wGreenLEDBus7; // green LED bus.
gatedClock 0:8e898e1270d6 158 wire [ 7:0] wGreenLEDBus6; // green LED bus.
gatedClock 0:8e898e1270d6 159 wire [ 7:0] wGreenLEDBus5; // green LED bus.
gatedClock 0:8e898e1270d6 160 wire [ 7:0] wGreenLEDBus4; // green LED bus.
gatedClock 0:8e898e1270d6 161 wire [ 7:0] wGreenLEDBus3; // green LED bus.
gatedClock 0:8e898e1270d6 162 wire [ 7:0] wGreenLEDBus2; // green LED bus.
gatedClock 0:8e898e1270d6 163 wire [ 7:0] wGreenLEDBus1; // green LED bus.
gatedClock 0:8e898e1270d6 164 wire [ 7:0] wGreenLEDBus0; // green LED bus.
gatedClock 0:8e898e1270d6 165 wire oDummyLoad; // anti-optimization.
gatedClock 0:8e898e1270d6 166 wire [ 3:0] wTrigger; // trigger control.
gatedClock 0:8e898e1270d6 167 /*---------------------------------registers----//----------------------------*/
gatedClock 0:8e898e1270d6 168 /*---------------------------------variables----//----------------------------*/
gatedClock 0:8e898e1270d6 169 /*---------------------------------parameters---//----------------------------*/
gatedClock 0:8e898e1270d6 170 /*-----------------------------------clocks-----//----------------------------*/
gatedClock 0:8e898e1270d6 171 /*---------------------------------instances----//----------------------------*/
gatedClock 0:8e898e1270d6 172
gatedClock 0:8e898e1270d6 173 //--- begin regular CPU section.
gatedClock 0:8e898e1270d6 174
gatedClock 0:8e898e1270d6 175
gatedClock 0:8e898e1270d6 176 reg_08 U00_R0 // CPU R0.
gatedClock 0:8e898e1270d6 177 (
gatedClock 0:8e898e1270d6 178 .oParallel (wR0),
gatedClock 0:8e898e1270d6 179 .iParallel7 (wShadow0),
gatedClock 0:8e898e1270d6 180 .iParallel6 (wR1 + wR2), // adder.
gatedClock 0:8e898e1270d6 181 .iParallel5 (wImmediate),
gatedClock 0:8e898e1270d6 182 .iParallel4 (wR0),
gatedClock 0:8e898e1270d6 183 .iParallel3 (wR3),
gatedClock 0:8e898e1270d6 184 .iParallel2 (wR2),
gatedClock 0:8e898e1270d6 185 .iParallel1 (wR1),
gatedClock 0:8e898e1270d6 186 .iParallel0 (wR0), // needed for zero vector no-op.
gatedClock 0:8e898e1270d6 187 .iSel (wSel),
gatedClock 0:8e898e1270d6 188 .oSerial (),
gatedClock 0:8e898e1270d6 189 .iSerial (1'b0),
gatedClock 0:8e898e1270d6 190 .iLoadEnable (wLER0),
gatedClock 0:8e898e1270d6 191 .iShiftEnable(1'b0),
gatedClock 0:8e898e1270d6 192 .iResetN (wRstn),
gatedClock 0:8e898e1270d6 193 .iClk (iCPUclk)
gatedClock 0:8e898e1270d6 194 );
gatedClock 0:8e898e1270d6 195
gatedClock 0:8e898e1270d6 196
gatedClock 0:8e898e1270d6 197
gatedClock 0:8e898e1270d6 198 reg_08 U01_R1 // CPU R1.
gatedClock 0:8e898e1270d6 199 (
gatedClock 0:8e898e1270d6 200 .oParallel (wR1),
gatedClock 0:8e898e1270d6 201 .iParallel7 (wShadow1),
gatedClock 0:8e898e1270d6 202 .iParallel6 (wMMD[7:0]),
gatedClock 0:8e898e1270d6 203 .iParallel5 (wImmediate),
gatedClock 0:8e898e1270d6 204 .iParallel4 (wR1),
gatedClock 0:8e898e1270d6 205 .iParallel3 (wR3),
gatedClock 0:8e898e1270d6 206 .iParallel2 (wR2),
gatedClock 0:8e898e1270d6 207 .iParallel1 (wR1),
gatedClock 0:8e898e1270d6 208 .iParallel0 (wR0),
gatedClock 0:8e898e1270d6 209 .iSel (wSel),
gatedClock 0:8e898e1270d6 210 .oSerial (),
gatedClock 0:8e898e1270d6 211 .iSerial (1'b0),
gatedClock 0:8e898e1270d6 212 .iLoadEnable (wLER1),
gatedClock 0:8e898e1270d6 213 .iShiftEnable(1'b0),
gatedClock 0:8e898e1270d6 214 .iResetN (wRstn),
gatedClock 0:8e898e1270d6 215 .iClk (iCPUclk)
gatedClock 0:8e898e1270d6 216 );
gatedClock 0:8e898e1270d6 217
gatedClock 0:8e898e1270d6 218
gatedClock 0:8e898e1270d6 219
gatedClock 0:8e898e1270d6 220 reg_08 U02_R2 // CPU R2.
gatedClock 0:8e898e1270d6 221 (
gatedClock 0:8e898e1270d6 222 .oParallel (wR2),
gatedClock 0:8e898e1270d6 223 .iParallel7 (wShadow2),
gatedClock 0:8e898e1270d6 224 .iParallel6 (wMMD[15:8]),
gatedClock 0:8e898e1270d6 225 .iParallel5 (wImmediate),
gatedClock 0:8e898e1270d6 226 .iParallel4 (wR2),
gatedClock 0:8e898e1270d6 227 .iParallel3 (wR3),
gatedClock 0:8e898e1270d6 228 .iParallel2 (wR2),
gatedClock 0:8e898e1270d6 229 .iParallel1 (wR1),
gatedClock 0:8e898e1270d6 230 .iParallel0 (wR0),
gatedClock 0:8e898e1270d6 231 .iSel (wSel),
gatedClock 0:8e898e1270d6 232 .oSerial (),
gatedClock 0:8e898e1270d6 233 .iSerial (1'b0),
gatedClock 0:8e898e1270d6 234 .iLoadEnable (wLER2),
gatedClock 0:8e898e1270d6 235 .iShiftEnable(1'b0),
gatedClock 0:8e898e1270d6 236 .iResetN (wRstn),
gatedClock 0:8e898e1270d6 237 .iClk (iCPUclk)
gatedClock 0:8e898e1270d6 238 );
gatedClock 0:8e898e1270d6 239
gatedClock 0:8e898e1270d6 240
gatedClock 0:8e898e1270d6 241 reg_08 U03_R3 // CPU R3.
gatedClock 0:8e898e1270d6 242 (
gatedClock 0:8e898e1270d6 243 .oParallel (wR3),
gatedClock 0:8e898e1270d6 244 .iParallel7 (wShadow3),
gatedClock 0:8e898e1270d6 245 .iParallel6 (wMMD[7:0]),
gatedClock 0:8e898e1270d6 246 .iParallel5 (wImmediate),
gatedClock 0:8e898e1270d6 247 .iParallel4 (wR3),
gatedClock 0:8e898e1270d6 248 .iParallel3 (wR3),
gatedClock 0:8e898e1270d6 249 .iParallel2 (wR2),
gatedClock 0:8e898e1270d6 250 .iParallel1 (wR1),
gatedClock 0:8e898e1270d6 251 .iParallel0 (wR0),
gatedClock 0:8e898e1270d6 252 .iSel (wSel),
gatedClock 0:8e898e1270d6 253 .oSerial (),
gatedClock 0:8e898e1270d6 254 .iSerial (1'b0),
gatedClock 0:8e898e1270d6 255 .iLoadEnable (wLER3),
gatedClock 0:8e898e1270d6 256 .iShiftEnable(1'b0),
gatedClock 0:8e898e1270d6 257 .iResetN (wRstn),
gatedClock 0:8e898e1270d6 258 .iClk (iCPUclk)
gatedClock 0:8e898e1270d6 259 );
gatedClock 0:8e898e1270d6 260
gatedClock 0:8e898e1270d6 261
gatedClock 0:8e898e1270d6 262
gatedClock 0:8e898e1270d6 263 counter_08 U04_PC // CPU program counter.
gatedClock 0:8e898e1270d6 264 (
gatedClock 0:8e898e1270d6 265 .oCount (wPC),
gatedClock 0:8e898e1270d6 266 .iParallel7 (wShadowPC),
gatedClock 0:8e898e1270d6 267 .iParallel6 (wMMD[7:0]),
gatedClock 0:8e898e1270d6 268 .iParallel5 (wImmediate),
gatedClock 0:8e898e1270d6 269 .iParallel4 (wPC),
gatedClock 0:8e898e1270d6 270 .iParallel3 (wR3),
gatedClock 0:8e898e1270d6 271 .iParallel2 (wR2),
gatedClock 0:8e898e1270d6 272 .iParallel1 (wR1),
gatedClock 0:8e898e1270d6 273 .iParallel0 (wR0),
gatedClock 0:8e898e1270d6 274 .iSel (wSel),
gatedClock 0:8e898e1270d6 275 .oSerial (),
gatedClock 0:8e898e1270d6 276 .iSerial (1'b0),
gatedClock 0:8e898e1270d6 277 .iLoadEnable (wLEPC),
gatedClock 0:8e898e1270d6 278 .iShiftEnable(1'b0),
gatedClock 0:8e898e1270d6 279 .iCountEnable(wCEPC),
gatedClock 0:8e898e1270d6 280 .iResetN (wRstn),
gatedClock 0:8e898e1270d6 281 .iClk (iCPUclk)
gatedClock 0:8e898e1270d6 282 );
gatedClock 0:8e898e1270d6 283
gatedClock 0:8e898e1270d6 284
gatedClock 0:8e898e1270d6 285 reg_16 U05_IR // CPU instruction register.
gatedClock 0:8e898e1270d6 286 (
gatedClock 0:8e898e1270d6 287 .oParallel (wIR), // IR state.
gatedClock 0:8e898e1270d6 288 .iParallel1 (wShadowIR), // IR shadow state.
gatedClock 0:8e898e1270d6 289 .iParallel0 (wMMI), // MM output.
gatedClock 0:8e898e1270d6 290 .iSel (wSpiControl[2]), // special control.
gatedClock 0:8e898e1270d6 291 .oSerial (),
gatedClock 0:8e898e1270d6 292 .iSerial (1'b0),
gatedClock 0:8e898e1270d6 293 .iLoadEnable (wLEIR),
gatedClock 0:8e898e1270d6 294 .iShiftEnable(1'b0),
gatedClock 0:8e898e1270d6 295 .iResetN (wRstn),
gatedClock 0:8e898e1270d6 296 .iClk (iCPUclk)
gatedClock 0:8e898e1270d6 297 );
gatedClock 0:8e898e1270d6 298
gatedClock 0:8e898e1270d6 299
gatedClock 0:8e898e1270d6 300 instruction_decoder U06_ID // instruction decoder.
gatedClock 0:8e898e1270d6 301 (
gatedClock 0:8e898e1270d6 302 .iSquelch (wSquelch), // squelch when writing to IR.
gatedClock 0:8e898e1270d6 303 .iIR (wIR), // instruction register.
gatedClock 0:8e898e1270d6 304 .iBypass (wShadowIR), // IR bypass from SPI.
gatedClock 0:8e898e1270d6 305 .iBypassIR (wBypassIR), // bypass the IR.
gatedClock 0:8e898e1270d6 306 .oSel (wSel), // common data-in selector.
gatedClock 0:8e898e1270d6 307 .oLER0 (wLER0), // R0 load-enable.
gatedClock 0:8e898e1270d6 308 .oLER1 (wLER1), // R1 load-enable.
gatedClock 0:8e898e1270d6 309 .oLER2 (wLER2), // R2 load-enable.
gatedClock 0:8e898e1270d6 310 .oLER3 (wLER3), // R3 load-enable.
gatedClock 0:8e898e1270d6 311 .oLEPC (wLEPC), // PC load-enable.
gatedClock 0:8e898e1270d6 312 .oWE (wWE), // write-enable pulse.
gatedClock 0:8e898e1270d6 313 .oCEPC (wCEPC), // PC count-enable.
gatedClock 0:8e898e1270d6 314 .oImmediate(wImmediate) // immediate data.
gatedClock 0:8e898e1270d6 315 );
gatedClock 0:8e898e1270d6 316
gatedClock 0:8e898e1270d6 317
gatedClock 0:8e898e1270d6 318
gatedClock 0:8e898e1270d6 319 // main memory:
gatedClock 0:8e898e1270d6 320 // the program counter reads from read-port-0.
gatedClock 0:8e898e1270d6 321 // the R2:R1 port reads from read-port-1.
gatedClock 0:8e898e1270d6 322 // the R2:R1 port writes to the write port.
gatedClock 0:8e898e1270d6 323 // the R2:R1 port reads/writes using address from R3.
gatedClock 0:8e898e1270d6 324
gatedClock 0:8e898e1270d6 325
gatedClock 0:8e898e1270d6 326 main_memory U07_MM // main-memory.
gatedClock 0:8e898e1270d6 327 (
gatedClock 0:8e898e1270d6 328 .iReadAddress1(wR3), // from R3.
gatedClock 0:8e898e1270d6 329 .iReadAddress0(wPC), // from PC
gatedClock 0:8e898e1270d6 330 .iWriteAddress(wR3), // from R3
gatedClock 0:8e898e1270d6 331 .oReadData1 (wMMD), // to <R2:R1>
gatedClock 0:8e898e1270d6 332 .oReadData0 (wMMI), // to IR.
gatedClock 0:8e898e1270d6 333 .iWriteData ({wR2,wR1}), // from <R2:R1>.
gatedClock 0:8e898e1270d6 334 .iWE (wWE), // from the instruction decoder.
gatedClock 0:8e898e1270d6 335 .iCPUclk (iCPUclk)
gatedClock 0:8e898e1270d6 336 );
gatedClock 0:8e898e1270d6 337
gatedClock 0:8e898e1270d6 338
gatedClock 0:8e898e1270d6 339 // load shadow-registers upon rising
gatedClock 0:8e898e1270d6 340 // edge of first SPI clock following
gatedClock 0:8e898e1270d6 341 // the falling edge of a CPU clock.
gatedClock 0:8e898e1270d6 342 shadow_load_control U08_shadow_load // shadow-register load control.
gatedClock 0:8e898e1270d6 343 (
gatedClock 0:8e898e1270d6 344 .iCPUclk(iCPUclk),
gatedClock 0:8e898e1270d6 345 .iSPIclk(iSPIclk),
gatedClock 0:8e898e1270d6 346 .iRstn(wRstn),
gatedClock 0:8e898e1270d6 347 .oLoadEnable(wLoadShadows)
gatedClock 0:8e898e1270d6 348 );
gatedClock 0:8e898e1270d6 349
gatedClock 0:8e898e1270d6 350
gatedClock 0:8e898e1270d6 351 //--- begin SPI shadow-scan section.
gatedClock 0:8e898e1270d6 352
gatedClock 0:8e898e1270d6 353
gatedClock 0:8e898e1270d6 354 // the SPI scan registers are generally
gatedClock 0:8e898e1270d6 355 // given the term 'shadow registers'.
gatedClock 0:8e898e1270d6 356
gatedClock 0:8e898e1270d6 357
gatedClock 0:8e898e1270d6 358 scan_08 U19_spi_control // top of SPI scan chain, used for control.
gatedClock 0:8e898e1270d6 359 (
gatedClock 0:8e898e1270d6 360 .oParallel (wSpiControl), // green LED select 7.
gatedClock 0:8e898e1270d6 361 .iParallel (wSpiControl), // self-refresh.
gatedClock 0:8e898e1270d6 362 .oSerial (oMISO),
gatedClock 0:8e898e1270d6 363 .iSerial (wSR0),
gatedClock 0:8e898e1270d6 364 .iLoadEnable (wLoadShadows),
gatedClock 0:8e898e1270d6 365 .iShiftEnable(1'b1),
gatedClock 0:8e898e1270d6 366 .iResetN (wRstn),
gatedClock 0:8e898e1270d6 367 .iClk (iSPIclk)
gatedClock 0:8e898e1270d6 368 );
gatedClock 0:8e898e1270d6 369
gatedClock 0:8e898e1270d6 370
gatedClock 0:8e898e1270d6 371
gatedClock 0:8e898e1270d6 372 scan_08 U20_shadowR0 // R0 shadow register.
gatedClock 0:8e898e1270d6 373 (
gatedClock 0:8e898e1270d6 374 .oParallel (wShadow0), // green LED select 6.
gatedClock 0:8e898e1270d6 375 .iParallel (wR0),
gatedClock 0:8e898e1270d6 376 .oSerial (wSR0),
gatedClock 0:8e898e1270d6 377 .iSerial (wSR1),
gatedClock 0:8e898e1270d6 378 .iLoadEnable (wLoadShadows),
gatedClock 0:8e898e1270d6 379 .iShiftEnable(1'b1),
gatedClock 0:8e898e1270d6 380 .iResetN (wRstn),
gatedClock 0:8e898e1270d6 381 .iClk (iSPIclk)
gatedClock 0:8e898e1270d6 382 );
gatedClock 0:8e898e1270d6 383
gatedClock 0:8e898e1270d6 384 scan_08 U21_shadowR1 // R1 shadow register.
gatedClock 0:8e898e1270d6 385 (
gatedClock 0:8e898e1270d6 386 .oParallel (wShadow1), // green LED select 5.
gatedClock 0:8e898e1270d6 387 .iParallel (wR1),
gatedClock 0:8e898e1270d6 388 .oSerial (wSR1),
gatedClock 0:8e898e1270d6 389 .iSerial (wSR2),
gatedClock 0:8e898e1270d6 390 .iLoadEnable (wLoadShadows),
gatedClock 0:8e898e1270d6 391 .iShiftEnable(1'b1),
gatedClock 0:8e898e1270d6 392 .iResetN (wRstn),
gatedClock 0:8e898e1270d6 393 .iClk (iSPIclk)
gatedClock 0:8e898e1270d6 394 );
gatedClock 0:8e898e1270d6 395
gatedClock 0:8e898e1270d6 396 scan_08 U22_shadowR2 // R2 shadow register.
gatedClock 0:8e898e1270d6 397 (
gatedClock 0:8e898e1270d6 398 .oParallel (wShadow2), // green LED select 4.
gatedClock 0:8e898e1270d6 399 .iParallel (wR2),
gatedClock 0:8e898e1270d6 400 .oSerial (wSR2),
gatedClock 0:8e898e1270d6 401 .iSerial (wSR3),
gatedClock 0:8e898e1270d6 402 .iLoadEnable (wLoadShadows),
gatedClock 0:8e898e1270d6 403 .iShiftEnable(1'b1),
gatedClock 0:8e898e1270d6 404 .iResetN (wRstn),
gatedClock 0:8e898e1270d6 405 .iClk (iSPIclk)
gatedClock 0:8e898e1270d6 406 );
gatedClock 0:8e898e1270d6 407
gatedClock 0:8e898e1270d6 408 scan_08 U23_shadowR3 // R3 shadow register.
gatedClock 0:8e898e1270d6 409 (
gatedClock 0:8e898e1270d6 410 .oParallel (wShadow3), // green LED select 3.
gatedClock 0:8e898e1270d6 411 .iParallel (wR3),
gatedClock 0:8e898e1270d6 412 .oSerial (wSR3),
gatedClock 0:8e898e1270d6 413 .iSerial (wSPC),
gatedClock 0:8e898e1270d6 414 .iLoadEnable (wLoadShadows),
gatedClock 0:8e898e1270d6 415 .iShiftEnable(1'b1),
gatedClock 0:8e898e1270d6 416 .iResetN (wRstn),
gatedClock 0:8e898e1270d6 417 .iClk (iSPIclk)
gatedClock 0:8e898e1270d6 418 );
gatedClock 0:8e898e1270d6 419
gatedClock 0:8e898e1270d6 420 scan_08 U24_shadowPC // program-counter shadow register.
gatedClock 0:8e898e1270d6 421 (
gatedClock 0:8e898e1270d6 422 .oParallel (wShadowPC), // green LED select 2.
gatedClock 0:8e898e1270d6 423 .iParallel (wPC),
gatedClock 0:8e898e1270d6 424 .oSerial (wSPC),
gatedClock 0:8e898e1270d6 425 .iSerial (wSIR),
gatedClock 0:8e898e1270d6 426 .iLoadEnable (wLoadShadows),
gatedClock 0:8e898e1270d6 427 .iShiftEnable(1'b1),
gatedClock 0:8e898e1270d6 428 .iResetN (wRstn),
gatedClock 0:8e898e1270d6 429 .iClk (iSPIclk)
gatedClock 0:8e898e1270d6 430 );
gatedClock 0:8e898e1270d6 431
gatedClock 0:8e898e1270d6 432 scan_16 U25_shadowIR // instruction-register shadow register.
gatedClock 0:8e898e1270d6 433 (
gatedClock 0:8e898e1270d6 434 .oParallel (wShadowIR), // green LED select 1,0.
gatedClock 0:8e898e1270d6 435 .iParallel (wIR),
gatedClock 0:8e898e1270d6 436 .oSerial (wSIR),
gatedClock 0:8e898e1270d6 437 .iSerial (iMOSI),
gatedClock 0:8e898e1270d6 438 .iLoadEnable (wLoadShadows),
gatedClock 0:8e898e1270d6 439 .iShiftEnable(1'b1),
gatedClock 0:8e898e1270d6 440 .iResetN (wRstn),
gatedClock 0:8e898e1270d6 441 .iClk (iSPIclk)
gatedClock 0:8e898e1270d6 442 );
gatedClock 0:8e898e1270d6 443
gatedClock 0:8e898e1270d6 444
gatedClock 0:8e898e1270d6 445
gatedClock 0:8e898e1270d6 446 //--- begin green LED signal-monitoring section.
gatedClock 0:8e898e1270d6 447
gatedClock 0:8e898e1270d6 448
gatedClock 0:8e898e1270d6 449
gatedClock 0:8e898e1270d6 450 mux8x16 U30_green_led_mux // green LED diagnostic mux.
gatedClock 0:8e898e1270d6 451 (
gatedClock 0:8e898e1270d6 452 .iDin15({wLER0,wLER1,wLER2,wLER3,wLEPC,wLEIR,wWE,wCEPC}),
gatedClock 0:8e898e1270d6 453 .iDin14(wIR[15:8]), // IR-H.
gatedClock 0:8e898e1270d6 454 .iDin13(wIR[7:0]), // IR-L.
gatedClock 0:8e898e1270d6 455 .iDin12(wPC), // PC.
gatedClock 0:8e898e1270d6 456 .iDin11(wR3), // R3.
gatedClock 0:8e898e1270d6 457 .iDin10(wR2), // R2.
gatedClock 0:8e898e1270d6 458 .iDin9 (wR1), // R1.
gatedClock 0:8e898e1270d6 459 .iDin8 (wR0), // R0.
gatedClock 0:8e898e1270d6 460 .iDin7 (wSpiControl), // SPI control.
gatedClock 0:8e898e1270d6 461 .iDin6 (wShadowIR[15:8]), // IR-H shadow.
gatedClock 0:8e898e1270d6 462 .iDin5 (wShadowIR[7:0]), // IR-L shadow.
gatedClock 0:8e898e1270d6 463 .iDin4 (wShadowPC), // PC shadow.
gatedClock 0:8e898e1270d6 464 .iDin3 (wShadow3), // R3 shadow.
gatedClock 0:8e898e1270d6 465 .iDin2 (wShadow2), // R2 shadow.
gatedClock 0:8e898e1270d6 466 .iDin1 (wShadow1), // R1 shadow.
gatedClock 0:8e898e1270d6 467 .iDin0 (wShadow0), // R0 shadow.
gatedClock 0:8e898e1270d6 468 .iSel (iSW[3:0]), // mux-select.
gatedClock 0:8e898e1270d6 469 .oDout (oLEDG) // to green LED bank.
gatedClock 0:8e898e1270d6 470 );
gatedClock 0:8e898e1270d6 471 /*-----------------------------------logic------//----------------------------*/
gatedClock 0:8e898e1270d6 472 assign wRstn = iKEY[0]; // pushbutton system reset.
gatedClock 0:8e898e1270d6 473 assign wSquelch = wSpiControl[2]; // for python squelching ins. decode.
gatedClock 0:8e898e1270d6 474 assign wBypassIR = wSpiControl[1]; // for python controlling CPU.
gatedClock 0:8e898e1270d6 475 assign wTrigger = wSpiControl[7:4]; // for signaltap triggering, not used.
gatedClock 0:8e898e1270d6 476
gatedClock 0:8e898e1270d6 477 // load instruction register
gatedClock 0:8e898e1270d6 478 // if neither or both shadow
gatedClock 0:8e898e1270d6 479 // control signals asserted.
gatedClock 0:8e898e1270d6 480 assign wLEIR = !(wSquelch ^ wBypassIR);
gatedClock 0:8e898e1270d6 481
gatedClock 0:8e898e1270d6 482
gatedClock 0:8e898e1270d6 483 assign oLEDR[9] = 1'b0; // red LED hookup.
gatedClock 0:8e898e1270d6 484 assign oLEDR[8] = 1'b0;
gatedClock 0:8e898e1270d6 485 assign oLEDR[7] = wSel[2];
gatedClock 0:8e898e1270d6 486 assign oLEDR[6] = wSel[1];
gatedClock 0:8e898e1270d6 487 assign oLEDR[5] = wSel[0];
gatedClock 0:8e898e1270d6 488 assign oLEDR[4] = wRstn;
gatedClock 0:8e898e1270d6 489 assign oLEDR[3] = iCPUclk;
gatedClock 0:8e898e1270d6 490 assign oLEDR[2] = oMISO;
gatedClock 0:8e898e1270d6 491 assign oLEDR[1] = iMOSI;
gatedClock 0:8e898e1270d6 492 assign oLEDR[0] = iSPIclk;
gatedClock 0:8e898e1270d6 493
gatedClock 0:8e898e1270d6 494
gatedClock 0:8e898e1270d6 495 // signals not to be optimized
gatedClock 0:8e898e1270d6 496 // out, place here.
gatedClock 0:8e898e1270d6 497 assign oDummyLoad = (|wShadowIR) | wSIR | (|wSpiControl) | (|wTrigger);
gatedClock 0:8e898e1270d6 498 /*-------------------------------*/endmodule/*--------------------------------*/
gatedClock 0:8e898e1270d6 499
gatedClock 0:8e898e1270d6 500
gatedClock 0:8e898e1270d6 501
gatedClock 0:8e898e1270d6 502
gatedClock 0:8e898e1270d6 503
gatedClock 0:8e898e1270d6 504
gatedClock 0:8e898e1270d6 505
gatedClock 0:8e898e1270d6 506
gatedClock 0:8e898e1270d6 507
gatedClock 0:8e898e1270d6 508
gatedClock 0:8e898e1270d6 509
gatedClock 0:8e898e1270d6 510
gatedClock 0:8e898e1270d6 511
gatedClock 0:8e898e1270d6 512
gatedClock 0:8e898e1270d6 513
gatedClock 0:8e898e1270d6 514
gatedClock 0:8e898e1270d6 515
gatedClock 0:8e898e1270d6 516
gatedClock 0:8e898e1270d6 517
gatedClock 0:8e898e1270d6 518
gatedClock 0:8e898e1270d6 519
gatedClock 0:8e898e1270d6 520
gatedClock 0:8e898e1270d6 521
gatedClock 0:8e898e1270d6 522
gatedClock 0:8e898e1270d6 523
gatedClock 0:8e898e1270d6 524
gatedClock 0:8e898e1270d6 525
gatedClock 0:8e898e1270d6 526
gatedClock 0:8e898e1270d6 527
gatedClock 0:8e898e1270d6 528
gatedClock 0:8e898e1270d6 529
gatedClock 0:8e898e1270d6 530
gatedClock 0:8e898e1270d6 531