Mike Moore / Mbed 2 deprecated RTOS_project_fork_01

embedded RTOS class project.

Fork of RTOS_project by Mike Moore

mmRTL/scan_08.txt@4:e3887e314551, 2013-09-17 (annotated)

Committer:
gatedClock
Date:
Tue Sep 17 23:59:15 2013 +0000
Revision:
4:e3887e314551
Parent:
0:8e898e1270d6 
add to structure initialization function.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gatedClock 0:8e898e1270d6 1 /*----------------------------------copyright---------------------------------*/
gatedClock 0:8e898e1270d6 2 // licensed for personal and academic use.
gatedClock 0:8e898e1270d6 3 // commercial use must be approved by the account-holder of
gatedClock 0:8e898e1270d6 4 // gated.clock@gmail.com
gatedClock 0:8e898e1270d6 5 /*-----------------------------------module-----------------------------------*/
gatedClock 0:8e898e1270d6 6 module scan_08 // shadow register.
gatedClock 0:8e898e1270d6 7 (
gatedClock 0:8e898e1270d6 8 oParallel, // parallel-output data.
gatedClock 0:8e898e1270d6 9 iParallel, // parallel-input data.
gatedClock 0:8e898e1270d6 10 oSerial, // serial-output data.
gatedClock 0:8e898e1270d6 11 iSerial, // serial-input data.
gatedClock 0:8e898e1270d6 12 iLoadEnable, // parallel-load-enable.
gatedClock 0:8e898e1270d6 13 iShiftEnable, // serial-shift-enable.
gatedClock 0:8e898e1270d6 14 iResetN, // synchronous reset*.
gatedClock 0:8e898e1270d6 15 iClk // module clock.
gatedClock 0:8e898e1270d6 16 );
gatedClock 0:8e898e1270d6 17 /*--------------------------------description-----------------------------------
gatedClock 0:8e898e1270d6 18 an 8-bit parallel shift-register.
gatedClock 0:8e898e1270d6 19 -------------------------------------notes--------------------------------------
gatedClock 0:8e898e1270d6 20 shifting is LSB->MSB.
gatedClock 0:8e898e1270d6 21 ------------------------------------defines-----------------------------------*/
gatedClock 0:8e898e1270d6 22 /*-----------------------------------ports------------------------------------*/
gatedClock 0:8e898e1270d6 23 output [ 7:0] oParallel; // parallel-output data.
gatedClock 0:8e898e1270d6 24 input [ 7:0] iParallel; // parallel-input data.
gatedClock 0:8e898e1270d6 25 output oSerial; // serial-output data.
gatedClock 0:8e898e1270d6 26 input iSerial; // serial-input data.
gatedClock 0:8e898e1270d6 27 input iLoadEnable; // parallel-load-enable.
gatedClock 0:8e898e1270d6 28 input iShiftEnable; // serial-shift-enable.
gatedClock 0:8e898e1270d6 29 input iResetN; // synchronous reset*.
gatedClock 0:8e898e1270d6 30 input iClk; // module clock.
gatedClock 0:8e898e1270d6 31 /*-----------------------------------wires------------------------------------*/
gatedClock 0:8e898e1270d6 32 wire [ 7:0] oParallel; // parallel-output data.
gatedClock 0:8e898e1270d6 33 wire [ 7:0] iParallel; // parallel-input data.
gatedClock 0:8e898e1270d6 34 wire [ 7:0] wParallelIn; // select the parallel input.
gatedClock 0:8e898e1270d6 35 wire oSerial; // serial-output data.
gatedClock 0:8e898e1270d6 36 wire iSerial; // serial-input data.
gatedClock 0:8e898e1270d6 37 wire iLoadEnable; // parallel-load-enable.
gatedClock 0:8e898e1270d6 38 wire iShiftEnable; // serial-shift-enable.
gatedClock 0:8e898e1270d6 39 wire iResetN; // synchronous reset*.
gatedClock 0:8e898e1270d6 40 wire iClk; // module clock.
gatedClock 0:8e898e1270d6 41 /*---------------------------------registers----------------------------------*/
gatedClock 0:8e898e1270d6 42 reg [ 7:0] rRegister; // the register.
gatedClock 0:8e898e1270d6 43 /*---------------------------------variables----------------------------------*/
gatedClock 0:8e898e1270d6 44 /*---------------------------------parameters---------------------------------*/
gatedClock 0:8e898e1270d6 45 /*-----------------------------------clocks-----------------------------------*/
gatedClock 0:8e898e1270d6 46 /*---------------------------------instances----------------------------------*/
gatedClock 0:8e898e1270d6 47 /*-----------------------------------logic------------------------------------*/
gatedClock 0:8e898e1270d6 48 always @ (posedge iClk or negedge iResetN)
gatedClock 0:8e898e1270d6 49 begin
gatedClock 0:8e898e1270d6 50 if (!iResetN) rRegister <= 8'h00;
gatedClock 0:8e898e1270d6 51 else if (iLoadEnable) rRegister <= iParallel;
gatedClock 0:8e898e1270d6 52 else if (iShiftEnable) rRegister <= {rRegister[6:0], iSerial};
gatedClock 0:8e898e1270d6 53 else rRegister <= rRegister;
gatedClock 0:8e898e1270d6 54 end
gatedClock 0:8e898e1270d6 55
gatedClock 0:8e898e1270d6 56 assign oParallel = rRegister; // propagate parallel-out.
gatedClock 0:8e898e1270d6 57 assign oSerial = rRegister[7]; // propagate serial-out.
gatedClock 0:8e898e1270d6 58 /*-------------------------------*/endmodule/*--------------------------------*/
gatedClock 0:8e898e1270d6 59
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