Mike Moore / Mbed 2 deprecated RTOS_project_fork_01

embedded RTOS class project.

Fork of RTOS_project by Mike Moore

mmRTL/mux8x16.txt@4:e3887e314551, 2013-09-17 (annotated)

Committer:
gatedClock
Date:
Tue Sep 17 23:59:15 2013 +0000
Revision:
4:e3887e314551
Parent:
0:8e898e1270d6 
add to structure initialization function.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gatedClock 0:8e898e1270d6 1 /*----------------------------------copyright---------------------------------*/
gatedClock 0:8e898e1270d6 2 // licensed for personal and academic use.
gatedClock 0:8e898e1270d6 3 // commercial use must be approved by the account-holder of
gatedClock 0:8e898e1270d6 4 // gated.clock@gmail.com
gatedClock 0:8e898e1270d6 5 /*-----------------------------------module-----------------------------------*/
gatedClock 0:8e898e1270d6 6 module mux8x16
gatedClock 0:8e898e1270d6 7 (
gatedClock 0:8e898e1270d6 8 iDin15, // data-input 15.
gatedClock 0:8e898e1270d6 9 iDin14, // data-input 14.
gatedClock 0:8e898e1270d6 10 iDin13, // data-input 13.
gatedClock 0:8e898e1270d6 11 iDin12, // data-input 12.
gatedClock 0:8e898e1270d6 12 iDin11, // data-input 11.
gatedClock 0:8e898e1270d6 13 iDin10, // data-input 10.
gatedClock 0:8e898e1270d6 14 iDin9, // data-input 9.
gatedClock 0:8e898e1270d6 15 iDin8, // data-input 8.
gatedClock 0:8e898e1270d6 16 iDin7, // data-input 7.
gatedClock 0:8e898e1270d6 17 iDin6, // data-input 6.
gatedClock 0:8e898e1270d6 18 iDin5, // data-input 5.
gatedClock 0:8e898e1270d6 19 iDin4, // data-input 4.
gatedClock 0:8e898e1270d6 20 iDin3, // data-input 3.
gatedClock 0:8e898e1270d6 21 iDin2, // data-input 2.
gatedClock 0:8e898e1270d6 22 iDin1, // data-input 1.
gatedClock 0:8e898e1270d6 23 iDin0, // data-input 0.
gatedClock 0:8e898e1270d6 24 iSel, // multiplexor select.
gatedClock 0:8e898e1270d6 25 oDout // data-out.
gatedClock 0:8e898e1270d6 26 );
gatedClock 0:8e898e1270d6 27 /*--------------------------------description-----------------------------------
gatedClock 0:8e898e1270d6 28 a 8-bit-wide, 16-selection multiplexor.
gatedClock 0:8e898e1270d6 29 -------------------------------------notes--------------------------------------
gatedClock 0:8e898e1270d6 30 ------------------------------------defines-----------------------------------*/
gatedClock 0:8e898e1270d6 31 /*-----------------------------------ports------------------------------------*/
gatedClock 0:8e898e1270d6 32 input [ 7:0] iDin15; // data-input 15.
gatedClock 0:8e898e1270d6 33 input [ 7:0] iDin14; // data-input 14.
gatedClock 0:8e898e1270d6 34 input [ 7:0] iDin13; // data-input 13.
gatedClock 0:8e898e1270d6 35 input [ 7:0] iDin12; // data-input 12.
gatedClock 0:8e898e1270d6 36 input [ 7:0] iDin11; // data-input 11.
gatedClock 0:8e898e1270d6 37 input [ 7:0] iDin10; // data-input 10.
gatedClock 0:8e898e1270d6 38 input [ 7:0] iDin9; // data-input 9.
gatedClock 0:8e898e1270d6 39 input [ 7:0] iDin8; // data-input 8.
gatedClock 0:8e898e1270d6 40 input [ 7:0] iDin7; // data-input 7.
gatedClock 0:8e898e1270d6 41 input [ 7:0] iDin6; // data-input 6.
gatedClock 0:8e898e1270d6 42 input [ 7:0] iDin5; // data-input 5.
gatedClock 0:8e898e1270d6 43 input [ 7:0] iDin4; // data-input 4.
gatedClock 0:8e898e1270d6 44 input [ 7:0] iDin3; // data-input 3.
gatedClock 0:8e898e1270d6 45 input [ 7:0] iDin2; // data-input 2.
gatedClock 0:8e898e1270d6 46 input [ 7:0] iDin1; // data-input 1.
gatedClock 0:8e898e1270d6 47 input [ 7:0] iDin0; // data-input 0.
gatedClock 0:8e898e1270d6 48 input [ 3:0] iSel; // multiplexor select.
gatedClock 0:8e898e1270d6 49 output [ 7:0] oDout; // data-out.
gatedClock 0:8e898e1270d6 50 /*-----------------------------------wires------------------------------------*/
gatedClock 0:8e898e1270d6 51 wire [ 7:0] iDin15; // data-input 15.
gatedClock 0:8e898e1270d6 52 wire [ 7:0] iDin14; // data-input 14.
gatedClock 0:8e898e1270d6 53 wire [ 7:0] iDin13; // data-input 13.
gatedClock 0:8e898e1270d6 54 wire [ 7:0] iDin12; // data-input 12.
gatedClock 0:8e898e1270d6 55 wire [ 7:0] iDin11; // data-input 11.
gatedClock 0:8e898e1270d6 56 wire [ 7:0] iDin10; // data-input 10.
gatedClock 0:8e898e1270d6 57 wire [ 7:0] iDin9; // data-input 9.
gatedClock 0:8e898e1270d6 58 wire [ 7:0] iDin8; // data-input 8.
gatedClock 0:8e898e1270d6 59 wire [ 7:0] iDin7; // data-input 7.
gatedClock 0:8e898e1270d6 60 wire [ 7:0] iDin6; // data-input 6.
gatedClock 0:8e898e1270d6 61 wire [ 7:0] iDin5; // data-input 5.
gatedClock 0:8e898e1270d6 62 wire [ 7:0] iDin4; // data-input 4.
gatedClock 0:8e898e1270d6 63 wire [ 7:0] iDin3; // data-input 3.
gatedClock 0:8e898e1270d6 64 wire [ 7:0] iDin2; // data-input 2.
gatedClock 0:8e898e1270d6 65 wire [ 7:0] iDin1; // data-input 1.
gatedClock 0:8e898e1270d6 66 wire [ 7:0] iDin0; // data-input 0.
gatedClock 0:8e898e1270d6 67 wire [ 3:0] iSel; // multiplexor select.
gatedClock 0:8e898e1270d6 68 wire [ 7:0] oDout; // data-out.
gatedClock 0:8e898e1270d6 69 /*---------------------------------registers----------------------------------*/
gatedClock 0:8e898e1270d6 70 reg [ 7:0] rDout; // output register.
gatedClock 0:8e898e1270d6 71 /*---------------------------------variables----------------------------------*/
gatedClock 0:8e898e1270d6 72 /*---------------------------------parameters---------------------------------*/
gatedClock 0:8e898e1270d6 73 /*-----------------------------------clocks-----------------------------------*/
gatedClock 0:8e898e1270d6 74 /*---------------------------------instances----------------------------------*/
gatedClock 0:8e898e1270d6 75 /*-----------------------------------logic------------------------------------*/
gatedClock 0:8e898e1270d6 76
gatedClock 0:8e898e1270d6 77 always @ (iDin15 or iDin14 or iDin13 or iDin12 or
gatedClock 0:8e898e1270d6 78 iDin11 or iDin10 or iDin9 or iDin8 or
gatedClock 0:8e898e1270d6 79 iDin7 or iDin6 or iDin5 or iDin4 or
gatedClock 0:8e898e1270d6 80 iDin3 or iDin2 or iDin1 or iDin0 or iSel)
gatedClock 0:8e898e1270d6 81 case (iSel)
gatedClock 0:8e898e1270d6 82 15 : rDout = iDin15;
gatedClock 0:8e898e1270d6 83 14 : rDout = iDin14;
gatedClock 0:8e898e1270d6 84 13 : rDout = iDin13;
gatedClock 0:8e898e1270d6 85 12 : rDout = iDin12;
gatedClock 0:8e898e1270d6 86 11 : rDout = iDin11;
gatedClock 0:8e898e1270d6 87 10 : rDout = iDin10;
gatedClock 0:8e898e1270d6 88 9 : rDout = iDin9;
gatedClock 0:8e898e1270d6 89 8 : rDout = iDin8;
gatedClock 0:8e898e1270d6 90 7 : rDout = iDin7;
gatedClock 0:8e898e1270d6 91 6 : rDout = iDin6;
gatedClock 0:8e898e1270d6 92 5 : rDout = iDin5;
gatedClock 0:8e898e1270d6 93 4 : rDout = iDin4;
gatedClock 0:8e898e1270d6 94 3 : rDout = iDin3;
gatedClock 0:8e898e1270d6 95 2 : rDout = iDin2;
gatedClock 0:8e898e1270d6 96 1 : rDout = iDin1;
gatedClock 0:8e898e1270d6 97 0 : rDout = iDin0;
gatedClock 0:8e898e1270d6 98 endcase
gatedClock 0:8e898e1270d6 99
gatedClock 0:8e898e1270d6 100 assign oDout = rDout; // propagate output.
gatedClock 0:8e898e1270d6 101 /*-------------------------------*/endmodule/*--------------------------------*/
gatedClock 0:8e898e1270d6 102
gatedClock 0:8e898e1270d6 103
gatedClock 0:8e898e1270d6 104
gatedClock 0:8e898e1270d6 105
gatedClock 0:8e898e1270d6 106
gatedClock 0:8e898e1270d6 107
gatedClock 0:8e898e1270d6 108
gatedClock 0:8e898e1270d6 109
gatedClock 0:8e898e1270d6 110
gatedClock 0:8e898e1270d6 111
gatedClock 0:8e898e1270d6 112
gatedClock 0:8e898e1270d6 113
gatedClock 0:8e898e1270d6 114
gatedClock 0:8e898e1270d6 115
gatedClock 0:8e898e1270d6 116
gatedClock 0:8e898e1270d6 117
gatedClock 0:8e898e1270d6 118
gatedClock 0:8e898e1270d6 119
gatedClock 0:8e898e1270d6 120