Mike Moore
/
RTOS_project_fork_01
embedded RTOS class project.
Fork of RTOS_project by
mmRTL/shadow_load_control.txt@0:8e898e1270d6, 2013-09-17 (annotated)
- Committer:
- gatedClock
- Date:
- Tue Sep 17 19:42:49 2013 +0000
- Revision:
- 0:8e898e1270d6
title.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
gatedClock | 0:8e898e1270d6 | 1 | /*----------------------------------copyright---------------------------------*/ |
gatedClock | 0:8e898e1270d6 | 2 | // licensed for personal and academic use. |
gatedClock | 0:8e898e1270d6 | 3 | // commercial use must be approved by the account-holder of |
gatedClock | 0:8e898e1270d6 | 4 | // gated.clock@gmail.com |
gatedClock | 0:8e898e1270d6 | 5 | /*-----------------------------------module-----------------------------------*/ |
gatedClock | 0:8e898e1270d6 | 6 | module shadow_load_control |
gatedClock | 0:8e898e1270d6 | 7 | ( |
gatedClock | 0:8e898e1270d6 | 8 | iCPUclk, |
gatedClock | 0:8e898e1270d6 | 9 | iSPIclk, |
gatedClock | 0:8e898e1270d6 | 10 | iRstn, // direct clear. |
gatedClock | 0:8e898e1270d6 | 11 | oLoadEnable // shadow registers load enable. |
gatedClock | 0:8e898e1270d6 | 12 | ); |
gatedClock | 0:8e898e1270d6 | 13 | /*--------------------------------description----------------------------------- |
gatedClock | 0:8e898e1270d6 | 14 | when the CPU clock goes low, the CPU state is stable, and its time |
gatedClock | 0:8e898e1270d6 | 15 | for the SPI shadow registers to do a parallel load of the CPU state, |
gatedClock | 0:8e898e1270d6 | 16 | so its time to turn on the load-enable signal. |
gatedClock | 0:8e898e1270d6 | 17 | |
gatedClock | 0:8e898e1270d6 | 18 | when the first SPI clock goes high, the parallel load completes and |
gatedClock | 0:8e898e1270d6 | 19 | its time to turn off the load-enable signal. |
gatedClock | 0:8e898e1270d6 | 20 | -------------------------------------notes-------------------------------------- |
gatedClock | 0:8e898e1270d6 | 21 | ------------------------------------defines-----------------------------------*/ |
gatedClock | 0:8e898e1270d6 | 22 | /*-----------------------------------ports------------------------------------*/ |
gatedClock | 0:8e898e1270d6 | 23 | input iCPUclk; |
gatedClock | 0:8e898e1270d6 | 24 | input iSPIclk; |
gatedClock | 0:8e898e1270d6 | 25 | input iRstn; // direct clear. |
gatedClock | 0:8e898e1270d6 | 26 | output oLoadEnable; // shadow registers load enable. |
gatedClock | 0:8e898e1270d6 | 27 | /*-----------------------------------wires------------------------------------*/ |
gatedClock | 0:8e898e1270d6 | 28 | wire iCPUclk; |
gatedClock | 0:8e898e1270d6 | 29 | wire iSPIclk; |
gatedClock | 0:8e898e1270d6 | 30 | wire iRstn; // direct clear. |
gatedClock | 0:8e898e1270d6 | 31 | wire oLoadEnable; // shadow registers load enable. |
gatedClock | 0:8e898e1270d6 | 32 | |
gatedClock | 0:8e898e1270d6 | 33 | wire wOrClock; // OR the clocks. |
gatedClock | 0:8e898e1270d6 | 34 | /*---------------------------------registers----------------------------------*/ |
gatedClock | 0:8e898e1270d6 | 35 | reg rRegister; |
gatedClock | 0:8e898e1270d6 | 36 | /*---------------------------------variables----------------------------------*/ |
gatedClock | 0:8e898e1270d6 | 37 | /*---------------------------------parameters---------------------------------*/ |
gatedClock | 0:8e898e1270d6 | 38 | /*-----------------------------------clocks-----------------------------------*/ |
gatedClock | 0:8e898e1270d6 | 39 | /*---------------------------------instances----------------------------------*/ |
gatedClock | 0:8e898e1270d6 | 40 | /*-----------------------------------logic------------------------------------*/ |
gatedClock | 0:8e898e1270d6 | 41 | always @ (negedge wOrClock or negedge iRstn) |
gatedClock | 0:8e898e1270d6 | 42 | begin |
gatedClock | 0:8e898e1270d6 | 43 | if (!iRstn ) rRegister <= 1'b0; |
gatedClock | 0:8e898e1270d6 | 44 | else if (!wOrClock) rRegister <= !iSPIclk; |
gatedClock | 0:8e898e1270d6 | 45 | end |
gatedClock | 0:8e898e1270d6 | 46 | |
gatedClock | 0:8e898e1270d6 | 47 | assign wOrClock = iCPUclk | iSPIclk; |
gatedClock | 0:8e898e1270d6 | 48 | assign oLoadEnable = rRegister; |
gatedClock | 0:8e898e1270d6 | 49 | /*-------------------------------*/endmodule/*--------------------------------*/ |
gatedClock | 0:8e898e1270d6 | 50 | |
gatedClock | 0:8e898e1270d6 | 51 | |
gatedClock | 0:8e898e1270d6 | 52 | |
gatedClock | 0:8e898e1270d6 | 53 | |
gatedClock | 0:8e898e1270d6 | 54 | |
gatedClock | 0:8e898e1270d6 | 55 | |
gatedClock | 0:8e898e1270d6 | 56 | |
gatedClock | 0:8e898e1270d6 | 57 | |
gatedClock | 0:8e898e1270d6 | 58 | |
gatedClock | 0:8e898e1270d6 | 59 | |
gatedClock | 0:8e898e1270d6 | 60 | |
gatedClock | 0:8e898e1270d6 | 61 | |
gatedClock | 0:8e898e1270d6 | 62 | |
gatedClock | 0:8e898e1270d6 | 63 | |
gatedClock | 0:8e898e1270d6 | 64 | |
gatedClock | 0:8e898e1270d6 | 65 | |
gatedClock | 0:8e898e1270d6 | 66 | |
gatedClock | 0:8e898e1270d6 | 67 | |
gatedClock | 0:8e898e1270d6 | 68 | |
gatedClock | 0:8e898e1270d6 | 69 | |
gatedClock | 0:8e898e1270d6 | 70 | |
gatedClock | 0:8e898e1270d6 | 71 | |
gatedClock | 0:8e898e1270d6 | 72 | |
gatedClock | 0:8e898e1270d6 | 73 | |
gatedClock | 0:8e898e1270d6 | 74 | |
gatedClock | 0:8e898e1270d6 | 75 | |
gatedClock | 0:8e898e1270d6 | 76 | |
gatedClock | 0:8e898e1270d6 | 77 | |
gatedClock | 0:8e898e1270d6 | 78 | |
gatedClock | 0:8e898e1270d6 | 79 | |
gatedClock | 0:8e898e1270d6 | 80 | |
gatedClock | 0:8e898e1270d6 | 81 | |
gatedClock | 0:8e898e1270d6 | 82 |