Mike Moore / Mbed 2 deprecated RTOS_project_fork_01

embedded RTOS class project.

Fork of RTOS_project by Mike Moore

mmRTL/main_memory.txt@0:8e898e1270d6, 2013-09-17 (annotated)

Committer:
gatedClock
Date:
Tue Sep 17 19:42:49 2013 +0000
Revision:
0:8e898e1270d6
title.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gatedClock 0:8e898e1270d6 1 /*----------------------------------copyright---------------------------------*/
gatedClock 0:8e898e1270d6 2 // licensed for personal and academic use.
gatedClock 0:8e898e1270d6 3 // commercial use must be approved by the account-holder of
gatedClock 0:8e898e1270d6 4 // gated.clock@gmail.com
gatedClock 0:8e898e1270d6 5 /*-----------------------------------module-----------------------------------*/
gatedClock 0:8e898e1270d6 6 module main_memory
gatedClock 0:8e898e1270d6 7 (
gatedClock 0:8e898e1270d6 8 iReadAddress1, // read-address 1.
gatedClock 0:8e898e1270d6 9 iReadAddress0, // read-address 0.
gatedClock 0:8e898e1270d6 10 iWriteAddress, // write-address.
gatedClock 0:8e898e1270d6 11 oReadData1, // read-data 1.
gatedClock 0:8e898e1270d6 12 oReadData0, // read-data 0.
gatedClock 0:8e898e1270d6 13 iWriteData, // write-data.
gatedClock 0:8e898e1270d6 14 iWE, // write-enable.
gatedClock 0:8e898e1270d6 15 iCPUclk // cpu clock.
gatedClock 0:8e898e1270d6 16 );
gatedClock 0:8e898e1270d6 17 /*--------------------------------description-----------------------------------
gatedClock 0:8e898e1270d6 18 CPU main memory.
gatedClock 0:8e898e1270d6 19 two read-ports, one write-port.
gatedClock 0:8e898e1270d6 20 -------------------------------------notes--------------------------------------
gatedClock 0:8e898e1270d6 21 level-sensitive write-enable.
gatedClock 0:8e898e1270d6 22 the memory needs to be sixteen bits wide in order to hold
gatedClock 0:8e898e1270d6 23 immediate data for the instruction set.
gatedClock 0:8e898e1270d6 24 ------------------------------------defines-----------------------------------*/
gatedClock 0:8e898e1270d6 25 /*-----------------------------------ports------------------------------------*/
gatedClock 0:8e898e1270d6 26 input [ 7:0] iReadAddress1; // read-address 1.
gatedClock 0:8e898e1270d6 27 input [ 7:0] iReadAddress0; // read-address 0.
gatedClock 0:8e898e1270d6 28 input [ 7:0] iWriteAddress; // write-address.
gatedClock 0:8e898e1270d6 29 output [15:0] oReadData1; // read-data 1.
gatedClock 0:8e898e1270d6 30 output [15:0] oReadData0; // read-data 0.
gatedClock 0:8e898e1270d6 31 input [15:0] iWriteData; // write-data.
gatedClock 0:8e898e1270d6 32 input iWE; // write-enable.
gatedClock 0:8e898e1270d6 33 input iCPUclk; // cpu clock.
gatedClock 0:8e898e1270d6 34 /*-----------------------------------wires------------------------------------*/
gatedClock 0:8e898e1270d6 35 wire [ 7:0] iReadAddress1; // read-address 1.
gatedClock 0:8e898e1270d6 36 wire [ 7:0] iReadAddress0; // read-address 0.
gatedClock 0:8e898e1270d6 37 wire [ 7:0] iWriteAddress; // write-address.
gatedClock 0:8e898e1270d6 38 wire [15:0] oReadData1; // read-data 1.
gatedClock 0:8e898e1270d6 39 wire [15:0] oReadData0; // read-data 0.
gatedClock 0:8e898e1270d6 40 wire [15:0] iWriteData; // write-data.
gatedClock 0:8e898e1270d6 41 wire iWE; // write-enable.
gatedClock 0:8e898e1270d6 42 wire iCPUclk; // cpu clock.
gatedClock 0:8e898e1270d6 43 /*---------------------------------registers----------------------------------*/
gatedClock 0:8e898e1270d6 44 reg [15:0] mem_bank [0:255]; // memory bank.
gatedClock 0:8e898e1270d6 45 reg [15:0] rData1; // data-out-1 register.
gatedClock 0:8e898e1270d6 46 reg [15:0] rData0; // data-out-0 register.
gatedClock 0:8e898e1270d6 47 /*---------------------------------variables----------------------------------*/
gatedClock 0:8e898e1270d6 48 /*---------------------------------parameters---------------------------------*/
gatedClock 0:8e898e1270d6 49 /*-----------------------------------clocks-----------------------------------*/
gatedClock 0:8e898e1270d6 50 /*---------------------------------instances----------------------------------*/
gatedClock 0:8e898e1270d6 51 /*-----------------------------------logic------------------------------------*/
gatedClock 0:8e898e1270d6 52 always @ (posedge iCPUclk)
gatedClock 0:8e898e1270d6 53 if (iWE) mem_bank[iWriteAddress] = iWriteData;
gatedClock 0:8e898e1270d6 54 else mem_bank[iWriteAddress] = mem_bank[iWriteAddress];
gatedClock 0:8e898e1270d6 55
gatedClock 0:8e898e1270d6 56 assign oReadData1 = mem_bank[iReadAddress1];
gatedClock 0:8e898e1270d6 57 assign oReadData0 = mem_bank[iReadAddress0];
gatedClock 0:8e898e1270d6 58 /*-------------------------------*/endmodule/*--------------------------------*/
gatedClock 0:8e898e1270d6 59
gatedClock 0:8e898e1270d6 60
gatedClock 0:8e898e1270d6 61
gatedClock 0:8e898e1270d6 62
gatedClock 0:8e898e1270d6 63
gatedClock 0:8e898e1270d6 64
gatedClock 0:8e898e1270d6 65
gatedClock 0:8e898e1270d6 66
gatedClock 0:8e898e1270d6 67
gatedClock 0:8e898e1270d6 68
gatedClock 0:8e898e1270d6 69
gatedClock 0:8e898e1270d6 70
gatedClock 0:8e898e1270d6 71
gatedClock 0:8e898e1270d6 72
gatedClock 0:8e898e1270d6 73
gatedClock 0:8e898e1270d6 74