Mike Moore / Mbed 2 deprecated RTOS_project_fork_01

embedded RTOS class project.

Fork of RTOS_project by Mike Moore

mmRTL/instruction_decoder.txt@0:8e898e1270d6, 2013-09-17 (annotated)

Committer:
gatedClock
Date:
Tue Sep 17 19:42:49 2013 +0000
Revision:
0:8e898e1270d6
title.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gatedClock 0:8e898e1270d6 1 /*----------------------------------copyright---------------------------------*/
gatedClock 0:8e898e1270d6 2 // licensed for personal and academic use.
gatedClock 0:8e898e1270d6 3 // commercial use must be approved by the account-holder of
gatedClock 0:8e898e1270d6 4 // gated.clock@gmail.com
gatedClock 0:8e898e1270d6 5 /*-----------------------------------module-----------------------------------*/
gatedClock 0:8e898e1270d6 6 module instruction_decoder
gatedClock 0:8e898e1270d6 7 (
gatedClock 0:8e898e1270d6 8 iSquelch, // disrupt output enables.
gatedClock 0:8e898e1270d6 9 iIR, // instruction register.
gatedClock 0:8e898e1270d6 10 iBypass, // instruction from SPI.
gatedClock 0:8e898e1270d6 11 iBypassIR, // override the IR.
gatedClock 0:8e898e1270d6 12 oSel, // common data-in selector.
gatedClock 0:8e898e1270d6 13 oLER0, // R0 load-enable.
gatedClock 0:8e898e1270d6 14 oLER1, // R1 load-enable.
gatedClock 0:8e898e1270d6 15 oLER2, // R2 load-enable.
gatedClock 0:8e898e1270d6 16 oLER3, // R3 load-enable.
gatedClock 0:8e898e1270d6 17 oLEPC, // PC load-enable.
gatedClock 0:8e898e1270d6 18 oWE, // write-enable pulse.
gatedClock 0:8e898e1270d6 19 oCEPC, // PC count-enable.
gatedClock 0:8e898e1270d6 20 oImmediate // immediate data.
gatedClock 0:8e898e1270d6 21 );
gatedClock 0:8e898e1270d6 22 /*--------------------------------description-----------------------------------
gatedClock 0:8e898e1270d6 23 the instruction decoder.
gatedClock 0:8e898e1270d6 24 -------------------------------------notes--------------------------------------
gatedClock 0:8e898e1270d6 25 this instruction decoder operates in three different 'modes'.
gatedClock 0:8e898e1270d6 26 1. nominal mode: the instruction word is decoded as per the CPU spec.
gatedClock 0:8e898e1270d6 27 2. regular test mode: the instruction register is ignored, and instead
gatedClock 0:8e898e1270d6 28 this decoder makes use of iBypass, which is the instruction pattern
gatedClock 0:8e898e1270d6 29 provided by the instruction word shadow register (which is part of
gatedClock 0:8e898e1270d6 30 the spi scan chain). this allows the python code to take over the
gatedClock 0:8e898e1270d6 31 operation of the CPU.
gatedClock 0:8e898e1270d6 32 3. IR-write test mode: a special-case mode which occurs when python
gatedClock 0:8e898e1270d6 33 writes to the instruction register. in this case, the outputs of
gatedClock 0:8e898e1270d6 34 this decoder which are used to provide load-enables to CPU
gatedClock 0:8e898e1270d6 35 resources, must be squelched. this is because we don't want the
gatedClock 0:8e898e1270d6 36 python-written instruction register content to be decoded and
gatedClock 0:8e898e1270d6 37 the decoded signals sent into the CPU. why? because most likely
gatedClock 0:8e898e1270d6 38 the python-write to the IR is only to check that it can be done,
gatedClock 0:8e898e1270d6 39 and if the result of such a write were allowed to propagate, then
gatedClock 0:8e898e1270d6 40 the other registers may be arbitrarily updated, confusing the
gatedClock 0:8e898e1270d6 41 user at the python end.
gatedClock 0:8e898e1270d6 42 ------------------------------------defines-----------------------------------*/
gatedClock 0:8e898e1270d6 43 /*-----------------------------------ports------------------------------------*/
gatedClock 0:8e898e1270d6 44 input iSquelch; // disrupt output enables.
gatedClock 0:8e898e1270d6 45 input [15:0] iIR; // instruction register.
gatedClock 0:8e898e1270d6 46 input [15:0] iBypass; // instruction from SPI.
gatedClock 0:8e898e1270d6 47 input iBypassIR; // override the IR.
gatedClock 0:8e898e1270d6 48 output [ 2:0] oSel; // common data-in selector.
gatedClock 0:8e898e1270d6 49 output oLER0; // R0 load-enable.
gatedClock 0:8e898e1270d6 50 output oLER1; // R1 load-enable.
gatedClock 0:8e898e1270d6 51 output oLER2; // R2 load-enable.
gatedClock 0:8e898e1270d6 52 output oLER3; // R3 load-enable.
gatedClock 0:8e898e1270d6 53 output oLEPC; // PC load-enable.
gatedClock 0:8e898e1270d6 54 output oWE; // write-enable pulse.
gatedClock 0:8e898e1270d6 55 output oCEPC; // PC count-enable.
gatedClock 0:8e898e1270d6 56 output [ 7:0] oImmediate; // immediate data.
gatedClock 0:8e898e1270d6 57 /*-----------------------------------wires------------------------------------*/
gatedClock 0:8e898e1270d6 58 wire iSquelch; // disrupt output enables.
gatedClock 0:8e898e1270d6 59 wire [15:0] iIR; // instruction register.
gatedClock 0:8e898e1270d6 60 wire [15:0] iBypass; // instruction from SPI.
gatedClock 0:8e898e1270d6 61 wire iBypassIR; // override the IR.
gatedClock 0:8e898e1270d6 62 wire [ 2:0] oSel; // common data-in selector.
gatedClock 0:8e898e1270d6 63 wire oLER0; // R0 load-enable.
gatedClock 0:8e898e1270d6 64 wire oLER1; // R1 load-enable.
gatedClock 0:8e898e1270d6 65 wire oLER2; // R2 load-enable.
gatedClock 0:8e898e1270d6 66 wire oLER3; // R3 load-enable.
gatedClock 0:8e898e1270d6 67 wire oLEPC; // PC load-enable.
gatedClock 0:8e898e1270d6 68 wire oWE; // write-enable pulse.
gatedClock 0:8e898e1270d6 69 wire oCEPC; // PC count-enable.
gatedClock 0:8e898e1270d6 70 wire [ 7:0] oImmediate; // immediate data.
gatedClock 0:8e898e1270d6 71 /*---------------------------------registers----------------------------------*/
gatedClock 0:8e898e1270d6 72 reg [15:0] rIR; // instruction.
gatedClock 0:8e898e1270d6 73 reg rLER0; // R0 load-enable.
gatedClock 0:8e898e1270d6 74 reg rLER1; // R1 load-enable.
gatedClock 0:8e898e1270d6 75 reg rLER2; // R2 load-enable.
gatedClock 0:8e898e1270d6 76 reg rLER3; // R3 load-enable.
gatedClock 0:8e898e1270d6 77 reg rLEPC; // PC load-enable.
gatedClock 0:8e898e1270d6 78 /*---------------------------------variables----------------------------------*/
gatedClock 0:8e898e1270d6 79 /*---------------------------------parameters---------------------------------*/
gatedClock 0:8e898e1270d6 80 /*-----------------------------------clocks-----------------------------------*/
gatedClock 0:8e898e1270d6 81 /*---------------------------------instances----------------------------------*/
gatedClock 0:8e898e1270d6 82 /*-----------------------------------logic------------------------------------*/
gatedClock 0:8e898e1270d6 83
gatedClock 0:8e898e1270d6 84
gatedClock 0:8e898e1270d6 85 always @ (rIR)
gatedClock 0:8e898e1270d6 86 case (rIR[12:10]) // decode the load-enables.
gatedClock 0:8e898e1270d6 87
gatedClock 0:8e898e1270d6 88 7 : begin // no register.
gatedClock 0:8e898e1270d6 89 rLER0 = 1'b0;
gatedClock 0:8e898e1270d6 90 rLER1 = 1'b0;
gatedClock 0:8e898e1270d6 91 rLER2 = 1'b0;
gatedClock 0:8e898e1270d6 92 rLER3 = 1'b0;
gatedClock 0:8e898e1270d6 93 rLEPC = 1'b0;
gatedClock 0:8e898e1270d6 94 end
gatedClock 0:8e898e1270d6 95
gatedClock 0:8e898e1270d6 96 6 : begin // no register.
gatedClock 0:8e898e1270d6 97 rLER0 = 1'b0;
gatedClock 0:8e898e1270d6 98 rLER1 = 1'b0;
gatedClock 0:8e898e1270d6 99 rLER2 = 1'b0;
gatedClock 0:8e898e1270d6 100 rLER3 = 1'b0;
gatedClock 0:8e898e1270d6 101 rLEPC = 1'b0;
gatedClock 0:8e898e1270d6 102 end
gatedClock 0:8e898e1270d6 103
gatedClock 0:8e898e1270d6 104 5 : begin // no register.
gatedClock 0:8e898e1270d6 105 rLER0 = 1'b0;
gatedClock 0:8e898e1270d6 106 rLER1 = 1'b0;
gatedClock 0:8e898e1270d6 107 rLER2 = 1'b0;
gatedClock 0:8e898e1270d6 108 rLER3 = 1'b0;
gatedClock 0:8e898e1270d6 109 rLEPC = 1'b0;
gatedClock 0:8e898e1270d6 110 end
gatedClock 0:8e898e1270d6 111
gatedClock 0:8e898e1270d6 112 4 : begin // PC
gatedClock 0:8e898e1270d6 113 rLER0 = 1'b0;
gatedClock 0:8e898e1270d6 114 rLER1 = 1'b0;
gatedClock 0:8e898e1270d6 115 rLER2 = 1'b0;
gatedClock 0:8e898e1270d6 116 rLER3 = 1'b0;
gatedClock 0:8e898e1270d6 117 rLEPC = 1'b1;
gatedClock 0:8e898e1270d6 118 end
gatedClock 0:8e898e1270d6 119
gatedClock 0:8e898e1270d6 120 3 : begin // R3
gatedClock 0:8e898e1270d6 121 rLER0 = 1'b0;
gatedClock 0:8e898e1270d6 122 rLER1 = 1'b0;
gatedClock 0:8e898e1270d6 123 rLER2 = 1'b0;
gatedClock 0:8e898e1270d6 124 rLER3 = 1'b1;
gatedClock 0:8e898e1270d6 125 rLEPC = 1'b0;
gatedClock 0:8e898e1270d6 126 end
gatedClock 0:8e898e1270d6 127
gatedClock 0:8e898e1270d6 128 2 : begin // R2
gatedClock 0:8e898e1270d6 129 rLER0 = 1'b0;
gatedClock 0:8e898e1270d6 130 rLER1 = 1'b0;
gatedClock 0:8e898e1270d6 131 rLER2 = 1'b1;
gatedClock 0:8e898e1270d6 132 rLER3 = 1'b0;
gatedClock 0:8e898e1270d6 133 rLEPC = 1'b0;
gatedClock 0:8e898e1270d6 134 end
gatedClock 0:8e898e1270d6 135
gatedClock 0:8e898e1270d6 136 1 : begin // R1
gatedClock 0:8e898e1270d6 137 rLER0 = 1'b0;
gatedClock 0:8e898e1270d6 138 rLER1 = 1'b1;
gatedClock 0:8e898e1270d6 139 rLER2 = 1'b0;
gatedClock 0:8e898e1270d6 140 rLER3 = 1'b0;
gatedClock 0:8e898e1270d6 141 rLEPC = 1'b0;
gatedClock 0:8e898e1270d6 142 end
gatedClock 0:8e898e1270d6 143
gatedClock 0:8e898e1270d6 144 0 : begin // R0
gatedClock 0:8e898e1270d6 145 rLER0 = 1'b1;
gatedClock 0:8e898e1270d6 146 rLER1 = 1'b0;
gatedClock 0:8e898e1270d6 147 rLER2 = 1'b0;
gatedClock 0:8e898e1270d6 148 rLER3 = 1'b0;
gatedClock 0:8e898e1270d6 149 rLEPC = 1'b0;
gatedClock 0:8e898e1270d6 150 end
gatedClock 0:8e898e1270d6 151
gatedClock 0:8e898e1270d6 152
gatedClock 0:8e898e1270d6 153 endcase
gatedClock 0:8e898e1270d6 154
gatedClock 0:8e898e1270d6 155 assign oSel = rIR[15:13]; // pass-through.
gatedClock 0:8e898e1270d6 156 assign oLER0 = rLER0 & !iSquelch; // decode iIR[12:10].
gatedClock 0:8e898e1270d6 157 assign oLER1 = rLER1 & !iSquelch; // decode iIR[12:10].
gatedClock 0:8e898e1270d6 158 assign oLER2 = rLER2 & !iSquelch; // decode iIR[12:10].
gatedClock 0:8e898e1270d6 159 assign oLER3 = rLER3 & !iSquelch; // decode iIR[12:10].
gatedClock 0:8e898e1270d6 160 assign oLEPC = rLEPC & !iSquelch; // decode iIR[12:10].
gatedClock 0:8e898e1270d6 161 assign oWE = rIR[9] & !iSquelch; // pass-through.
gatedClock 0:8e898e1270d6 162 assign oCEPC = rIR[8] & !iSquelch; // pass-through.
gatedClock 0:8e898e1270d6 163 assign oImmediate = rIR[7:0]; // pass-through.
gatedClock 0:8e898e1270d6 164
gatedClock 0:8e898e1270d6 165
gatedClock 0:8e898e1270d6 166 always @ (iIR or iBypass or iBypassIR)
gatedClock 0:8e898e1270d6 167 if (iBypassIR) rIR = iBypass;
gatedClock 0:8e898e1270d6 168 else rIR = iIR;
gatedClock 0:8e898e1270d6 169 /*-------------------------------*/endmodule/*--------------------------------*/
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