Mike Moore / Mbed 2 deprecated RTOS_HW_04

RTOS homework 4

Dependencies:   C12832_lcd mbed

PowerControl/EthernetPowerControl.cpp@27:c380923f02d8, 2013-09-13 (annotated)

Committer:
gatedClock
Date:
Fri Sep 13 04:27:27 2013 +0000
Revision:
27:c380923f02d8
ok, got power control without cheating.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gatedClock 27:c380923f02d8 1 #include "EthernetPowerControl.h"
gatedClock 27:c380923f02d8 2
gatedClock 27:c380923f02d8 3 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
gatedClock 27:c380923f02d8 4 /* Write a data 'Value' to PHY register 'PhyReg'. */
gatedClock 27:c380923f02d8 5 unsigned int tout;
gatedClock 27:c380923f02d8 6 /* Hardware MII Management for LPC176x devices. */
gatedClock 27:c380923f02d8 7 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
gatedClock 27:c380923f02d8 8 LPC_EMAC->MWTD = Value;
gatedClock 27:c380923f02d8 9
gatedClock 27:c380923f02d8 10 /* Wait utill operation completed */
gatedClock 27:c380923f02d8 11 for (tout = 0; tout < MII_WR_TOUT; tout++) {
gatedClock 27:c380923f02d8 12 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
gatedClock 27:c380923f02d8 13 break;
gatedClock 27:c380923f02d8 14 }
gatedClock 27:c380923f02d8 15 }
gatedClock 27:c380923f02d8 16 }
gatedClock 27:c380923f02d8 17
gatedClock 27:c380923f02d8 18 static unsigned short read_PHY (unsigned int PhyReg) {
gatedClock 27:c380923f02d8 19 /* Read a PHY register 'PhyReg'. */
gatedClock 27:c380923f02d8 20 unsigned int tout, val;
gatedClock 27:c380923f02d8 21
gatedClock 27:c380923f02d8 22 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
gatedClock 27:c380923f02d8 23 LPC_EMAC->MCMD = MCMD_READ;
gatedClock 27:c380923f02d8 24
gatedClock 27:c380923f02d8 25 /* Wait until operation completed */
gatedClock 27:c380923f02d8 26 for (tout = 0; tout < MII_RD_TOUT; tout++) {
gatedClock 27:c380923f02d8 27 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
gatedClock 27:c380923f02d8 28 break;
gatedClock 27:c380923f02d8 29 }
gatedClock 27:c380923f02d8 30 }
gatedClock 27:c380923f02d8 31 LPC_EMAC->MCMD = 0;
gatedClock 27:c380923f02d8 32 val = LPC_EMAC->MRDD;
gatedClock 27:c380923f02d8 33
gatedClock 27:c380923f02d8 34 return (val);
gatedClock 27:c380923f02d8 35 }
gatedClock 27:c380923f02d8 36
gatedClock 27:c380923f02d8 37 void EMAC_Init()
gatedClock 27:c380923f02d8 38 {
gatedClock 27:c380923f02d8 39 unsigned int tout,regv;
gatedClock 27:c380923f02d8 40 /* Power Up the EMAC controller. */
gatedClock 27:c380923f02d8 41 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
gatedClock 27:c380923f02d8 42
gatedClock 27:c380923f02d8 43 LPC_PINCON->PINSEL2 = 0x50150105;
gatedClock 27:c380923f02d8 44 LPC_PINCON->PINSEL3 &= ~0x0000000F;
gatedClock 27:c380923f02d8 45 LPC_PINCON->PINSEL3 |= 0x00000005;
gatedClock 27:c380923f02d8 46
gatedClock 27:c380923f02d8 47 /* Reset all EMAC internal modules. */
gatedClock 27:c380923f02d8 48 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
gatedClock 27:c380923f02d8 49 MAC1_SIM_RES | MAC1_SOFT_RES;
gatedClock 27:c380923f02d8 50 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
gatedClock 27:c380923f02d8 51
gatedClock 27:c380923f02d8 52 /* A short delay after reset. */
gatedClock 27:c380923f02d8 53 for (tout = 100; tout; tout--);
gatedClock 27:c380923f02d8 54
gatedClock 27:c380923f02d8 55 /* Initialize MAC control registers. */
gatedClock 27:c380923f02d8 56 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
gatedClock 27:c380923f02d8 57 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
gatedClock 27:c380923f02d8 58 LPC_EMAC->MAXF = ETH_MAX_FLEN;
gatedClock 27:c380923f02d8 59 LPC_EMAC->CLRT = CLRT_DEF;
gatedClock 27:c380923f02d8 60 LPC_EMAC->IPGR = IPGR_DEF;
gatedClock 27:c380923f02d8 61
gatedClock 27:c380923f02d8 62 /* Enable Reduced MII interface. */
gatedClock 27:c380923f02d8 63 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
gatedClock 27:c380923f02d8 64
gatedClock 27:c380923f02d8 65 /* Reset Reduced MII Logic. */
gatedClock 27:c380923f02d8 66 LPC_EMAC->SUPP = SUPP_RES_RMII;
gatedClock 27:c380923f02d8 67 for (tout = 100; tout; tout--);
gatedClock 27:c380923f02d8 68 LPC_EMAC->SUPP = 0;
gatedClock 27:c380923f02d8 69
gatedClock 27:c380923f02d8 70 /* Put the DP83848C in reset mode */
gatedClock 27:c380923f02d8 71 write_PHY (PHY_REG_BMCR, 0x8000);
gatedClock 27:c380923f02d8 72
gatedClock 27:c380923f02d8 73 /* Wait for hardware reset to end. */
gatedClock 27:c380923f02d8 74 for (tout = 0; tout < 0x100000; tout++) {
gatedClock 27:c380923f02d8 75 regv = read_PHY (PHY_REG_BMCR);
gatedClock 27:c380923f02d8 76 if (!(regv & 0x8000)) {
gatedClock 27:c380923f02d8 77 /* Reset complete */
gatedClock 27:c380923f02d8 78 break;
gatedClock 27:c380923f02d8 79 }
gatedClock 27:c380923f02d8 80 }
gatedClock 27:c380923f02d8 81 }
gatedClock 27:c380923f02d8 82
gatedClock 27:c380923f02d8 83
gatedClock 27:c380923f02d8 84 void PHY_PowerDown()
gatedClock 27:c380923f02d8 85 {
gatedClock 27:c380923f02d8 86 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
gatedClock 27:c380923f02d8 87 EMAC_Init(); //init EMAC if it is not already init'd
gatedClock 27:c380923f02d8 88
gatedClock 27:c380923f02d8 89 unsigned int regv;
gatedClock 27:c380923f02d8 90 regv = read_PHY(PHY_REG_BMCR);
gatedClock 27:c380923f02d8 91 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
gatedClock 27:c380923f02d8 92 regv = read_PHY(PHY_REG_BMCR);
gatedClock 27:c380923f02d8 93
gatedClock 27:c380923f02d8 94 //shouldn't need the EMAC now.
gatedClock 27:c380923f02d8 95 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
gatedClock 27:c380923f02d8 96
gatedClock 27:c380923f02d8 97 //and turn off the PHY OSC
gatedClock 27:c380923f02d8 98 LPC_GPIO1->FIODIR |= 0x8000000;
gatedClock 27:c380923f02d8 99 LPC_GPIO1->FIOCLR = 0x8000000;
gatedClock 27:c380923f02d8 100 }
gatedClock 27:c380923f02d8 101
gatedClock 27:c380923f02d8 102 void PHY_PowerUp()
gatedClock 27:c380923f02d8 103 {
gatedClock 27:c380923f02d8 104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
gatedClock 27:c380923f02d8 105 EMAC_Init(); //init EMAC if it is not already init'd
gatedClock 27:c380923f02d8 106
gatedClock 27:c380923f02d8 107 LPC_GPIO1->FIODIR |= 0x8000000;
gatedClock 27:c380923f02d8 108 LPC_GPIO1->FIOSET = 0x8000000;
gatedClock 27:c380923f02d8 109
gatedClock 27:c380923f02d8 110 //wait for osc to be stable
gatedClock 27:c380923f02d8 111 wait_ms(200);
gatedClock 27:c380923f02d8 112
gatedClock 27:c380923f02d8 113 unsigned int regv;
gatedClock 27:c380923f02d8 114 regv = read_PHY(PHY_REG_BMCR);
gatedClock 27:c380923f02d8 115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
gatedClock 27:c380923f02d8 116 regv = read_PHY(PHY_REG_BMCR);
gatedClock 27:c380923f02d8 117 }
gatedClock 27:c380923f02d8 118
gatedClock 27:c380923f02d8 119 void PHY_EnergyDetect_Enable()
gatedClock 27:c380923f02d8 120 {
gatedClock 27:c380923f02d8 121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
gatedClock 27:c380923f02d8 122 EMAC_Init(); //init EMAC if it is not already init'd
gatedClock 27:c380923f02d8 123
gatedClock 27:c380923f02d8 124 unsigned int regv;
gatedClock 27:c380923f02d8 125 regv = read_PHY(PHY_REG_EDCR);
gatedClock 27:c380923f02d8 126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
gatedClock 27:c380923f02d8 127 regv = read_PHY(PHY_REG_EDCR);
gatedClock 27:c380923f02d8 128 }
gatedClock 27:c380923f02d8 129
gatedClock 27:c380923f02d8 130 void PHY_EnergyDetect_Disable()
gatedClock 27:c380923f02d8 131 {
gatedClock 27:c380923f02d8 132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
gatedClock 27:c380923f02d8 133 EMAC_Init(); //init EMAC if it is not already init'd
gatedClock 27:c380923f02d8 134 unsigned int regv;
gatedClock 27:c380923f02d8 135 regv = read_PHY(PHY_REG_EDCR);
gatedClock 27:c380923f02d8 136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
gatedClock 27:c380923f02d8 137 regv = read_PHY(PHY_REG_EDCR);
gatedClock 27:c380923f02d8 138 }