Mike Moore / Mbed 2 deprecated RTOS_HW_04

RTOS homework 4

Dependencies:   C12832_lcd mbed

PowerControl.h@26:986b539170fc, 2013-09-13 (annotated)

Committer:
gatedClock
Date:
Fri Sep 13 04:16:05 2013 +0000
Revision:
26:986b539170fc
Parent:
21:eb692e90ae8d 
still doesn't recognise phy power down.  why?

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gatedClock 21:eb692e90ae8d 1 /* mbed PowerControl Library
gatedClock 21:eb692e90ae8d 2 * Copyright (c) 2010 Michael Wei
gatedClock 21:eb692e90ae8d 3 */
gatedClock 21:eb692e90ae8d 4
gatedClock 21:eb692e90ae8d 5 #ifndef MBED_POWERCONTROL_H
gatedClock 21:eb692e90ae8d 6 #define MBED_POWERCONTROL_H
gatedClock 21:eb692e90ae8d 7
gatedClock 21:eb692e90ae8d 8 //shouldn't have to include, but fixes weird problems with defines
gatedClock 21:eb692e90ae8d 9 //#include "LPC1768/LPC17xx.h"
gatedClock 21:eb692e90ae8d 10
gatedClock 21:eb692e90ae8d 11 //System Control Register
gatedClock 21:eb692e90ae8d 12 // bit 0: Reserved
gatedClock 21:eb692e90ae8d 13 // bit 1: Sleep on Exit
gatedClock 21:eb692e90ae8d 14 #define LPC1768_SCR_SLEEPONEXIT 0x2
gatedClock 21:eb692e90ae8d 15 // bit 2: Deep Sleep
gatedClock 21:eb692e90ae8d 16 #define LPC1768_SCR_SLEEPDEEP 0x4
gatedClock 21:eb692e90ae8d 17 // bit 3: Resereved
gatedClock 21:eb692e90ae8d 18 // bit 4: Send on Pending
gatedClock 21:eb692e90ae8d 19 #define LPC1768_SCR_SEVONPEND 0x10
gatedClock 21:eb692e90ae8d 20 // bit 5-31: Reserved
gatedClock 21:eb692e90ae8d 21
gatedClock 21:eb692e90ae8d 22 //Power Control Register
gatedClock 21:eb692e90ae8d 23 // bit 0: Power mode control bit 0 (power-down mode)
gatedClock 21:eb692e90ae8d 24 #define LPC1768_PCON_PM0 0x1
gatedClock 21:eb692e90ae8d 25 // bit 1: Power mode control bit 1 (deep power-down mode)
gatedClock 21:eb692e90ae8d 26 #define LPC1768_PCON_PM1 0x2
gatedClock 21:eb692e90ae8d 27 // bit 2: Brown-out reduced power mode
gatedClock 21:eb692e90ae8d 28 #define LPC1768_PCON_BODRPM 0x4
gatedClock 21:eb692e90ae8d 29 // bit 3: Brown-out global disable
gatedClock 21:eb692e90ae8d 30 #define LPC1768_PCON_BOGD 0x8
gatedClock 21:eb692e90ae8d 31 // bit 4: Brown-out reset disable
gatedClock 21:eb692e90ae8d 32 #define LPC1768_PCON_BORD 0x10
gatedClock 21:eb692e90ae8d 33 // bit 5-7 : Reserved
gatedClock 21:eb692e90ae8d 34 // bit 8: Sleep Mode Entry Flag
gatedClock 21:eb692e90ae8d 35 #define LPC1768_PCON_SMFLAG 0x100
gatedClock 21:eb692e90ae8d 36 // bit 9: Deep Sleep Entry Flag
gatedClock 21:eb692e90ae8d 37 #define LPC1768_PCON_DSFLAG 0x200
gatedClock 21:eb692e90ae8d 38 // bit 10: Power Down Entry Flag
gatedClock 21:eb692e90ae8d 39 #define LPC1768_PCON_PDFLAG 0x400
gatedClock 21:eb692e90ae8d 40 // bit 11: Deep Power Down Entry Flag
gatedClock 21:eb692e90ae8d 41 #define LPC1768_PCON_DPDFLAG 0x800
gatedClock 21:eb692e90ae8d 42 // bit 12-31: Reserved
gatedClock 21:eb692e90ae8d 43
gatedClock 21:eb692e90ae8d 44 //"Sleep Mode" (WFI).
gatedClock 21:eb692e90ae8d 45 inline void Sleep(void)
gatedClock 21:eb692e90ae8d 46 {
gatedClock 21:eb692e90ae8d 47 __WFI();
gatedClock 21:eb692e90ae8d 48 }
gatedClock 21:eb692e90ae8d 49
gatedClock 21:eb692e90ae8d 50 //"Deep Sleep" Mode
gatedClock 21:eb692e90ae8d 51 inline void DeepSleep(void)
gatedClock 21:eb692e90ae8d 52 {
gatedClock 21:eb692e90ae8d 53 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
gatedClock 21:eb692e90ae8d 54 __WFI();
gatedClock 21:eb692e90ae8d 55 }
gatedClock 21:eb692e90ae8d 56
gatedClock 21:eb692e90ae8d 57 //"Power-Down" Mode
gatedClock 21:eb692e90ae8d 58 inline void PowerDown(void)
gatedClock 21:eb692e90ae8d 59 {
gatedClock 21:eb692e90ae8d 60 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
gatedClock 21:eb692e90ae8d 61 LPC_SC->PCON &= ~LPC1768_PCON_PM1;
gatedClock 21:eb692e90ae8d 62 LPC_SC->PCON |= LPC1768_PCON_PM0;
gatedClock 21:eb692e90ae8d 63 __WFI();
gatedClock 21:eb692e90ae8d 64 //reset back to normal
gatedClock 21:eb692e90ae8d 65 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
gatedClock 21:eb692e90ae8d 66 }
gatedClock 21:eb692e90ae8d 67
gatedClock 21:eb692e90ae8d 68 //"Deep Power-Down" Mode
gatedClock 21:eb692e90ae8d 69 inline void DeepPowerDown(void)
gatedClock 21:eb692e90ae8d 70 {
gatedClock 21:eb692e90ae8d 71 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
gatedClock 21:eb692e90ae8d 72 LPC_SC->PCON |= LPC1768_PCON_PM1 | LPC1768_PCON_PM0;
gatedClock 21:eb692e90ae8d 73 __WFI();
gatedClock 21:eb692e90ae8d 74 //reset back to normal
gatedClock 21:eb692e90ae8d 75 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
gatedClock 21:eb692e90ae8d 76 }
gatedClock 21:eb692e90ae8d 77
gatedClock 21:eb692e90ae8d 78 //shut down BOD during power-down/deep sleep
gatedClock 21:eb692e90ae8d 79 inline void BrownOut_ReducedPowerMode_Enable(void)
gatedClock 21:eb692e90ae8d 80 {
gatedClock 21:eb692e90ae8d 81 LPC_SC->PCON |= LPC1768_PCON_BODRPM;
gatedClock 21:eb692e90ae8d 82 }
gatedClock 21:eb692e90ae8d 83
gatedClock 21:eb692e90ae8d 84 //turn on BOD during power-down/deep sleep
gatedClock 21:eb692e90ae8d 85 inline void BrownOut_ReducedPowerMode_Disable(void)
gatedClock 21:eb692e90ae8d 86 {
gatedClock 21:eb692e90ae8d 87 LPC_SC->PCON &= ~LPC1768_PCON_BODRPM;
gatedClock 21:eb692e90ae8d 88 }
gatedClock 21:eb692e90ae8d 89
gatedClock 21:eb692e90ae8d 90 //turn off brown out circutry
gatedClock 21:eb692e90ae8d 91 inline void BrownOut_Global_Disable(void)
gatedClock 21:eb692e90ae8d 92 {
gatedClock 21:eb692e90ae8d 93 LPC_SC->PCON |= LPC1768_PCON_BOGD;
gatedClock 21:eb692e90ae8d 94 }
gatedClock 21:eb692e90ae8d 95
gatedClock 21:eb692e90ae8d 96 //turn on brown out circutry
gatedClock 21:eb692e90ae8d 97 inline void BrownOut_Global_Enable(void)
gatedClock 21:eb692e90ae8d 98 {
gatedClock 21:eb692e90ae8d 99 LPC_SC->PCON &= !LPC1768_PCON_BOGD;
gatedClock 21:eb692e90ae8d 100 }
gatedClock 21:eb692e90ae8d 101
gatedClock 21:eb692e90ae8d 102 //turn off brown out reset circutry
gatedClock 21:eb692e90ae8d 103 inline void BrownOut_Reset_Disable(void)
gatedClock 21:eb692e90ae8d 104 {
gatedClock 21:eb692e90ae8d 105 LPC_SC->PCON |= LPC1768_PCON_BORD;
gatedClock 21:eb692e90ae8d 106 }
gatedClock 21:eb692e90ae8d 107
gatedClock 21:eb692e90ae8d 108 //turn on brown outreset circutry
gatedClock 21:eb692e90ae8d 109 inline void BrownOut_Reset_Enable(void)
gatedClock 21:eb692e90ae8d 110 {
gatedClock 21:eb692e90ae8d 111 LPC_SC->PCON &= ~LPC1768_PCON_BORD;
gatedClock 21:eb692e90ae8d 112 }
gatedClock 21:eb692e90ae8d 113 //Peripheral Control Register
gatedClock 21:eb692e90ae8d 114 // bit 0: Reserved
gatedClock 21:eb692e90ae8d 115 // bit 1: PCTIM0: Timer/Counter 0 power/clock enable
gatedClock 21:eb692e90ae8d 116 #define LPC1768_PCONP_PCTIM0 0x2
gatedClock 21:eb692e90ae8d 117 // bit 2: PCTIM1: Timer/Counter 1 power/clock enable
gatedClock 21:eb692e90ae8d 118 #define LPC1768_PCONP_PCTIM1 0x4
gatedClock 21:eb692e90ae8d 119 // bit 3: PCUART0: UART 0 power/clock enable
gatedClock 21:eb692e90ae8d 120 #define LPC1768_PCONP_PCUART0 0x8
gatedClock 21:eb692e90ae8d 121 // bit 4: PCUART1: UART 1 power/clock enable
gatedClock 21:eb692e90ae8d 122 #define LPC1768_PCONP_PCUART1 0x10
gatedClock 21:eb692e90ae8d 123 // bit 5: Reserved
gatedClock 21:eb692e90ae8d 124 // bit 6: PCPWM1: PWM 1 power/clock enable
gatedClock 21:eb692e90ae8d 125 #define LPC1768_PCONP_PCPWM1 0x40
gatedClock 21:eb692e90ae8d 126 // bit 7: PCI2C0: I2C interface 0 power/clock enable
gatedClock 21:eb692e90ae8d 127 #define LPC1768_PCONP_PCI2C0 0x80
gatedClock 21:eb692e90ae8d 128 // bit 8: PCSPI: SPI interface power/clock enable
gatedClock 21:eb692e90ae8d 129 #define LPC1768_PCONP_PCSPI 0x100
gatedClock 21:eb692e90ae8d 130 // bit 9: PCRTC: RTC power/clock enable
gatedClock 21:eb692e90ae8d 131 #define LPC1768_PCONP_PCRTC 0x200
gatedClock 21:eb692e90ae8d 132 // bit 10: PCSSP1: SSP interface 1 power/clock enable
gatedClock 21:eb692e90ae8d 133 #define LPC1768_PCONP_PCSSP1 0x400
gatedClock 21:eb692e90ae8d 134 // bit 11: Reserved
gatedClock 21:eb692e90ae8d 135 // bit 12: PCADC: A/D converter power/clock enable
gatedClock 21:eb692e90ae8d 136 #define LPC1768_PCONP_PCADC 0x1000
gatedClock 21:eb692e90ae8d 137 // bit 13: PCCAN1: CAN controller 1 power/clock enable
gatedClock 21:eb692e90ae8d 138 #define LPC1768_PCONP_PCCAN1 0x2000
gatedClock 21:eb692e90ae8d 139 // bit 14: PCCAN2: CAN controller 2 power/clock enable
gatedClock 21:eb692e90ae8d 140 #define LPC1768_PCONP_PCCAN2 0x4000
gatedClock 21:eb692e90ae8d 141 // bit 15: PCGPIO: GPIOs power/clock enable
gatedClock 21:eb692e90ae8d 142 #define LPC1768_PCONP_PCGPIO 0x8000
gatedClock 21:eb692e90ae8d 143 // bit 16: PCRIT: Repetitive interrupt timer power/clock enable
gatedClock 21:eb692e90ae8d 144 #define LPC1768_PCONP_PCRIT 0x10000
gatedClock 21:eb692e90ae8d 145 // bit 17: PCMCPWM: Motor control PWM power/clock enable
gatedClock 21:eb692e90ae8d 146 #define LPC1768_PCONP_PCMCPWM 0x20000
gatedClock 21:eb692e90ae8d 147 // bit 18: PCQEI: Quadrature encoder interface power/clock enable
gatedClock 21:eb692e90ae8d 148 #define LPC1768_PCONP_PCQEI 0x40000
gatedClock 21:eb692e90ae8d 149 // bit 19: PCI2C1: I2C interface 1 power/clock enable
gatedClock 21:eb692e90ae8d 150 #define LPC1768_PCONP_PCI2C1 0x80000
gatedClock 21:eb692e90ae8d 151 // bit 20: Reserved
gatedClock 21:eb692e90ae8d 152 // bit 21: PCSSP0: SSP interface 0 power/clock enable
gatedClock 21:eb692e90ae8d 153 #define LPC1768_PCONP_PCSSP0 0x200000
gatedClock 21:eb692e90ae8d 154 // bit 22: PCTIM2: Timer 2 power/clock enable
gatedClock 21:eb692e90ae8d 155 #define LPC1768_PCONP_PCTIM2 0x400000
gatedClock 21:eb692e90ae8d 156 // bit 23: PCTIM3: Timer 3 power/clock enable
gatedClock 21:eb692e90ae8d 157 #define LPC1768_PCONP_PCQTIM3 0x800000
gatedClock 21:eb692e90ae8d 158 // bit 24: PCUART2: UART 2 power/clock enable
gatedClock 21:eb692e90ae8d 159 #define LPC1768_PCONP_PCUART2 0x1000000
gatedClock 21:eb692e90ae8d 160 // bit 25: PCUART3: UART 3 power/clock enable
gatedClock 21:eb692e90ae8d 161 #define LPC1768_PCONP_PCUART3 0x2000000
gatedClock 21:eb692e90ae8d 162 // bit 26: PCI2C2: I2C interface 2 power/clock enable
gatedClock 21:eb692e90ae8d 163 #define LPC1768_PCONP_PCI2C2 0x4000000
gatedClock 21:eb692e90ae8d 164 // bit 27: PCI2S: I2S interface power/clock enable
gatedClock 21:eb692e90ae8d 165 #define LPC1768_PCONP_PCI2S 0x8000000
gatedClock 21:eb692e90ae8d 166 // bit 28: Reserved
gatedClock 21:eb692e90ae8d 167 // bit 29: PCGPDMA: GP DMA function power/clock enable
gatedClock 21:eb692e90ae8d 168 #define LPC1768_PCONP_PCGPDMA 0x20000000
gatedClock 21:eb692e90ae8d 169 // bit 30: PCENET: Ethernet block power/clock enable
gatedClock 21:eb692e90ae8d 170 #define LPC1768_PCONP_PCENET 0x40000000
gatedClock 21:eb692e90ae8d 171 // bit 31: PCUSB: USB interface power/clock enable
gatedClock 21:eb692e90ae8d 172 #define LPC1768_PCONP_PCUSB 0x80000000
gatedClock 21:eb692e90ae8d 173
gatedClock 21:eb692e90ae8d 174 //Powers Up specified Peripheral(s)
gatedClock 21:eb692e90ae8d 175 inline unsigned int Peripheral_PowerUp(unsigned int bitMask)
gatedClock 21:eb692e90ae8d 176 {
gatedClock 21:eb692e90ae8d 177 return LPC_SC->PCONP |= bitMask;
gatedClock 21:eb692e90ae8d 178 }
gatedClock 21:eb692e90ae8d 179
gatedClock 21:eb692e90ae8d 180 //Powers Down specified Peripheral(s)
gatedClock 21:eb692e90ae8d 181 inline unsigned int Peripheral_PowerDown(unsigned int bitMask)
gatedClock 21:eb692e90ae8d 182 {
gatedClock 21:eb692e90ae8d 183 return LPC_SC->PCONP &= ~bitMask;
gatedClock 21:eb692e90ae8d 184 }
gatedClock 21:eb692e90ae8d 185
gatedClock 21:eb692e90ae8d 186 //returns if the peripheral is on or off
gatedClock 21:eb692e90ae8d 187 inline bool Peripheral_GetStatus(unsigned int peripheral)
gatedClock 21:eb692e90ae8d 188 {
gatedClock 21:eb692e90ae8d 189 return (LPC_SC->PCONP & peripheral) ? true : false;
gatedClock 21:eb692e90ae8d 190 }
gatedClock 21:eb692e90ae8d 191
gatedClock 21:eb692e90ae8d 192 #endif