Diff: mmRTL/main_memory.txt

Revision:

3:659ffc90b59e

Child:

7:d1aca9ccbab8

diff -r 08655e2bb776 -r 659ffc90b59e mmRTL/main_memory.txt
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/main_memory.txt	Sun Sep 01 02:53:39 2013 +0000
@@ -0,0 +1,74 @@
+/*----------------------------------copyright---------------------------------*/
+//  licensed for personal and academic use.
+//  commercial use must be approved by the account-holder of
+//  gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+    module main_memory
+        (
+     iReadAddress1,             // read-address 1.
+     iReadAddress0,             // read-address 0.
+     iWriteAddress,             // write-address.
+     oReadData1,                // read-data 1.
+     oReadData0,                // read-data 0.
+     iWriteData,                // write-data.
+     iWE,                   // write-enable.
+     iCPUclk                // cpu clock.
+        );
+/*--------------------------------description-----------------------------------
+    CPU main memory.
+    two read-ports, one write-port.
+-------------------------------------notes--------------------------------------
+    level-sensitive write-enable.
+    the memory needs to be sixteen bits wide in order to hold
+    immediate data for the instruction set.
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+    input   [ 7:0]  iReadAddress1;      // read-address 1.
+    input   [ 7:0]  iReadAddress0;      // read-address 0.
+    input   [ 7:0]  iWriteAddress;      // write-address.
+    output  [15:0]  oReadData1;     // read-data 1.
+    output  [15:0]  oReadData0;     // read-data 0.
+    input   [15:0]  iWriteData;     // write-data.
+    input           iWE;            // write-enable.
+    input           iCPUclk;        // cpu clock.
+/*-----------------------------------wires------------------------------------*/
+    wire    [ 7:0]  iReadAddress1;      // read-address 1.
+    wire    [ 7:0]  iReadAddress0;      // read-address 0.
+    wire    [ 7:0]  iWriteAddress;      // write-address.
+    wire    [15:0]  oReadData1;     // read-data 1.
+    wire    [15:0]  oReadData0;     // read-data 0.
+    wire    [15:0]  iWriteData;     // write-data.
+    wire            iWE;            // write-enable.
+    wire            iCPUclk;        // cpu clock.
+/*---------------------------------registers----------------------------------*/
+    reg     [15:0] mem_bank [0:255];    // memory bank.
+    reg     [15:0] rData1;          // data-out-1 register.
+    reg     [15:0] rData0;          // data-out-0 register.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+/*-----------------------------------logic------------------------------------*/
+    always @ (posedge iCPUclk) 
+    if (iWE) mem_bank[iWriteAddress] = iWriteData;
+    else     mem_bank[iWriteAddress] = mem_bank[iWriteAddress];
+
+    assign oReadData1 = mem_bank[iReadAddress1];
+    assign oReadData0 = mem_bank[iReadAddress0];
+/*-------------------------------*/endmodule/*--------------------------------*/
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