Mike Moore / Mbed 2 deprecated Embedded_RTOS_Project

Embedded RTOS class project. This project allows a Python/Tk program running on a PC host to monitor/control a test-CPU programmed into an altera development board.

Dependencies:   C12832_lcd USBDevice mbed-rtos mbed mmSPI-2 watchdog

Fork of USB_device_project by Mike Moore

mmRTL/mux8x8.txt

Committer:
gatedClock
Date:
2013-09-01
Revision:
3:659ffc90b59e
Child:
7:d1aca9ccbab8

File content as of revision 3:659ffc90b59e:

/*----------------------------------copyright---------------------------------*/
//  licensed for personal and academic use.
//  commercial use must be approved by the account-holder of
//  gated.clock@gmail.com
/*-----------------------------------module-----------------------------------*/
    module mux8x8
        (
      iDin7,                // data-input 7.
      iDin6,                // data-input 6.
      iDin5,                // data-input 5.
      iDin4,                // data-input 4.
      iDin3,                // data-input 3.
      iDin2,                // data-input 2.
      iDin1,                // data-input 1.
      iDin0,                // data-input 0.
      iSel,                 // multiplexor select.
      oDout                 // data-out.
        );
/*--------------------------------description-----------------------------------
    an 8-bit-wide, 8-selection multiplexor.
-------------------------------------notes--------------------------------------
------------------------------------defines-----------------------------------*/
/*-----------------------------------ports------------------------------------*/
    input   [ 7:0]  iDin7;          // data-input 7.
    input   [ 7:0]  iDin6;          // data-input 6.
    input   [ 7:0]  iDin5;          // data-input 5.
    input   [ 7:0]  iDin4;          // data-input 4.
    input   [ 7:0]  iDin3;          // data-input 3.
    input   [ 7:0]  iDin2;          // data-input 2.
    input   [ 7:0]  iDin1;          // data-input 1.
    input   [ 7:0]  iDin0;          // data-input 0.
    input   [ 2:0]  iSel;           // multiplexor select.
    output  [ 7:0]  oDout;          // data-out.
/*-----------------------------------wires------------------------------------*/
    wire    [ 7:0]  iDin7;          // data-input 7.
    wire    [ 7:0]  iDin6;          // data-input 6.
    wire    [ 7:0]  iDin5;          // data-input 5.
    wire    [ 7:0]  iDin4;          // data-input 4.
    wire    [ 7:0]  iDin3;          // data-input 3.
    wire    [ 7:0]  iDin2;          // data-input 2.
    wire    [ 7:0]  iDin1;          // data-input 1.
    wire    [ 7:0]  iDin0;          // data-input 0.
    wire    [ 2:0]  iSel;           // multiplexor select.
    wire    [ 7:0]  oDout;          // data-out.
/*---------------------------------registers----------------------------------*/
    reg     [ 7:0]  rDout;          // output register.
/*---------------------------------variables----------------------------------*/
/*---------------------------------parameters---------------------------------*/
/*-----------------------------------clocks-----------------------------------*/
/*---------------------------------instances----------------------------------*/
/*-----------------------------------logic------------------------------------*/
    always @ (iDin7 or iDin6 or iDin5 or iDin4 or
                  iDin3 or iDin2 or iDin1 or iDin0 or iSel)
    case (iSel)
    7 : rDout = iDin7;
    6 : rDout = iDin6;
    5 : rDout = iDin5;
    4 : rDout = iDin4;
    3 : rDout = iDin3;
    2 : rDout = iDin2;
    1 : rDout = iDin1;
    0 : rDout = iDin0;
    endcase

    assign oDout = rDout;           // propagate output.
/*-------------------------------*/endmodule/*--------------------------------*/