Mike Moore
Embedded RTOS class project. This project allows a Python/Tk program running on a PC host to monitor/control a test-CPU programmed into an altera development board.
Dependencies: C12832_lcd USBDevice mbed-rtos mbed mmSPI-2 watchdog
Fork of
USB_device_project
by 
Mike Moore
Diff: mmRTL/scan_08.txt
- Revision:
- 7:d1aca9ccbab8
- Parent:
- 3:659ffc90b59e
--- a/mmRTL/scan_08.txt Sun Sep 01 03:19:59 2013 +0000
+++ b/mmRTL/scan_08.txt Sun Sep 01 03:48:07 2013 +0000
@@ -1,58 +1,75 @@
/*----------------------------------copyright---------------------------------*/
-// licensed for personal and academic use.
-// commercial use must be approved by the account-holder of
-// gated.clock@gmail.com
+// licensed for personal and academic use.
+// commercial use must be approved by the account-holder of
+// gated.clock@gmail.com
/*-----------------------------------module-----------------------------------*/
- module scan_08 // shadow register.
+ module scan_08 // shadow register.
(
- oParallel, // parallel-output data.
- iParallel, // parallel-input data.
- oSerial, // serial-output data.
- iSerial, // serial-input data.
- iLoadEnable, // parallel-load-enable.
- iShiftEnable, // serial-shift-enable.
- iResetN, // synchronous reset*.
- iClk // module clock.
+ oParallel, // parallel-output data.
+ iParallel, // parallel-input data.
+ oSerial, // serial-output data.
+ iSerial, // serial-input data.
+ iLoadEnable, // parallel-load-enable.
+ iShiftEnable, // serial-shift-enable.
+ iResetN, // synchronous reset*.
+ iClk // module clock.
);
/*--------------------------------description-----------------------------------
- an 8-bit parallel shift-register.
+ an 8-bit parallel shift-register.
-------------------------------------notes--------------------------------------
- shifting is LSB->MSB.
+ shifting is LSB->MSB.
------------------------------------defines-----------------------------------*/
/*-----------------------------------ports------------------------------------*/
- output [ 7:0] oParallel; // parallel-output data.
- input [ 7:0] iParallel; // parallel-input data.
- output oSerial; // serial-output data.
- input iSerial; // serial-input data.
- input iLoadEnable; // parallel-load-enable.
- input iShiftEnable; // serial-shift-enable.
- input iResetN; // synchronous reset*.
- input iClk; // module clock.
+ output [ 7:0] oParallel; // parallel-output data.
+ input [ 7:0] iParallel; // parallel-input data.
+ output oSerial; // serial-output data.
+ input iSerial; // serial-input data.
+ input iLoadEnable; // parallel-load-enable.
+ input iShiftEnable; // serial-shift-enable.
+ input iResetN; // synchronous reset*.
+ input iClk; // module clock.
/*-----------------------------------wires------------------------------------*/
- wire [ 7:0] oParallel; // parallel-output data.
- wire [ 7:0] iParallel; // parallel-input data.
- wire [ 7:0] wParallelIn; // select the parallel input.
- wire oSerial; // serial-output data.
- wire iSerial; // serial-input data.
- wire iLoadEnable; // parallel-load-enable.
- wire iShiftEnable; // serial-shift-enable.
- wire iResetN; // synchronous reset*.
- wire iClk; // module clock.
+ wire [ 7:0] oParallel; // parallel-output data.
+ wire [ 7:0] iParallel; // parallel-input data.
+ wire [ 7:0] wParallelIn; // select the parallel input.
+ wire oSerial; // serial-output data.
+ wire iSerial; // serial-input data.
+ wire iLoadEnable; // parallel-load-enable.
+ wire iShiftEnable; // serial-shift-enable.
+ wire iResetN; // synchronous reset*.
+ wire iClk; // module clock.
/*---------------------------------registers----------------------------------*/
- reg [ 7:0] rRegister; // the register.
+ reg [ 7:0] rRegister; // the register.
/*---------------------------------variables----------------------------------*/
/*---------------------------------parameters---------------------------------*/
/*-----------------------------------clocks-----------------------------------*/
/*---------------------------------instances----------------------------------*/
/*-----------------------------------logic------------------------------------*/
- always @ (posedge iClk or negedge iResetN)
- begin
- if (!iResetN) rRegister <= 8'h00;
- else if (iLoadEnable) rRegister <= iParallel;
- else if (iShiftEnable) rRegister <= {rRegister[6:0], iSerial};
- else rRegister <= rRegister;
- end
+ always @ (posedge iClk or negedge iResetN)
+ begin
+ if (!iResetN) rRegister <= 8'h00;
+ else if (iLoadEnable) rRegister <= iParallel;
+ else if (iShiftEnable) rRegister <= {rRegister[6:0], iSerial};
+ else rRegister <= rRegister;
+ end
+
+ assign oParallel = rRegister; // propagate parallel-out.
+ assign oSerial = rRegister[7]; // propagate serial-out.
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
- assign oParallel = rRegister; // propagate parallel-out.
- assign oSerial = rRegister[7]; // propagate serial-out.
-/*-------------------------------*/endmodule/*--------------------------------*/
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