Mike Moore / Mbed 2 deprecated Embedded_RTOS_Project

Embedded RTOS class project. This project allows a Python/Tk program running on a PC host to monitor/control a test-CPU programmed into an altera development board.

Dependencies:   C12832_lcd USBDevice mbed-rtos mbed mmSPI-2 watchdog

Fork of USB_device_project by Mike Moore

mmRTL/scan_16.txt@13:7e1688393abc, 2013-09-17 (annotated)

Committer:
gatedClock
Date:
Tue Sep 17 19:07:00 2013 +0000
Revision:
13:7e1688393abc
Parent:
7:d1aca9ccbab8 
updates for RTOS class project.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gatedClock 3:659ffc90b59e 1 /*----------------------------------copyright---------------------------------*/
gatedClock 7:d1aca9ccbab8 2 // licensed for personal and academic use.
gatedClock 7:d1aca9ccbab8 3 // commercial use must be approved by the account-holder of
gatedClock 7:d1aca9ccbab8 4 // gated.clock@gmail.com
gatedClock 3:659ffc90b59e 5 /*-----------------------------------module-----------------------------------*/
gatedClock 7:d1aca9ccbab8 6 module scan_16 // shadow register.
gatedClock 3:659ffc90b59e 7 (
gatedClock 7:d1aca9ccbab8 8 oParallel, // parallel-output data.
gatedClock 7:d1aca9ccbab8 9 iParallel, // parallel-input data.
gatedClock 7:d1aca9ccbab8 10 oSerial, // serial-output data.
gatedClock 7:d1aca9ccbab8 11 iSerial, // serial-input data.
gatedClock 7:d1aca9ccbab8 12 iLoadEnable, // parallel-load-enable.
gatedClock 7:d1aca9ccbab8 13 iShiftEnable, // serial-shift-enable.
gatedClock 7:d1aca9ccbab8 14 iResetN, // synchronous reset*.
gatedClock 7:d1aca9ccbab8 15 iClk // module clock.
gatedClock 3:659ffc90b59e 16 );
gatedClock 3:659ffc90b59e 17 /*--------------------------------description-----------------------------------
gatedClock 7:d1aca9ccbab8 18 a 16-bit parallel shift-register.
gatedClock 3:659ffc90b59e 19 -------------------------------------notes--------------------------------------
gatedClock 7:d1aca9ccbab8 20 shifting is LSB->MSB.
gatedClock 3:659ffc90b59e 21 ------------------------------------defines-----------------------------------*/
gatedClock 3:659ffc90b59e 22 /*-----------------------------------ports------------------------------------*/
gatedClock 7:d1aca9ccbab8 23 output [15:0] oParallel; // parallel-output data.
gatedClock 7:d1aca9ccbab8 24 input [15:0] iParallel; // parallel-input data.
gatedClock 7:d1aca9ccbab8 25 output oSerial; // serial-output data.
gatedClock 7:d1aca9ccbab8 26 input iSerial; // serial-input data.
gatedClock 7:d1aca9ccbab8 27 input iLoadEnable; // parallel-load-enable.
gatedClock 7:d1aca9ccbab8 28 input iShiftEnable; // serial-shift-enable.
gatedClock 7:d1aca9ccbab8 29 input iResetN; // synchronous reset*.
gatedClock 7:d1aca9ccbab8 30 input iClk; // module clock.
gatedClock 3:659ffc90b59e 31 /*-----------------------------------wires------------------------------------*/
gatedClock 7:d1aca9ccbab8 32 wire [15:0] oParallel; // parallel-output data.
gatedClock 7:d1aca9ccbab8 33 wire [15:0] iParallel; // parallel-input data.
gatedClock 7:d1aca9ccbab8 34 wire [15:0] wParallelIn; // select the parallel input.
gatedClock 7:d1aca9ccbab8 35 wire oSerial; // serial-output data.
gatedClock 7:d1aca9ccbab8 36 wire iSerial; // serial-input data.
gatedClock 7:d1aca9ccbab8 37 wire iLoadEnable; // parallel-load-enable.
gatedClock 7:d1aca9ccbab8 38 wire iShiftEnable; // serial-shift-enable.
gatedClock 7:d1aca9ccbab8 39 wire iResetN; // synchronous reset*.
gatedClock 7:d1aca9ccbab8 40 wire iClk; // module clock.
gatedClock 3:659ffc90b59e 41 /*---------------------------------registers----------------------------------*/
gatedClock 7:d1aca9ccbab8 42 reg [15:0] rRegister; // the register.
gatedClock 3:659ffc90b59e 43 /*---------------------------------variables----------------------------------*/
gatedClock 3:659ffc90b59e 44 /*---------------------------------parameters---------------------------------*/
gatedClock 3:659ffc90b59e 45 /*-----------------------------------clocks-----------------------------------*/
gatedClock 3:659ffc90b59e 46 /*---------------------------------instances----------------------------------*/
gatedClock 3:659ffc90b59e 47 /*-----------------------------------logic------------------------------------*/
gatedClock 7:d1aca9ccbab8 48 always @ (posedge iClk or negedge iResetN)
gatedClock 7:d1aca9ccbab8 49 begin
gatedClock 7:d1aca9ccbab8 50 if (!iResetN) rRegister[15:0] <= 16'h0000;
gatedClock 7:d1aca9ccbab8 51 else if (iLoadEnable) rRegister[15:0] <= iParallel[15:0];
gatedClock 7:d1aca9ccbab8 52 else if (iShiftEnable) rRegister[15:0] <= {rRegister[14:0], iSerial};
gatedClock 7:d1aca9ccbab8 53 else rRegister[15:0] <= rRegister[15:0];
gatedClock 7:d1aca9ccbab8 54 end
gatedClock 3:659ffc90b59e 55
gatedClock 7:d1aca9ccbab8 56 // propagate parallel-out.
gatedClock 7:d1aca9ccbab8 57 assign oParallel[15:0] = rRegister[15:0];
gatedClock 7:d1aca9ccbab8 58 assign oSerial = rRegister[15]; // propagate serial-out.
gatedClock 3:659ffc90b59e 59 /*-------------------------------*/endmodule/*--------------------------------*/
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