Gan likun / mbed1-dev

001

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_cortex.h@0:13413ea9a877, 2022-06-12 (annotated)

Committer:
ganlikun
Date:
Sun Jun 12 14:02:44 2022 +0000
Revision:
0:13413ea9a877
00

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ganlikun 0:13413ea9a877 1 /**
ganlikun 0:13413ea9a877 2 ******************************************************************************
ganlikun 0:13413ea9a877 3 * @file stm32f4xx_ll_cortex.h
ganlikun 0:13413ea9a877 4 * @author MCD Application Team
ganlikun 0:13413ea9a877 5 * @version V1.7.1
ganlikun 0:13413ea9a877 6 * @date 14-April-2017
ganlikun 0:13413ea9a877 7 * @brief Header file of CORTEX LL module.
ganlikun 0:13413ea9a877 8 @verbatim
ganlikun 0:13413ea9a877 9 ==============================================================================
ganlikun 0:13413ea9a877 10 ##### How to use this driver #####
ganlikun 0:13413ea9a877 11 ==============================================================================
ganlikun 0:13413ea9a877 12 [..]
ganlikun 0:13413ea9a877 13 The LL CORTEX driver contains a set of generic APIs that can be
ganlikun 0:13413ea9a877 14 used by user:
ganlikun 0:13413ea9a877 15 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
ganlikun 0:13413ea9a877 16 functions
ganlikun 0:13413ea9a877 17 (+) Low power mode configuration (SCB register of Cortex-MCU)
ganlikun 0:13413ea9a877 18 (+) MPU API to configure and enable regions
ganlikun 0:13413ea9a877 19 (MPU services provided only on some devices)
ganlikun 0:13413ea9a877 20 (+) API to access to MCU info (CPUID register)
ganlikun 0:13413ea9a877 21 (+) API to enable fault handler (SHCSR accesses)
ganlikun 0:13413ea9a877 22
ganlikun 0:13413ea9a877 23 @endverbatim
ganlikun 0:13413ea9a877 24 ******************************************************************************
ganlikun 0:13413ea9a877 25 * @attention
ganlikun 0:13413ea9a877 26 *
ganlikun 0:13413ea9a877 27 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun 0:13413ea9a877 28 *
ganlikun 0:13413ea9a877 29 * Redistribution and use in source and binary forms, with or without modification,
ganlikun 0:13413ea9a877 30 * are permitted provided that the following conditions are met:
ganlikun 0:13413ea9a877 31 * 1. Redistributions of source code must retain the above copyright notice,
ganlikun 0:13413ea9a877 32 * this list of conditions and the following disclaimer.
ganlikun 0:13413ea9a877 33 * 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun 0:13413ea9a877 34 * this list of conditions and the following disclaimer in the documentation
ganlikun 0:13413ea9a877 35 * and/or other materials provided with the distribution.
ganlikun 0:13413ea9a877 36 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun 0:13413ea9a877 37 * may be used to endorse or promote products derived from this software
ganlikun 0:13413ea9a877 38 * without specific prior written permission.
ganlikun 0:13413ea9a877 39 *
ganlikun 0:13413ea9a877 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun 0:13413ea9a877 41 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun 0:13413ea9a877 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun 0:13413ea9a877 43 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun 0:13413ea9a877 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun 0:13413ea9a877 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun 0:13413ea9a877 46 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun 0:13413ea9a877 47 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun 0:13413ea9a877 48 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun 0:13413ea9a877 49 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun 0:13413ea9a877 50 *
ganlikun 0:13413ea9a877 51 ******************************************************************************
ganlikun 0:13413ea9a877 52 */
ganlikun 0:13413ea9a877 53
ganlikun 0:13413ea9a877 54 /* Define to prevent recursive inclusion -------------------------------------*/
ganlikun 0:13413ea9a877 55 #ifndef __STM32F4xx_LL_CORTEX_H
ganlikun 0:13413ea9a877 56 #define __STM32F4xx_LL_CORTEX_H
ganlikun 0:13413ea9a877 57
ganlikun 0:13413ea9a877 58 #ifdef __cplusplus
ganlikun 0:13413ea9a877 59 extern "C" {
ganlikun 0:13413ea9a877 60 #endif
ganlikun 0:13413ea9a877 61
ganlikun 0:13413ea9a877 62 /* Includes ------------------------------------------------------------------*/
ganlikun 0:13413ea9a877 63 #include "stm32f4xx.h"
ganlikun 0:13413ea9a877 64
ganlikun 0:13413ea9a877 65 /** @addtogroup STM32F4xx_LL_Driver
ganlikun 0:13413ea9a877 66 * @{
ganlikun 0:13413ea9a877 67 */
ganlikun 0:13413ea9a877 68
ganlikun 0:13413ea9a877 69 /** @defgroup CORTEX_LL CORTEX
ganlikun 0:13413ea9a877 70 * @{
ganlikun 0:13413ea9a877 71 */
ganlikun 0:13413ea9a877 72
ganlikun 0:13413ea9a877 73 /* Private types -------------------------------------------------------------*/
ganlikun 0:13413ea9a877 74 /* Private variables ---------------------------------------------------------*/
ganlikun 0:13413ea9a877 75
ganlikun 0:13413ea9a877 76 /* Private constants ---------------------------------------------------------*/
ganlikun 0:13413ea9a877 77
ganlikun 0:13413ea9a877 78 /* Private macros ------------------------------------------------------------*/
ganlikun 0:13413ea9a877 79
ganlikun 0:13413ea9a877 80 /* Exported types ------------------------------------------------------------*/
ganlikun 0:13413ea9a877 81 /* Exported constants --------------------------------------------------------*/
ganlikun 0:13413ea9a877 82 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
ganlikun 0:13413ea9a877 83 * @{
ganlikun 0:13413ea9a877 84 */
ganlikun 0:13413ea9a877 85
ganlikun 0:13413ea9a877 86 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
ganlikun 0:13413ea9a877 87 * @{
ganlikun 0:13413ea9a877 88 */
ganlikun 0:13413ea9a877 89 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
ganlikun 0:13413ea9a877 90 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
ganlikun 0:13413ea9a877 91 /**
ganlikun 0:13413ea9a877 92 * @}
ganlikun 0:13413ea9a877 93 */
ganlikun 0:13413ea9a877 94
ganlikun 0:13413ea9a877 95 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
ganlikun 0:13413ea9a877 96 * @{
ganlikun 0:13413ea9a877 97 */
ganlikun 0:13413ea9a877 98 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
ganlikun 0:13413ea9a877 99 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
ganlikun 0:13413ea9a877 100 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
ganlikun 0:13413ea9a877 101 /**
ganlikun 0:13413ea9a877 102 * @}
ganlikun 0:13413ea9a877 103 */
ganlikun 0:13413ea9a877 104
ganlikun 0:13413ea9a877 105 #if __MPU_PRESENT
ganlikun 0:13413ea9a877 106
ganlikun 0:13413ea9a877 107 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
ganlikun 0:13413ea9a877 108 * @{
ganlikun 0:13413ea9a877 109 */
ganlikun 0:13413ea9a877 110 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
ganlikun 0:13413ea9a877 111 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
ganlikun 0:13413ea9a877 112 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
ganlikun 0:13413ea9a877 113 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
ganlikun 0:13413ea9a877 114 /**
ganlikun 0:13413ea9a877 115 * @}
ganlikun 0:13413ea9a877 116 */
ganlikun 0:13413ea9a877 117
ganlikun 0:13413ea9a877 118 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
ganlikun 0:13413ea9a877 119 * @{
ganlikun 0:13413ea9a877 120 */
ganlikun 0:13413ea9a877 121 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
ganlikun 0:13413ea9a877 122 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
ganlikun 0:13413ea9a877 123 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
ganlikun 0:13413ea9a877 124 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
ganlikun 0:13413ea9a877 125 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
ganlikun 0:13413ea9a877 126 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
ganlikun 0:13413ea9a877 127 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
ganlikun 0:13413ea9a877 128 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
ganlikun 0:13413ea9a877 129 /**
ganlikun 0:13413ea9a877 130 * @}
ganlikun 0:13413ea9a877 131 */
ganlikun 0:13413ea9a877 132
ganlikun 0:13413ea9a877 133 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
ganlikun 0:13413ea9a877 134 * @{
ganlikun 0:13413ea9a877 135 */
ganlikun 0:13413ea9a877 136 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
ganlikun 0:13413ea9a877 137 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
ganlikun 0:13413ea9a877 138 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
ganlikun 0:13413ea9a877 139 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
ganlikun 0:13413ea9a877 140 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
ganlikun 0:13413ea9a877 141 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
ganlikun 0:13413ea9a877 142 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
ganlikun 0:13413ea9a877 143 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
ganlikun 0:13413ea9a877 144 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
ganlikun 0:13413ea9a877 145 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
ganlikun 0:13413ea9a877 146 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
ganlikun 0:13413ea9a877 147 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
ganlikun 0:13413ea9a877 148 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
ganlikun 0:13413ea9a877 149 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
ganlikun 0:13413ea9a877 150 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
ganlikun 0:13413ea9a877 151 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
ganlikun 0:13413ea9a877 152 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
ganlikun 0:13413ea9a877 153 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
ganlikun 0:13413ea9a877 154 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
ganlikun 0:13413ea9a877 155 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
ganlikun 0:13413ea9a877 156 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
ganlikun 0:13413ea9a877 157 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
ganlikun 0:13413ea9a877 158 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
ganlikun 0:13413ea9a877 159 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
ganlikun 0:13413ea9a877 160 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
ganlikun 0:13413ea9a877 161 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
ganlikun 0:13413ea9a877 162 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
ganlikun 0:13413ea9a877 163 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
ganlikun 0:13413ea9a877 164 /**
ganlikun 0:13413ea9a877 165 * @}
ganlikun 0:13413ea9a877 166 */
ganlikun 0:13413ea9a877 167
ganlikun 0:13413ea9a877 168 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
ganlikun 0:13413ea9a877 169 * @{
ganlikun 0:13413ea9a877 170 */
ganlikun 0:13413ea9a877 171 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
ganlikun 0:13413ea9a877 172 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
ganlikun 0:13413ea9a877 173 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
ganlikun 0:13413ea9a877 174 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
ganlikun 0:13413ea9a877 175 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
ganlikun 0:13413ea9a877 176 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
ganlikun 0:13413ea9a877 177 /**
ganlikun 0:13413ea9a877 178 * @}
ganlikun 0:13413ea9a877 179 */
ganlikun 0:13413ea9a877 180
ganlikun 0:13413ea9a877 181 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
ganlikun 0:13413ea9a877 182 * @{
ganlikun 0:13413ea9a877 183 */
ganlikun 0:13413ea9a877 184 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
ganlikun 0:13413ea9a877 185 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
ganlikun 0:13413ea9a877 186 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
ganlikun 0:13413ea9a877 187 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
ganlikun 0:13413ea9a877 188 /**
ganlikun 0:13413ea9a877 189 * @}
ganlikun 0:13413ea9a877 190 */
ganlikun 0:13413ea9a877 191
ganlikun 0:13413ea9a877 192 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
ganlikun 0:13413ea9a877 193 * @{
ganlikun 0:13413ea9a877 194 */
ganlikun 0:13413ea9a877 195 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
ganlikun 0:13413ea9a877 196 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
ganlikun 0:13413ea9a877 197 /**
ganlikun 0:13413ea9a877 198 * @}
ganlikun 0:13413ea9a877 199 */
ganlikun 0:13413ea9a877 200
ganlikun 0:13413ea9a877 201 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
ganlikun 0:13413ea9a877 202 * @{
ganlikun 0:13413ea9a877 203 */
ganlikun 0:13413ea9a877 204 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
ganlikun 0:13413ea9a877 205 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
ganlikun 0:13413ea9a877 206 /**
ganlikun 0:13413ea9a877 207 * @}
ganlikun 0:13413ea9a877 208 */
ganlikun 0:13413ea9a877 209
ganlikun 0:13413ea9a877 210 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
ganlikun 0:13413ea9a877 211 * @{
ganlikun 0:13413ea9a877 212 */
ganlikun 0:13413ea9a877 213 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
ganlikun 0:13413ea9a877 214 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
ganlikun 0:13413ea9a877 215 /**
ganlikun 0:13413ea9a877 216 * @}
ganlikun 0:13413ea9a877 217 */
ganlikun 0:13413ea9a877 218
ganlikun 0:13413ea9a877 219 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
ganlikun 0:13413ea9a877 220 * @{
ganlikun 0:13413ea9a877 221 */
ganlikun 0:13413ea9a877 222 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
ganlikun 0:13413ea9a877 223 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
ganlikun 0:13413ea9a877 224 /**
ganlikun 0:13413ea9a877 225 * @}
ganlikun 0:13413ea9a877 226 */
ganlikun 0:13413ea9a877 227 #endif /* __MPU_PRESENT */
ganlikun 0:13413ea9a877 228 /**
ganlikun 0:13413ea9a877 229 * @}
ganlikun 0:13413ea9a877 230 */
ganlikun 0:13413ea9a877 231
ganlikun 0:13413ea9a877 232 /* Exported macro ------------------------------------------------------------*/
ganlikun 0:13413ea9a877 233
ganlikun 0:13413ea9a877 234 /* Exported functions --------------------------------------------------------*/
ganlikun 0:13413ea9a877 235 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
ganlikun 0:13413ea9a877 236 * @{
ganlikun 0:13413ea9a877 237 */
ganlikun 0:13413ea9a877 238
ganlikun 0:13413ea9a877 239 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
ganlikun 0:13413ea9a877 240 * @{
ganlikun 0:13413ea9a877 241 */
ganlikun 0:13413ea9a877 242
ganlikun 0:13413ea9a877 243 /**
ganlikun 0:13413ea9a877 244 * @brief This function checks if the Systick counter flag is active or not.
ganlikun 0:13413ea9a877 245 * @note It can be used in timeout function on application side.
ganlikun 0:13413ea9a877 246 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
ganlikun 0:13413ea9a877 247 * @retval State of bit (1 or 0).
ganlikun 0:13413ea9a877 248 */
ganlikun 0:13413ea9a877 249 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
ganlikun 0:13413ea9a877 250 {
ganlikun 0:13413ea9a877 251 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
ganlikun 0:13413ea9a877 252 }
ganlikun 0:13413ea9a877 253
ganlikun 0:13413ea9a877 254 /**
ganlikun 0:13413ea9a877 255 * @brief Configures the SysTick clock source
ganlikun 0:13413ea9a877 256 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
ganlikun 0:13413ea9a877 257 * @param Source This parameter can be one of the following values:
ganlikun 0:13413ea9a877 258 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
ganlikun 0:13413ea9a877 259 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
ganlikun 0:13413ea9a877 260 * @retval None
ganlikun 0:13413ea9a877 261 */
ganlikun 0:13413ea9a877 262 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
ganlikun 0:13413ea9a877 263 {
ganlikun 0:13413ea9a877 264 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
ganlikun 0:13413ea9a877 265 {
ganlikun 0:13413ea9a877 266 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
ganlikun 0:13413ea9a877 267 }
ganlikun 0:13413ea9a877 268 else
ganlikun 0:13413ea9a877 269 {
ganlikun 0:13413ea9a877 270 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
ganlikun 0:13413ea9a877 271 }
ganlikun 0:13413ea9a877 272 }
ganlikun 0:13413ea9a877 273
ganlikun 0:13413ea9a877 274 /**
ganlikun 0:13413ea9a877 275 * @brief Get the SysTick clock source
ganlikun 0:13413ea9a877 276 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
ganlikun 0:13413ea9a877 277 * @retval Returned value can be one of the following values:
ganlikun 0:13413ea9a877 278 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
ganlikun 0:13413ea9a877 279 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
ganlikun 0:13413ea9a877 280 */
ganlikun 0:13413ea9a877 281 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
ganlikun 0:13413ea9a877 282 {
ganlikun 0:13413ea9a877 283 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
ganlikun 0:13413ea9a877 284 }
ganlikun 0:13413ea9a877 285
ganlikun 0:13413ea9a877 286 /**
ganlikun 0:13413ea9a877 287 * @brief Enable SysTick exception request
ganlikun 0:13413ea9a877 288 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
ganlikun 0:13413ea9a877 289 * @retval None
ganlikun 0:13413ea9a877 290 */
ganlikun 0:13413ea9a877 291 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
ganlikun 0:13413ea9a877 292 {
ganlikun 0:13413ea9a877 293 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
ganlikun 0:13413ea9a877 294 }
ganlikun 0:13413ea9a877 295
ganlikun 0:13413ea9a877 296 /**
ganlikun 0:13413ea9a877 297 * @brief Disable SysTick exception request
ganlikun 0:13413ea9a877 298 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
ganlikun 0:13413ea9a877 299 * @retval None
ganlikun 0:13413ea9a877 300 */
ganlikun 0:13413ea9a877 301 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
ganlikun 0:13413ea9a877 302 {
ganlikun 0:13413ea9a877 303 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
ganlikun 0:13413ea9a877 304 }
ganlikun 0:13413ea9a877 305
ganlikun 0:13413ea9a877 306 /**
ganlikun 0:13413ea9a877 307 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
ganlikun 0:13413ea9a877 308 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
ganlikun 0:13413ea9a877 309 * @retval State of bit (1 or 0).
ganlikun 0:13413ea9a877 310 */
ganlikun 0:13413ea9a877 311 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
ganlikun 0:13413ea9a877 312 {
ganlikun 0:13413ea9a877 313 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
ganlikun 0:13413ea9a877 314 }
ganlikun 0:13413ea9a877 315
ganlikun 0:13413ea9a877 316 /**
ganlikun 0:13413ea9a877 317 * @}
ganlikun 0:13413ea9a877 318 */
ganlikun 0:13413ea9a877 319
ganlikun 0:13413ea9a877 320 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
ganlikun 0:13413ea9a877 321 * @{
ganlikun 0:13413ea9a877 322 */
ganlikun 0:13413ea9a877 323
ganlikun 0:13413ea9a877 324 /**
ganlikun 0:13413ea9a877 325 * @brief Processor uses sleep as its low power mode
ganlikun 0:13413ea9a877 326 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
ganlikun 0:13413ea9a877 327 * @retval None
ganlikun 0:13413ea9a877 328 */
ganlikun 0:13413ea9a877 329 __STATIC_INLINE void LL_LPM_EnableSleep(void)
ganlikun 0:13413ea9a877 330 {
ganlikun 0:13413ea9a877 331 /* Clear SLEEPDEEP bit of Cortex System Control Register */
ganlikun 0:13413ea9a877 332 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
ganlikun 0:13413ea9a877 333 }
ganlikun 0:13413ea9a877 334
ganlikun 0:13413ea9a877 335 /**
ganlikun 0:13413ea9a877 336 * @brief Processor uses deep sleep as its low power mode
ganlikun 0:13413ea9a877 337 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
ganlikun 0:13413ea9a877 338 * @retval None
ganlikun 0:13413ea9a877 339 */
ganlikun 0:13413ea9a877 340 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
ganlikun 0:13413ea9a877 341 {
ganlikun 0:13413ea9a877 342 /* Set SLEEPDEEP bit of Cortex System Control Register */
ganlikun 0:13413ea9a877 343 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
ganlikun 0:13413ea9a877 344 }
ganlikun 0:13413ea9a877 345
ganlikun 0:13413ea9a877 346 /**
ganlikun 0:13413ea9a877 347 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
ganlikun 0:13413ea9a877 348 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
ganlikun 0:13413ea9a877 349 * empty main application.
ganlikun 0:13413ea9a877 350 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
ganlikun 0:13413ea9a877 351 * @retval None
ganlikun 0:13413ea9a877 352 */
ganlikun 0:13413ea9a877 353 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
ganlikun 0:13413ea9a877 354 {
ganlikun 0:13413ea9a877 355 /* Set SLEEPONEXIT bit of Cortex System Control Register */
ganlikun 0:13413ea9a877 356 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
ganlikun 0:13413ea9a877 357 }
ganlikun 0:13413ea9a877 358
ganlikun 0:13413ea9a877 359 /**
ganlikun 0:13413ea9a877 360 * @brief Do not sleep when returning to Thread mode.
ganlikun 0:13413ea9a877 361 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
ganlikun 0:13413ea9a877 362 * @retval None
ganlikun 0:13413ea9a877 363 */
ganlikun 0:13413ea9a877 364 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
ganlikun 0:13413ea9a877 365 {
ganlikun 0:13413ea9a877 366 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
ganlikun 0:13413ea9a877 367 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
ganlikun 0:13413ea9a877 368 }
ganlikun 0:13413ea9a877 369
ganlikun 0:13413ea9a877 370 /**
ganlikun 0:13413ea9a877 371 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
ganlikun 0:13413ea9a877 372 * processor.
ganlikun 0:13413ea9a877 373 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
ganlikun 0:13413ea9a877 374 * @retval None
ganlikun 0:13413ea9a877 375 */
ganlikun 0:13413ea9a877 376 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
ganlikun 0:13413ea9a877 377 {
ganlikun 0:13413ea9a877 378 /* Set SEVEONPEND bit of Cortex System Control Register */
ganlikun 0:13413ea9a877 379 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
ganlikun 0:13413ea9a877 380 }
ganlikun 0:13413ea9a877 381
ganlikun 0:13413ea9a877 382 /**
ganlikun 0:13413ea9a877 383 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
ganlikun 0:13413ea9a877 384 * excluded
ganlikun 0:13413ea9a877 385 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
ganlikun 0:13413ea9a877 386 * @retval None
ganlikun 0:13413ea9a877 387 */
ganlikun 0:13413ea9a877 388 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
ganlikun 0:13413ea9a877 389 {
ganlikun 0:13413ea9a877 390 /* Clear SEVEONPEND bit of Cortex System Control Register */
ganlikun 0:13413ea9a877 391 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
ganlikun 0:13413ea9a877 392 }
ganlikun 0:13413ea9a877 393
ganlikun 0:13413ea9a877 394 /**
ganlikun 0:13413ea9a877 395 * @}
ganlikun 0:13413ea9a877 396 */
ganlikun 0:13413ea9a877 397
ganlikun 0:13413ea9a877 398 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
ganlikun 0:13413ea9a877 399 * @{
ganlikun 0:13413ea9a877 400 */
ganlikun 0:13413ea9a877 401
ganlikun 0:13413ea9a877 402 /**
ganlikun 0:13413ea9a877 403 * @brief Enable a fault in System handler control register (SHCSR)
ganlikun 0:13413ea9a877 404 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
ganlikun 0:13413ea9a877 405 * @param Fault This parameter can be a combination of the following values:
ganlikun 0:13413ea9a877 406 * @arg @ref LL_HANDLER_FAULT_USG
ganlikun 0:13413ea9a877 407 * @arg @ref LL_HANDLER_FAULT_BUS
ganlikun 0:13413ea9a877 408 * @arg @ref LL_HANDLER_FAULT_MEM
ganlikun 0:13413ea9a877 409 * @retval None
ganlikun 0:13413ea9a877 410 */
ganlikun 0:13413ea9a877 411 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
ganlikun 0:13413ea9a877 412 {
ganlikun 0:13413ea9a877 413 /* Enable the system handler fault */
ganlikun 0:13413ea9a877 414 SET_BIT(SCB->SHCSR, Fault);
ganlikun 0:13413ea9a877 415 }
ganlikun 0:13413ea9a877 416
ganlikun 0:13413ea9a877 417 /**
ganlikun 0:13413ea9a877 418 * @brief Disable a fault in System handler control register (SHCSR)
ganlikun 0:13413ea9a877 419 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
ganlikun 0:13413ea9a877 420 * @param Fault This parameter can be a combination of the following values:
ganlikun 0:13413ea9a877 421 * @arg @ref LL_HANDLER_FAULT_USG
ganlikun 0:13413ea9a877 422 * @arg @ref LL_HANDLER_FAULT_BUS
ganlikun 0:13413ea9a877 423 * @arg @ref LL_HANDLER_FAULT_MEM
ganlikun 0:13413ea9a877 424 * @retval None
ganlikun 0:13413ea9a877 425 */
ganlikun 0:13413ea9a877 426 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
ganlikun 0:13413ea9a877 427 {
ganlikun 0:13413ea9a877 428 /* Disable the system handler fault */
ganlikun 0:13413ea9a877 429 CLEAR_BIT(SCB->SHCSR, Fault);
ganlikun 0:13413ea9a877 430 }
ganlikun 0:13413ea9a877 431
ganlikun 0:13413ea9a877 432 /**
ganlikun 0:13413ea9a877 433 * @}
ganlikun 0:13413ea9a877 434 */
ganlikun 0:13413ea9a877 435
ganlikun 0:13413ea9a877 436 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
ganlikun 0:13413ea9a877 437 * @{
ganlikun 0:13413ea9a877 438 */
ganlikun 0:13413ea9a877 439
ganlikun 0:13413ea9a877 440 /**
ganlikun 0:13413ea9a877 441 * @brief Get Implementer code
ganlikun 0:13413ea9a877 442 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
ganlikun 0:13413ea9a877 443 * @retval Value should be equal to 0x41 for ARM
ganlikun 0:13413ea9a877 444 */
ganlikun 0:13413ea9a877 445 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
ganlikun 0:13413ea9a877 446 {
ganlikun 0:13413ea9a877 447 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
ganlikun 0:13413ea9a877 448 }
ganlikun 0:13413ea9a877 449
ganlikun 0:13413ea9a877 450 /**
ganlikun 0:13413ea9a877 451 * @brief Get Variant number (The r value in the rnpn product revision identifier)
ganlikun 0:13413ea9a877 452 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
ganlikun 0:13413ea9a877 453 * @retval Value between 0 and 255 (0x0: revision 0)
ganlikun 0:13413ea9a877 454 */
ganlikun 0:13413ea9a877 455 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
ganlikun 0:13413ea9a877 456 {
ganlikun 0:13413ea9a877 457 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
ganlikun 0:13413ea9a877 458 }
ganlikun 0:13413ea9a877 459
ganlikun 0:13413ea9a877 460 /**
ganlikun 0:13413ea9a877 461 * @brief Get Constant number
ganlikun 0:13413ea9a877 462 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
ganlikun 0:13413ea9a877 463 * @retval Value should be equal to 0xF for Cortex-M4 devices
ganlikun 0:13413ea9a877 464 */
ganlikun 0:13413ea9a877 465 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
ganlikun 0:13413ea9a877 466 {
ganlikun 0:13413ea9a877 467 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
ganlikun 0:13413ea9a877 468 }
ganlikun 0:13413ea9a877 469
ganlikun 0:13413ea9a877 470 /**
ganlikun 0:13413ea9a877 471 * @brief Get Part number
ganlikun 0:13413ea9a877 472 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
ganlikun 0:13413ea9a877 473 * @retval Value should be equal to 0xC24 for Cortex-M4
ganlikun 0:13413ea9a877 474 */
ganlikun 0:13413ea9a877 475 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
ganlikun 0:13413ea9a877 476 {
ganlikun 0:13413ea9a877 477 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
ganlikun 0:13413ea9a877 478 }
ganlikun 0:13413ea9a877 479
ganlikun 0:13413ea9a877 480 /**
ganlikun 0:13413ea9a877 481 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
ganlikun 0:13413ea9a877 482 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
ganlikun 0:13413ea9a877 483 * @retval Value between 0 and 255 (0x1: patch 1)
ganlikun 0:13413ea9a877 484 */
ganlikun 0:13413ea9a877 485 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
ganlikun 0:13413ea9a877 486 {
ganlikun 0:13413ea9a877 487 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
ganlikun 0:13413ea9a877 488 }
ganlikun 0:13413ea9a877 489
ganlikun 0:13413ea9a877 490 /**
ganlikun 0:13413ea9a877 491 * @}
ganlikun 0:13413ea9a877 492 */
ganlikun 0:13413ea9a877 493
ganlikun 0:13413ea9a877 494 #if __MPU_PRESENT
ganlikun 0:13413ea9a877 495 /** @defgroup CORTEX_LL_EF_MPU MPU
ganlikun 0:13413ea9a877 496 * @{
ganlikun 0:13413ea9a877 497 */
ganlikun 0:13413ea9a877 498
ganlikun 0:13413ea9a877 499 /**
ganlikun 0:13413ea9a877 500 * @brief Enable MPU with input options
ganlikun 0:13413ea9a877 501 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
ganlikun 0:13413ea9a877 502 * @param Options This parameter can be one of the following values:
ganlikun 0:13413ea9a877 503 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
ganlikun 0:13413ea9a877 504 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
ganlikun 0:13413ea9a877 505 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
ganlikun 0:13413ea9a877 506 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
ganlikun 0:13413ea9a877 507 * @retval None
ganlikun 0:13413ea9a877 508 */
ganlikun 0:13413ea9a877 509 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
ganlikun 0:13413ea9a877 510 {
ganlikun 0:13413ea9a877 511 /* Enable the MPU*/
ganlikun 0:13413ea9a877 512 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
ganlikun 0:13413ea9a877 513 /* Ensure MPU settings take effects */
ganlikun 0:13413ea9a877 514 __DSB();
ganlikun 0:13413ea9a877 515 /* Sequence instruction fetches using update settings */
ganlikun 0:13413ea9a877 516 __ISB();
ganlikun 0:13413ea9a877 517 }
ganlikun 0:13413ea9a877 518
ganlikun 0:13413ea9a877 519 /**
ganlikun 0:13413ea9a877 520 * @brief Disable MPU
ganlikun 0:13413ea9a877 521 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
ganlikun 0:13413ea9a877 522 * @retval None
ganlikun 0:13413ea9a877 523 */
ganlikun 0:13413ea9a877 524 __STATIC_INLINE void LL_MPU_Disable(void)
ganlikun 0:13413ea9a877 525 {
ganlikun 0:13413ea9a877 526 /* Make sure outstanding transfers are done */
ganlikun 0:13413ea9a877 527 __DMB();
ganlikun 0:13413ea9a877 528 /* Disable MPU*/
ganlikun 0:13413ea9a877 529 WRITE_REG(MPU->CTRL, 0U);
ganlikun 0:13413ea9a877 530 }
ganlikun 0:13413ea9a877 531
ganlikun 0:13413ea9a877 532 /**
ganlikun 0:13413ea9a877 533 * @brief Check if MPU is enabled or not
ganlikun 0:13413ea9a877 534 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
ganlikun 0:13413ea9a877 535 * @retval State of bit (1 or 0).
ganlikun 0:13413ea9a877 536 */
ganlikun 0:13413ea9a877 537 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
ganlikun 0:13413ea9a877 538 {
ganlikun 0:13413ea9a877 539 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
ganlikun 0:13413ea9a877 540 }
ganlikun 0:13413ea9a877 541
ganlikun 0:13413ea9a877 542 /**
ganlikun 0:13413ea9a877 543 * @brief Enable a MPU region
ganlikun 0:13413ea9a877 544 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
ganlikun 0:13413ea9a877 545 * @param Region This parameter can be one of the following values:
ganlikun 0:13413ea9a877 546 * @arg @ref LL_MPU_REGION_NUMBER0
ganlikun 0:13413ea9a877 547 * @arg @ref LL_MPU_REGION_NUMBER1
ganlikun 0:13413ea9a877 548 * @arg @ref LL_MPU_REGION_NUMBER2
ganlikun 0:13413ea9a877 549 * @arg @ref LL_MPU_REGION_NUMBER3
ganlikun 0:13413ea9a877 550 * @arg @ref LL_MPU_REGION_NUMBER4
ganlikun 0:13413ea9a877 551 * @arg @ref LL_MPU_REGION_NUMBER5
ganlikun 0:13413ea9a877 552 * @arg @ref LL_MPU_REGION_NUMBER6
ganlikun 0:13413ea9a877 553 * @arg @ref LL_MPU_REGION_NUMBER7
ganlikun 0:13413ea9a877 554 * @retval None
ganlikun 0:13413ea9a877 555 */
ganlikun 0:13413ea9a877 556 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
ganlikun 0:13413ea9a877 557 {
ganlikun 0:13413ea9a877 558 /* Set Region number */
ganlikun 0:13413ea9a877 559 WRITE_REG(MPU->RNR, Region);
ganlikun 0:13413ea9a877 560 /* Enable the MPU region */
ganlikun 0:13413ea9a877 561 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
ganlikun 0:13413ea9a877 562 }
ganlikun 0:13413ea9a877 563
ganlikun 0:13413ea9a877 564 /**
ganlikun 0:13413ea9a877 565 * @brief Configure and enable a region
ganlikun 0:13413ea9a877 566 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
ganlikun 0:13413ea9a877 567 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
ganlikun 0:13413ea9a877 568 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
ganlikun 0:13413ea9a877 569 * MPU_RASR XN LL_MPU_ConfigRegion\n
ganlikun 0:13413ea9a877 570 * MPU_RASR AP LL_MPU_ConfigRegion\n
ganlikun 0:13413ea9a877 571 * MPU_RASR S LL_MPU_ConfigRegion\n
ganlikun 0:13413ea9a877 572 * MPU_RASR C LL_MPU_ConfigRegion\n
ganlikun 0:13413ea9a877 573 * MPU_RASR B LL_MPU_ConfigRegion\n
ganlikun 0:13413ea9a877 574 * MPU_RASR SIZE LL_MPU_ConfigRegion
ganlikun 0:13413ea9a877 575 * @param Region This parameter can be one of the following values:
ganlikun 0:13413ea9a877 576 * @arg @ref LL_MPU_REGION_NUMBER0
ganlikun 0:13413ea9a877 577 * @arg @ref LL_MPU_REGION_NUMBER1
ganlikun 0:13413ea9a877 578 * @arg @ref LL_MPU_REGION_NUMBER2
ganlikun 0:13413ea9a877 579 * @arg @ref LL_MPU_REGION_NUMBER3
ganlikun 0:13413ea9a877 580 * @arg @ref LL_MPU_REGION_NUMBER4
ganlikun 0:13413ea9a877 581 * @arg @ref LL_MPU_REGION_NUMBER5
ganlikun 0:13413ea9a877 582 * @arg @ref LL_MPU_REGION_NUMBER6
ganlikun 0:13413ea9a877 583 * @arg @ref LL_MPU_REGION_NUMBER7
ganlikun 0:13413ea9a877 584 * @param Address Value of region base address
ganlikun 0:13413ea9a877 585 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
ganlikun 0:13413ea9a877 586 * @param Attributes This parameter can be a combination of the following values:
ganlikun 0:13413ea9a877 587 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
ganlikun 0:13413ea9a877 588 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
ganlikun 0:13413ea9a877 589 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
ganlikun 0:13413ea9a877 590 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
ganlikun 0:13413ea9a877 591 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
ganlikun 0:13413ea9a877 592 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
ganlikun 0:13413ea9a877 593 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
ganlikun 0:13413ea9a877 594 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
ganlikun 0:13413ea9a877 595 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
ganlikun 0:13413ea9a877 596 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
ganlikun 0:13413ea9a877 597 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
ganlikun 0:13413ea9a877 598 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
ganlikun 0:13413ea9a877 599 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
ganlikun 0:13413ea9a877 600 * @retval None
ganlikun 0:13413ea9a877 601 */
ganlikun 0:13413ea9a877 602 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
ganlikun 0:13413ea9a877 603 {
ganlikun 0:13413ea9a877 604 /* Set Region number */
ganlikun 0:13413ea9a877 605 WRITE_REG(MPU->RNR, Region);
ganlikun 0:13413ea9a877 606 /* Set base address */
ganlikun 0:13413ea9a877 607 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
ganlikun 0:13413ea9a877 608 /* Configure MPU */
ganlikun 0:13413ea9a877 609 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
ganlikun 0:13413ea9a877 610 }
ganlikun 0:13413ea9a877 611
ganlikun 0:13413ea9a877 612 /**
ganlikun 0:13413ea9a877 613 * @brief Disable a region
ganlikun 0:13413ea9a877 614 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
ganlikun 0:13413ea9a877 615 * MPU_RASR ENABLE LL_MPU_DisableRegion
ganlikun 0:13413ea9a877 616 * @param Region This parameter can be one of the following values:
ganlikun 0:13413ea9a877 617 * @arg @ref LL_MPU_REGION_NUMBER0
ganlikun 0:13413ea9a877 618 * @arg @ref LL_MPU_REGION_NUMBER1
ganlikun 0:13413ea9a877 619 * @arg @ref LL_MPU_REGION_NUMBER2
ganlikun 0:13413ea9a877 620 * @arg @ref LL_MPU_REGION_NUMBER3
ganlikun 0:13413ea9a877 621 * @arg @ref LL_MPU_REGION_NUMBER4
ganlikun 0:13413ea9a877 622 * @arg @ref LL_MPU_REGION_NUMBER5
ganlikun 0:13413ea9a877 623 * @arg @ref LL_MPU_REGION_NUMBER6
ganlikun 0:13413ea9a877 624 * @arg @ref LL_MPU_REGION_NUMBER7
ganlikun 0:13413ea9a877 625 * @retval None
ganlikun 0:13413ea9a877 626 */
ganlikun 0:13413ea9a877 627 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
ganlikun 0:13413ea9a877 628 {
ganlikun 0:13413ea9a877 629 /* Set Region number */
ganlikun 0:13413ea9a877 630 WRITE_REG(MPU->RNR, Region);
ganlikun 0:13413ea9a877 631 /* Disable the MPU region */
ganlikun 0:13413ea9a877 632 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
ganlikun 0:13413ea9a877 633 }
ganlikun 0:13413ea9a877 634
ganlikun 0:13413ea9a877 635 /**
ganlikun 0:13413ea9a877 636 * @}
ganlikun 0:13413ea9a877 637 */
ganlikun 0:13413ea9a877 638
ganlikun 0:13413ea9a877 639 #endif /* __MPU_PRESENT */
ganlikun 0:13413ea9a877 640 /**
ganlikun 0:13413ea9a877 641 * @}
ganlikun 0:13413ea9a877 642 */
ganlikun 0:13413ea9a877 643
ganlikun 0:13413ea9a877 644 /**
ganlikun 0:13413ea9a877 645 * @}
ganlikun 0:13413ea9a877 646 */
ganlikun 0:13413ea9a877 647
ganlikun 0:13413ea9a877 648 /**
ganlikun 0:13413ea9a877 649 * @}
ganlikun 0:13413ea9a877 650 */
ganlikun 0:13413ea9a877 651
ganlikun 0:13413ea9a877 652 #ifdef __cplusplus
ganlikun 0:13413ea9a877 653 }
ganlikun 0:13413ea9a877 654 #endif
ganlikun 0:13413ea9a877 655
ganlikun 0:13413ea9a877 656 #endif /* __STM32F4xx_LL_CORTEX_H */
ganlikun 0:13413ea9a877 657
ganlikun 0:13413ea9a877 658 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
ganlikun 0:13413ea9a877 659