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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.c@0:13413ea9a877, 2022-06-12 (annotated)

Committer:: ganlikun
Date:: Sun Jun 12 14:02:44 2022 +0000
Revision:: 0:13413ea9a877

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User	Revision	Line number	New contents of line
ganlikun	0:13413ea9a877	1	/**
ganlikun	0:13413ea9a877	2	******************************************************************************
ganlikun	0:13413ea9a877	3	* @file stm32f4xx_hal_dma2d.c
ganlikun	0:13413ea9a877	4	* @author MCD Application Team
ganlikun	0:13413ea9a877	5	* @version V1.7.1
ganlikun	0:13413ea9a877	6	* @date 14-April-2017
ganlikun	0:13413ea9a877	7	* @brief DMA2D HAL module driver.
ganlikun	0:13413ea9a877	8	* This file provides firmware functions to manage the following
ganlikun	0:13413ea9a877	9	* functionalities of the DMA2D peripheral:
ganlikun	0:13413ea9a877	10	* + Initialization and de-initialization functions
ganlikun	0:13413ea9a877	11	* + IO operation functions
ganlikun	0:13413ea9a877	12	* + Peripheral Control functions
ganlikun	0:13413ea9a877	13	* + Peripheral State and Errors functions
ganlikun	0:13413ea9a877	14	*
ganlikun	0:13413ea9a877	15	@verbatim
ganlikun	0:13413ea9a877	16	==============================================================================
ganlikun	0:13413ea9a877	17	##### How to use this driver #####
ganlikun	0:13413ea9a877	18	==============================================================================
ganlikun	0:13413ea9a877	19	[..]
ganlikun	0:13413ea9a877	20	(#) Program the required configuration through the following parameters:
ganlikun	0:13413ea9a877	21	the transfer mode, the output color mode and the output offset using
ganlikun	0:13413ea9a877	22	HAL_DMA2D_Init() function.
ganlikun	0:13413ea9a877	23
ganlikun	0:13413ea9a877	24	(#) Program the required configuration through the following parameters:
ganlikun	0:13413ea9a877	25	the input color mode, the input color, the input alpha value, the alpha mode,
ganlikun	0:13413ea9a877	26	and the input offset using HAL_DMA2D_ConfigLayer() function for foreground
ganlikun	0:13413ea9a877	27	or/and background layer.
ganlikun	0:13413ea9a877	28
ganlikun	0:13413ea9a877	29	* Polling mode IO operation *
ganlikun	0:13413ea9a877	30	=================================
ganlikun	0:13413ea9a877	31	[..]
ganlikun	0:13413ea9a877	32	(#) Configure pdata parameter (explained hereafter), destination and data length
ganlikun	0:13413ea9a877	33	and enable the transfer using HAL_DMA2D_Start().
ganlikun	0:13413ea9a877	34	(#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
ganlikun	0:13413ea9a877	35	user can specify the value of timeout according to his end application.
ganlikun	0:13413ea9a877	36
ganlikun	0:13413ea9a877	37	* Interrupt mode IO operation *
ganlikun	0:13413ea9a877	38	===================================
ganlikun	0:13413ea9a877	39	[..]
ganlikun	0:13413ea9a877	40	(#) Configure pdata parameter, destination and data length and enable
ganlikun	0:13413ea9a877	41	the transfer using HAL_DMA2D_Start_IT().
ganlikun	0:13413ea9a877	42	(#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine
ganlikun	0:13413ea9a877	43	(#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
ganlikun	0:13413ea9a877	44	add his own function by customization of function pointer XferCpltCallback (member
ganlikun	0:13413ea9a877	45	of DMA2D handle structure).
ganlikun	0:13413ea9a877	46	(#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback
ganlikun	0:13413ea9a877	47	XferErrorCallback.
ganlikun	0:13413ea9a877	48
ganlikun	0:13413ea9a877	49	-@- In Register-to-Memory transfer mode, pdata parameter is the register
ganlikun	0:13413ea9a877	50	color, in Memory-to-memory or Memory-to-Memory with pixel format
ganlikun	0:13413ea9a877	51	conversion pdata is the source address.
ganlikun	0:13413ea9a877	52
ganlikun	0:13413ea9a877	53	-@- Configure the foreground source address, the background source address,
ganlikun	0:13413ea9a877	54	the destination and data length then Enable the transfer using
ganlikun	0:13413ea9a877	55	HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
ganlikun	0:13413ea9a877	56	in interrupt mode
ganlikun	0:13413ea9a877	57
ganlikun	0:13413ea9a877	58	-@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
ganlikun	0:13413ea9a877	59	are used if the memory to memory with blending transfer mode is selected.
ganlikun	0:13413ea9a877	60
ganlikun	0:13413ea9a877	61	(#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
ganlikun	0:13413ea9a877	62	mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
ganlikun	0:13413ea9a877	63
ganlikun	0:13413ea9a877	64	(#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent()
ganlikun	0:13413ea9a877	65
ganlikun	0:13413ea9a877	66	(#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
ganlikun	0:13413ea9a877	67	consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
ganlikun	0:13413ea9a877	68	and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or
ganlikun	0:13413ea9a877	69	HAL_DMA2D_DisableDeadTime().
ganlikun	0:13413ea9a877	70
ganlikun	0:13413ea9a877	71	(#) The transfer can be suspended, resumed and aborted using the following
ganlikun	0:13413ea9a877	72	functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
ganlikun	0:13413ea9a877	73
ganlikun	0:13413ea9a877	74	(#) The CLUT loading can be suspended, resumed and aborted using the following
ganlikun	0:13413ea9a877	75	functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
ganlikun	0:13413ea9a877	76	HAL_DMA2D_CLUTLoading_Abort().
ganlikun	0:13413ea9a877	77
ganlikun	0:13413ea9a877	78	(#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
ganlikun	0:13413ea9a877	79
ganlikun	0:13413ea9a877	80	(#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
ganlikun	0:13413ea9a877	81
ganlikun	0:13413ea9a877	82	* DMA2D HAL driver macros list *
ganlikun	0:13413ea9a877	83	=============================================
ganlikun	0:13413ea9a877	84	[..]
ganlikun	0:13413ea9a877	85	Below the list of most used macros in DMA2D HAL driver :
ganlikun	0:13413ea9a877	86
ganlikun	0:13413ea9a877	87	(+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
ganlikun	0:13413ea9a877	88	(+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
ganlikun	0:13413ea9a877	89	(+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
ganlikun	0:13413ea9a877	90	(+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
ganlikun	0:13413ea9a877	91	(+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
ganlikun	0:13413ea9a877	92	(+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not
ganlikun	0:13413ea9a877	93
ganlikun	0:13413ea9a877	94	[..]
ganlikun	0:13413ea9a877	95	(@) You can refer to the DMA2D HAL driver header file for more useful macros
ganlikun	0:13413ea9a877	96
ganlikun	0:13413ea9a877	97	@endverbatim
ganlikun	0:13413ea9a877	98	******************************************************************************
ganlikun	0:13413ea9a877	99	* @attention
ganlikun	0:13413ea9a877	100	*
ganlikun	0:13413ea9a877	101	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun	0:13413ea9a877	102	*
ganlikun	0:13413ea9a877	103	* Redistribution and use in source and binary forms, with or without modification,
ganlikun	0:13413ea9a877	104	* are permitted provided that the following conditions are met:
ganlikun	0:13413ea9a877	105	* 1. Redistributions of source code must retain the above copyright notice,
ganlikun	0:13413ea9a877	106	* this list of conditions and the following disclaimer.
ganlikun	0:13413ea9a877	107	* 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun	0:13413ea9a877	108	* this list of conditions and the following disclaimer in the documentation
ganlikun	0:13413ea9a877	109	* and/or other materials provided with the distribution.
ganlikun	0:13413ea9a877	110	* 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun	0:13413ea9a877	111	* may be used to endorse or promote products derived from this software
ganlikun	0:13413ea9a877	112	* without specific prior written permission.
ganlikun	0:13413ea9a877	113	*
ganlikun	0:13413ea9a877	114	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun	0:13413ea9a877	115	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun	0:13413ea9a877	116	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun	0:13413ea9a877	117	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun	0:13413ea9a877	118	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun	0:13413ea9a877	119	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun	0:13413ea9a877	120	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun	0:13413ea9a877	121	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun	0:13413ea9a877	122	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun	0:13413ea9a877	123	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun	0:13413ea9a877	124	*
ganlikun	0:13413ea9a877	125	******************************************************************************
ganlikun	0:13413ea9a877	126	*/
ganlikun	0:13413ea9a877	127
ganlikun	0:13413ea9a877	128	/* Includes ------------------------------------------------------------------*/
ganlikun	0:13413ea9a877	129	#include "stm32f4xx_hal.h"
ganlikun	0:13413ea9a877	130
ganlikun	0:13413ea9a877	131	/** @addtogroup STM32F4xx_HAL_Driver
ganlikun	0:13413ea9a877	132	* @{
ganlikun	0:13413ea9a877	133	*/
ganlikun	0:13413ea9a877	134
ganlikun	0:13413ea9a877	135	/** @defgroup DMA2D DMA2D
ganlikun	0:13413ea9a877	136	* @brief DMA2D HAL module driver
ganlikun	0:13413ea9a877	137	* @{
ganlikun	0:13413ea9a877	138	*/
ganlikun	0:13413ea9a877	139
ganlikun	0:13413ea9a877	140	#ifdef HAL_DMA2D_MODULE_ENABLED
ganlikun	0:13413ea9a877	141
ganlikun	0:13413ea9a877	142	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
ganlikun	0:13413ea9a877	143
ganlikun	0:13413ea9a877	144	/* Private types -------------------------------------------------------------*/
ganlikun	0:13413ea9a877	145	/* Private define ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	146	/** @defgroup DMA2D_Private_Constants DMA2D Private Constants
ganlikun	0:13413ea9a877	147	* @{
ganlikun	0:13413ea9a877	148	*/
ganlikun	0:13413ea9a877	149
ganlikun	0:13413ea9a877	150	/** @defgroup DMA2D_TimeOut DMA2D Time Out
ganlikun	0:13413ea9a877	151	* @{
ganlikun	0:13413ea9a877	152	*/
ganlikun	0:13413ea9a877	153	#define DMA2D_TIMEOUT_ABORT 1000U /!< 1s /
ganlikun	0:13413ea9a877	154	#define DMA2D_TIMEOUT_SUSPEND 1000U /!< 1s /
ganlikun	0:13413ea9a877	155	/**
ganlikun	0:13413ea9a877	156	* @}
ganlikun	0:13413ea9a877	157	*/
ganlikun	0:13413ea9a877	158
ganlikun	0:13413ea9a877	159	/** @defgroup DMA2D_Shifts DMA2D Shifts
ganlikun	0:13413ea9a877	160	* @{
ganlikun	0:13413ea9a877	161	*/
ganlikun	0:13413ea9a877	162	#define DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS) /!< Required left shift to set foreground CLUT size /
ganlikun	0:13413ea9a877	163	#define DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS) /!< Required left shift to set background CLUT size /
ganlikun	0:13413ea9a877	164
ganlikun	0:13413ea9a877	165	#define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM) /!< Required left shift to set foreground CLUT color mode /
ganlikun	0:13413ea9a877	166	#define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM) /!< Required left shift to set background CLUT color mode /
ganlikun	0:13413ea9a877	167
ganlikun	0:13413ea9a877	168	#define DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT) /!< Required left shift to set deadtime value /
ganlikun	0:13413ea9a877	169
ganlikun	0:13413ea9a877	170	#define DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM) /!< Required left shift to set foreground alpha mode /
ganlikun	0:13413ea9a877	171	#define DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM) /!< Required left shift to set background alpha mode /
ganlikun	0:13413ea9a877	172
ganlikun	0:13413ea9a877	173	#define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /!< Required left shift to set foreground alpha value /
ganlikun	0:13413ea9a877	174	#define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /!< Required left shift to set background alpha value /
ganlikun	0:13413ea9a877	175
ganlikun	0:13413ea9a877	176	#define DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL) /!< Required left shift to set pixels per lines value /
ganlikun	0:13413ea9a877	177	/**
ganlikun	0:13413ea9a877	178	* @}
ganlikun	0:13413ea9a877	179	*/
ganlikun	0:13413ea9a877	180
ganlikun	0:13413ea9a877	181	/**
ganlikun	0:13413ea9a877	182	* @}
ganlikun	0:13413ea9a877	183	*/
ganlikun	0:13413ea9a877	184
ganlikun	0:13413ea9a877	185	/* Private variables ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	186	/* Private constants ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	187	/* Private macro -------------------------------------------------------------*/
ganlikun	0:13413ea9a877	188	/* Private function prototypes -----------------------------------------------*/
ganlikun	0:13413ea9a877	189	/** @addtogroup DMA2D_Private_Functions_Prototypes
ganlikun	0:13413ea9a877	190	* @{
ganlikun	0:13413ea9a877	191	*/
ganlikun	0:13413ea9a877	192	static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
ganlikun	0:13413ea9a877	193	/**
ganlikun	0:13413ea9a877	194	* @}
ganlikun	0:13413ea9a877	195	*/
ganlikun	0:13413ea9a877	196
ganlikun	0:13413ea9a877	197	/* Private functions ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	198	/* Exported functions --------------------------------------------------------*/
ganlikun	0:13413ea9a877	199	/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
ganlikun	0:13413ea9a877	200	* @{
ganlikun	0:13413ea9a877	201	*/
ganlikun	0:13413ea9a877	202
ganlikun	0:13413ea9a877	203	/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
ganlikun	0:13413ea9a877	204	* @brief Initialization and Configuration functions
ganlikun	0:13413ea9a877	205	*
ganlikun	0:13413ea9a877	206	@verbatim
ganlikun	0:13413ea9a877	207	===============================================================================
ganlikun	0:13413ea9a877	208	##### Initialization and Configuration functions #####
ganlikun	0:13413ea9a877	209	===============================================================================
ganlikun	0:13413ea9a877	210	[..] This section provides functions allowing to:
ganlikun	0:13413ea9a877	211	(+) Initialize and configure the DMA2D
ganlikun	0:13413ea9a877	212	(+) De-initialize the DMA2D
ganlikun	0:13413ea9a877	213
ganlikun	0:13413ea9a877	214	@endverbatim
ganlikun	0:13413ea9a877	215	* @{
ganlikun	0:13413ea9a877	216	*/
ganlikun	0:13413ea9a877	217
ganlikun	0:13413ea9a877	218	/**
ganlikun	0:13413ea9a877	219	* @brief Initialize the DMA2D according to the specified
ganlikun	0:13413ea9a877	220	* parameters in the DMA2D_InitTypeDef and create the associated handle.
ganlikun	0:13413ea9a877	221	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	222	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	223	* @retval HAL status
ganlikun	0:13413ea9a877	224	*/
ganlikun	0:13413ea9a877	225	HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
ganlikun	0:13413ea9a877	226	{
ganlikun	0:13413ea9a877	227	/* Check the DMA2D peripheral state */
ganlikun	0:13413ea9a877	228	if(hdma2d == NULL)
ganlikun	0:13413ea9a877	229	{
ganlikun	0:13413ea9a877	230	return HAL_ERROR;
ganlikun	0:13413ea9a877	231	}
ganlikun	0:13413ea9a877	232
ganlikun	0:13413ea9a877	233	/* Check the parameters */
ganlikun	0:13413ea9a877	234	assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
ganlikun	0:13413ea9a877	235	assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
ganlikun	0:13413ea9a877	236	assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
ganlikun	0:13413ea9a877	237	assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
ganlikun	0:13413ea9a877	238
ganlikun	0:13413ea9a877	239	if(hdma2d->State == HAL_DMA2D_STATE_RESET)
ganlikun	0:13413ea9a877	240	{
ganlikun	0:13413ea9a877	241	/* Allocate lock resource and initialize it */
ganlikun	0:13413ea9a877	242	hdma2d->Lock = HAL_UNLOCKED;
ganlikun	0:13413ea9a877	243	/* Init the low level hardware */
ganlikun	0:13413ea9a877	244	HAL_DMA2D_MspInit(hdma2d);
ganlikun	0:13413ea9a877	245	}
ganlikun	0:13413ea9a877	246
ganlikun	0:13413ea9a877	247	/* Change DMA2D peripheral state */
ganlikun	0:13413ea9a877	248	hdma2d->State = HAL_DMA2D_STATE_BUSY;
ganlikun	0:13413ea9a877	249
ganlikun	0:13413ea9a877	250	/* DMA2D CR register configuration -------------------------------------------*/
ganlikun	0:13413ea9a877	251	MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
ganlikun	0:13413ea9a877	252
ganlikun	0:13413ea9a877	253	/* DMA2D OPFCCR register configuration ---------------------------------------*/
ganlikun	0:13413ea9a877	254	MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
ganlikun	0:13413ea9a877	255
ganlikun	0:13413ea9a877	256	/* DMA2D OOR register configuration ------------------------------------------*/
ganlikun	0:13413ea9a877	257	MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
ganlikun	0:13413ea9a877	258
ganlikun	0:13413ea9a877	259	/* Update error code */
ganlikun	0:13413ea9a877	260	hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
ganlikun	0:13413ea9a877	261
ganlikun	0:13413ea9a877	262	/* Initialize the DMA2D state*/
ganlikun	0:13413ea9a877	263	hdma2d->State = HAL_DMA2D_STATE_READY;
ganlikun	0:13413ea9a877	264
ganlikun	0:13413ea9a877	265	return HAL_OK;
ganlikun	0:13413ea9a877	266	}
ganlikun	0:13413ea9a877	267
ganlikun	0:13413ea9a877	268	/**
ganlikun	0:13413ea9a877	269	* @brief Deinitializes the DMA2D peripheral registers to their default reset
ganlikun	0:13413ea9a877	270	* values.
ganlikun	0:13413ea9a877	271	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	272	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	273	* @retval None
ganlikun	0:13413ea9a877	274	*/
ganlikun	0:13413ea9a877	275
ganlikun	0:13413ea9a877	276	HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
ganlikun	0:13413ea9a877	277	{
ganlikun	0:13413ea9a877	278	/* Check the DMA2D peripheral state */
ganlikun	0:13413ea9a877	279	if(hdma2d == NULL)
ganlikun	0:13413ea9a877	280	{
ganlikun	0:13413ea9a877	281	return HAL_ERROR;
ganlikun	0:13413ea9a877	282	}
ganlikun	0:13413ea9a877	283
ganlikun	0:13413ea9a877	284	/* Before aborting any DMA2D transfer or CLUT loading, check
ganlikun	0:13413ea9a877	285	first whether or not DMA2D clock is enabled */
ganlikun	0:13413ea9a877	286	if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
ganlikun	0:13413ea9a877	287	{
ganlikun	0:13413ea9a877	288	/* Abort DMA2D transfer if any */
ganlikun	0:13413ea9a877	289	if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
ganlikun	0:13413ea9a877	290	{
ganlikun	0:13413ea9a877	291	if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
ganlikun	0:13413ea9a877	292	{
ganlikun	0:13413ea9a877	293	/* Issue when aborting DMA2D transfer */
ganlikun	0:13413ea9a877	294	return HAL_ERROR;
ganlikun	0:13413ea9a877	295	}
ganlikun	0:13413ea9a877	296	}
ganlikun	0:13413ea9a877	297	else
ganlikun	0:13413ea9a877	298	{
ganlikun	0:13413ea9a877	299	/* Abort background CLUT loading if any */
ganlikun	0:13413ea9a877	300	if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
ganlikun	0:13413ea9a877	301	{
ganlikun	0:13413ea9a877	302	if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
ganlikun	0:13413ea9a877	303	{
ganlikun	0:13413ea9a877	304	/* Issue when aborting background CLUT loading */
ganlikun	0:13413ea9a877	305	return HAL_ERROR;
ganlikun	0:13413ea9a877	306	}
ganlikun	0:13413ea9a877	307	}
ganlikun	0:13413ea9a877	308	else
ganlikun	0:13413ea9a877	309	{
ganlikun	0:13413ea9a877	310	/* Abort foreground CLUT loading if any */
ganlikun	0:13413ea9a877	311	if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
ganlikun	0:13413ea9a877	312	{
ganlikun	0:13413ea9a877	313	if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
ganlikun	0:13413ea9a877	314	{
ganlikun	0:13413ea9a877	315	/* Issue when aborting foreground CLUT loading */
ganlikun	0:13413ea9a877	316	return HAL_ERROR;
ganlikun	0:13413ea9a877	317	}
ganlikun	0:13413ea9a877	318	}
ganlikun	0:13413ea9a877	319	}
ganlikun	0:13413ea9a877	320	}
ganlikun	0:13413ea9a877	321	}
ganlikun	0:13413ea9a877	322
ganlikun	0:13413ea9a877	323	/* Carry on with de-initialization of low level hardware */
ganlikun	0:13413ea9a877	324	HAL_DMA2D_MspDeInit(hdma2d);
ganlikun	0:13413ea9a877	325
ganlikun	0:13413ea9a877	326	/* Reset DMA2D control registers*/
ganlikun	0:13413ea9a877	327	hdma2d->Instance->CR = 0U;
ganlikun	0:13413ea9a877	328	hdma2d->Instance->FGOR = 0U;
ganlikun	0:13413ea9a877	329	hdma2d->Instance->BGOR = 0U;
ganlikun	0:13413ea9a877	330	hdma2d->Instance->FGPFCCR = 0U;
ganlikun	0:13413ea9a877	331	hdma2d->Instance->BGPFCCR = 0U;
ganlikun	0:13413ea9a877	332	hdma2d->Instance->OPFCCR = 0U;
ganlikun	0:13413ea9a877	333
ganlikun	0:13413ea9a877	334	/* Update error code */
ganlikun	0:13413ea9a877	335	hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
ganlikun	0:13413ea9a877	336
ganlikun	0:13413ea9a877	337	/* Initialize the DMA2D state*/
ganlikun	0:13413ea9a877	338	hdma2d->State = HAL_DMA2D_STATE_RESET;
ganlikun	0:13413ea9a877	339
ganlikun	0:13413ea9a877	340	/* Release Lock */
ganlikun	0:13413ea9a877	341	__HAL_UNLOCK(hdma2d);
ganlikun	0:13413ea9a877	342
ganlikun	0:13413ea9a877	343	return HAL_OK;
ganlikun	0:13413ea9a877	344	}
ganlikun	0:13413ea9a877	345
ganlikun	0:13413ea9a877	346	/**
ganlikun	0:13413ea9a877	347	* @brief Initializes the DMA2D MSP.
ganlikun	0:13413ea9a877	348	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	349	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	350	* @retval None
ganlikun	0:13413ea9a877	351	*/
ganlikun	0:13413ea9a877	352	__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
ganlikun	0:13413ea9a877	353	{
ganlikun	0:13413ea9a877	354	/* Prevent unused argument(s) compilation warning */
ganlikun	0:13413ea9a877	355	UNUSED(hdma2d);
ganlikun	0:13413ea9a877	356
ganlikun	0:13413ea9a877	357	/* NOTE : This function should not be modified; when the callback is needed,
ganlikun	0:13413ea9a877	358	the HAL_DMA2D_MspInit can be implemented in the user file.
ganlikun	0:13413ea9a877	359	*/
ganlikun	0:13413ea9a877	360	}
ganlikun	0:13413ea9a877	361
ganlikun	0:13413ea9a877	362	/**
ganlikun	0:13413ea9a877	363	* @brief DeInitializes the DMA2D MSP.
ganlikun	0:13413ea9a877	364	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	365	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	366	* @retval None
ganlikun	0:13413ea9a877	367	*/
ganlikun	0:13413ea9a877	368	__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
ganlikun	0:13413ea9a877	369	{
ganlikun	0:13413ea9a877	370	/* Prevent unused argument(s) compilation warning */
ganlikun	0:13413ea9a877	371	UNUSED(hdma2d);
ganlikun	0:13413ea9a877	372
ganlikun	0:13413ea9a877	373	/* NOTE : This function should not be modified; when the callback is needed,
ganlikun	0:13413ea9a877	374	the HAL_DMA2D_MspDeInit can be implemented in the user file.
ganlikun	0:13413ea9a877	375	*/
ganlikun	0:13413ea9a877	376	}
ganlikun	0:13413ea9a877	377
ganlikun	0:13413ea9a877	378	/**
ganlikun	0:13413ea9a877	379	* @}
ganlikun	0:13413ea9a877	380	*/
ganlikun	0:13413ea9a877	381
ganlikun	0:13413ea9a877	382	/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
ganlikun	0:13413ea9a877	383	* @brief IO operation functions
ganlikun	0:13413ea9a877	384	*
ganlikun	0:13413ea9a877	385	@verbatim
ganlikun	0:13413ea9a877	386	===============================================================================
ganlikun	0:13413ea9a877	387	##### IO operation functions #####
ganlikun	0:13413ea9a877	388	===============================================================================
ganlikun	0:13413ea9a877	389	[..] This section provides functions allowing to:
ganlikun	0:13413ea9a877	390	(+) Configure the pdata, destination address and data size then
ganlikun	0:13413ea9a877	391	start the DMA2D transfer.
ganlikun	0:13413ea9a877	392	(+) Configure the source for foreground and background, destination address
ganlikun	0:13413ea9a877	393	and data size then start a MultiBuffer DMA2D transfer.
ganlikun	0:13413ea9a877	394	(+) Configure the pdata, destination address and data size then
ganlikun	0:13413ea9a877	395	start the DMA2D transfer with interrupt.
ganlikun	0:13413ea9a877	396	(+) Configure the source for foreground and background, destination address
ganlikun	0:13413ea9a877	397	and data size then start a MultiBuffer DMA2D transfer with interrupt.
ganlikun	0:13413ea9a877	398	(+) Abort DMA2D transfer.
ganlikun	0:13413ea9a877	399	(+) Suspend DMA2D transfer.
ganlikun	0:13413ea9a877	400	(+) Resume DMA2D transfer.
ganlikun	0:13413ea9a877	401	(+) Enable CLUT transfer.
ganlikun	0:13413ea9a877	402	(+) Configure CLUT loading then start transfer in polling mode.
ganlikun	0:13413ea9a877	403	(+) Configure CLUT loading then start transfer in interrupt mode.
ganlikun	0:13413ea9a877	404	(+) Abort DMA2D CLUT loading.
ganlikun	0:13413ea9a877	405	(+) Suspend DMA2D CLUT loading.
ganlikun	0:13413ea9a877	406	(+) Resume DMA2D CLUT loading.
ganlikun	0:13413ea9a877	407	(+) Poll for transfer complete.
ganlikun	0:13413ea9a877	408	(+) handle DMA2D interrupt request.
ganlikun	0:13413ea9a877	409	(+) Transfer watermark callback.
ganlikun	0:13413ea9a877	410	(+) CLUT Transfer Complete callback.
ganlikun	0:13413ea9a877	411
ganlikun	0:13413ea9a877	412	@endverbatim
ganlikun	0:13413ea9a877	413	* @{
ganlikun	0:13413ea9a877	414	*/
ganlikun	0:13413ea9a877	415
ganlikun	0:13413ea9a877	416	/**
ganlikun	0:13413ea9a877	417	* @brief Start the DMA2D Transfer.
ganlikun	0:13413ea9a877	418	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	419	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	420	* @param pdata: Configure the source memory Buffer address if
ganlikun	0:13413ea9a877	421	* Memory-to-Memory or Memory-to-Memory with pixel format
ganlikun	0:13413ea9a877	422	* conversion mode is selected, or configure
ganlikun	0:13413ea9a877	423	* the color value if Register-to-Memory mode is selected.
ganlikun	0:13413ea9a877	424	* @param DstAddress: The destination memory Buffer address.
ganlikun	0:13413ea9a877	425	* @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
ganlikun	0:13413ea9a877	426	* @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
ganlikun	0:13413ea9a877	427	* @retval HAL status
ganlikun	0:13413ea9a877	428	*/
ganlikun	0:13413ea9a877	429	HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
ganlikun	0:13413ea9a877	430	{
ganlikun	0:13413ea9a877	431	/* Check the parameters */
ganlikun	0:13413ea9a877	432	assert_param(IS_DMA2D_LINE(Height));
ganlikun	0:13413ea9a877	433	assert_param(IS_DMA2D_PIXEL(Width));
ganlikun	0:13413ea9a877	434
ganlikun	0:13413ea9a877	435	/* Process locked */
ganlikun	0:13413ea9a877	436	__HAL_LOCK(hdma2d);
ganlikun	0:13413ea9a877	437
ganlikun	0:13413ea9a877	438	/* Change DMA2D peripheral state */
ganlikun	0:13413ea9a877	439	hdma2d->State = HAL_DMA2D_STATE_BUSY;
ganlikun	0:13413ea9a877	440
ganlikun	0:13413ea9a877	441	/* Configure the source, destination address and the data size */
ganlikun	0:13413ea9a877	442	DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
ganlikun	0:13413ea9a877	443
ganlikun	0:13413ea9a877	444	/* Enable the Peripheral */
ganlikun	0:13413ea9a877	445	__HAL_DMA2D_ENABLE(hdma2d);
ganlikun	0:13413ea9a877	446
ganlikun	0:13413ea9a877	447	return HAL_OK;
ganlikun	0:13413ea9a877	448	}
ganlikun	0:13413ea9a877	449
ganlikun	0:13413ea9a877	450	/**
ganlikun	0:13413ea9a877	451	* @brief Start the DMA2D Transfer with interrupt enabled.
ganlikun	0:13413ea9a877	452	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	453	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	454	* @param pdata: Configure the source memory Buffer address if
ganlikun	0:13413ea9a877	455	* the Memory-to-Memory or Memory-to-Memory with pixel format
ganlikun	0:13413ea9a877	456	* conversion mode is selected, or configure
ganlikun	0:13413ea9a877	457	* the color value if Register-to-Memory mode is selected.
ganlikun	0:13413ea9a877	458	* @param DstAddress: The destination memory Buffer address.
ganlikun	0:13413ea9a877	459	* @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
ganlikun	0:13413ea9a877	460	* @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
ganlikun	0:13413ea9a877	461	* @retval HAL status
ganlikun	0:13413ea9a877	462	*/
ganlikun	0:13413ea9a877	463	HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
ganlikun	0:13413ea9a877	464	{
ganlikun	0:13413ea9a877	465	/* Check the parameters */
ganlikun	0:13413ea9a877	466	assert_param(IS_DMA2D_LINE(Height));
ganlikun	0:13413ea9a877	467	assert_param(IS_DMA2D_PIXEL(Width));
ganlikun	0:13413ea9a877	468
ganlikun	0:13413ea9a877	469	/* Process locked */
ganlikun	0:13413ea9a877	470	__HAL_LOCK(hdma2d);
ganlikun	0:13413ea9a877	471
ganlikun	0:13413ea9a877	472	/* Change DMA2D peripheral state */
ganlikun	0:13413ea9a877	473	hdma2d->State = HAL_DMA2D_STATE_BUSY;
ganlikun	0:13413ea9a877	474
ganlikun	0:13413ea9a877	475	/* Configure the source, destination address and the data size */
ganlikun	0:13413ea9a877	476	DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
ganlikun	0:13413ea9a877	477
ganlikun	0:13413ea9a877	478	/* Enable the transfer complete, transfer error and configuration error interrupts */
ganlikun	0:13413ea9a877	479	__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC\|DMA2D_IT_TE\|DMA2D_IT_CE);
ganlikun	0:13413ea9a877	480
ganlikun	0:13413ea9a877	481	/* Enable the Peripheral */
ganlikun	0:13413ea9a877	482	__HAL_DMA2D_ENABLE(hdma2d);
ganlikun	0:13413ea9a877	483
ganlikun	0:13413ea9a877	484	return HAL_OK;
ganlikun	0:13413ea9a877	485	}
ganlikun	0:13413ea9a877	486
ganlikun	0:13413ea9a877	487	/**
ganlikun	0:13413ea9a877	488	* @brief Start the multi-source DMA2D Transfer.
ganlikun	0:13413ea9a877	489	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	490	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	491	* @param SrcAddress1: The source memory Buffer address for the foreground layer.
ganlikun	0:13413ea9a877	492	* @param SrcAddress2: The source memory Buffer address for the background layer.
ganlikun	0:13413ea9a877	493	* @param DstAddress: The destination memory Buffer address.
ganlikun	0:13413ea9a877	494	* @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
ganlikun	0:13413ea9a877	495	* @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
ganlikun	0:13413ea9a877	496	* @retval HAL status
ganlikun	0:13413ea9a877	497	*/
ganlikun	0:13413ea9a877	498	HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
ganlikun	0:13413ea9a877	499	{
ganlikun	0:13413ea9a877	500	/* Check the parameters */
ganlikun	0:13413ea9a877	501	assert_param(IS_DMA2D_LINE(Height));
ganlikun	0:13413ea9a877	502	assert_param(IS_DMA2D_PIXEL(Width));
ganlikun	0:13413ea9a877	503
ganlikun	0:13413ea9a877	504	/* Process locked */
ganlikun	0:13413ea9a877	505	__HAL_LOCK(hdma2d);
ganlikun	0:13413ea9a877	506
ganlikun	0:13413ea9a877	507	/* Change DMA2D peripheral state */
ganlikun	0:13413ea9a877	508	hdma2d->State = HAL_DMA2D_STATE_BUSY;
ganlikun	0:13413ea9a877	509
ganlikun	0:13413ea9a877	510	/* Configure DMA2D Stream source2 address */
ganlikun	0:13413ea9a877	511	WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
ganlikun	0:13413ea9a877	512
ganlikun	0:13413ea9a877	513	/* Configure the source, destination address and the data size */
ganlikun	0:13413ea9a877	514	DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
ganlikun	0:13413ea9a877	515
ganlikun	0:13413ea9a877	516	/* Enable the Peripheral */
ganlikun	0:13413ea9a877	517	__HAL_DMA2D_ENABLE(hdma2d);
ganlikun	0:13413ea9a877	518
ganlikun	0:13413ea9a877	519	return HAL_OK;
ganlikun	0:13413ea9a877	520	}
ganlikun	0:13413ea9a877	521
ganlikun	0:13413ea9a877	522	/**
ganlikun	0:13413ea9a877	523	* @brief Start the multi-source DMA2D Transfer with interrupt enabled.
ganlikun	0:13413ea9a877	524	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	525	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	526	* @param SrcAddress1: The source memory Buffer address for the foreground layer.
ganlikun	0:13413ea9a877	527	* @param SrcAddress2: The source memory Buffer address for the background layer.
ganlikun	0:13413ea9a877	528	* @param DstAddress: The destination memory Buffer address.
ganlikun	0:13413ea9a877	529	* @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
ganlikun	0:13413ea9a877	530	* @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
ganlikun	0:13413ea9a877	531	* @retval HAL status
ganlikun	0:13413ea9a877	532	*/
ganlikun	0:13413ea9a877	533	HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
ganlikun	0:13413ea9a877	534	{
ganlikun	0:13413ea9a877	535	/* Check the parameters */
ganlikun	0:13413ea9a877	536	assert_param(IS_DMA2D_LINE(Height));
ganlikun	0:13413ea9a877	537	assert_param(IS_DMA2D_PIXEL(Width));
ganlikun	0:13413ea9a877	538
ganlikun	0:13413ea9a877	539	/* Process locked */
ganlikun	0:13413ea9a877	540	__HAL_LOCK(hdma2d);
ganlikun	0:13413ea9a877	541
ganlikun	0:13413ea9a877	542	/* Change DMA2D peripheral state */
ganlikun	0:13413ea9a877	543	hdma2d->State = HAL_DMA2D_STATE_BUSY;
ganlikun	0:13413ea9a877	544
ganlikun	0:13413ea9a877	545	/* Configure DMA2D Stream source2 address */
ganlikun	0:13413ea9a877	546	WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
ganlikun	0:13413ea9a877	547
ganlikun	0:13413ea9a877	548	/* Configure the source, destination address and the data size */
ganlikun	0:13413ea9a877	549	DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
ganlikun	0:13413ea9a877	550
ganlikun	0:13413ea9a877	551	/* Enable the transfer complete, transfer error and configuration error interrupts */
ganlikun	0:13413ea9a877	552	__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC\|DMA2D_IT_TE\|DMA2D_IT_CE);
ganlikun	0:13413ea9a877	553
ganlikun	0:13413ea9a877	554	/* Enable the Peripheral */
ganlikun	0:13413ea9a877	555	__HAL_DMA2D_ENABLE(hdma2d);
ganlikun	0:13413ea9a877	556
ganlikun	0:13413ea9a877	557	return HAL_OK;
ganlikun	0:13413ea9a877	558	}
ganlikun	0:13413ea9a877	559
ganlikun	0:13413ea9a877	560	/**
ganlikun	0:13413ea9a877	561	* @brief Abort the DMA2D Transfer.
ganlikun	0:13413ea9a877	562	* @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	563	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	564	* @retval HAL status
ganlikun	0:13413ea9a877	565	*/
ganlikun	0:13413ea9a877	566	HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
ganlikun	0:13413ea9a877	567	{
ganlikun	0:13413ea9a877	568	uint32_t tickstart = 0U;
ganlikun	0:13413ea9a877	569
ganlikun	0:13413ea9a877	570	/* Abort the DMA2D transfer */
ganlikun	0:13413ea9a877	571	/* START bit is reset to make sure not to set it again, in the event the HW clears it
ganlikun	0:13413ea9a877	572	between the register read and the register write by the CPU (writing 0 has no
ganlikun	0:13413ea9a877	573	effect on START bitvalue) */
ganlikun	0:13413ea9a877	574	MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT\|DMA2D_CR_START, DMA2D_CR_ABORT);
ganlikun	0:13413ea9a877	575
ganlikun	0:13413ea9a877	576	/* Get tick */
ganlikun	0:13413ea9a877	577	tickstart = HAL_GetTick();
ganlikun	0:13413ea9a877	578
ganlikun	0:13413ea9a877	579	/* Check if the DMA2D is effectively disabled */
ganlikun	0:13413ea9a877	580	while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
ganlikun	0:13413ea9a877	581	{
ganlikun	0:13413ea9a877	582	if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
ganlikun	0:13413ea9a877	583	{
ganlikun	0:13413ea9a877	584	/* Update error code */
ganlikun	0:13413ea9a877	585	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TIMEOUT;
ganlikun	0:13413ea9a877	586
ganlikun	0:13413ea9a877	587	/* Change the DMA2D state */
ganlikun	0:13413ea9a877	588	hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
ganlikun	0:13413ea9a877	589
ganlikun	0:13413ea9a877	590	/* Process Unlocked */
ganlikun	0:13413ea9a877	591	__HAL_UNLOCK(hdma2d);
ganlikun	0:13413ea9a877	592
ganlikun	0:13413ea9a877	593	return HAL_TIMEOUT;
ganlikun	0:13413ea9a877	594	}
ganlikun	0:13413ea9a877	595	}
ganlikun	0:13413ea9a877	596
ganlikun	0:13413ea9a877	597	/* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
ganlikun	0:13413ea9a877	598	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC\|DMA2D_IT_TE\|DMA2D_IT_CE);
ganlikun	0:13413ea9a877	599
ganlikun	0:13413ea9a877	600	/* Change the DMA2D state*/
ganlikun	0:13413ea9a877	601	hdma2d->State = HAL_DMA2D_STATE_READY;
ganlikun	0:13413ea9a877	602
ganlikun	0:13413ea9a877	603	/* Process Unlocked */
ganlikun	0:13413ea9a877	604	__HAL_UNLOCK(hdma2d);
ganlikun	0:13413ea9a877	605
ganlikun	0:13413ea9a877	606	return HAL_OK;
ganlikun	0:13413ea9a877	607	}
ganlikun	0:13413ea9a877	608
ganlikun	0:13413ea9a877	609	/**
ganlikun	0:13413ea9a877	610	* @brief Suspend the DMA2D Transfer.
ganlikun	0:13413ea9a877	611	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	612	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	613	* @retval HAL status
ganlikun	0:13413ea9a877	614	*/
ganlikun	0:13413ea9a877	615	HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
ganlikun	0:13413ea9a877	616	{
ganlikun	0:13413ea9a877	617	uint32_t tickstart = 0U;
ganlikun	0:13413ea9a877	618
ganlikun	0:13413ea9a877	619	/* Suspend the DMA2D transfer */
ganlikun	0:13413ea9a877	620	/* START bit is reset to make sure not to set it again, in the event the HW clears it
ganlikun	0:13413ea9a877	621	between the register read and the register write by the CPU (writing 0 has no
ganlikun	0:13413ea9a877	622	effect on START bitvalue) */
ganlikun	0:13413ea9a877	623	MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP\|DMA2D_CR_START, DMA2D_CR_SUSP);
ganlikun	0:13413ea9a877	624
ganlikun	0:13413ea9a877	625	/* Get tick */
ganlikun	0:13413ea9a877	626	tickstart = HAL_GetTick();
ganlikun	0:13413ea9a877	627
ganlikun	0:13413ea9a877	628	/* Check if the DMA2D is effectively suspended */
ganlikun	0:13413ea9a877	629	while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
ganlikun	0:13413ea9a877	630	&& ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))
ganlikun	0:13413ea9a877	631	{
ganlikun	0:13413ea9a877	632	if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
ganlikun	0:13413ea9a877	633	{
ganlikun	0:13413ea9a877	634	/* Update error code */
ganlikun	0:13413ea9a877	635	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TIMEOUT;
ganlikun	0:13413ea9a877	636
ganlikun	0:13413ea9a877	637	/* Change the DMA2D state */
ganlikun	0:13413ea9a877	638	hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
ganlikun	0:13413ea9a877	639
ganlikun	0:13413ea9a877	640	return HAL_TIMEOUT;
ganlikun	0:13413ea9a877	641	}
ganlikun	0:13413ea9a877	642	}
ganlikun	0:13413ea9a877	643
ganlikun	0:13413ea9a877	644	/* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
ganlikun	0:13413ea9a877	645	if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
ganlikun	0:13413ea9a877	646	{
ganlikun	0:13413ea9a877	647	hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
ganlikun	0:13413ea9a877	648	}
ganlikun	0:13413ea9a877	649	else
ganlikun	0:13413ea9a877	650	{
ganlikun	0:13413ea9a877	651	/* Make sure SUSP bit is cleared since it is meaningless
ganlikun	0:13413ea9a877	652	when no tranfer is on-going */
ganlikun	0:13413ea9a877	653	CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
ganlikun	0:13413ea9a877	654	}
ganlikun	0:13413ea9a877	655
ganlikun	0:13413ea9a877	656	return HAL_OK;
ganlikun	0:13413ea9a877	657	}
ganlikun	0:13413ea9a877	658
ganlikun	0:13413ea9a877	659	/**
ganlikun	0:13413ea9a877	660	* @brief Resume the DMA2D Transfer.
ganlikun	0:13413ea9a877	661	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	662	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	663	* @retval HAL status
ganlikun	0:13413ea9a877	664	*/
ganlikun	0:13413ea9a877	665	HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
ganlikun	0:13413ea9a877	666	{
ganlikun	0:13413ea9a877	667	/* Check the SUSP and START bits */
ganlikun	0:13413ea9a877	668	if((hdma2d->Instance->CR & (DMA2D_CR_SUSP \| DMA2D_CR_START)) == (DMA2D_CR_SUSP \| DMA2D_CR_START))
ganlikun	0:13413ea9a877	669	{
ganlikun	0:13413ea9a877	670	/* Ongoing transfer is suspended: change the DMA2D state before resuming */
ganlikun	0:13413ea9a877	671	hdma2d->State = HAL_DMA2D_STATE_BUSY;
ganlikun	0:13413ea9a877	672	}
ganlikun	0:13413ea9a877	673
ganlikun	0:13413ea9a877	674	/* Resume the DMA2D transfer */
ganlikun	0:13413ea9a877	675	/* START bit is reset to make sure not to set it again, in the event the HW clears it
ganlikun	0:13413ea9a877	676	between the register read and the register write by the CPU (writing 0 has no
ganlikun	0:13413ea9a877	677	effect on START bitvalue) */
ganlikun	0:13413ea9a877	678	CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP\|DMA2D_CR_START));
ganlikun	0:13413ea9a877	679
ganlikun	0:13413ea9a877	680	return HAL_OK;
ganlikun	0:13413ea9a877	681	}
ganlikun	0:13413ea9a877	682
ganlikun	0:13413ea9a877	683	/**
ganlikun	0:13413ea9a877	684	* @brief Enable the DMA2D CLUT Transfer.
ganlikun	0:13413ea9a877	685	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	686	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	687	* @param LayerIdx: DMA2D Layer index.
ganlikun	0:13413ea9a877	688	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	689	* 0(background) / 1(foreground)
ganlikun	0:13413ea9a877	690	* @retval HAL status
ganlikun	0:13413ea9a877	691	*/
ganlikun	0:13413ea9a877	692	HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
ganlikun	0:13413ea9a877	693	{
ganlikun	0:13413ea9a877	694	/* Check the parameters */
ganlikun	0:13413ea9a877	695	assert_param(IS_DMA2D_LAYER(LayerIdx));
ganlikun	0:13413ea9a877	696
ganlikun	0:13413ea9a877	697	/* Process locked */
ganlikun	0:13413ea9a877	698	__HAL_LOCK(hdma2d);
ganlikun	0:13413ea9a877	699
ganlikun	0:13413ea9a877	700	/* Change DMA2D peripheral state */
ganlikun	0:13413ea9a877	701	hdma2d->State = HAL_DMA2D_STATE_BUSY;
ganlikun	0:13413ea9a877	702
ganlikun	0:13413ea9a877	703	if(LayerIdx == 0U)
ganlikun	0:13413ea9a877	704	{
ganlikun	0:13413ea9a877	705	/* Enable the background CLUT loading */
ganlikun	0:13413ea9a877	706	SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
ganlikun	0:13413ea9a877	707	}
ganlikun	0:13413ea9a877	708	else
ganlikun	0:13413ea9a877	709	{
ganlikun	0:13413ea9a877	710	/* Enable the foreground CLUT loading */
ganlikun	0:13413ea9a877	711	SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
ganlikun	0:13413ea9a877	712	}
ganlikun	0:13413ea9a877	713
ganlikun	0:13413ea9a877	714	return HAL_OK;
ganlikun	0:13413ea9a877	715	}
ganlikun	0:13413ea9a877	716
ganlikun	0:13413ea9a877	717	/**
ganlikun	0:13413ea9a877	718	* @brief Start DMA2D CLUT Loading.
ganlikun	0:13413ea9a877	719	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	720	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	721	* @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
ganlikun	0:13413ea9a877	722	* the configuration information for the color look up table.
ganlikun	0:13413ea9a877	723	* @param LayerIdx: DMA2D Layer index.
ganlikun	0:13413ea9a877	724	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	725	* 0(background) / 1(foreground)
ganlikun	0:13413ea9a877	726	* @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
ganlikun	0:13413ea9a877	727	* @retval HAL status
ganlikun	0:13413ea9a877	728	*/
ganlikun	0:13413ea9a877	729	HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
ganlikun	0:13413ea9a877	730	{
ganlikun	0:13413ea9a877	731	/* Check the parameters */
ganlikun	0:13413ea9a877	732	assert_param(IS_DMA2D_LAYER(LayerIdx));
ganlikun	0:13413ea9a877	733	assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
ganlikun	0:13413ea9a877	734	assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
ganlikun	0:13413ea9a877	735
ganlikun	0:13413ea9a877	736	/* Process locked */
ganlikun	0:13413ea9a877	737	__HAL_LOCK(hdma2d);
ganlikun	0:13413ea9a877	738
ganlikun	0:13413ea9a877	739	/* Change DMA2D peripheral state */
ganlikun	0:13413ea9a877	740	hdma2d->State = HAL_DMA2D_STATE_BUSY;
ganlikun	0:13413ea9a877	741
ganlikun	0:13413ea9a877	742	/* Configure the CLUT of the background DMA2D layer */
ganlikun	0:13413ea9a877	743	if(LayerIdx == 0U)
ganlikun	0:13413ea9a877	744	{
ganlikun	0:13413ea9a877	745	/* Write background CLUT memory address */
ganlikun	0:13413ea9a877	746	WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
ganlikun	0:13413ea9a877	747
ganlikun	0:13413ea9a877	748	/* Write background CLUT size and CLUT color mode */
ganlikun	0:13413ea9a877	749	MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS \| DMA2D_BGPFCCR_CCM),
ganlikun	0:13413ea9a877	750	((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) \| (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
ganlikun	0:13413ea9a877	751
ganlikun	0:13413ea9a877	752	/* Enable the CLUT loading for the background */
ganlikun	0:13413ea9a877	753	SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
ganlikun	0:13413ea9a877	754	}
ganlikun	0:13413ea9a877	755	/* Configure the CLUT of the foreground DMA2D layer */
ganlikun	0:13413ea9a877	756	else
ganlikun	0:13413ea9a877	757	{
ganlikun	0:13413ea9a877	758	/* Write foreground CLUT memory address */
ganlikun	0:13413ea9a877	759	WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
ganlikun	0:13413ea9a877	760
ganlikun	0:13413ea9a877	761	/* Write foreground CLUT size and CLUT color mode */
ganlikun	0:13413ea9a877	762	MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS \| DMA2D_FGPFCCR_CCM),
ganlikun	0:13413ea9a877	763	((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) \| (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
ganlikun	0:13413ea9a877	764
ganlikun	0:13413ea9a877	765	/* Enable the CLUT loading for the foreground */
ganlikun	0:13413ea9a877	766	SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
ganlikun	0:13413ea9a877	767	}
ganlikun	0:13413ea9a877	768
ganlikun	0:13413ea9a877	769	return HAL_OK;
ganlikun	0:13413ea9a877	770	}
ganlikun	0:13413ea9a877	771
ganlikun	0:13413ea9a877	772	/**
ganlikun	0:13413ea9a877	773	* @brief Start DMA2D CLUT Loading with interrupt enabled.
ganlikun	0:13413ea9a877	774	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	775	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	776	* @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
ganlikun	0:13413ea9a877	777	* the configuration information for the color look up table.
ganlikun	0:13413ea9a877	778	* @param LayerIdx: DMA2D Layer index.
ganlikun	0:13413ea9a877	779	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	780	* 0(background) / 1(foreground)
ganlikun	0:13413ea9a877	781	* @retval HAL status
ganlikun	0:13413ea9a877	782	*/
ganlikun	0:13413ea9a877	783	HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
ganlikun	0:13413ea9a877	784	{
ganlikun	0:13413ea9a877	785	/* Check the parameters */
ganlikun	0:13413ea9a877	786	assert_param(IS_DMA2D_LAYER(LayerIdx));
ganlikun	0:13413ea9a877	787	assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
ganlikun	0:13413ea9a877	788	assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
ganlikun	0:13413ea9a877	789
ganlikun	0:13413ea9a877	790	/* Process locked */
ganlikun	0:13413ea9a877	791	__HAL_LOCK(hdma2d);
ganlikun	0:13413ea9a877	792
ganlikun	0:13413ea9a877	793	/* Change DMA2D peripheral state */
ganlikun	0:13413ea9a877	794	hdma2d->State = HAL_DMA2D_STATE_BUSY;
ganlikun	0:13413ea9a877	795
ganlikun	0:13413ea9a877	796	/* Configure the CLUT of the background DMA2D layer */
ganlikun	0:13413ea9a877	797	if(LayerIdx == 0U)
ganlikun	0:13413ea9a877	798	{
ganlikun	0:13413ea9a877	799	/* Write background CLUT memory address */
ganlikun	0:13413ea9a877	800	WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
ganlikun	0:13413ea9a877	801
ganlikun	0:13413ea9a877	802	/* Write background CLUT size and CLUT color mode */
ganlikun	0:13413ea9a877	803	MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS \| DMA2D_BGPFCCR_CCM),
ganlikun	0:13413ea9a877	804	((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) \| (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
ganlikun	0:13413ea9a877	805
ganlikun	0:13413ea9a877	806	/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
ganlikun	0:13413ea9a877	807	__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC \| DMA2D_IT_TE \| DMA2D_IT_CE \|DMA2D_IT_CAE);
ganlikun	0:13413ea9a877	808
ganlikun	0:13413ea9a877	809	/* Enable the CLUT loading for the background */
ganlikun	0:13413ea9a877	810	SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
ganlikun	0:13413ea9a877	811	}
ganlikun	0:13413ea9a877	812	/* Configure the CLUT of the foreground DMA2D layer */
ganlikun	0:13413ea9a877	813	else
ganlikun	0:13413ea9a877	814	{
ganlikun	0:13413ea9a877	815	/* Write foreground CLUT memory address */
ganlikun	0:13413ea9a877	816	WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
ganlikun	0:13413ea9a877	817
ganlikun	0:13413ea9a877	818	/* Write foreground CLUT size and CLUT color mode */
ganlikun	0:13413ea9a877	819	MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS \| DMA2D_FGPFCCR_CCM),
ganlikun	0:13413ea9a877	820	((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) \| (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
ganlikun	0:13413ea9a877	821
ganlikun	0:13413ea9a877	822	/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
ganlikun	0:13413ea9a877	823	__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC \| DMA2D_IT_TE \| DMA2D_IT_CE \|DMA2D_IT_CAE);
ganlikun	0:13413ea9a877	824
ganlikun	0:13413ea9a877	825	/* Enable the CLUT loading for the foreground */
ganlikun	0:13413ea9a877	826	SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
ganlikun	0:13413ea9a877	827	}
ganlikun	0:13413ea9a877	828
ganlikun	0:13413ea9a877	829	return HAL_OK;
ganlikun	0:13413ea9a877	830	}
ganlikun	0:13413ea9a877	831
ganlikun	0:13413ea9a877	832	/**
ganlikun	0:13413ea9a877	833	* @brief Abort the DMA2D CLUT loading.
ganlikun	0:13413ea9a877	834	* @param hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	835	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	836	* @param LayerIdx: DMA2D Layer index.
ganlikun	0:13413ea9a877	837	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	838	* 0(background) / 1(foreground)
ganlikun	0:13413ea9a877	839	* @retval HAL status
ganlikun	0:13413ea9a877	840	*/
ganlikun	0:13413ea9a877	841	HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
ganlikun	0:13413ea9a877	842	{
ganlikun	0:13413ea9a877	843	uint32_t tickstart = 0U;
ganlikun	0:13413ea9a877	844	__IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
ganlikun	0:13413ea9a877	845
ganlikun	0:13413ea9a877	846	/* Abort the CLUT loading */
ganlikun	0:13413ea9a877	847	SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
ganlikun	0:13413ea9a877	848
ganlikun	0:13413ea9a877	849	/* If foreground CLUT loading is considered, update local variables */
ganlikun	0:13413ea9a877	850	if(LayerIdx == 1)
ganlikun	0:13413ea9a877	851	{
ganlikun	0:13413ea9a877	852	reg = &(hdma2d->Instance->FGPFCCR);
ganlikun	0:13413ea9a877	853	}
ganlikun	0:13413ea9a877	854
ganlikun	0:13413ea9a877	855	/* Get tick */
ganlikun	0:13413ea9a877	856	tickstart = HAL_GetTick();
ganlikun	0:13413ea9a877	857
ganlikun	0:13413ea9a877	858	/* Check if the CLUT loading is aborted */
ganlikun	0:13413ea9a877	859	while((*reg & DMA2D_BGPFCCR_START) != RESET)
ganlikun	0:13413ea9a877	860	{
ganlikun	0:13413ea9a877	861	if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
ganlikun	0:13413ea9a877	862	{
ganlikun	0:13413ea9a877	863	/* Update error code */
ganlikun	0:13413ea9a877	864	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TIMEOUT;
ganlikun	0:13413ea9a877	865
ganlikun	0:13413ea9a877	866	/* Change the DMA2D state */
ganlikun	0:13413ea9a877	867	hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
ganlikun	0:13413ea9a877	868
ganlikun	0:13413ea9a877	869	/* Process Unlocked */
ganlikun	0:13413ea9a877	870	__HAL_UNLOCK(hdma2d);
ganlikun	0:13413ea9a877	871
ganlikun	0:13413ea9a877	872	return HAL_TIMEOUT;
ganlikun	0:13413ea9a877	873	}
ganlikun	0:13413ea9a877	874	}
ganlikun	0:13413ea9a877	875
ganlikun	0:13413ea9a877	876	/* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
ganlikun	0:13413ea9a877	877	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC \| DMA2D_IT_TE \| DMA2D_IT_CE \|DMA2D_IT_CAE);
ganlikun	0:13413ea9a877	878
ganlikun	0:13413ea9a877	879	/* Change the DMA2D state*/
ganlikun	0:13413ea9a877	880	hdma2d->State = HAL_DMA2D_STATE_READY;
ganlikun	0:13413ea9a877	881
ganlikun	0:13413ea9a877	882	/* Process Unlocked */
ganlikun	0:13413ea9a877	883	__HAL_UNLOCK(hdma2d);
ganlikun	0:13413ea9a877	884
ganlikun	0:13413ea9a877	885	return HAL_OK;
ganlikun	0:13413ea9a877	886	}
ganlikun	0:13413ea9a877	887
ganlikun	0:13413ea9a877	888	/**
ganlikun	0:13413ea9a877	889	* @brief Suspend the DMA2D CLUT loading.
ganlikun	0:13413ea9a877	890	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	891	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	892	* @param LayerIdx: DMA2D Layer index.
ganlikun	0:13413ea9a877	893	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	894	* 0(background) / 1(foreground)
ganlikun	0:13413ea9a877	895	* @retval HAL status
ganlikun	0:13413ea9a877	896	*/
ganlikun	0:13413ea9a877	897	HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
ganlikun	0:13413ea9a877	898	{
ganlikun	0:13413ea9a877	899	uint32_t tickstart = 0U;
ganlikun	0:13413ea9a877	900	__IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
ganlikun	0:13413ea9a877	901
ganlikun	0:13413ea9a877	902	/* Suspend the CLUT loading */
ganlikun	0:13413ea9a877	903	SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
ganlikun	0:13413ea9a877	904
ganlikun	0:13413ea9a877	905	/* If foreground CLUT loading is considered, update local variables */
ganlikun	0:13413ea9a877	906	if(LayerIdx == 1U)
ganlikun	0:13413ea9a877	907	{
ganlikun	0:13413ea9a877	908	reg = &(hdma2d->Instance->FGPFCCR);
ganlikun	0:13413ea9a877	909	}
ganlikun	0:13413ea9a877	910
ganlikun	0:13413ea9a877	911	/* Get tick */
ganlikun	0:13413ea9a877	912	tickstart = HAL_GetTick();
ganlikun	0:13413ea9a877	913
ganlikun	0:13413ea9a877	914	/* Check if the CLUT loading is suspended */
ganlikun	0:13413ea9a877	915	while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
ganlikun	0:13413ea9a877	916	&& ((*reg & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
ganlikun	0:13413ea9a877	917	{
ganlikun	0:13413ea9a877	918	if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
ganlikun	0:13413ea9a877	919	{
ganlikun	0:13413ea9a877	920	/* Update error code */
ganlikun	0:13413ea9a877	921	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TIMEOUT;
ganlikun	0:13413ea9a877	922
ganlikun	0:13413ea9a877	923	/* Change the DMA2D state */
ganlikun	0:13413ea9a877	924	hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
ganlikun	0:13413ea9a877	925
ganlikun	0:13413ea9a877	926	return HAL_TIMEOUT;
ganlikun	0:13413ea9a877	927	}
ganlikun	0:13413ea9a877	928	}
ganlikun	0:13413ea9a877	929
ganlikun	0:13413ea9a877	930	/* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
ganlikun	0:13413ea9a877	931	if ((*reg & DMA2D_BGPFCCR_START) != RESET)
ganlikun	0:13413ea9a877	932	{
ganlikun	0:13413ea9a877	933	hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
ganlikun	0:13413ea9a877	934	}
ganlikun	0:13413ea9a877	935	else
ganlikun	0:13413ea9a877	936	{
ganlikun	0:13413ea9a877	937	/* Make sure SUSP bit is cleared since it is meaningless
ganlikun	0:13413ea9a877	938	when no tranfer is on-going */
ganlikun	0:13413ea9a877	939	CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
ganlikun	0:13413ea9a877	940	}
ganlikun	0:13413ea9a877	941
ganlikun	0:13413ea9a877	942	return HAL_OK;
ganlikun	0:13413ea9a877	943	}
ganlikun	0:13413ea9a877	944
ganlikun	0:13413ea9a877	945	/**
ganlikun	0:13413ea9a877	946	* @brief Resume the DMA2D CLUT loading.
ganlikun	0:13413ea9a877	947	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	948	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	949	* @param LayerIdx: DMA2D Layer index.
ganlikun	0:13413ea9a877	950	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	951	* 0(background) / 1(foreground)
ganlikun	0:13413ea9a877	952	* @retval HAL status
ganlikun	0:13413ea9a877	953	*/
ganlikun	0:13413ea9a877	954	HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
ganlikun	0:13413ea9a877	955	{
ganlikun	0:13413ea9a877	956	/* Check the SUSP and START bits for background or foreground CLUT loading */
ganlikun	0:13413ea9a877	957	if(LayerIdx == 0U)
ganlikun	0:13413ea9a877	958	{
ganlikun	0:13413ea9a877	959	/* Background CLUT loading suspension check */
ganlikun	0:13413ea9a877	960	if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
ganlikun	0:13413ea9a877	961	&& ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
ganlikun	0:13413ea9a877	962	{
ganlikun	0:13413ea9a877	963	/* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
ganlikun	0:13413ea9a877	964	hdma2d->State = HAL_DMA2D_STATE_BUSY;
ganlikun	0:13413ea9a877	965	}
ganlikun	0:13413ea9a877	966	}
ganlikun	0:13413ea9a877	967	else
ganlikun	0:13413ea9a877	968	{
ganlikun	0:13413ea9a877	969	/* Foreground CLUT loading suspension check */
ganlikun	0:13413ea9a877	970	if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
ganlikun	0:13413ea9a877	971	&& ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START))
ganlikun	0:13413ea9a877	972	{
ganlikun	0:13413ea9a877	973	/* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
ganlikun	0:13413ea9a877	974	hdma2d->State = HAL_DMA2D_STATE_BUSY;
ganlikun	0:13413ea9a877	975	}
ganlikun	0:13413ea9a877	976	}
ganlikun	0:13413ea9a877	977
ganlikun	0:13413ea9a877	978	/* Resume the CLUT loading */
ganlikun	0:13413ea9a877	979	CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
ganlikun	0:13413ea9a877	980
ganlikun	0:13413ea9a877	981	return HAL_OK;
ganlikun	0:13413ea9a877	982	}
ganlikun	0:13413ea9a877	983
ganlikun	0:13413ea9a877	984	/**
ganlikun	0:13413ea9a877	985	* @brief Polling for transfer complete or CLUT loading.
ganlikun	0:13413ea9a877	986	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	987	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	988	* @param Timeout: Timeout duration
ganlikun	0:13413ea9a877	989	* @retval HAL status
ganlikun	0:13413ea9a877	990	*/
ganlikun	0:13413ea9a877	991	HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
ganlikun	0:13413ea9a877	992	{
ganlikun	0:13413ea9a877	993	uint32_t tickstart = 0U;
ganlikun	0:13413ea9a877	994	__IO uint32_t isrflags = 0x0U;
ganlikun	0:13413ea9a877	995
ganlikun	0:13413ea9a877	996	/* Polling for DMA2D transfer */
ganlikun	0:13413ea9a877	997	if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
ganlikun	0:13413ea9a877	998	{
ganlikun	0:13413ea9a877	999	/* Get tick */
ganlikun	0:13413ea9a877	1000	tickstart = HAL_GetTick();
ganlikun	0:13413ea9a877	1001
ganlikun	0:13413ea9a877	1002	while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
ganlikun	0:13413ea9a877	1003	{
ganlikun	0:13413ea9a877	1004	isrflags = READ_REG(hdma2d->Instance->ISR);
ganlikun	0:13413ea9a877	1005	if ((isrflags & (DMA2D_FLAG_CE\|DMA2D_FLAG_TE)) != RESET)
ganlikun	0:13413ea9a877	1006	{
ganlikun	0:13413ea9a877	1007	if ((isrflags & DMA2D_FLAG_CE) != RESET)
ganlikun	0:13413ea9a877	1008	{
ganlikun	0:13413ea9a877	1009	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_CE;
ganlikun	0:13413ea9a877	1010	}
ganlikun	0:13413ea9a877	1011	if ((isrflags & DMA2D_FLAG_TE) != RESET)
ganlikun	0:13413ea9a877	1012	{
ganlikun	0:13413ea9a877	1013	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TE;
ganlikun	0:13413ea9a877	1014	}
ganlikun	0:13413ea9a877	1015	/* Clear the transfer and configuration error flags */
ganlikun	0:13413ea9a877	1016	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE \| DMA2D_FLAG_TE);
ganlikun	0:13413ea9a877	1017
ganlikun	0:13413ea9a877	1018	/* Change DMA2D state */
ganlikun	0:13413ea9a877	1019	hdma2d->State = HAL_DMA2D_STATE_ERROR;
ganlikun	0:13413ea9a877	1020
ganlikun	0:13413ea9a877	1021	/* Process unlocked */
ganlikun	0:13413ea9a877	1022	__HAL_UNLOCK(hdma2d);
ganlikun	0:13413ea9a877	1023
ganlikun	0:13413ea9a877	1024	return HAL_ERROR;
ganlikun	0:13413ea9a877	1025	}
ganlikun	0:13413ea9a877	1026	/* Check for the Timeout */
ganlikun	0:13413ea9a877	1027	if(Timeout != HAL_MAX_DELAY)
ganlikun	0:13413ea9a877	1028	{
ganlikun	0:13413ea9a877	1029	if((Timeout == 0U)\|\|((HAL_GetTick() - tickstart ) > Timeout))
ganlikun	0:13413ea9a877	1030	{
ganlikun	0:13413ea9a877	1031	/* Update error code */
ganlikun	0:13413ea9a877	1032	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TIMEOUT;
ganlikun	0:13413ea9a877	1033
ganlikun	0:13413ea9a877	1034	/* Change the DMA2D state */
ganlikun	0:13413ea9a877	1035	hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
ganlikun	0:13413ea9a877	1036
ganlikun	0:13413ea9a877	1037	/* Process unlocked */
ganlikun	0:13413ea9a877	1038	__HAL_UNLOCK(hdma2d);
ganlikun	0:13413ea9a877	1039
ganlikun	0:13413ea9a877	1040	return HAL_TIMEOUT;
ganlikun	0:13413ea9a877	1041	}
ganlikun	0:13413ea9a877	1042	}
ganlikun	0:13413ea9a877	1043	}
ganlikun	0:13413ea9a877	1044	}
ganlikun	0:13413ea9a877	1045	/* Polling for CLUT loading (foreground or background) */
ganlikun	0:13413ea9a877	1046	if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET) \|\|
ganlikun	0:13413ea9a877	1047	((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET))
ganlikun	0:13413ea9a877	1048	{
ganlikun	0:13413ea9a877	1049	/* Get tick */
ganlikun	0:13413ea9a877	1050	tickstart = HAL_GetTick();
ganlikun	0:13413ea9a877	1051
ganlikun	0:13413ea9a877	1052	while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
ganlikun	0:13413ea9a877	1053	{
ganlikun	0:13413ea9a877	1054	isrflags = READ_REG(hdma2d->Instance->ISR);
ganlikun	0:13413ea9a877	1055	if ((isrflags & (DMA2D_FLAG_CAE\|DMA2D_FLAG_CE\|DMA2D_FLAG_TE)) != RESET)
ganlikun	0:13413ea9a877	1056	{
ganlikun	0:13413ea9a877	1057	if ((isrflags & DMA2D_FLAG_CAE) != RESET)
ganlikun	0:13413ea9a877	1058	{
ganlikun	0:13413ea9a877	1059	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_CAE;
ganlikun	0:13413ea9a877	1060	}
ganlikun	0:13413ea9a877	1061	if ((isrflags & DMA2D_FLAG_CE) != RESET)
ganlikun	0:13413ea9a877	1062	{
ganlikun	0:13413ea9a877	1063	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_CE;
ganlikun	0:13413ea9a877	1064	}
ganlikun	0:13413ea9a877	1065	if ((isrflags & DMA2D_FLAG_TE) != RESET)
ganlikun	0:13413ea9a877	1066	{
ganlikun	0:13413ea9a877	1067	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TE;
ganlikun	0:13413ea9a877	1068	}
ganlikun	0:13413ea9a877	1069	/* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
ganlikun	0:13413ea9a877	1070	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE \| DMA2D_FLAG_CE \| DMA2D_FLAG_TE);
ganlikun	0:13413ea9a877	1071
ganlikun	0:13413ea9a877	1072	/* Change DMA2D state */
ganlikun	0:13413ea9a877	1073	hdma2d->State= HAL_DMA2D_STATE_ERROR;
ganlikun	0:13413ea9a877	1074
ganlikun	0:13413ea9a877	1075	/* Process unlocked */
ganlikun	0:13413ea9a877	1076	__HAL_UNLOCK(hdma2d);
ganlikun	0:13413ea9a877	1077
ganlikun	0:13413ea9a877	1078	return HAL_ERROR;
ganlikun	0:13413ea9a877	1079	}
ganlikun	0:13413ea9a877	1080	/* Check for the Timeout */
ganlikun	0:13413ea9a877	1081	if(Timeout != HAL_MAX_DELAY)
ganlikun	0:13413ea9a877	1082	{
ganlikun	0:13413ea9a877	1083	if((Timeout == 0U)\|\|((HAL_GetTick() - tickstart ) > Timeout))
ganlikun	0:13413ea9a877	1084	{
ganlikun	0:13413ea9a877	1085	/* Update error code */
ganlikun	0:13413ea9a877	1086	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TIMEOUT;
ganlikun	0:13413ea9a877	1087
ganlikun	0:13413ea9a877	1088	/* Change the DMA2D state */
ganlikun	0:13413ea9a877	1089	hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
ganlikun	0:13413ea9a877	1090
ganlikun	0:13413ea9a877	1091	/* Process unlocked */
ganlikun	0:13413ea9a877	1092	__HAL_UNLOCK(hdma2d);
ganlikun	0:13413ea9a877	1093
ganlikun	0:13413ea9a877	1094	return HAL_TIMEOUT;
ganlikun	0:13413ea9a877	1095	}
ganlikun	0:13413ea9a877	1096	}
ganlikun	0:13413ea9a877	1097	}
ganlikun	0:13413ea9a877	1098	}
ganlikun	0:13413ea9a877	1099
ganlikun	0:13413ea9a877	1100	/* Clear the transfer complete and CLUT loading flags */
ganlikun	0:13413ea9a877	1101	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC\|DMA2D_FLAG_CTC);
ganlikun	0:13413ea9a877	1102
ganlikun	0:13413ea9a877	1103	/* Change DMA2D state */
ganlikun	0:13413ea9a877	1104	hdma2d->State = HAL_DMA2D_STATE_READY;
ganlikun	0:13413ea9a877	1105
ganlikun	0:13413ea9a877	1106	/* Process unlocked */
ganlikun	0:13413ea9a877	1107	__HAL_UNLOCK(hdma2d);
ganlikun	0:13413ea9a877	1108
ganlikun	0:13413ea9a877	1109	return HAL_OK;
ganlikun	0:13413ea9a877	1110	}
ganlikun	0:13413ea9a877	1111	/**
ganlikun	0:13413ea9a877	1112	* @brief Handle DMA2D interrupt request.
ganlikun	0:13413ea9a877	1113	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	1114	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	1115	* @retval HAL status
ganlikun	0:13413ea9a877	1116	*/
ganlikun	0:13413ea9a877	1117	void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
ganlikun	0:13413ea9a877	1118	{
ganlikun	0:13413ea9a877	1119	uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
ganlikun	0:13413ea9a877	1120	uint32_t crflags = READ_REG(hdma2d->Instance->CR);
ganlikun	0:13413ea9a877	1121
ganlikun	0:13413ea9a877	1122	/* Transfer Error Interrupt management ***************************************/
ganlikun	0:13413ea9a877	1123	if ((isrflags & DMA2D_FLAG_TE) != RESET)
ganlikun	0:13413ea9a877	1124	{
ganlikun	0:13413ea9a877	1125	if ((crflags & DMA2D_IT_TE) != RESET)
ganlikun	0:13413ea9a877	1126	{
ganlikun	0:13413ea9a877	1127	/* Disable the transfer Error interrupt */
ganlikun	0:13413ea9a877	1128	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
ganlikun	0:13413ea9a877	1129
ganlikun	0:13413ea9a877	1130	/* Update error code */
ganlikun	0:13413ea9a877	1131	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_TE;
ganlikun	0:13413ea9a877	1132
ganlikun	0:13413ea9a877	1133	/* Clear the transfer error flag */
ganlikun	0:13413ea9a877	1134	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
ganlikun	0:13413ea9a877	1135
ganlikun	0:13413ea9a877	1136	/* Change DMA2D state */
ganlikun	0:13413ea9a877	1137	hdma2d->State = HAL_DMA2D_STATE_ERROR;
ganlikun	0:13413ea9a877	1138
ganlikun	0:13413ea9a877	1139	/* Process Unlocked */
ganlikun	0:13413ea9a877	1140	__HAL_UNLOCK(hdma2d);
ganlikun	0:13413ea9a877	1141
ganlikun	0:13413ea9a877	1142	if(hdma2d->XferErrorCallback != NULL)
ganlikun	0:13413ea9a877	1143	{
ganlikun	0:13413ea9a877	1144	/* Transfer error Callback */
ganlikun	0:13413ea9a877	1145	hdma2d->XferErrorCallback(hdma2d);
ganlikun	0:13413ea9a877	1146	}
ganlikun	0:13413ea9a877	1147	}
ganlikun	0:13413ea9a877	1148	}
ganlikun	0:13413ea9a877	1149	/* Configuration Error Interrupt management **********************************/
ganlikun	0:13413ea9a877	1150	if ((isrflags & DMA2D_FLAG_CE) != RESET)
ganlikun	0:13413ea9a877	1151	{
ganlikun	0:13413ea9a877	1152	if ((crflags & DMA2D_IT_CE) != RESET)
ganlikun	0:13413ea9a877	1153	{
ganlikun	0:13413ea9a877	1154	/* Disable the Configuration Error interrupt */
ganlikun	0:13413ea9a877	1155	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
ganlikun	0:13413ea9a877	1156
ganlikun	0:13413ea9a877	1157	/* Clear the Configuration error flag */
ganlikun	0:13413ea9a877	1158	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
ganlikun	0:13413ea9a877	1159
ganlikun	0:13413ea9a877	1160	/* Update error code */
ganlikun	0:13413ea9a877	1161	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_CE;
ganlikun	0:13413ea9a877	1162
ganlikun	0:13413ea9a877	1163	/* Change DMA2D state */
ganlikun	0:13413ea9a877	1164	hdma2d->State = HAL_DMA2D_STATE_ERROR;
ganlikun	0:13413ea9a877	1165
ganlikun	0:13413ea9a877	1166	/* Process Unlocked */
ganlikun	0:13413ea9a877	1167	__HAL_UNLOCK(hdma2d);
ganlikun	0:13413ea9a877	1168
ganlikun	0:13413ea9a877	1169	if(hdma2d->XferErrorCallback != NULL)
ganlikun	0:13413ea9a877	1170	{
ganlikun	0:13413ea9a877	1171	/* Transfer error Callback */
ganlikun	0:13413ea9a877	1172	hdma2d->XferErrorCallback(hdma2d);
ganlikun	0:13413ea9a877	1173	}
ganlikun	0:13413ea9a877	1174	}
ganlikun	0:13413ea9a877	1175	}
ganlikun	0:13413ea9a877	1176	/* CLUT access Error Interrupt management ***********************************/
ganlikun	0:13413ea9a877	1177	if ((isrflags & DMA2D_FLAG_CAE) != RESET)
ganlikun	0:13413ea9a877	1178	{
ganlikun	0:13413ea9a877	1179	if ((crflags & DMA2D_IT_CAE) != RESET)
ganlikun	0:13413ea9a877	1180	{
ganlikun	0:13413ea9a877	1181	/* Disable the CLUT access error interrupt */
ganlikun	0:13413ea9a877	1182	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
ganlikun	0:13413ea9a877	1183
ganlikun	0:13413ea9a877	1184	/* Clear the CLUT access error flag */
ganlikun	0:13413ea9a877	1185	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
ganlikun	0:13413ea9a877	1186
ganlikun	0:13413ea9a877	1187	/* Update error code */
ganlikun	0:13413ea9a877	1188	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_CAE;
ganlikun	0:13413ea9a877	1189
ganlikun	0:13413ea9a877	1190	/* Change DMA2D state */
ganlikun	0:13413ea9a877	1191	hdma2d->State = HAL_DMA2D_STATE_ERROR;
ganlikun	0:13413ea9a877	1192
ganlikun	0:13413ea9a877	1193	/* Process Unlocked */
ganlikun	0:13413ea9a877	1194	__HAL_UNLOCK(hdma2d);
ganlikun	0:13413ea9a877	1195
ganlikun	0:13413ea9a877	1196	if(hdma2d->XferErrorCallback != NULL)
ganlikun	0:13413ea9a877	1197	{
ganlikun	0:13413ea9a877	1198	/* Transfer error Callback */
ganlikun	0:13413ea9a877	1199	hdma2d->XferErrorCallback(hdma2d);
ganlikun	0:13413ea9a877	1200	}
ganlikun	0:13413ea9a877	1201	}
ganlikun	0:13413ea9a877	1202	}
ganlikun	0:13413ea9a877	1203	/* Transfer watermark Interrupt management **********************************/
ganlikun	0:13413ea9a877	1204	if ((isrflags & DMA2D_FLAG_TW) != RESET)
ganlikun	0:13413ea9a877	1205	{
ganlikun	0:13413ea9a877	1206	if ((crflags & DMA2D_IT_TW) != RESET)
ganlikun	0:13413ea9a877	1207	{
ganlikun	0:13413ea9a877	1208	/* Disable the transfer watermark interrupt */
ganlikun	0:13413ea9a877	1209	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
ganlikun	0:13413ea9a877	1210
ganlikun	0:13413ea9a877	1211	/* Clear the transfer watermark flag */
ganlikun	0:13413ea9a877	1212	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
ganlikun	0:13413ea9a877	1213
ganlikun	0:13413ea9a877	1214	/* Transfer watermark Callback */
ganlikun	0:13413ea9a877	1215	HAL_DMA2D_LineEventCallback(hdma2d);
ganlikun	0:13413ea9a877	1216	}
ganlikun	0:13413ea9a877	1217	}
ganlikun	0:13413ea9a877	1218	/* Transfer Complete Interrupt management ************************************/
ganlikun	0:13413ea9a877	1219	if ((isrflags & DMA2D_FLAG_TC) != RESET)
ganlikun	0:13413ea9a877	1220	{
ganlikun	0:13413ea9a877	1221	if ((crflags & DMA2D_IT_TC) != RESET)
ganlikun	0:13413ea9a877	1222	{
ganlikun	0:13413ea9a877	1223	/* Disable the transfer complete interrupt */
ganlikun	0:13413ea9a877	1224	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
ganlikun	0:13413ea9a877	1225
ganlikun	0:13413ea9a877	1226	/* Clear the transfer complete flag */
ganlikun	0:13413ea9a877	1227	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
ganlikun	0:13413ea9a877	1228
ganlikun	0:13413ea9a877	1229	/* Update error code */
ganlikun	0:13413ea9a877	1230	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_NONE;
ganlikun	0:13413ea9a877	1231
ganlikun	0:13413ea9a877	1232	/* Change DMA2D state */
ganlikun	0:13413ea9a877	1233	hdma2d->State = HAL_DMA2D_STATE_READY;
ganlikun	0:13413ea9a877	1234
ganlikun	0:13413ea9a877	1235	/* Process Unlocked */
ganlikun	0:13413ea9a877	1236	__HAL_UNLOCK(hdma2d);
ganlikun	0:13413ea9a877	1237
ganlikun	0:13413ea9a877	1238	if(hdma2d->XferCpltCallback != NULL)
ganlikun	0:13413ea9a877	1239	{
ganlikun	0:13413ea9a877	1240	/* Transfer complete Callback */
ganlikun	0:13413ea9a877	1241	hdma2d->XferCpltCallback(hdma2d);
ganlikun	0:13413ea9a877	1242	}
ganlikun	0:13413ea9a877	1243	}
ganlikun	0:13413ea9a877	1244	}
ganlikun	0:13413ea9a877	1245	/* CLUT Transfer Complete Interrupt management ******************************/
ganlikun	0:13413ea9a877	1246	if ((isrflags & DMA2D_FLAG_CTC) != RESET)
ganlikun	0:13413ea9a877	1247	{
ganlikun	0:13413ea9a877	1248	if ((crflags & DMA2D_IT_CTC) != RESET)
ganlikun	0:13413ea9a877	1249	{
ganlikun	0:13413ea9a877	1250	/* Disable the CLUT transfer complete interrupt */
ganlikun	0:13413ea9a877	1251	__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
ganlikun	0:13413ea9a877	1252
ganlikun	0:13413ea9a877	1253	/* Clear the CLUT transfer complete flag */
ganlikun	0:13413ea9a877	1254	__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
ganlikun	0:13413ea9a877	1255
ganlikun	0:13413ea9a877	1256	/* Update error code */
ganlikun	0:13413ea9a877	1257	hdma2d->ErrorCode \|= HAL_DMA2D_ERROR_NONE;
ganlikun	0:13413ea9a877	1258
ganlikun	0:13413ea9a877	1259	/* Change DMA2D state */
ganlikun	0:13413ea9a877	1260	hdma2d->State = HAL_DMA2D_STATE_READY;
ganlikun	0:13413ea9a877	1261
ganlikun	0:13413ea9a877	1262	/* Process Unlocked */
ganlikun	0:13413ea9a877	1263	__HAL_UNLOCK(hdma2d);
ganlikun	0:13413ea9a877	1264
ganlikun	0:13413ea9a877	1265	/* CLUT Transfer complete Callback */
ganlikun	0:13413ea9a877	1266	HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
ganlikun	0:13413ea9a877	1267	}
ganlikun	0:13413ea9a877	1268	}
ganlikun	0:13413ea9a877	1269	}
ganlikun	0:13413ea9a877	1270
ganlikun	0:13413ea9a877	1271	/**
ganlikun	0:13413ea9a877	1272	* @brief Transfer watermark callback.
ganlikun	0:13413ea9a877	1273	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	1274	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	1275	* @retval None
ganlikun	0:13413ea9a877	1276	*/
ganlikun	0:13413ea9a877	1277	__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
ganlikun	0:13413ea9a877	1278	{
ganlikun	0:13413ea9a877	1279	/* Prevent unused argument(s) compilation warning */
ganlikun	0:13413ea9a877	1280	UNUSED(hdma2d);
ganlikun	0:13413ea9a877	1281
ganlikun	0:13413ea9a877	1282	/* NOTE : This function should not be modified; when the callback is needed,
ganlikun	0:13413ea9a877	1283	the HAL_DMA2D_LineEventCallback can be implemented in the user file.
ganlikun	0:13413ea9a877	1284	*/
ganlikun	0:13413ea9a877	1285	}
ganlikun	0:13413ea9a877	1286
ganlikun	0:13413ea9a877	1287	/**
ganlikun	0:13413ea9a877	1288	* @brief CLUT Transfer Complete callback.
ganlikun	0:13413ea9a877	1289	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	1290	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	1291	* @retval None
ganlikun	0:13413ea9a877	1292	*/
ganlikun	0:13413ea9a877	1293	__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
ganlikun	0:13413ea9a877	1294	{
ganlikun	0:13413ea9a877	1295	/* Prevent unused argument(s) compilation warning */
ganlikun	0:13413ea9a877	1296	UNUSED(hdma2d);
ganlikun	0:13413ea9a877	1297
ganlikun	0:13413ea9a877	1298	/* NOTE : This function should not be modified; when the callback is needed,
ganlikun	0:13413ea9a877	1299	the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
ganlikun	0:13413ea9a877	1300	*/
ganlikun	0:13413ea9a877	1301	}
ganlikun	0:13413ea9a877	1302
ganlikun	0:13413ea9a877	1303	/**
ganlikun	0:13413ea9a877	1304	* @}
ganlikun	0:13413ea9a877	1305	*/
ganlikun	0:13413ea9a877	1306
ganlikun	0:13413ea9a877	1307	/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
ganlikun	0:13413ea9a877	1308	* @brief Peripheral Control functions
ganlikun	0:13413ea9a877	1309	*
ganlikun	0:13413ea9a877	1310	@verbatim
ganlikun	0:13413ea9a877	1311	===============================================================================
ganlikun	0:13413ea9a877	1312	##### Peripheral Control functions #####
ganlikun	0:13413ea9a877	1313	===============================================================================
ganlikun	0:13413ea9a877	1314	[..] This section provides functions allowing to:
ganlikun	0:13413ea9a877	1315	(+) Configure the DMA2D foreground or background layer parameters.
ganlikun	0:13413ea9a877	1316	(+) Configure the DMA2D CLUT transfer.
ganlikun	0:13413ea9a877	1317	(+) Configure the line watermark
ganlikun	0:13413ea9a877	1318	(+) Configure the dead time value.
ganlikun	0:13413ea9a877	1319	(+) Enable or disable the dead time value functionality.
ganlikun	0:13413ea9a877	1320
ganlikun	0:13413ea9a877	1321	@endverbatim
ganlikun	0:13413ea9a877	1322	* @{
ganlikun	0:13413ea9a877	1323	*/
ganlikun	0:13413ea9a877	1324
ganlikun	0:13413ea9a877	1325	/**
ganlikun	0:13413ea9a877	1326	* @brief Configure the DMA2D Layer according to the specified
ganlikun	0:13413ea9a877	1327	* parameters in the DMA2D_InitTypeDef and create the associated handle.
ganlikun	0:13413ea9a877	1328	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	1329	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	1330	* @param LayerIdx: DMA2D Layer index.
ganlikun	0:13413ea9a877	1331	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1332	* 0(background) / 1(foreground)
ganlikun	0:13413ea9a877	1333	* @retval HAL status
ganlikun	0:13413ea9a877	1334	*/
ganlikun	0:13413ea9a877	1335	HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
ganlikun	0:13413ea9a877	1336	{
ganlikun	0:13413ea9a877	1337	DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
ganlikun	0:13413ea9a877	1338	uint32_t regValue = 0U;
ganlikun	0:13413ea9a877	1339
ganlikun	0:13413ea9a877	1340	/* Check the parameters */
ganlikun	0:13413ea9a877	1341	assert_param(IS_DMA2D_LAYER(LayerIdx));
ganlikun	0:13413ea9a877	1342	assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));
ganlikun	0:13413ea9a877	1343	if(hdma2d->Init.Mode != DMA2D_R2M)
ganlikun	0:13413ea9a877	1344	{
ganlikun	0:13413ea9a877	1345	assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
ganlikun	0:13413ea9a877	1346	if(hdma2d->Init.Mode != DMA2D_M2M)
ganlikun	0:13413ea9a877	1347	{
ganlikun	0:13413ea9a877	1348	assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));
ganlikun	0:13413ea9a877	1349	}
ganlikun	0:13413ea9a877	1350	}
ganlikun	0:13413ea9a877	1351
ganlikun	0:13413ea9a877	1352	/* Process locked */
ganlikun	0:13413ea9a877	1353	__HAL_LOCK(hdma2d);
ganlikun	0:13413ea9a877	1354
ganlikun	0:13413ea9a877	1355	/* Change DMA2D peripheral state */
ganlikun	0:13413ea9a877	1356	hdma2d->State = HAL_DMA2D_STATE_BUSY;
ganlikun	0:13413ea9a877	1357
ganlikun	0:13413ea9a877	1358	/* DMA2D BGPFCR register configuration -----------------------------------*/
ganlikun	0:13413ea9a877	1359	/* Prepare the value to be written to the BGPFCCR register */
ganlikun	0:13413ea9a877	1360
ganlikun	0:13413ea9a877	1361	if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) \|\| (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
ganlikun	0:13413ea9a877	1362	{
ganlikun	0:13413ea9a877	1363	regValue = pLayerCfg->InputColorMode \| (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) \| (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
ganlikun	0:13413ea9a877	1364	}
ganlikun	0:13413ea9a877	1365	else
ganlikun	0:13413ea9a877	1366	{
ganlikun	0:13413ea9a877	1367	regValue = pLayerCfg->InputColorMode \| (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) \| (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA);
ganlikun	0:13413ea9a877	1368	}
ganlikun	0:13413ea9a877	1369
ganlikun	0:13413ea9a877	1370	/* Configure the background DMA2D layer */
ganlikun	0:13413ea9a877	1371	if(LayerIdx == 0)
ganlikun	0:13413ea9a877	1372	{
ganlikun	0:13413ea9a877	1373	/* Write DMA2D BGPFCCR register */
ganlikun	0:13413ea9a877	1374	MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CM \| DMA2D_BGPFCCR_AM \| DMA2D_BGPFCCR_ALPHA), regValue);
ganlikun	0:13413ea9a877	1375
ganlikun	0:13413ea9a877	1376	/* DMA2D BGOR register configuration -------------------------------------*/
ganlikun	0:13413ea9a877	1377	WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
ganlikun	0:13413ea9a877	1378
ganlikun	0:13413ea9a877	1379	/* DMA2D BGCOLR register configuration -------------------------------------*/
ganlikun	0:13413ea9a877	1380	if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) \|\| (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
ganlikun	0:13413ea9a877	1381	{
ganlikun	0:13413ea9a877	1382	WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE\|DMA2D_BGCOLR_GREEN\|DMA2D_BGCOLR_RED));
ganlikun	0:13413ea9a877	1383	}
ganlikun	0:13413ea9a877	1384	}
ganlikun	0:13413ea9a877	1385	/* Configure the foreground DMA2D layer */
ganlikun	0:13413ea9a877	1386	else
ganlikun	0:13413ea9a877	1387	{
ganlikun	0:13413ea9a877	1388	/* Write DMA2D FGPFCCR register */
ganlikun	0:13413ea9a877	1389	MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_BGPFCCR_CM \| DMA2D_BGPFCCR_AM \| DMA2D_BGPFCCR_ALPHA), regValue);
ganlikun	0:13413ea9a877	1390
ganlikun	0:13413ea9a877	1391	/* DMA2D FGOR register configuration -------------------------------------*/
ganlikun	0:13413ea9a877	1392	WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
ganlikun	0:13413ea9a877	1393
ganlikun	0:13413ea9a877	1394	/* DMA2D FGCOLR register configuration -------------------------------------*/
ganlikun	0:13413ea9a877	1395	if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) \|\| (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
ganlikun	0:13413ea9a877	1396	{
ganlikun	0:13413ea9a877	1397	WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE\|DMA2D_FGCOLR_GREEN\|DMA2D_FGCOLR_RED));
ganlikun	0:13413ea9a877	1398	}
ganlikun	0:13413ea9a877	1399	}
ganlikun	0:13413ea9a877	1400	/* Initialize the DMA2D state*/
ganlikun	0:13413ea9a877	1401	hdma2d->State = HAL_DMA2D_STATE_READY;
ganlikun	0:13413ea9a877	1402
ganlikun	0:13413ea9a877	1403	/* Process unlocked */
ganlikun	0:13413ea9a877	1404	__HAL_UNLOCK(hdma2d);
ganlikun	0:13413ea9a877	1405
ganlikun	0:13413ea9a877	1406	return HAL_OK;
ganlikun	0:13413ea9a877	1407	}
ganlikun	0:13413ea9a877	1408
ganlikun	0:13413ea9a877	1409	/**
ganlikun	0:13413ea9a877	1410	* @brief Configure the DMA2D CLUT Transfer.
ganlikun	0:13413ea9a877	1411	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	1412	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	1413	* @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
ganlikun	0:13413ea9a877	1414	* the configuration information for the color look up table.
ganlikun	0:13413ea9a877	1415	* @param LayerIdx: DMA2D Layer index.
ganlikun	0:13413ea9a877	1416	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1417	* 0(background) / 1(foreground)
ganlikun	0:13413ea9a877	1418	* @retval HAL status
ganlikun	0:13413ea9a877	1419	*/
ganlikun	0:13413ea9a877	1420	HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
ganlikun	0:13413ea9a877	1421	{
ganlikun	0:13413ea9a877	1422	/* Check the parameters */
ganlikun	0:13413ea9a877	1423	assert_param(IS_DMA2D_LAYER(LayerIdx));
ganlikun	0:13413ea9a877	1424	assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
ganlikun	0:13413ea9a877	1425	assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
ganlikun	0:13413ea9a877	1426
ganlikun	0:13413ea9a877	1427	/* Process locked */
ganlikun	0:13413ea9a877	1428	__HAL_LOCK(hdma2d);
ganlikun	0:13413ea9a877	1429
ganlikun	0:13413ea9a877	1430	/* Change DMA2D peripheral state */
ganlikun	0:13413ea9a877	1431	hdma2d->State = HAL_DMA2D_STATE_BUSY;
ganlikun	0:13413ea9a877	1432
ganlikun	0:13413ea9a877	1433	/* Configure the CLUT of the background DMA2D layer */
ganlikun	0:13413ea9a877	1434	if(LayerIdx == 0U)
ganlikun	0:13413ea9a877	1435	{
ganlikun	0:13413ea9a877	1436	/* Write background CLUT memory address */
ganlikun	0:13413ea9a877	1437	WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
ganlikun	0:13413ea9a877	1438
ganlikun	0:13413ea9a877	1439	/* Write background CLUT size and CLUT color mode */
ganlikun	0:13413ea9a877	1440	MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS \| DMA2D_BGPFCCR_CCM),
ganlikun	0:13413ea9a877	1441	((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) \| (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
ganlikun	0:13413ea9a877	1442	}
ganlikun	0:13413ea9a877	1443	/* Configure the CLUT of the foreground DMA2D layer */
ganlikun	0:13413ea9a877	1444	else
ganlikun	0:13413ea9a877	1445	{
ganlikun	0:13413ea9a877	1446	/* Write foreground CLUT memory address */
ganlikun	0:13413ea9a877	1447	WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
ganlikun	0:13413ea9a877	1448
ganlikun	0:13413ea9a877	1449	/* Write foreground CLUT size and CLUT color mode */
ganlikun	0:13413ea9a877	1450	MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS \| DMA2D_FGPFCCR_CCM),
ganlikun	0:13413ea9a877	1451	((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) \| (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
ganlikun	0:13413ea9a877	1452	}
ganlikun	0:13413ea9a877	1453
ganlikun	0:13413ea9a877	1454	/* Set the DMA2D state to Ready */
ganlikun	0:13413ea9a877	1455	hdma2d->State = HAL_DMA2D_STATE_READY;
ganlikun	0:13413ea9a877	1456
ganlikun	0:13413ea9a877	1457	/* Process unlocked */
ganlikun	0:13413ea9a877	1458	__HAL_UNLOCK(hdma2d);
ganlikun	0:13413ea9a877	1459
ganlikun	0:13413ea9a877	1460	return HAL_OK;
ganlikun	0:13413ea9a877	1461	}
ganlikun	0:13413ea9a877	1462
ganlikun	0:13413ea9a877	1463	/**
ganlikun	0:13413ea9a877	1464	* @brief Configure the line watermark.
ganlikun	0:13413ea9a877	1465	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	1466	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	1467	* @param Line: Line Watermark configuration (maximum 16-bit long value expected).
ganlikun	0:13413ea9a877	1468	* @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
ganlikun	0:13413ea9a877	1469	* @note The transfer watermark interrupt is disabled once it has occurred.
ganlikun	0:13413ea9a877	1470	* @retval HAL status
ganlikun	0:13413ea9a877	1471	*/
ganlikun	0:13413ea9a877	1472
ganlikun	0:13413ea9a877	1473	HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
ganlikun	0:13413ea9a877	1474	{
ganlikun	0:13413ea9a877	1475	/* Check the parameters */
ganlikun	0:13413ea9a877	1476	assert_param(IS_DMA2D_LINEWATERMARK(Line));
ganlikun	0:13413ea9a877	1477
ganlikun	0:13413ea9a877	1478	if (Line > DMA2D_LWR_LW)
ganlikun	0:13413ea9a877	1479	{
ganlikun	0:13413ea9a877	1480	return HAL_ERROR;
ganlikun	0:13413ea9a877	1481	}
ganlikun	0:13413ea9a877	1482	else
ganlikun	0:13413ea9a877	1483	{
ganlikun	0:13413ea9a877	1484	/* Process locked */
ganlikun	0:13413ea9a877	1485	__HAL_LOCK(hdma2d);
ganlikun	0:13413ea9a877	1486
ganlikun	0:13413ea9a877	1487	/* Change DMA2D peripheral state */
ganlikun	0:13413ea9a877	1488	hdma2d->State = HAL_DMA2D_STATE_BUSY;
ganlikun	0:13413ea9a877	1489
ganlikun	0:13413ea9a877	1490	/* Sets the Line watermark configuration */
ganlikun	0:13413ea9a877	1491	WRITE_REG(hdma2d->Instance->LWR, Line);
ganlikun	0:13413ea9a877	1492
ganlikun	0:13413ea9a877	1493	/* Enable the Line interrupt */
ganlikun	0:13413ea9a877	1494	__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
ganlikun	0:13413ea9a877	1495
ganlikun	0:13413ea9a877	1496	/* Initialize the DMA2D state */
ganlikun	0:13413ea9a877	1497	hdma2d->State = HAL_DMA2D_STATE_READY;
ganlikun	0:13413ea9a877	1498
ganlikun	0:13413ea9a877	1499	/* Process unlocked */
ganlikun	0:13413ea9a877	1500	__HAL_UNLOCK(hdma2d);
ganlikun	0:13413ea9a877	1501
ganlikun	0:13413ea9a877	1502	return HAL_OK;
ganlikun	0:13413ea9a877	1503	}
ganlikun	0:13413ea9a877	1504	}
ganlikun	0:13413ea9a877	1505
ganlikun	0:13413ea9a877	1506	/**
ganlikun	0:13413ea9a877	1507	* @brief Enable DMA2D dead time feature.
ganlikun	0:13413ea9a877	1508	* @param hdma2d: DMA2D handle.
ganlikun	0:13413ea9a877	1509	* @retval HAL status
ganlikun	0:13413ea9a877	1510	*/
ganlikun	0:13413ea9a877	1511	HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
ganlikun	0:13413ea9a877	1512	{
ganlikun	0:13413ea9a877	1513	/* Process Locked */
ganlikun	0:13413ea9a877	1514	__HAL_LOCK(hdma2d);
ganlikun	0:13413ea9a877	1515
ganlikun	0:13413ea9a877	1516	hdma2d->State = HAL_DMA2D_STATE_BUSY;
ganlikun	0:13413ea9a877	1517
ganlikun	0:13413ea9a877	1518	/* Set DMA2D_AMTCR EN bit */
ganlikun	0:13413ea9a877	1519	SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
ganlikun	0:13413ea9a877	1520
ganlikun	0:13413ea9a877	1521	hdma2d->State = HAL_DMA2D_STATE_READY;
ganlikun	0:13413ea9a877	1522
ganlikun	0:13413ea9a877	1523	/* Process Unlocked */
ganlikun	0:13413ea9a877	1524	__HAL_UNLOCK(hdma2d);
ganlikun	0:13413ea9a877	1525
ganlikun	0:13413ea9a877	1526	return HAL_OK;
ganlikun	0:13413ea9a877	1527	}
ganlikun	0:13413ea9a877	1528
ganlikun	0:13413ea9a877	1529	/**
ganlikun	0:13413ea9a877	1530	* @brief Disable DMA2D dead time feature.
ganlikun	0:13413ea9a877	1531	* @param hdma2d: DMA2D handle.
ganlikun	0:13413ea9a877	1532	* @retval HAL status
ganlikun	0:13413ea9a877	1533	*/
ganlikun	0:13413ea9a877	1534	HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
ganlikun	0:13413ea9a877	1535	{
ganlikun	0:13413ea9a877	1536	/* Process Locked */
ganlikun	0:13413ea9a877	1537	__HAL_LOCK(hdma2d);
ganlikun	0:13413ea9a877	1538
ganlikun	0:13413ea9a877	1539	hdma2d->State = HAL_DMA2D_STATE_BUSY;
ganlikun	0:13413ea9a877	1540
ganlikun	0:13413ea9a877	1541	/* Clear DMA2D_AMTCR EN bit */
ganlikun	0:13413ea9a877	1542	CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
ganlikun	0:13413ea9a877	1543
ganlikun	0:13413ea9a877	1544	hdma2d->State = HAL_DMA2D_STATE_READY;
ganlikun	0:13413ea9a877	1545
ganlikun	0:13413ea9a877	1546	/* Process Unlocked */
ganlikun	0:13413ea9a877	1547	__HAL_UNLOCK(hdma2d);
ganlikun	0:13413ea9a877	1548
ganlikun	0:13413ea9a877	1549	return HAL_OK;
ganlikun	0:13413ea9a877	1550	}
ganlikun	0:13413ea9a877	1551
ganlikun	0:13413ea9a877	1552	/**
ganlikun	0:13413ea9a877	1553	* @brief Configure dead time.
ganlikun	0:13413ea9a877	1554	* @note The dead time value represents the guaranteed minimum number of cycles between
ganlikun	0:13413ea9a877	1555	* two consecutive transactions on the AHB bus.
ganlikun	0:13413ea9a877	1556	* @param hdma2d: DMA2D handle.
ganlikun	0:13413ea9a877	1557	* @param DeadTime: dead time value.
ganlikun	0:13413ea9a877	1558	* @retval HAL status
ganlikun	0:13413ea9a877	1559	*/
ganlikun	0:13413ea9a877	1560	HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
ganlikun	0:13413ea9a877	1561	{
ganlikun	0:13413ea9a877	1562	/* Process Locked */
ganlikun	0:13413ea9a877	1563	__HAL_LOCK(hdma2d);
ganlikun	0:13413ea9a877	1564
ganlikun	0:13413ea9a877	1565	hdma2d->State = HAL_DMA2D_STATE_BUSY;
ganlikun	0:13413ea9a877	1566
ganlikun	0:13413ea9a877	1567	/* Set DMA2D_AMTCR DT field */
ganlikun	0:13413ea9a877	1568	MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT));
ganlikun	0:13413ea9a877	1569
ganlikun	0:13413ea9a877	1570	hdma2d->State = HAL_DMA2D_STATE_READY;
ganlikun	0:13413ea9a877	1571
ganlikun	0:13413ea9a877	1572	/* Process Unlocked */
ganlikun	0:13413ea9a877	1573	__HAL_UNLOCK(hdma2d);
ganlikun	0:13413ea9a877	1574
ganlikun	0:13413ea9a877	1575	return HAL_OK;
ganlikun	0:13413ea9a877	1576	}
ganlikun	0:13413ea9a877	1577
ganlikun	0:13413ea9a877	1578	/**
ganlikun	0:13413ea9a877	1579	* @}
ganlikun	0:13413ea9a877	1580	*/
ganlikun	0:13413ea9a877	1581
ganlikun	0:13413ea9a877	1582	/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
ganlikun	0:13413ea9a877	1583	* @brief Peripheral State functions
ganlikun	0:13413ea9a877	1584	*
ganlikun	0:13413ea9a877	1585	@verbatim
ganlikun	0:13413ea9a877	1586	===============================================================================
ganlikun	0:13413ea9a877	1587	##### Peripheral State and Errors functions #####
ganlikun	0:13413ea9a877	1588	===============================================================================
ganlikun	0:13413ea9a877	1589	[..]
ganlikun	0:13413ea9a877	1590	This subsection provides functions allowing to :
ganlikun	0:13413ea9a877	1591	(+) Get the DMA2D state
ganlikun	0:13413ea9a877	1592	(+) Get the DMA2D error code
ganlikun	0:13413ea9a877	1593
ganlikun	0:13413ea9a877	1594	@endverbatim
ganlikun	0:13413ea9a877	1595	* @{
ganlikun	0:13413ea9a877	1596	*/
ganlikun	0:13413ea9a877	1597
ganlikun	0:13413ea9a877	1598	/**
ganlikun	0:13413ea9a877	1599	* @brief Return the DMA2D state
ganlikun	0:13413ea9a877	1600	* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	1601	* the configuration information for the DMA2D.
ganlikun	0:13413ea9a877	1602	* @retval HAL state
ganlikun	0:13413ea9a877	1603	*/
ganlikun	0:13413ea9a877	1604	HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
ganlikun	0:13413ea9a877	1605	{
ganlikun	0:13413ea9a877	1606	return hdma2d->State;
ganlikun	0:13413ea9a877	1607	}
ganlikun	0:13413ea9a877	1608
ganlikun	0:13413ea9a877	1609	/**
ganlikun	0:13413ea9a877	1610	* @brief Return the DMA2D error code
ganlikun	0:13413ea9a877	1611	* @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	1612	* the configuration information for DMA2D.
ganlikun	0:13413ea9a877	1613	* @retval DMA2D Error Code
ganlikun	0:13413ea9a877	1614	*/
ganlikun	0:13413ea9a877	1615	uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
ganlikun	0:13413ea9a877	1616	{
ganlikun	0:13413ea9a877	1617	return hdma2d->ErrorCode;
ganlikun	0:13413ea9a877	1618	}
ganlikun	0:13413ea9a877	1619
ganlikun	0:13413ea9a877	1620	/**
ganlikun	0:13413ea9a877	1621	* @}
ganlikun	0:13413ea9a877	1622	*/
ganlikun	0:13413ea9a877	1623
ganlikun	0:13413ea9a877	1624	/**
ganlikun	0:13413ea9a877	1625	* @}
ganlikun	0:13413ea9a877	1626	*/
ganlikun	0:13413ea9a877	1627
ganlikun	0:13413ea9a877	1628	/** @defgroup DMA2D_Private_Functions DMA2D Private Functions
ganlikun	0:13413ea9a877	1629	* @{
ganlikun	0:13413ea9a877	1630	*/
ganlikun	0:13413ea9a877	1631
ganlikun	0:13413ea9a877	1632	/**
ganlikun	0:13413ea9a877	1633	* @brief Set the DMA2D transfer parameters.
ganlikun	0:13413ea9a877	1634	* @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
ganlikun	0:13413ea9a877	1635	* the configuration information for the specified DMA2D.
ganlikun	0:13413ea9a877	1636	* @param pdata: The source memory Buffer address
ganlikun	0:13413ea9a877	1637	* @param DstAddress: The destination memory Buffer address
ganlikun	0:13413ea9a877	1638	* @param Width: The width of data to be transferred from source to destination.
ganlikun	0:13413ea9a877	1639	* @param Height: The height of data to be transferred from source to destination.
ganlikun	0:13413ea9a877	1640	* @retval HAL status
ganlikun	0:13413ea9a877	1641	*/
ganlikun	0:13413ea9a877	1642	static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
ganlikun	0:13413ea9a877	1643	{
ganlikun	0:13413ea9a877	1644	uint32_t tmp = 0U;
ganlikun	0:13413ea9a877	1645	uint32_t tmp1 = 0U;
ganlikun	0:13413ea9a877	1646	uint32_t tmp2 = 0U;
ganlikun	0:13413ea9a877	1647	uint32_t tmp3 = 0U;
ganlikun	0:13413ea9a877	1648	uint32_t tmp4 = 0U;
ganlikun	0:13413ea9a877	1649
ganlikun	0:13413ea9a877	1650	/* Configure DMA2D data size */
ganlikun	0:13413ea9a877	1651	MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL\|DMA2D_NLR_PL), (Height\| (Width << DMA2D_POSITION_NLR_PL)));
ganlikun	0:13413ea9a877	1652
ganlikun	0:13413ea9a877	1653	/* Configure DMA2D destination address */
ganlikun	0:13413ea9a877	1654	WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
ganlikun	0:13413ea9a877	1655
ganlikun	0:13413ea9a877	1656	/* Register to memory DMA2D mode selected */
ganlikun	0:13413ea9a877	1657	if (hdma2d->Init.Mode == DMA2D_R2M)
ganlikun	0:13413ea9a877	1658	{
ganlikun	0:13413ea9a877	1659	tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
ganlikun	0:13413ea9a877	1660	tmp2 = pdata & DMA2D_OCOLR_RED_1;
ganlikun	0:13413ea9a877	1661	tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
ganlikun	0:13413ea9a877	1662	tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
ganlikun	0:13413ea9a877	1663
ganlikun	0:13413ea9a877	1664	/* Prepare the value to be written to the OCOLR register according to the color mode */
ganlikun	0:13413ea9a877	1665	if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
ganlikun	0:13413ea9a877	1666	{
ganlikun	0:13413ea9a877	1667	tmp = (tmp3 \| tmp2 \| tmp1\| tmp4);
ganlikun	0:13413ea9a877	1668	}
ganlikun	0:13413ea9a877	1669	else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
ganlikun	0:13413ea9a877	1670	{
ganlikun	0:13413ea9a877	1671	tmp = (tmp3 \| tmp2 \| tmp4);
ganlikun	0:13413ea9a877	1672	}
ganlikun	0:13413ea9a877	1673	else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
ganlikun	0:13413ea9a877	1674	{
ganlikun	0:13413ea9a877	1675	tmp2 = (tmp2 >> 19U);
ganlikun	0:13413ea9a877	1676	tmp3 = (tmp3 >> 10U);
ganlikun	0:13413ea9a877	1677	tmp4 = (tmp4 >> 3U);
ganlikun	0:13413ea9a877	1678	tmp = ((tmp3 << 5U) \| (tmp2 << 11U) \| tmp4);
ganlikun	0:13413ea9a877	1679	}
ganlikun	0:13413ea9a877	1680	else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
ganlikun	0:13413ea9a877	1681	{
ganlikun	0:13413ea9a877	1682	tmp1 = (tmp1 >> 31U);
ganlikun	0:13413ea9a877	1683	tmp2 = (tmp2 >> 19U);
ganlikun	0:13413ea9a877	1684	tmp3 = (tmp3 >> 11U);
ganlikun	0:13413ea9a877	1685	tmp4 = (tmp4 >> 3U);
ganlikun	0:13413ea9a877	1686	tmp = ((tmp3 << 5U) \| (tmp2 << 10U) \| (tmp1 << 15U) \| tmp4);
ganlikun	0:13413ea9a877	1687	}
ganlikun	0:13413ea9a877	1688	else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
ganlikun	0:13413ea9a877	1689	{
ganlikun	0:13413ea9a877	1690	tmp1 = (tmp1 >> 28U);
ganlikun	0:13413ea9a877	1691	tmp2 = (tmp2 >> 20U);
ganlikun	0:13413ea9a877	1692	tmp3 = (tmp3 >> 12U);
ganlikun	0:13413ea9a877	1693	tmp4 = (tmp4 >> 4U);
ganlikun	0:13413ea9a877	1694	tmp = ((tmp3 << 4U) \| (tmp2 << 8U) \| (tmp1 << 12U) \| tmp4);
ganlikun	0:13413ea9a877	1695	}
ganlikun	0:13413ea9a877	1696	/* Write to DMA2D OCOLR register */
ganlikun	0:13413ea9a877	1697	WRITE_REG(hdma2d->Instance->OCOLR, tmp);
ganlikun	0:13413ea9a877	1698	}
ganlikun	0:13413ea9a877	1699	else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
ganlikun	0:13413ea9a877	1700	{
ganlikun	0:13413ea9a877	1701	/* Configure DMA2D source address */
ganlikun	0:13413ea9a877	1702	WRITE_REG(hdma2d->Instance->FGMAR, pdata);
ganlikun	0:13413ea9a877	1703	}
ganlikun	0:13413ea9a877	1704	}
ganlikun	0:13413ea9a877	1705
ganlikun	0:13413ea9a877	1706	/**
ganlikun	0:13413ea9a877	1707	* @}
ganlikun	0:13413ea9a877	1708	*/
ganlikun	0:13413ea9a877	1709	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
ganlikun	0:13413ea9a877	1710	#endif /* HAL_DMA2D_MODULE_ENABLED */
ganlikun	0:13413ea9a877	1711	/**
ganlikun	0:13413ea9a877	1712	* @}
ganlikun	0:13413ea9a877	1713	*/
ganlikun	0:13413ea9a877	1714
ganlikun	0:13413ea9a877	1715	/**
ganlikun	0:13413ea9a877	1716	* @}
ganlikun	0:13413ea9a877	1717	*/
ganlikun	0:13413ea9a877	1718
ganlikun	0:13413ea9a877	1719	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
ganlikun	0:13413ea9a877	1720

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Type:	Library
Created:	05 Jul 2022
Imports:	1
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Commits:	1
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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.c@0:13413ea9a877, 2022-06-12 (annotated)

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