Gan likun / mbed1-dev

001

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_utils.c@0:13413ea9a877, 2022-06-12 (annotated)

Committer:
ganlikun
Date:
Sun Jun 12 14:02:44 2022 +0000
Revision:
0:13413ea9a877
00

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ganlikun 0:13413ea9a877 1 /**
ganlikun 0:13413ea9a877 2 ******************************************************************************
ganlikun 0:13413ea9a877 3 * @file stm32f4xx_ll_utils.c
ganlikun 0:13413ea9a877 4 * @author MCD Application Team
ganlikun 0:13413ea9a877 5 * @version V1.7.1
ganlikun 0:13413ea9a877 6 * @date 14-April-2017
ganlikun 0:13413ea9a877 7 * @brief UTILS LL module driver.
ganlikun 0:13413ea9a877 8 ******************************************************************************
ganlikun 0:13413ea9a877 9 * @attention
ganlikun 0:13413ea9a877 10 *
ganlikun 0:13413ea9a877 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun 0:13413ea9a877 12 *
ganlikun 0:13413ea9a877 13 * Redistribution and use in source and binary forms, with or without modification,
ganlikun 0:13413ea9a877 14 * are permitted provided that the following conditions are met:
ganlikun 0:13413ea9a877 15 * 1. Redistributions of source code must retain the above copyright notice,
ganlikun 0:13413ea9a877 16 * this list of conditions and the following disclaimer.
ganlikun 0:13413ea9a877 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun 0:13413ea9a877 18 * this list of conditions and the following disclaimer in the documentation
ganlikun 0:13413ea9a877 19 * and/or other materials provided with the distribution.
ganlikun 0:13413ea9a877 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun 0:13413ea9a877 21 * may be used to endorse or promote products derived from this software
ganlikun 0:13413ea9a877 22 * without specific prior written permission.
ganlikun 0:13413ea9a877 23 *
ganlikun 0:13413ea9a877 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun 0:13413ea9a877 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun 0:13413ea9a877 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun 0:13413ea9a877 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun 0:13413ea9a877 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun 0:13413ea9a877 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun 0:13413ea9a877 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun 0:13413ea9a877 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun 0:13413ea9a877 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun 0:13413ea9a877 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun 0:13413ea9a877 34 *
ganlikun 0:13413ea9a877 35 ******************************************************************************
ganlikun 0:13413ea9a877 36 */
ganlikun 0:13413ea9a877 37 /* Includes ------------------------------------------------------------------*/
ganlikun 0:13413ea9a877 38 #include "stm32f4xx_ll_utils.h"
ganlikun 0:13413ea9a877 39 #include "stm32f4xx_ll_rcc.h"
ganlikun 0:13413ea9a877 40 #include "stm32f4xx_ll_system.h"
ganlikun 0:13413ea9a877 41 #include "stm32f4xx_ll_pwr.h"
ganlikun 0:13413ea9a877 42
ganlikun 0:13413ea9a877 43 /** @addtogroup STM32F4xx_LL_Driver
ganlikun 0:13413ea9a877 44 * @{
ganlikun 0:13413ea9a877 45 */
ganlikun 0:13413ea9a877 46
ganlikun 0:13413ea9a877 47 /** @addtogroup UTILS_LL
ganlikun 0:13413ea9a877 48 * @{
ganlikun 0:13413ea9a877 49 */
ganlikun 0:13413ea9a877 50
ganlikun 0:13413ea9a877 51 /* Private types -------------------------------------------------------------*/
ganlikun 0:13413ea9a877 52 /* Private variables ---------------------------------------------------------*/
ganlikun 0:13413ea9a877 53 /* Private constants ---------------------------------------------------------*/
ganlikun 0:13413ea9a877 54 /** @addtogroup UTILS_LL_Private_Constants
ganlikun 0:13413ea9a877 55 * @{
ganlikun 0:13413ea9a877 56 */
ganlikun 0:13413ea9a877 57 #if defined(RCC_MAX_FREQUENCY_SCALE1)
ganlikun 0:13413ea9a877 58 #define UTILS_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
ganlikun 0:13413ea9a877 59 #endif /*RCC_MAX_FREQUENCY_SCALE1 */
ganlikun 0:13413ea9a877 60 #define UTILS_MAX_FREQUENCY_SCALE2 RCC_MAX_FREQUENCY_SCALE2 /*!< Maximum frequency for system clock at power scale2, in Hz */
ganlikun 0:13413ea9a877 61 #if defined(RCC_MAX_FREQUENCY_SCALE3)
ganlikun 0:13413ea9a877 62 #define UTILS_MAX_FREQUENCY_SCALE3 RCC_MAX_FREQUENCY_SCALE3 /*!< Maximum frequency for system clock at power scale3, in Hz */
ganlikun 0:13413ea9a877 63 #endif /* MAX_FREQUENCY_SCALE3 */
ganlikun 0:13413ea9a877 64
ganlikun 0:13413ea9a877 65 /* Defines used for PLL range */
ganlikun 0:13413ea9a877 66 #define UTILS_PLLVCO_INPUT_MIN RCC_PLLVCO_INPUT_MIN /*!< Frequency min for PLLVCO input, in Hz */
ganlikun 0:13413ea9a877 67 #define UTILS_PLLVCO_INPUT_MAX RCC_PLLVCO_INPUT_MAX /*!< Frequency max for PLLVCO input, in Hz */
ganlikun 0:13413ea9a877 68 #define UTILS_PLLVCO_OUTPUT_MIN RCC_PLLVCO_OUTPUT_MIN /*!< Frequency min for PLLVCO output, in Hz */
ganlikun 0:13413ea9a877 69 #define UTILS_PLLVCO_OUTPUT_MAX RCC_PLLVCO_OUTPUT_MAX /*!< Frequency max for PLLVCO output, in Hz */
ganlikun 0:13413ea9a877 70
ganlikun 0:13413ea9a877 71 /* Defines used for HSE range */
ganlikun 0:13413ea9a877 72 #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
ganlikun 0:13413ea9a877 73 #define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz */
ganlikun 0:13413ea9a877 74
ganlikun 0:13413ea9a877 75 /* Defines used for FLASH latency according to HCLK Frequency */
ganlikun 0:13413ea9a877 76 #if defined(FLASH_SCALE1_LATENCY1_FREQ)
ganlikun 0:13413ea9a877 77 #define UTILS_SCALE1_LATENCY1_FREQ FLASH_SCALE1_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
ganlikun 0:13413ea9a877 78 #endif
ganlikun 0:13413ea9a877 79 #if defined(FLASH_SCALE1_LATENCY2_FREQ)
ganlikun 0:13413ea9a877 80 #define UTILS_SCALE1_LATENCY2_FREQ FLASH_SCALE1_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
ganlikun 0:13413ea9a877 81 #endif
ganlikun 0:13413ea9a877 82 #if defined(FLASH_SCALE1_LATENCY3_FREQ)
ganlikun 0:13413ea9a877 83 #define UTILS_SCALE1_LATENCY3_FREQ FLASH_SCALE1_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
ganlikun 0:13413ea9a877 84 #endif
ganlikun 0:13413ea9a877 85 #if defined(FLASH_SCALE1_LATENCY4_FREQ)
ganlikun 0:13413ea9a877 86 #define UTILS_SCALE1_LATENCY4_FREQ FLASH_SCALE1_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
ganlikun 0:13413ea9a877 87 #endif
ganlikun 0:13413ea9a877 88 #if defined(FLASH_SCALE1_LATENCY5_FREQ)
ganlikun 0:13413ea9a877 89 #define UTILS_SCALE1_LATENCY5_FREQ FLASH_SCALE1_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
ganlikun 0:13413ea9a877 90 #endif
ganlikun 0:13413ea9a877 91 #define UTILS_SCALE2_LATENCY1_FREQ FLASH_SCALE2_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
ganlikun 0:13413ea9a877 92 #define UTILS_SCALE2_LATENCY2_FREQ FLASH_SCALE2_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
ganlikun 0:13413ea9a877 93 #if defined(FLASH_SCALE2_LATENCY3_FREQ)
ganlikun 0:13413ea9a877 94 #define UTILS_SCALE2_LATENCY3_FREQ FLASH_SCALE2_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
ganlikun 0:13413ea9a877 95 #endif
ganlikun 0:13413ea9a877 96 #if defined(FLASH_SCALE2_LATENCY4_FREQ)
ganlikun 0:13413ea9a877 97 #define UTILS_SCALE2_LATENCY4_FREQ FLASH_SCALE2_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
ganlikun 0:13413ea9a877 98 #endif
ganlikun 0:13413ea9a877 99 #if defined(FLASH_SCALE2_LATENCY5_FREQ)
ganlikun 0:13413ea9a877 100 #define UTILS_SCALE2_LATENCY5_FREQ FLASH_SCALE2_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
ganlikun 0:13413ea9a877 101 #endif
ganlikun 0:13413ea9a877 102 #if defined(FLASH_SCALE3_LATENCY1_FREQ)
ganlikun 0:13413ea9a877 103 #define UTILS_SCALE3_LATENCY1_FREQ FLASH_SCALE3_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
ganlikun 0:13413ea9a877 104 #endif
ganlikun 0:13413ea9a877 105 #if defined(FLASH_SCALE3_LATENCY2_FREQ)
ganlikun 0:13413ea9a877 106 #define UTILS_SCALE3_LATENCY2_FREQ FLASH_SCALE3_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
ganlikun 0:13413ea9a877 107 #endif
ganlikun 0:13413ea9a877 108 #if defined(FLASH_SCALE3_LATENCY3_FREQ)
ganlikun 0:13413ea9a877 109 #define UTILS_SCALE3_LATENCY3_FREQ FLASH_SCALE3_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
ganlikun 0:13413ea9a877 110 #endif
ganlikun 0:13413ea9a877 111 #if defined(FLASH_SCALE3_LATENCY4_FREQ)
ganlikun 0:13413ea9a877 112 #define UTILS_SCALE3_LATENCY4_FREQ FLASH_SCALE3_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */
ganlikun 0:13413ea9a877 113 #endif
ganlikun 0:13413ea9a877 114 #if defined(FLASH_SCALE3_LATENCY5_FREQ)
ganlikun 0:13413ea9a877 115 #define UTILS_SCALE3_LATENCY5_FREQ FLASH_SCALE3_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 3 */
ganlikun 0:13413ea9a877 116 #endif
ganlikun 0:13413ea9a877 117 /**
ganlikun 0:13413ea9a877 118 * @}
ganlikun 0:13413ea9a877 119 */
ganlikun 0:13413ea9a877 120
ganlikun 0:13413ea9a877 121 /* Private macros ------------------------------------------------------------*/
ganlikun 0:13413ea9a877 122 /** @addtogroup UTILS_LL_Private_Macros
ganlikun 0:13413ea9a877 123 * @{
ganlikun 0:13413ea9a877 124 */
ganlikun 0:13413ea9a877 125 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
ganlikun 0:13413ea9a877 126 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
ganlikun 0:13413ea9a877 127 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
ganlikun 0:13413ea9a877 128 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
ganlikun 0:13413ea9a877 129 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
ganlikun 0:13413ea9a877 130 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
ganlikun 0:13413ea9a877 131 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
ganlikun 0:13413ea9a877 132 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
ganlikun 0:13413ea9a877 133 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
ganlikun 0:13413ea9a877 134
ganlikun 0:13413ea9a877 135 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
ganlikun 0:13413ea9a877 136 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
ganlikun 0:13413ea9a877 137 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
ganlikun 0:13413ea9a877 138 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
ganlikun 0:13413ea9a877 139 || ((__VALUE__) == LL_RCC_APB1_DIV_16))
ganlikun 0:13413ea9a877 140
ganlikun 0:13413ea9a877 141 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
ganlikun 0:13413ea9a877 142 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
ganlikun 0:13413ea9a877 143 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
ganlikun 0:13413ea9a877 144 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
ganlikun 0:13413ea9a877 145 || ((__VALUE__) == LL_RCC_APB2_DIV_16))
ganlikun 0:13413ea9a877 146
ganlikun 0:13413ea9a877 147 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \
ganlikun 0:13413ea9a877 148 || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
ganlikun 0:13413ea9a877 149 || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
ganlikun 0:13413ea9a877 150 || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
ganlikun 0:13413ea9a877 151 || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
ganlikun 0:13413ea9a877 152 || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
ganlikun 0:13413ea9a877 153 || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \
ganlikun 0:13413ea9a877 154 || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \
ganlikun 0:13413ea9a877 155 || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
ganlikun 0:13413ea9a877 156 || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
ganlikun 0:13413ea9a877 157 || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
ganlikun 0:13413ea9a877 158 || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
ganlikun 0:13413ea9a877 159 || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
ganlikun 0:13413ea9a877 160 || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
ganlikun 0:13413ea9a877 161 || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \
ganlikun 0:13413ea9a877 162 || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \
ganlikun 0:13413ea9a877 163 || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \
ganlikun 0:13413ea9a877 164 || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \
ganlikun 0:13413ea9a877 165 || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \
ganlikun 0:13413ea9a877 166 || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \
ganlikun 0:13413ea9a877 167 || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \
ganlikun 0:13413ea9a877 168 || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \
ganlikun 0:13413ea9a877 169 || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \
ganlikun 0:13413ea9a877 170 || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \
ganlikun 0:13413ea9a877 171 || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \
ganlikun 0:13413ea9a877 172 || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \
ganlikun 0:13413ea9a877 173 || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \
ganlikun 0:13413ea9a877 174 || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \
ganlikun 0:13413ea9a877 175 || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \
ganlikun 0:13413ea9a877 176 || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \
ganlikun 0:13413ea9a877 177 || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \
ganlikun 0:13413ea9a877 178 || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \
ganlikun 0:13413ea9a877 179 || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \
ganlikun 0:13413ea9a877 180 || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \
ganlikun 0:13413ea9a877 181 || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \
ganlikun 0:13413ea9a877 182 || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \
ganlikun 0:13413ea9a877 183 || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \
ganlikun 0:13413ea9a877 184 || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \
ganlikun 0:13413ea9a877 185 || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \
ganlikun 0:13413ea9a877 186 || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \
ganlikun 0:13413ea9a877 187 || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \
ganlikun 0:13413ea9a877 188 || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \
ganlikun 0:13413ea9a877 189 || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \
ganlikun 0:13413ea9a877 190 || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \
ganlikun 0:13413ea9a877 191 || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \
ganlikun 0:13413ea9a877 192 || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \
ganlikun 0:13413ea9a877 193 || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \
ganlikun 0:13413ea9a877 194 || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \
ganlikun 0:13413ea9a877 195 || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \
ganlikun 0:13413ea9a877 196 || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \
ganlikun 0:13413ea9a877 197 || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \
ganlikun 0:13413ea9a877 198 || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \
ganlikun 0:13413ea9a877 199 || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \
ganlikun 0:13413ea9a877 200 || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \
ganlikun 0:13413ea9a877 201 || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \
ganlikun 0:13413ea9a877 202 || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \
ganlikun 0:13413ea9a877 203 || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \
ganlikun 0:13413ea9a877 204 || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \
ganlikun 0:13413ea9a877 205 || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \
ganlikun 0:13413ea9a877 206 || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \
ganlikun 0:13413ea9a877 207 || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \
ganlikun 0:13413ea9a877 208 || ((__VALUE__) == LL_RCC_PLLM_DIV_63))
ganlikun 0:13413ea9a877 209
ganlikun 0:13413ea9a877 210 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((RCC_PLLN_MIN_VALUE <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLN_MAX_VALUE))
ganlikun 0:13413ea9a877 211
ganlikun 0:13413ea9a877 212 #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \
ganlikun 0:13413ea9a877 213 || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \
ganlikun 0:13413ea9a877 214 || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \
ganlikun 0:13413ea9a877 215 || ((__VALUE__) == LL_RCC_PLLP_DIV_8))
ganlikun 0:13413ea9a877 216
ganlikun 0:13413ea9a877 217 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
ganlikun 0:13413ea9a877 218
ganlikun 0:13413ea9a877 219 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
ganlikun 0:13413ea9a877 220
ganlikun 0:13413ea9a877 221 #if !defined(RCC_MAX_FREQUENCY_SCALE1)
ganlikun 0:13413ea9a877 222 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
ganlikun 0:13413ea9a877 223 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
ganlikun 0:13413ea9a877 224
ganlikun 0:13413ea9a877 225 #elif defined(RCC_MAX_FREQUENCY_SCALE3)
ganlikun 0:13413ea9a877 226 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
ganlikun 0:13413ea9a877 227 (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
ganlikun 0:13413ea9a877 228 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
ganlikun 0:13413ea9a877 229
ganlikun 0:13413ea9a877 230 #else
ganlikun 0:13413ea9a877 231 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
ganlikun 0:13413ea9a877 232 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))
ganlikun 0:13413ea9a877 233
ganlikun 0:13413ea9a877 234 #endif /* RCC_MAX_FREQUENCY_SCALE1*/
ganlikun 0:13413ea9a877 235 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
ganlikun 0:13413ea9a877 236 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
ganlikun 0:13413ea9a877 237
ganlikun 0:13413ea9a877 238 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
ganlikun 0:13413ea9a877 239 /**
ganlikun 0:13413ea9a877 240 * @}
ganlikun 0:13413ea9a877 241 */
ganlikun 0:13413ea9a877 242 /* Private function prototypes -----------------------------------------------*/
ganlikun 0:13413ea9a877 243 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
ganlikun 0:13413ea9a877 244 * @{
ganlikun 0:13413ea9a877 245 */
ganlikun 0:13413ea9a877 246 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
ganlikun 0:13413ea9a877 247 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
ganlikun 0:13413ea9a877 248 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);
ganlikun 0:13413ea9a877 249 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ganlikun 0:13413ea9a877 250 static ErrorStatus UTILS_PLL_IsBusy(void);
ganlikun 0:13413ea9a877 251 /**
ganlikun 0:13413ea9a877 252 * @}
ganlikun 0:13413ea9a877 253 */
ganlikun 0:13413ea9a877 254
ganlikun 0:13413ea9a877 255 /* Exported functions --------------------------------------------------------*/
ganlikun 0:13413ea9a877 256 /** @addtogroup UTILS_LL_Exported_Functions
ganlikun 0:13413ea9a877 257 * @{
ganlikun 0:13413ea9a877 258 */
ganlikun 0:13413ea9a877 259
ganlikun 0:13413ea9a877 260 /** @addtogroup UTILS_LL_EF_DELAY
ganlikun 0:13413ea9a877 261 * @{
ganlikun 0:13413ea9a877 262 */
ganlikun 0:13413ea9a877 263
ganlikun 0:13413ea9a877 264 /**
ganlikun 0:13413ea9a877 265 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
ganlikun 0:13413ea9a877 266 * @note When a RTOS is used, it is recommended to avoid changing the Systick
ganlikun 0:13413ea9a877 267 * configuration by calling this function, for a delay use rather osDelay RTOS service.
ganlikun 0:13413ea9a877 268 * @param HCLKFrequency HCLK frequency in Hz
ganlikun 0:13413ea9a877 269 * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
ganlikun 0:13413ea9a877 270 * @retval None
ganlikun 0:13413ea9a877 271 */
ganlikun 0:13413ea9a877 272 void LL_Init1msTick(uint32_t HCLKFrequency)
ganlikun 0:13413ea9a877 273 {
ganlikun 0:13413ea9a877 274 /* Use frequency provided in argument */
ganlikun 0:13413ea9a877 275 LL_InitTick(HCLKFrequency, 1000U);
ganlikun 0:13413ea9a877 276 }
ganlikun 0:13413ea9a877 277
ganlikun 0:13413ea9a877 278 /**
ganlikun 0:13413ea9a877 279 * @brief This function provides accurate delay (in milliseconds) based
ganlikun 0:13413ea9a877 280 * on SysTick counter flag
ganlikun 0:13413ea9a877 281 * @note When a RTOS is used, it is recommended to avoid using blocking delay
ganlikun 0:13413ea9a877 282 * and use rather osDelay service.
ganlikun 0:13413ea9a877 283 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
ganlikun 0:13413ea9a877 284 * will configure Systick to 1ms
ganlikun 0:13413ea9a877 285 * @param Delay specifies the delay time length, in milliseconds.
ganlikun 0:13413ea9a877 286 * @retval None
ganlikun 0:13413ea9a877 287 */
ganlikun 0:13413ea9a877 288 void LL_mDelay(uint32_t Delay)
ganlikun 0:13413ea9a877 289 {
ganlikun 0:13413ea9a877 290 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
ganlikun 0:13413ea9a877 291 /* Add this code to indicate that local variable is not used */
ganlikun 0:13413ea9a877 292 ((void)tmp);
ganlikun 0:13413ea9a877 293
ganlikun 0:13413ea9a877 294 /* Add a period to guaranty minimum wait */
ganlikun 0:13413ea9a877 295 if(Delay < LL_MAX_DELAY)
ganlikun 0:13413ea9a877 296 {
ganlikun 0:13413ea9a877 297 Delay++;
ganlikun 0:13413ea9a877 298 }
ganlikun 0:13413ea9a877 299
ganlikun 0:13413ea9a877 300 while (Delay)
ganlikun 0:13413ea9a877 301 {
ganlikun 0:13413ea9a877 302 if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
ganlikun 0:13413ea9a877 303 {
ganlikun 0:13413ea9a877 304 Delay--;
ganlikun 0:13413ea9a877 305 }
ganlikun 0:13413ea9a877 306 }
ganlikun 0:13413ea9a877 307 }
ganlikun 0:13413ea9a877 308
ganlikun 0:13413ea9a877 309 /**
ganlikun 0:13413ea9a877 310 * @}
ganlikun 0:13413ea9a877 311 */
ganlikun 0:13413ea9a877 312
ganlikun 0:13413ea9a877 313 /** @addtogroup UTILS_EF_SYSTEM
ganlikun 0:13413ea9a877 314 * @brief System Configuration functions
ganlikun 0:13413ea9a877 315 *
ganlikun 0:13413ea9a877 316 @verbatim
ganlikun 0:13413ea9a877 317 ===============================================================================
ganlikun 0:13413ea9a877 318 ##### System Configuration functions #####
ganlikun 0:13413ea9a877 319 ===============================================================================
ganlikun 0:13413ea9a877 320 [..]
ganlikun 0:13413ea9a877 321 System, AHB and APB buses clocks configuration
ganlikun 0:13413ea9a877 322
ganlikun 0:13413ea9a877 323 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 180000000 Hz.
ganlikun 0:13413ea9a877 324 @endverbatim
ganlikun 0:13413ea9a877 325 @internal
ganlikun 0:13413ea9a877 326 Depending on the device voltage range, the maximum frequency should be
ganlikun 0:13413ea9a877 327 adapted accordingly to the Refenece manual.
ganlikun 0:13413ea9a877 328 @endinternal
ganlikun 0:13413ea9a877 329 * @{
ganlikun 0:13413ea9a877 330 */
ganlikun 0:13413ea9a877 331
ganlikun 0:13413ea9a877 332 /**
ganlikun 0:13413ea9a877 333 * @brief This function sets directly SystemCoreClock CMSIS variable.
ganlikun 0:13413ea9a877 334 * @note Variable can be calculated also through SystemCoreClockUpdate function.
ganlikun 0:13413ea9a877 335 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
ganlikun 0:13413ea9a877 336 * @retval None
ganlikun 0:13413ea9a877 337 */
ganlikun 0:13413ea9a877 338 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
ganlikun 0:13413ea9a877 339 {
ganlikun 0:13413ea9a877 340 /* HCLK clock frequency */
ganlikun 0:13413ea9a877 341 SystemCoreClock = HCLKFrequency;
ganlikun 0:13413ea9a877 342 }
ganlikun 0:13413ea9a877 343
ganlikun 0:13413ea9a877 344 /**
ganlikun 0:13413ea9a877 345 * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
ganlikun 0:13413ea9a877 346 * @note The application need to ensure that PLL is disabled.
ganlikun 0:13413ea9a877 347 * @note Function is based on the following formula:
ganlikun 0:13413ea9a877 348 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
ganlikun 0:13413ea9a877 349 * - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)
ganlikun 0:13413ea9a877 350 * - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)
ganlikun 0:13413ea9a877 351 * - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)
ganlikun 0:13413ea9a877 352 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
ganlikun 0:13413ea9a877 353 * the configuration information for the PLL.
ganlikun 0:13413ea9a877 354 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
ganlikun 0:13413ea9a877 355 * the configuration information for the BUS prescalers.
ganlikun 0:13413ea9a877 356 * @retval An ErrorStatus enumeration value:
ganlikun 0:13413ea9a877 357 * - SUCCESS: Max frequency configuration done
ganlikun 0:13413ea9a877 358 * - ERROR: Max frequency configuration not done
ganlikun 0:13413ea9a877 359 */
ganlikun 0:13413ea9a877 360 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
ganlikun 0:13413ea9a877 361 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
ganlikun 0:13413ea9a877 362 {
ganlikun 0:13413ea9a877 363 ErrorStatus status = SUCCESS;
ganlikun 0:13413ea9a877 364 uint32_t pllfreq = 0U;
ganlikun 0:13413ea9a877 365
ganlikun 0:13413ea9a877 366 /* Check if one of the PLL is enabled */
ganlikun 0:13413ea9a877 367 if(UTILS_PLL_IsBusy() == SUCCESS)
ganlikun 0:13413ea9a877 368 {
ganlikun 0:13413ea9a877 369 /* Calculate the new PLL output frequency */
ganlikun 0:13413ea9a877 370 pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
ganlikun 0:13413ea9a877 371
ganlikun 0:13413ea9a877 372 /* Enable HSI if not enabled */
ganlikun 0:13413ea9a877 373 if(LL_RCC_HSI_IsReady() != 1U)
ganlikun 0:13413ea9a877 374 {
ganlikun 0:13413ea9a877 375 LL_RCC_HSI_Enable();
ganlikun 0:13413ea9a877 376 while (LL_RCC_HSI_IsReady() != 1U)
ganlikun 0:13413ea9a877 377 {
ganlikun 0:13413ea9a877 378 /* Wait for HSI ready */
ganlikun 0:13413ea9a877 379 }
ganlikun 0:13413ea9a877 380 }
ganlikun 0:13413ea9a877 381
ganlikun 0:13413ea9a877 382 /* Configure PLL */
ganlikun 0:13413ea9a877 383 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
ganlikun 0:13413ea9a877 384 UTILS_PLLInitStruct->PLLP);
ganlikun 0:13413ea9a877 385
ganlikun 0:13413ea9a877 386 /* Enable PLL and switch system clock to PLL */
ganlikun 0:13413ea9a877 387 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
ganlikun 0:13413ea9a877 388 }
ganlikun 0:13413ea9a877 389 else
ganlikun 0:13413ea9a877 390 {
ganlikun 0:13413ea9a877 391 /* Current PLL configuration cannot be modified */
ganlikun 0:13413ea9a877 392 status = ERROR;
ganlikun 0:13413ea9a877 393 }
ganlikun 0:13413ea9a877 394
ganlikun 0:13413ea9a877 395 return status;
ganlikun 0:13413ea9a877 396 }
ganlikun 0:13413ea9a877 397
ganlikun 0:13413ea9a877 398 /**
ganlikun 0:13413ea9a877 399 * @brief This function configures system clock with HSE as clock source of the PLL
ganlikun 0:13413ea9a877 400 * @note The application need to ensure that PLL is disabled.
ganlikun 0:13413ea9a877 401 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
ganlikun 0:13413ea9a877 402 * - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)
ganlikun 0:13413ea9a877 403 * - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)
ganlikun 0:13413ea9a877 404 * - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)
ganlikun 0:13413ea9a877 405 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000
ganlikun 0:13413ea9a877 406 * @param HSEBypass This parameter can be one of the following values:
ganlikun 0:13413ea9a877 407 * @arg @ref LL_UTILS_HSEBYPASS_ON
ganlikun 0:13413ea9a877 408 * @arg @ref LL_UTILS_HSEBYPASS_OFF
ganlikun 0:13413ea9a877 409 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
ganlikun 0:13413ea9a877 410 * the configuration information for the PLL.
ganlikun 0:13413ea9a877 411 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
ganlikun 0:13413ea9a877 412 * the configuration information for the BUS prescalers.
ganlikun 0:13413ea9a877 413 * @retval An ErrorStatus enumeration value:
ganlikun 0:13413ea9a877 414 * - SUCCESS: Max frequency configuration done
ganlikun 0:13413ea9a877 415 * - ERROR: Max frequency configuration not done
ganlikun 0:13413ea9a877 416 */
ganlikun 0:13413ea9a877 417 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
ganlikun 0:13413ea9a877 418 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
ganlikun 0:13413ea9a877 419 {
ganlikun 0:13413ea9a877 420 ErrorStatus status = SUCCESS;
ganlikun 0:13413ea9a877 421 uint32_t pllfreq = 0U;
ganlikun 0:13413ea9a877 422
ganlikun 0:13413ea9a877 423 /* Check the parameters */
ganlikun 0:13413ea9a877 424 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
ganlikun 0:13413ea9a877 425 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
ganlikun 0:13413ea9a877 426
ganlikun 0:13413ea9a877 427 /* Check if one of the PLL is enabled */
ganlikun 0:13413ea9a877 428 if(UTILS_PLL_IsBusy() == SUCCESS)
ganlikun 0:13413ea9a877 429 {
ganlikun 0:13413ea9a877 430 /* Calculate the new PLL output frequency */
ganlikun 0:13413ea9a877 431 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
ganlikun 0:13413ea9a877 432
ganlikun 0:13413ea9a877 433 /* Enable HSE if not enabled */
ganlikun 0:13413ea9a877 434 if(LL_RCC_HSE_IsReady() != 1U)
ganlikun 0:13413ea9a877 435 {
ganlikun 0:13413ea9a877 436 /* Check if need to enable HSE bypass feature or not */
ganlikun 0:13413ea9a877 437 if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
ganlikun 0:13413ea9a877 438 {
ganlikun 0:13413ea9a877 439 LL_RCC_HSE_EnableBypass();
ganlikun 0:13413ea9a877 440 }
ganlikun 0:13413ea9a877 441 else
ganlikun 0:13413ea9a877 442 {
ganlikun 0:13413ea9a877 443 LL_RCC_HSE_DisableBypass();
ganlikun 0:13413ea9a877 444 }
ganlikun 0:13413ea9a877 445
ganlikun 0:13413ea9a877 446 /* Enable HSE */
ganlikun 0:13413ea9a877 447 LL_RCC_HSE_Enable();
ganlikun 0:13413ea9a877 448 while (LL_RCC_HSE_IsReady() != 1U)
ganlikun 0:13413ea9a877 449 {
ganlikun 0:13413ea9a877 450 /* Wait for HSE ready */
ganlikun 0:13413ea9a877 451 }
ganlikun 0:13413ea9a877 452 }
ganlikun 0:13413ea9a877 453
ganlikun 0:13413ea9a877 454 /* Configure PLL */
ganlikun 0:13413ea9a877 455 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
ganlikun 0:13413ea9a877 456 UTILS_PLLInitStruct->PLLP);
ganlikun 0:13413ea9a877 457
ganlikun 0:13413ea9a877 458 /* Enable PLL and switch system clock to PLL */
ganlikun 0:13413ea9a877 459 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
ganlikun 0:13413ea9a877 460 }
ganlikun 0:13413ea9a877 461 else
ganlikun 0:13413ea9a877 462 {
ganlikun 0:13413ea9a877 463 /* Current PLL configuration cannot be modified */
ganlikun 0:13413ea9a877 464 status = ERROR;
ganlikun 0:13413ea9a877 465 }
ganlikun 0:13413ea9a877 466
ganlikun 0:13413ea9a877 467 return status;
ganlikun 0:13413ea9a877 468 }
ganlikun 0:13413ea9a877 469
ganlikun 0:13413ea9a877 470 /**
ganlikun 0:13413ea9a877 471 * @}
ganlikun 0:13413ea9a877 472 */
ganlikun 0:13413ea9a877 473
ganlikun 0:13413ea9a877 474 /**
ganlikun 0:13413ea9a877 475 * @}
ganlikun 0:13413ea9a877 476 */
ganlikun 0:13413ea9a877 477
ganlikun 0:13413ea9a877 478 /** @addtogroup UTILS_LL_Private_Functions
ganlikun 0:13413ea9a877 479 * @{
ganlikun 0:13413ea9a877 480 */
ganlikun 0:13413ea9a877 481 /**
ganlikun 0:13413ea9a877 482 * @brief Update number of Flash wait states in line with new frequency and current
ganlikun 0:13413ea9a877 483 voltage range.
ganlikun 0:13413ea9a877 484 * @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V
ganlikun 0:13413ea9a877 485 * @param HCLK_Frequency HCLK frequency
ganlikun 0:13413ea9a877 486 * @retval An ErrorStatus enumeration value:
ganlikun 0:13413ea9a877 487 * - SUCCESS: Latency has been modified
ganlikun 0:13413ea9a877 488 * - ERROR: Latency cannot be modified
ganlikun 0:13413ea9a877 489 */
ganlikun 0:13413ea9a877 490 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)
ganlikun 0:13413ea9a877 491 {
ganlikun 0:13413ea9a877 492 ErrorStatus status = SUCCESS;
ganlikun 0:13413ea9a877 493
ganlikun 0:13413ea9a877 494 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
ganlikun 0:13413ea9a877 495
ganlikun 0:13413ea9a877 496 /* Frequency cannot be equal to 0 */
ganlikun 0:13413ea9a877 497 if(HCLK_Frequency == 0U)
ganlikun 0:13413ea9a877 498 {
ganlikun 0:13413ea9a877 499 status = ERROR;
ganlikun 0:13413ea9a877 500 }
ganlikun 0:13413ea9a877 501 else
ganlikun 0:13413ea9a877 502 {
ganlikun 0:13413ea9a877 503 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
ganlikun 0:13413ea9a877 504 {
ganlikun 0:13413ea9a877 505 #if defined (UTILS_SCALE1_LATENCY5_FREQ)
ganlikun 0:13413ea9a877 506 if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
ganlikun 0:13413ea9a877 507 {
ganlikun 0:13413ea9a877 508 latency = LL_FLASH_LATENCY_5;
ganlikun 0:13413ea9a877 509 }
ganlikun 0:13413ea9a877 510 #endif /*UTILS_SCALE1_LATENCY5_FREQ */
ganlikun 0:13413ea9a877 511 #if defined (UTILS_SCALE1_LATENCY4_FREQ)
ganlikun 0:13413ea9a877 512 if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
ganlikun 0:13413ea9a877 513 {
ganlikun 0:13413ea9a877 514 latency = LL_FLASH_LATENCY_4;
ganlikun 0:13413ea9a877 515 }
ganlikun 0:13413ea9a877 516 #endif /* UTILS_SCALE1_LATENCY4_FREQ */
ganlikun 0:13413ea9a877 517 #if defined (UTILS_SCALE1_LATENCY3_FREQ)
ganlikun 0:13413ea9a877 518 if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
ganlikun 0:13413ea9a877 519 {
ganlikun 0:13413ea9a877 520 latency = LL_FLASH_LATENCY_3;
ganlikun 0:13413ea9a877 521 }
ganlikun 0:13413ea9a877 522 #endif /* UTILS_SCALE1_LATENCY3_FREQ */
ganlikun 0:13413ea9a877 523 #if defined (UTILS_SCALE1_LATENCY2_FREQ)
ganlikun 0:13413ea9a877 524 if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
ganlikun 0:13413ea9a877 525 {
ganlikun 0:13413ea9a877 526 latency = LL_FLASH_LATENCY_2;
ganlikun 0:13413ea9a877 527 }
ganlikun 0:13413ea9a877 528 else
ganlikun 0:13413ea9a877 529 {
ganlikun 0:13413ea9a877 530 if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
ganlikun 0:13413ea9a877 531 {
ganlikun 0:13413ea9a877 532 latency = LL_FLASH_LATENCY_1;
ganlikun 0:13413ea9a877 533 }
ganlikun 0:13413ea9a877 534 }
ganlikun 0:13413ea9a877 535 #endif /* UTILS_SCALE1_LATENCY2_FREQ */
ganlikun 0:13413ea9a877 536 }
ganlikun 0:13413ea9a877 537 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
ganlikun 0:13413ea9a877 538 {
ganlikun 0:13413ea9a877 539 #if defined (UTILS_SCALE2_LATENCY5_FREQ)
ganlikun 0:13413ea9a877 540 if((HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
ganlikun 0:13413ea9a877 541 {
ganlikun 0:13413ea9a877 542 latency = LL_FLASH_LATENCY_5;
ganlikun 0:13413ea9a877 543 }
ganlikun 0:13413ea9a877 544 #endif /*UTILS_SCALE1_LATENCY5_FREQ */
ganlikun 0:13413ea9a877 545 #if defined (UTILS_SCALE2_LATENCY4_FREQ)
ganlikun 0:13413ea9a877 546 if((HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
ganlikun 0:13413ea9a877 547 {
ganlikun 0:13413ea9a877 548 latency = LL_FLASH_LATENCY_4;
ganlikun 0:13413ea9a877 549 }
ganlikun 0:13413ea9a877 550 #endif /*UTILS_SCALE1_LATENCY4_FREQ */
ganlikun 0:13413ea9a877 551 #if defined (UTILS_SCALE2_LATENCY3_FREQ)
ganlikun 0:13413ea9a877 552 if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
ganlikun 0:13413ea9a877 553 {
ganlikun 0:13413ea9a877 554 latency = LL_FLASH_LATENCY_3;
ganlikun 0:13413ea9a877 555 }
ganlikun 0:13413ea9a877 556 #endif /*UTILS_SCALE1_LATENCY3_FREQ */
ganlikun 0:13413ea9a877 557 if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
ganlikun 0:13413ea9a877 558 {
ganlikun 0:13413ea9a877 559 latency = LL_FLASH_LATENCY_2;
ganlikun 0:13413ea9a877 560 }
ganlikun 0:13413ea9a877 561 else
ganlikun 0:13413ea9a877 562 {
ganlikun 0:13413ea9a877 563 if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
ganlikun 0:13413ea9a877 564 {
ganlikun 0:13413ea9a877 565 latency = LL_FLASH_LATENCY_1;
ganlikun 0:13413ea9a877 566 }
ganlikun 0:13413ea9a877 567 }
ganlikun 0:13413ea9a877 568 }
ganlikun 0:13413ea9a877 569 #if defined (LL_PWR_REGU_VOLTAGE_SCALE3)
ganlikun 0:13413ea9a877 570 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE3)
ganlikun 0:13413ea9a877 571 {
ganlikun 0:13413ea9a877 572 #if defined (UTILS_SCALE3_LATENCY3_FREQ)
ganlikun 0:13413ea9a877 573 if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
ganlikun 0:13413ea9a877 574 {
ganlikun 0:13413ea9a877 575 latency = LL_FLASH_LATENCY_3;
ganlikun 0:13413ea9a877 576 }
ganlikun 0:13413ea9a877 577 #endif /*UTILS_SCALE1_LATENCY3_FREQ */
ganlikun 0:13413ea9a877 578 #if defined (UTILS_SCALE3_LATENCY2_FREQ)
ganlikun 0:13413ea9a877 579 if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
ganlikun 0:13413ea9a877 580 {
ganlikun 0:13413ea9a877 581 latency = LL_FLASH_LATENCY_2;
ganlikun 0:13413ea9a877 582 }
ganlikun 0:13413ea9a877 583 else
ganlikun 0:13413ea9a877 584 {
ganlikun 0:13413ea9a877 585 if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
ganlikun 0:13413ea9a877 586 {
ganlikun 0:13413ea9a877 587 latency = LL_FLASH_LATENCY_1;
ganlikun 0:13413ea9a877 588 }
ganlikun 0:13413ea9a877 589 }
ganlikun 0:13413ea9a877 590 }
ganlikun 0:13413ea9a877 591 #endif /*UTILS_SCALE1_LATENCY2_FREQ */
ganlikun 0:13413ea9a877 592 #endif /* LL_PWR_REGU_VOLTAGE_SCALE3 */
ganlikun 0:13413ea9a877 593
ganlikun 0:13413ea9a877 594 LL_FLASH_SetLatency(latency);
ganlikun 0:13413ea9a877 595
ganlikun 0:13413ea9a877 596 /* Check that the new number of wait states is taken into account to access the Flash
ganlikun 0:13413ea9a877 597 memory by reading the FLASH_ACR register */
ganlikun 0:13413ea9a877 598 if(LL_FLASH_GetLatency() != latency)
ganlikun 0:13413ea9a877 599 {
ganlikun 0:13413ea9a877 600 status = ERROR;
ganlikun 0:13413ea9a877 601 }
ganlikun 0:13413ea9a877 602 }
ganlikun 0:13413ea9a877 603 return status;
ganlikun 0:13413ea9a877 604 }
ganlikun 0:13413ea9a877 605
ganlikun 0:13413ea9a877 606 /**
ganlikun 0:13413ea9a877 607 * @brief Function to check that PLL can be modified
ganlikun 0:13413ea9a877 608 * @param PLL_InputFrequency PLL input frequency (in Hz)
ganlikun 0:13413ea9a877 609 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
ganlikun 0:13413ea9a877 610 * the configuration information for the PLL.
ganlikun 0:13413ea9a877 611 * @retval PLL output frequency (in Hz)
ganlikun 0:13413ea9a877 612 */
ganlikun 0:13413ea9a877 613 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
ganlikun 0:13413ea9a877 614 {
ganlikun 0:13413ea9a877 615 uint32_t pllfreq = 0U;
ganlikun 0:13413ea9a877 616
ganlikun 0:13413ea9a877 617 /* Check the parameters */
ganlikun 0:13413ea9a877 618 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
ganlikun 0:13413ea9a877 619 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
ganlikun 0:13413ea9a877 620 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
ganlikun 0:13413ea9a877 621
ganlikun 0:13413ea9a877 622 /* Check different PLL parameters according to RM */
ganlikun 0:13413ea9a877 623 /* - PLLM: ensure that the VCO input frequency ranges from @ref UTILS_PLLVCO_INPUT_MIN to @ref UTILS_PLLVCO_INPUT_MAX MHz. */
ganlikun 0:13413ea9a877 624 pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos));
ganlikun 0:13413ea9a877 625 assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
ganlikun 0:13413ea9a877 626
ganlikun 0:13413ea9a877 627 /* - PLLN: ensure that the VCO output frequency is between @ref UTILS_PLLVCO_OUTPUT_MIN and @ref UTILS_PLLVCO_OUTPUT_MAX .*/
ganlikun 0:13413ea9a877 628 pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
ganlikun 0:13413ea9a877 629 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
ganlikun 0:13413ea9a877 630
ganlikun 0:13413ea9a877 631 /* - PLLP: ensure that max frequency at @ref RCC_MAX_FREQUENCY Hz is reached */
ganlikun 0:13413ea9a877 632 pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
ganlikun 0:13413ea9a877 633 assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
ganlikun 0:13413ea9a877 634
ganlikun 0:13413ea9a877 635 return pllfreq;
ganlikun 0:13413ea9a877 636 }
ganlikun 0:13413ea9a877 637
ganlikun 0:13413ea9a877 638 /**
ganlikun 0:13413ea9a877 639 * @brief Function to check that PLL can be modified
ganlikun 0:13413ea9a877 640 * @retval An ErrorStatus enumeration value:
ganlikun 0:13413ea9a877 641 * - SUCCESS: PLL modification can be done
ganlikun 0:13413ea9a877 642 * - ERROR: PLL is busy
ganlikun 0:13413ea9a877 643 */
ganlikun 0:13413ea9a877 644 static ErrorStatus UTILS_PLL_IsBusy(void)
ganlikun 0:13413ea9a877 645 {
ganlikun 0:13413ea9a877 646 ErrorStatus status = SUCCESS;
ganlikun 0:13413ea9a877 647
ganlikun 0:13413ea9a877 648 /* Check if PLL is busy*/
ganlikun 0:13413ea9a877 649 if(LL_RCC_PLL_IsReady() != 0U)
ganlikun 0:13413ea9a877 650 {
ganlikun 0:13413ea9a877 651 /* PLL configuration cannot be modified */
ganlikun 0:13413ea9a877 652 status = ERROR;
ganlikun 0:13413ea9a877 653 }
ganlikun 0:13413ea9a877 654
ganlikun 0:13413ea9a877 655 #if defined(RCC_PLLSAI_SUPPORT)
ganlikun 0:13413ea9a877 656 /* Check if PLLSAI is busy*/
ganlikun 0:13413ea9a877 657 if(LL_RCC_PLLSAI_IsReady() != 0U)
ganlikun 0:13413ea9a877 658 {
ganlikun 0:13413ea9a877 659 /* PLLSAI1 configuration cannot be modified */
ganlikun 0:13413ea9a877 660 status = ERROR;
ganlikun 0:13413ea9a877 661 }
ganlikun 0:13413ea9a877 662 #endif /*RCC_PLLSAI_SUPPORT*/
ganlikun 0:13413ea9a877 663 #if defined(RCC_PLLI2S_SUPPORT)
ganlikun 0:13413ea9a877 664 /* Check if PLLI2S is busy*/
ganlikun 0:13413ea9a877 665 if(LL_RCC_PLLI2S_IsReady() != 0U)
ganlikun 0:13413ea9a877 666 {
ganlikun 0:13413ea9a877 667 /* PLLI2S configuration cannot be modified */
ganlikun 0:13413ea9a877 668 status = ERROR;
ganlikun 0:13413ea9a877 669 }
ganlikun 0:13413ea9a877 670 #endif /*RCC_PLLI2S_SUPPORT*/
ganlikun 0:13413ea9a877 671 return status;
ganlikun 0:13413ea9a877 672 }
ganlikun 0:13413ea9a877 673
ganlikun 0:13413ea9a877 674 /**
ganlikun 0:13413ea9a877 675 * @brief Function to enable PLL and switch system clock to PLL
ganlikun 0:13413ea9a877 676 * @param SYSCLK_Frequency SYSCLK frequency
ganlikun 0:13413ea9a877 677 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
ganlikun 0:13413ea9a877 678 * the configuration information for the BUS prescalers.
ganlikun 0:13413ea9a877 679 * @retval An ErrorStatus enumeration value:
ganlikun 0:13413ea9a877 680 * - SUCCESS: No problem to switch system to PLL
ganlikun 0:13413ea9a877 681 * - ERROR: Problem to switch system to PLL
ganlikun 0:13413ea9a877 682 */
ganlikun 0:13413ea9a877 683 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
ganlikun 0:13413ea9a877 684 {
ganlikun 0:13413ea9a877 685 ErrorStatus status = SUCCESS;
ganlikun 0:13413ea9a877 686 uint32_t hclk_frequency = 0U;
ganlikun 0:13413ea9a877 687
ganlikun 0:13413ea9a877 688 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
ganlikun 0:13413ea9a877 689 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
ganlikun 0:13413ea9a877 690 assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
ganlikun 0:13413ea9a877 691
ganlikun 0:13413ea9a877 692 /* Calculate HCLK frequency */
ganlikun 0:13413ea9a877 693 hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
ganlikun 0:13413ea9a877 694
ganlikun 0:13413ea9a877 695 /* Increasing the number of wait states because of higher CPU frequency */
ganlikun 0:13413ea9a877 696 if(SystemCoreClock < hclk_frequency)
ganlikun 0:13413ea9a877 697 {
ganlikun 0:13413ea9a877 698 /* Set FLASH latency to highest latency */
ganlikun 0:13413ea9a877 699 status = UTILS_SetFlashLatency(hclk_frequency);
ganlikun 0:13413ea9a877 700 }
ganlikun 0:13413ea9a877 701
ganlikun 0:13413ea9a877 702 /* Update system clock configuration */
ganlikun 0:13413ea9a877 703 if(status == SUCCESS)
ganlikun 0:13413ea9a877 704 {
ganlikun 0:13413ea9a877 705 /* Enable PLL */
ganlikun 0:13413ea9a877 706 LL_RCC_PLL_Enable();
ganlikun 0:13413ea9a877 707 while (LL_RCC_PLL_IsReady() != 1U)
ganlikun 0:13413ea9a877 708 {
ganlikun 0:13413ea9a877 709 /* Wait for PLL ready */
ganlikun 0:13413ea9a877 710 }
ganlikun 0:13413ea9a877 711
ganlikun 0:13413ea9a877 712 /* Sysclk activation on the main PLL */
ganlikun 0:13413ea9a877 713 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
ganlikun 0:13413ea9a877 714 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
ganlikun 0:13413ea9a877 715 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
ganlikun 0:13413ea9a877 716 {
ganlikun 0:13413ea9a877 717 /* Wait for system clock switch to PLL */
ganlikun 0:13413ea9a877 718 }
ganlikun 0:13413ea9a877 719
ganlikun 0:13413ea9a877 720 /* Set APB1 & APB2 prescaler*/
ganlikun 0:13413ea9a877 721 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
ganlikun 0:13413ea9a877 722 LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
ganlikun 0:13413ea9a877 723 }
ganlikun 0:13413ea9a877 724
ganlikun 0:13413ea9a877 725 /* Decreasing the number of wait states because of lower CPU frequency */
ganlikun 0:13413ea9a877 726 if(SystemCoreClock > hclk_frequency)
ganlikun 0:13413ea9a877 727 {
ganlikun 0:13413ea9a877 728 /* Set FLASH latency to lowest latency */
ganlikun 0:13413ea9a877 729 status = UTILS_SetFlashLatency(hclk_frequency);
ganlikun 0:13413ea9a877 730 }
ganlikun 0:13413ea9a877 731
ganlikun 0:13413ea9a877 732 /* Update SystemCoreClock variable */
ganlikun 0:13413ea9a877 733 if(status == SUCCESS)
ganlikun 0:13413ea9a877 734 {
ganlikun 0:13413ea9a877 735 LL_SetSystemCoreClock(hclk_frequency);
ganlikun 0:13413ea9a877 736 }
ganlikun 0:13413ea9a877 737
ganlikun 0:13413ea9a877 738 return status;
ganlikun 0:13413ea9a877 739 }
ganlikun 0:13413ea9a877 740
ganlikun 0:13413ea9a877 741 /**
ganlikun 0:13413ea9a877 742 * @}
ganlikun 0:13413ea9a877 743 */
ganlikun 0:13413ea9a877 744
ganlikun 0:13413ea9a877 745 /**
ganlikun 0:13413ea9a877 746 * @}
ganlikun 0:13413ea9a877 747 */
ganlikun 0:13413ea9a877 748
ganlikun 0:13413ea9a877 749 /**
ganlikun 0:13413ea9a877 750 * @}
ganlikun 0:13413ea9a877 751 */
ganlikun 0:13413ea9a877 752
ganlikun 0:13413ea9a877 753 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
ganlikun 0:13413ea9a877 754