Gan likun / mbed1-dev

001

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usart.c@0:13413ea9a877, 2022-06-12 (annotated)

Committer:
ganlikun
Date:
Sun Jun 12 14:02:44 2022 +0000
Revision:
0:13413ea9a877
00

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ganlikun 0:13413ea9a877 1 /**
ganlikun 0:13413ea9a877 2 ******************************************************************************
ganlikun 0:13413ea9a877 3 * @file stm32f4xx_ll_usart.c
ganlikun 0:13413ea9a877 4 * @author MCD Application Team
ganlikun 0:13413ea9a877 5 * @version V1.7.1
ganlikun 0:13413ea9a877 6 * @date 14-April-2017
ganlikun 0:13413ea9a877 7 * @brief USART LL module driver.
ganlikun 0:13413ea9a877 8 ******************************************************************************
ganlikun 0:13413ea9a877 9 * @attention
ganlikun 0:13413ea9a877 10 *
ganlikun 0:13413ea9a877 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun 0:13413ea9a877 12 *
ganlikun 0:13413ea9a877 13 * Redistribution and use in source and binary forms, with or without modification,
ganlikun 0:13413ea9a877 14 * are permitted provided that the following conditions are met:
ganlikun 0:13413ea9a877 15 * 1. Redistributions of source code must retain the above copyright notice,
ganlikun 0:13413ea9a877 16 * this list of conditions and the following disclaimer.
ganlikun 0:13413ea9a877 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun 0:13413ea9a877 18 * this list of conditions and the following disclaimer in the documentation
ganlikun 0:13413ea9a877 19 * and/or other materials provided with the distribution.
ganlikun 0:13413ea9a877 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun 0:13413ea9a877 21 * may be used to endorse or promote products derived from this software
ganlikun 0:13413ea9a877 22 * without specific prior written permission.
ganlikun 0:13413ea9a877 23 *
ganlikun 0:13413ea9a877 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun 0:13413ea9a877 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun 0:13413ea9a877 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun 0:13413ea9a877 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun 0:13413ea9a877 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun 0:13413ea9a877 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun 0:13413ea9a877 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun 0:13413ea9a877 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun 0:13413ea9a877 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun 0:13413ea9a877 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun 0:13413ea9a877 34 *
ganlikun 0:13413ea9a877 35 ******************************************************************************
ganlikun 0:13413ea9a877 36 */
ganlikun 0:13413ea9a877 37 #if defined(USE_FULL_LL_DRIVER)
ganlikun 0:13413ea9a877 38
ganlikun 0:13413ea9a877 39 /* Includes ------------------------------------------------------------------*/
ganlikun 0:13413ea9a877 40 #include "stm32f4xx_ll_usart.h"
ganlikun 0:13413ea9a877 41 #include "stm32f4xx_ll_rcc.h"
ganlikun 0:13413ea9a877 42 #include "stm32f4xx_ll_bus.h"
ganlikun 0:13413ea9a877 43 #ifdef USE_FULL_ASSERT
ganlikun 0:13413ea9a877 44 #include "stm32_assert.h"
ganlikun 0:13413ea9a877 45 #else
ganlikun 0:13413ea9a877 46 #define assert_param(expr) ((void)0U)
ganlikun 0:13413ea9a877 47 #endif
ganlikun 0:13413ea9a877 48
ganlikun 0:13413ea9a877 49 /** @addtogroup STM32F4xx_LL_Driver
ganlikun 0:13413ea9a877 50 * @{
ganlikun 0:13413ea9a877 51 */
ganlikun 0:13413ea9a877 52
ganlikun 0:13413ea9a877 53 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (UART10)
ganlikun 0:13413ea9a877 54
ganlikun 0:13413ea9a877 55 /** @addtogroup USART_LL
ganlikun 0:13413ea9a877 56 * @{
ganlikun 0:13413ea9a877 57 */
ganlikun 0:13413ea9a877 58
ganlikun 0:13413ea9a877 59 /* Private types -------------------------------------------------------------*/
ganlikun 0:13413ea9a877 60 /* Private variables ---------------------------------------------------------*/
ganlikun 0:13413ea9a877 61 /* Private constants ---------------------------------------------------------*/
ganlikun 0:13413ea9a877 62 /** @addtogroup USART_LL_Private_Constants
ganlikun 0:13413ea9a877 63 * @{
ganlikun 0:13413ea9a877 64 */
ganlikun 0:13413ea9a877 65
ganlikun 0:13413ea9a877 66 /**
ganlikun 0:13413ea9a877 67 * @}
ganlikun 0:13413ea9a877 68 */
ganlikun 0:13413ea9a877 69
ganlikun 0:13413ea9a877 70
ganlikun 0:13413ea9a877 71 /* Private macros ------------------------------------------------------------*/
ganlikun 0:13413ea9a877 72 /** @addtogroup USART_LL_Private_Macros
ganlikun 0:13413ea9a877 73 * @{
ganlikun 0:13413ea9a877 74 */
ganlikun 0:13413ea9a877 75
ganlikun 0:13413ea9a877 76 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
ganlikun 0:13413ea9a877 77 * divided by the smallest oversampling used on the USART (i.e. 8) */
ganlikun 0:13413ea9a877 78 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U)
ganlikun 0:13413ea9a877 79
ganlikun 0:13413ea9a877 80 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
ganlikun 0:13413ea9a877 81 || ((__VALUE__) == LL_USART_DIRECTION_RX) \
ganlikun 0:13413ea9a877 82 || ((__VALUE__) == LL_USART_DIRECTION_TX) \
ganlikun 0:13413ea9a877 83 || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
ganlikun 0:13413ea9a877 84
ganlikun 0:13413ea9a877 85 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
ganlikun 0:13413ea9a877 86 || ((__VALUE__) == LL_USART_PARITY_EVEN) \
ganlikun 0:13413ea9a877 87 || ((__VALUE__) == LL_USART_PARITY_ODD))
ganlikun 0:13413ea9a877 88
ganlikun 0:13413ea9a877 89 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
ganlikun 0:13413ea9a877 90 || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
ganlikun 0:13413ea9a877 91
ganlikun 0:13413ea9a877 92 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
ganlikun 0:13413ea9a877 93 || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
ganlikun 0:13413ea9a877 94
ganlikun 0:13413ea9a877 95 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
ganlikun 0:13413ea9a877 96 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
ganlikun 0:13413ea9a877 97
ganlikun 0:13413ea9a877 98 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
ganlikun 0:13413ea9a877 99 || ((__VALUE__) == LL_USART_PHASE_2EDGE))
ganlikun 0:13413ea9a877 100
ganlikun 0:13413ea9a877 101 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
ganlikun 0:13413ea9a877 102 || ((__VALUE__) == LL_USART_POLARITY_HIGH))
ganlikun 0:13413ea9a877 103
ganlikun 0:13413ea9a877 104 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
ganlikun 0:13413ea9a877 105 || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
ganlikun 0:13413ea9a877 106
ganlikun 0:13413ea9a877 107 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
ganlikun 0:13413ea9a877 108 || ((__VALUE__) == LL_USART_STOPBITS_1) \
ganlikun 0:13413ea9a877 109 || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
ganlikun 0:13413ea9a877 110 || ((__VALUE__) == LL_USART_STOPBITS_2))
ganlikun 0:13413ea9a877 111
ganlikun 0:13413ea9a877 112 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
ganlikun 0:13413ea9a877 113 || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
ganlikun 0:13413ea9a877 114 || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
ganlikun 0:13413ea9a877 115 || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
ganlikun 0:13413ea9a877 116
ganlikun 0:13413ea9a877 117 /**
ganlikun 0:13413ea9a877 118 * @}
ganlikun 0:13413ea9a877 119 */
ganlikun 0:13413ea9a877 120
ganlikun 0:13413ea9a877 121 /* Private function prototypes -----------------------------------------------*/
ganlikun 0:13413ea9a877 122
ganlikun 0:13413ea9a877 123 /* Exported functions --------------------------------------------------------*/
ganlikun 0:13413ea9a877 124 /** @addtogroup USART_LL_Exported_Functions
ganlikun 0:13413ea9a877 125 * @{
ganlikun 0:13413ea9a877 126 */
ganlikun 0:13413ea9a877 127
ganlikun 0:13413ea9a877 128 /** @addtogroup USART_LL_EF_Init
ganlikun 0:13413ea9a877 129 * @{
ganlikun 0:13413ea9a877 130 */
ganlikun 0:13413ea9a877 131
ganlikun 0:13413ea9a877 132 /**
ganlikun 0:13413ea9a877 133 * @brief De-initialize USART registers (Registers restored to their default values).
ganlikun 0:13413ea9a877 134 * @param USARTx USART Instance
ganlikun 0:13413ea9a877 135 * @retval An ErrorStatus enumeration value:
ganlikun 0:13413ea9a877 136 * - SUCCESS: USART registers are de-initialized
ganlikun 0:13413ea9a877 137 * - ERROR: USART registers are not de-initialized
ganlikun 0:13413ea9a877 138 */
ganlikun 0:13413ea9a877 139 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
ganlikun 0:13413ea9a877 140 {
ganlikun 0:13413ea9a877 141 ErrorStatus status = SUCCESS;
ganlikun 0:13413ea9a877 142
ganlikun 0:13413ea9a877 143 /* Check the parameters */
ganlikun 0:13413ea9a877 144 assert_param(IS_UART_INSTANCE(USARTx));
ganlikun 0:13413ea9a877 145
ganlikun 0:13413ea9a877 146 if (USARTx == USART1)
ganlikun 0:13413ea9a877 147 {
ganlikun 0:13413ea9a877 148 /* Force reset of USART clock */
ganlikun 0:13413ea9a877 149 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
ganlikun 0:13413ea9a877 150
ganlikun 0:13413ea9a877 151 /* Release reset of USART clock */
ganlikun 0:13413ea9a877 152 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
ganlikun 0:13413ea9a877 153 }
ganlikun 0:13413ea9a877 154 else if (USARTx == USART2)
ganlikun 0:13413ea9a877 155 {
ganlikun 0:13413ea9a877 156 /* Force reset of USART clock */
ganlikun 0:13413ea9a877 157 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
ganlikun 0:13413ea9a877 158
ganlikun 0:13413ea9a877 159 /* Release reset of USART clock */
ganlikun 0:13413ea9a877 160 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
ganlikun 0:13413ea9a877 161 }
ganlikun 0:13413ea9a877 162 #if defined(USART3)
ganlikun 0:13413ea9a877 163 else if (USARTx == USART3)
ganlikun 0:13413ea9a877 164 {
ganlikun 0:13413ea9a877 165 /* Force reset of USART clock */
ganlikun 0:13413ea9a877 166 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
ganlikun 0:13413ea9a877 167
ganlikun 0:13413ea9a877 168 /* Release reset of USART clock */
ganlikun 0:13413ea9a877 169 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
ganlikun 0:13413ea9a877 170 }
ganlikun 0:13413ea9a877 171 #endif /* USART3 */
ganlikun 0:13413ea9a877 172 #if defined(USART6)
ganlikun 0:13413ea9a877 173 else if (USARTx == USART6)
ganlikun 0:13413ea9a877 174 {
ganlikun 0:13413ea9a877 175 /* Force reset of USART clock */
ganlikun 0:13413ea9a877 176 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6);
ganlikun 0:13413ea9a877 177
ganlikun 0:13413ea9a877 178 /* Release reset of USART clock */
ganlikun 0:13413ea9a877 179 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6);
ganlikun 0:13413ea9a877 180 }
ganlikun 0:13413ea9a877 181 #endif /* USART6 */
ganlikun 0:13413ea9a877 182 #if defined(UART4)
ganlikun 0:13413ea9a877 183 else if (USARTx == UART4)
ganlikun 0:13413ea9a877 184 {
ganlikun 0:13413ea9a877 185 /* Force reset of UART clock */
ganlikun 0:13413ea9a877 186 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
ganlikun 0:13413ea9a877 187
ganlikun 0:13413ea9a877 188 /* Release reset of UART clock */
ganlikun 0:13413ea9a877 189 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
ganlikun 0:13413ea9a877 190 }
ganlikun 0:13413ea9a877 191 #endif /* UART4 */
ganlikun 0:13413ea9a877 192 #if defined(UART5)
ganlikun 0:13413ea9a877 193 else if (USARTx == UART5)
ganlikun 0:13413ea9a877 194 {
ganlikun 0:13413ea9a877 195 /* Force reset of UART clock */
ganlikun 0:13413ea9a877 196 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
ganlikun 0:13413ea9a877 197
ganlikun 0:13413ea9a877 198 /* Release reset of UART clock */
ganlikun 0:13413ea9a877 199 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
ganlikun 0:13413ea9a877 200 }
ganlikun 0:13413ea9a877 201 #endif /* UART5 */
ganlikun 0:13413ea9a877 202 #if defined(UART7)
ganlikun 0:13413ea9a877 203 else if (USARTx == UART7)
ganlikun 0:13413ea9a877 204 {
ganlikun 0:13413ea9a877 205 /* Force reset of UART clock */
ganlikun 0:13413ea9a877 206 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7);
ganlikun 0:13413ea9a877 207
ganlikun 0:13413ea9a877 208 /* Release reset of UART clock */
ganlikun 0:13413ea9a877 209 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7);
ganlikun 0:13413ea9a877 210 }
ganlikun 0:13413ea9a877 211 #endif /* UART7 */
ganlikun 0:13413ea9a877 212 #if defined(UART8)
ganlikun 0:13413ea9a877 213 else if (USARTx == UART8)
ganlikun 0:13413ea9a877 214 {
ganlikun 0:13413ea9a877 215 /* Force reset of UART clock */
ganlikun 0:13413ea9a877 216 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8);
ganlikun 0:13413ea9a877 217
ganlikun 0:13413ea9a877 218 /* Release reset of UART clock */
ganlikun 0:13413ea9a877 219 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8);
ganlikun 0:13413ea9a877 220 }
ganlikun 0:13413ea9a877 221 #endif /* UART8 */
ganlikun 0:13413ea9a877 222 #if defined(UART9)
ganlikun 0:13413ea9a877 223 else if (USARTx == UART9)
ganlikun 0:13413ea9a877 224 {
ganlikun 0:13413ea9a877 225 /* Force reset of UART clock */
ganlikun 0:13413ea9a877 226 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART9);
ganlikun 0:13413ea9a877 227
ganlikun 0:13413ea9a877 228 /* Release reset of UART clock */
ganlikun 0:13413ea9a877 229 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART9);
ganlikun 0:13413ea9a877 230 }
ganlikun 0:13413ea9a877 231 #endif /* UART9 */
ganlikun 0:13413ea9a877 232 #if defined(UART10)
ganlikun 0:13413ea9a877 233 else if (USARTx == UART10)
ganlikun 0:13413ea9a877 234 {
ganlikun 0:13413ea9a877 235 /* Force reset of UART clock */
ganlikun 0:13413ea9a877 236 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART10);
ganlikun 0:13413ea9a877 237
ganlikun 0:13413ea9a877 238 /* Release reset of UART clock */
ganlikun 0:13413ea9a877 239 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART10);
ganlikun 0:13413ea9a877 240 }
ganlikun 0:13413ea9a877 241 #endif /* UART10 */
ganlikun 0:13413ea9a877 242 else
ganlikun 0:13413ea9a877 243 {
ganlikun 0:13413ea9a877 244 status = ERROR;
ganlikun 0:13413ea9a877 245 }
ganlikun 0:13413ea9a877 246
ganlikun 0:13413ea9a877 247 return (status);
ganlikun 0:13413ea9a877 248 }
ganlikun 0:13413ea9a877 249
ganlikun 0:13413ea9a877 250 /**
ganlikun 0:13413ea9a877 251 * @brief Initialize USART registers according to the specified
ganlikun 0:13413ea9a877 252 * parameters in USART_InitStruct.
ganlikun 0:13413ea9a877 253 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
ganlikun 0:13413ea9a877 254 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
ganlikun 0:13413ea9a877 255 * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
ganlikun 0:13413ea9a877 256 * @param USARTx USART Instance
ganlikun 0:13413ea9a877 257 * @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure
ganlikun 0:13413ea9a877 258 * that contains the configuration information for the specified USART peripheral.
ganlikun 0:13413ea9a877 259 * @retval An ErrorStatus enumeration value:
ganlikun 0:13413ea9a877 260 * - SUCCESS: USART registers are initialized according to USART_InitStruct content
ganlikun 0:13413ea9a877 261 * - ERROR: Problem occurred during USART Registers initialization
ganlikun 0:13413ea9a877 262 */
ganlikun 0:13413ea9a877 263 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
ganlikun 0:13413ea9a877 264 {
ganlikun 0:13413ea9a877 265 ErrorStatus status = ERROR;
ganlikun 0:13413ea9a877 266 uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
ganlikun 0:13413ea9a877 267 LL_RCC_ClocksTypeDef rcc_clocks;
ganlikun 0:13413ea9a877 268
ganlikun 0:13413ea9a877 269 /* Check the parameters */
ganlikun 0:13413ea9a877 270 assert_param(IS_UART_INSTANCE(USARTx));
ganlikun 0:13413ea9a877 271 assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
ganlikun 0:13413ea9a877 272 assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
ganlikun 0:13413ea9a877 273 assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
ganlikun 0:13413ea9a877 274 assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
ganlikun 0:13413ea9a877 275 assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
ganlikun 0:13413ea9a877 276 assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
ganlikun 0:13413ea9a877 277 assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
ganlikun 0:13413ea9a877 278
ganlikun 0:13413ea9a877 279 /* USART needs to be in disabled state, in order to be able to configure some bits in
ganlikun 0:13413ea9a877 280 CRx registers */
ganlikun 0:13413ea9a877 281 if (LL_USART_IsEnabled(USARTx) == 0U)
ganlikun 0:13413ea9a877 282 {
ganlikun 0:13413ea9a877 283 /*---------------------------- USART CR1 Configuration -----------------------
ganlikun 0:13413ea9a877 284 * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
ganlikun 0:13413ea9a877 285 * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
ganlikun 0:13413ea9a877 286 * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
ganlikun 0:13413ea9a877 287 * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
ganlikun 0:13413ea9a877 288 * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
ganlikun 0:13413ea9a877 289 */
ganlikun 0:13413ea9a877 290 MODIFY_REG(USARTx->CR1,
ganlikun 0:13413ea9a877 291 (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
ganlikun 0:13413ea9a877 292 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
ganlikun 0:13413ea9a877 293 (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
ganlikun 0:13413ea9a877 294 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
ganlikun 0:13413ea9a877 295
ganlikun 0:13413ea9a877 296 /*---------------------------- USART CR2 Configuration -----------------------
ganlikun 0:13413ea9a877 297 * Configure USARTx CR2 (Stop bits) with parameters:
ganlikun 0:13413ea9a877 298 * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
ganlikun 0:13413ea9a877 299 * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
ganlikun 0:13413ea9a877 300 */
ganlikun 0:13413ea9a877 301 LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
ganlikun 0:13413ea9a877 302
ganlikun 0:13413ea9a877 303 /*---------------------------- USART CR3 Configuration -----------------------
ganlikun 0:13413ea9a877 304 * Configure USARTx CR3 (Hardware Flow Control) with parameters:
ganlikun 0:13413ea9a877 305 * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
ganlikun 0:13413ea9a877 306 */
ganlikun 0:13413ea9a877 307 LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
ganlikun 0:13413ea9a877 308
ganlikun 0:13413ea9a877 309 /*---------------------------- USART BRR Configuration -----------------------
ganlikun 0:13413ea9a877 310 * Retrieve Clock frequency used for USART Peripheral
ganlikun 0:13413ea9a877 311 */
ganlikun 0:13413ea9a877 312 LL_RCC_GetSystemClocksFreq(&rcc_clocks);
ganlikun 0:13413ea9a877 313 if (USARTx == USART1)
ganlikun 0:13413ea9a877 314 {
ganlikun 0:13413ea9a877 315 periphclk = rcc_clocks.PCLK2_Frequency;
ganlikun 0:13413ea9a877 316 }
ganlikun 0:13413ea9a877 317 else if (USARTx == USART2)
ganlikun 0:13413ea9a877 318 {
ganlikun 0:13413ea9a877 319 periphclk = rcc_clocks.PCLK1_Frequency;
ganlikun 0:13413ea9a877 320 }
ganlikun 0:13413ea9a877 321 #if defined(USART3)
ganlikun 0:13413ea9a877 322 else if (USARTx == USART3)
ganlikun 0:13413ea9a877 323 {
ganlikun 0:13413ea9a877 324 periphclk = rcc_clocks.PCLK1_Frequency;
ganlikun 0:13413ea9a877 325 }
ganlikun 0:13413ea9a877 326 #endif /* USART3 */
ganlikun 0:13413ea9a877 327 #if defined(USART6)
ganlikun 0:13413ea9a877 328 else if (USARTx == USART6)
ganlikun 0:13413ea9a877 329 {
ganlikun 0:13413ea9a877 330 periphclk = rcc_clocks.PCLK2_Frequency;
ganlikun 0:13413ea9a877 331 }
ganlikun 0:13413ea9a877 332 #endif /* USART6 */
ganlikun 0:13413ea9a877 333 #if defined(UART4)
ganlikun 0:13413ea9a877 334 else if (USARTx == UART4)
ganlikun 0:13413ea9a877 335 {
ganlikun 0:13413ea9a877 336 periphclk = rcc_clocks.PCLK1_Frequency;
ganlikun 0:13413ea9a877 337 }
ganlikun 0:13413ea9a877 338 #endif /* UART4 */
ganlikun 0:13413ea9a877 339 #if defined(UART5)
ganlikun 0:13413ea9a877 340 else if (USARTx == UART5)
ganlikun 0:13413ea9a877 341 {
ganlikun 0:13413ea9a877 342 periphclk = rcc_clocks.PCLK1_Frequency;
ganlikun 0:13413ea9a877 343 }
ganlikun 0:13413ea9a877 344 #endif /* UART5 */
ganlikun 0:13413ea9a877 345 #if defined(UART7)
ganlikun 0:13413ea9a877 346 else if (USARTx == UART7)
ganlikun 0:13413ea9a877 347 {
ganlikun 0:13413ea9a877 348 periphclk = rcc_clocks.PCLK1_Frequency;
ganlikun 0:13413ea9a877 349 }
ganlikun 0:13413ea9a877 350 #endif /* UART7 */
ganlikun 0:13413ea9a877 351 #if defined(UART8)
ganlikun 0:13413ea9a877 352 else if (USARTx == UART8)
ganlikun 0:13413ea9a877 353 {
ganlikun 0:13413ea9a877 354 periphclk = rcc_clocks.PCLK1_Frequency;
ganlikun 0:13413ea9a877 355 }
ganlikun 0:13413ea9a877 356 #endif /* UART8 */
ganlikun 0:13413ea9a877 357 #if defined(UART9)
ganlikun 0:13413ea9a877 358 else if (USARTx == UART9)
ganlikun 0:13413ea9a877 359 {
ganlikun 0:13413ea9a877 360 periphclk = rcc_clocks.PCLK1_Frequency;
ganlikun 0:13413ea9a877 361 }
ganlikun 0:13413ea9a877 362 #endif /* UART9 */
ganlikun 0:13413ea9a877 363 #if defined(UART10)
ganlikun 0:13413ea9a877 364 else if (USARTx == UART5)
ganlikun 0:13413ea9a877 365 {
ganlikun 0:13413ea9a877 366 periphclk = rcc_clocks.PCLK1_Frequency;
ganlikun 0:13413ea9a877 367 }
ganlikun 0:13413ea9a877 368 #endif /* UART10 */
ganlikun 0:13413ea9a877 369 else
ganlikun 0:13413ea9a877 370 {
ganlikun 0:13413ea9a877 371 /* Nothing to do, as error code is already assigned to ERROR value */
ganlikun 0:13413ea9a877 372 }
ganlikun 0:13413ea9a877 373
ganlikun 0:13413ea9a877 374 /* Configure the USART Baud Rate :
ganlikun 0:13413ea9a877 375 - valid baud rate value (different from 0) is required
ganlikun 0:13413ea9a877 376 - Peripheral clock as returned by RCC service, should be valid (different from 0).
ganlikun 0:13413ea9a877 377 */
ganlikun 0:13413ea9a877 378 if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
ganlikun 0:13413ea9a877 379 && (USART_InitStruct->BaudRate != 0U))
ganlikun 0:13413ea9a877 380 {
ganlikun 0:13413ea9a877 381 status = SUCCESS;
ganlikun 0:13413ea9a877 382 LL_USART_SetBaudRate(USARTx,
ganlikun 0:13413ea9a877 383 periphclk,
ganlikun 0:13413ea9a877 384 USART_InitStruct->OverSampling,
ganlikun 0:13413ea9a877 385 USART_InitStruct->BaudRate);
ganlikun 0:13413ea9a877 386 }
ganlikun 0:13413ea9a877 387 }
ganlikun 0:13413ea9a877 388 /* Endif (=> USART not in Disabled state => return ERROR) */
ganlikun 0:13413ea9a877 389
ganlikun 0:13413ea9a877 390 return (status);
ganlikun 0:13413ea9a877 391 }
ganlikun 0:13413ea9a877 392
ganlikun 0:13413ea9a877 393 /**
ganlikun 0:13413ea9a877 394 * @brief Set each @ref LL_USART_InitTypeDef field to default value.
ganlikun 0:13413ea9a877 395 * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure
ganlikun 0:13413ea9a877 396 * whose fields will be set to default values.
ganlikun 0:13413ea9a877 397 * @retval None
ganlikun 0:13413ea9a877 398 */
ganlikun 0:13413ea9a877 399
ganlikun 0:13413ea9a877 400 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
ganlikun 0:13413ea9a877 401 {
ganlikun 0:13413ea9a877 402 /* Set USART_InitStruct fields to default values */
ganlikun 0:13413ea9a877 403 USART_InitStruct->BaudRate = 9600U;
ganlikun 0:13413ea9a877 404 USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
ganlikun 0:13413ea9a877 405 USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
ganlikun 0:13413ea9a877 406 USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
ganlikun 0:13413ea9a877 407 USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
ganlikun 0:13413ea9a877 408 USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
ganlikun 0:13413ea9a877 409 USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
ganlikun 0:13413ea9a877 410 }
ganlikun 0:13413ea9a877 411
ganlikun 0:13413ea9a877 412 /**
ganlikun 0:13413ea9a877 413 * @brief Initialize USART Clock related settings according to the
ganlikun 0:13413ea9a877 414 * specified parameters in the USART_ClockInitStruct.
ganlikun 0:13413ea9a877 415 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
ganlikun 0:13413ea9a877 416 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
ganlikun 0:13413ea9a877 417 * @param USARTx USART Instance
ganlikun 0:13413ea9a877 418 * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
ganlikun 0:13413ea9a877 419 * that contains the Clock configuration information for the specified USART peripheral.
ganlikun 0:13413ea9a877 420 * @retval An ErrorStatus enumeration value:
ganlikun 0:13413ea9a877 421 * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
ganlikun 0:13413ea9a877 422 * - ERROR: Problem occurred during USART Registers initialization
ganlikun 0:13413ea9a877 423 */
ganlikun 0:13413ea9a877 424 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
ganlikun 0:13413ea9a877 425 {
ganlikun 0:13413ea9a877 426 ErrorStatus status = SUCCESS;
ganlikun 0:13413ea9a877 427
ganlikun 0:13413ea9a877 428 /* Check USART Instance and Clock signal output parameters */
ganlikun 0:13413ea9a877 429 assert_param(IS_UART_INSTANCE(USARTx));
ganlikun 0:13413ea9a877 430 assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
ganlikun 0:13413ea9a877 431
ganlikun 0:13413ea9a877 432 /* USART needs to be in disabled state, in order to be able to configure some bits in
ganlikun 0:13413ea9a877 433 CRx registers */
ganlikun 0:13413ea9a877 434 if (LL_USART_IsEnabled(USARTx) == 0U)
ganlikun 0:13413ea9a877 435 {
ganlikun 0:13413ea9a877 436 /*---------------------------- USART CR2 Configuration -----------------------*/
ganlikun 0:13413ea9a877 437 /* If Clock signal has to be output */
ganlikun 0:13413ea9a877 438 if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
ganlikun 0:13413ea9a877 439 {
ganlikun 0:13413ea9a877 440 /* Deactivate Clock signal delivery :
ganlikun 0:13413ea9a877 441 * - Disable Clock Output: USART_CR2_CLKEN cleared
ganlikun 0:13413ea9a877 442 */
ganlikun 0:13413ea9a877 443 LL_USART_DisableSCLKOutput(USARTx);
ganlikun 0:13413ea9a877 444 }
ganlikun 0:13413ea9a877 445 else
ganlikun 0:13413ea9a877 446 {
ganlikun 0:13413ea9a877 447 /* Ensure USART instance is USART capable */
ganlikun 0:13413ea9a877 448 assert_param(IS_USART_INSTANCE(USARTx));
ganlikun 0:13413ea9a877 449
ganlikun 0:13413ea9a877 450 /* Check clock related parameters */
ganlikun 0:13413ea9a877 451 assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
ganlikun 0:13413ea9a877 452 assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
ganlikun 0:13413ea9a877 453 assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
ganlikun 0:13413ea9a877 454
ganlikun 0:13413ea9a877 455 /*---------------------------- USART CR2 Configuration -----------------------
ganlikun 0:13413ea9a877 456 * Configure USARTx CR2 (Clock signal related bits) with parameters:
ganlikun 0:13413ea9a877 457 * - Enable Clock Output: USART_CR2_CLKEN set
ganlikun 0:13413ea9a877 458 * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
ganlikun 0:13413ea9a877 459 * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
ganlikun 0:13413ea9a877 460 * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
ganlikun 0:13413ea9a877 461 */
ganlikun 0:13413ea9a877 462 MODIFY_REG(USARTx->CR2,
ganlikun 0:13413ea9a877 463 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
ganlikun 0:13413ea9a877 464 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
ganlikun 0:13413ea9a877 465 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
ganlikun 0:13413ea9a877 466 }
ganlikun 0:13413ea9a877 467 }
ganlikun 0:13413ea9a877 468 /* Else (USART not in Disabled state => return ERROR */
ganlikun 0:13413ea9a877 469 else
ganlikun 0:13413ea9a877 470 {
ganlikun 0:13413ea9a877 471 status = ERROR;
ganlikun 0:13413ea9a877 472 }
ganlikun 0:13413ea9a877 473
ganlikun 0:13413ea9a877 474 return (status);
ganlikun 0:13413ea9a877 475 }
ganlikun 0:13413ea9a877 476
ganlikun 0:13413ea9a877 477 /**
ganlikun 0:13413ea9a877 478 * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
ganlikun 0:13413ea9a877 479 * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
ganlikun 0:13413ea9a877 480 * whose fields will be set to default values.
ganlikun 0:13413ea9a877 481 * @retval None
ganlikun 0:13413ea9a877 482 */
ganlikun 0:13413ea9a877 483 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
ganlikun 0:13413ea9a877 484 {
ganlikun 0:13413ea9a877 485 /* Set LL_USART_ClockInitStruct fields with default values */
ganlikun 0:13413ea9a877 486 USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
ganlikun 0:13413ea9a877 487 USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
ganlikun 0:13413ea9a877 488 USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
ganlikun 0:13413ea9a877 489 USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
ganlikun 0:13413ea9a877 490 }
ganlikun 0:13413ea9a877 491
ganlikun 0:13413ea9a877 492 /**
ganlikun 0:13413ea9a877 493 * @}
ganlikun 0:13413ea9a877 494 */
ganlikun 0:13413ea9a877 495
ganlikun 0:13413ea9a877 496 /**
ganlikun 0:13413ea9a877 497 * @}
ganlikun 0:13413ea9a877 498 */
ganlikun 0:13413ea9a877 499
ganlikun 0:13413ea9a877 500 /**
ganlikun 0:13413ea9a877 501 * @}
ganlikun 0:13413ea9a877 502 */
ganlikun 0:13413ea9a877 503
ganlikun 0:13413ea9a877 504 #endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || UART10 */
ganlikun 0:13413ea9a877 505
ganlikun 0:13413ea9a877 506 /**
ganlikun 0:13413ea9a877 507 * @}
ganlikun 0:13413ea9a877 508 */
ganlikun 0:13413ea9a877 509
ganlikun 0:13413ea9a877 510 #endif /* USE_FULL_LL_DRIVER */
ganlikun 0:13413ea9a877 511
ganlikun 0:13413ea9a877 512 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
ganlikun 0:13413ea9a877 513
ganlikun 0:13413ea9a877 514