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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.c@0:13413ea9a877, 2022-06-12 (annotated)

Committer:: ganlikun
Date:: Sun Jun 12 14:02:44 2022 +0000
Revision:: 0:13413ea9a877

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User	Revision	Line number	New contents of line
ganlikun	0:13413ea9a877	1	/**
ganlikun	0:13413ea9a877	2	******************************************************************************
ganlikun	0:13413ea9a877	3	* @file stm32f4xx_ll_tim.c
ganlikun	0:13413ea9a877	4	* @author MCD Application Team
ganlikun	0:13413ea9a877	5	* @version V1.7.1
ganlikun	0:13413ea9a877	6	* @date 14-April-2017
ganlikun	0:13413ea9a877	7	* @brief TIM LL module driver.
ganlikun	0:13413ea9a877	8	******************************************************************************
ganlikun	0:13413ea9a877	9	* @attention
ganlikun	0:13413ea9a877	10	*
ganlikun	0:13413ea9a877	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun	0:13413ea9a877	12	*
ganlikun	0:13413ea9a877	13	* Redistribution and use in source and binary forms, with or without modification,
ganlikun	0:13413ea9a877	14	* are permitted provided that the following conditions are met:
ganlikun	0:13413ea9a877	15	* 1. Redistributions of source code must retain the above copyright notice,
ganlikun	0:13413ea9a877	16	* this list of conditions and the following disclaimer.
ganlikun	0:13413ea9a877	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun	0:13413ea9a877	18	* this list of conditions and the following disclaimer in the documentation
ganlikun	0:13413ea9a877	19	* and/or other materials provided with the distribution.
ganlikun	0:13413ea9a877	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun	0:13413ea9a877	21	* may be used to endorse or promote products derived from this software
ganlikun	0:13413ea9a877	22	* without specific prior written permission.
ganlikun	0:13413ea9a877	23	*
ganlikun	0:13413ea9a877	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun	0:13413ea9a877	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun	0:13413ea9a877	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun	0:13413ea9a877	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun	0:13413ea9a877	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun	0:13413ea9a877	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun	0:13413ea9a877	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun	0:13413ea9a877	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun	0:13413ea9a877	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun	0:13413ea9a877	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun	0:13413ea9a877	34	*
ganlikun	0:13413ea9a877	35	******************************************************************************
ganlikun	0:13413ea9a877	36	*/
ganlikun	0:13413ea9a877	37	#if defined(USE_FULL_LL_DRIVER)
ganlikun	0:13413ea9a877	38
ganlikun	0:13413ea9a877	39	/* Includes ------------------------------------------------------------------*/
ganlikun	0:13413ea9a877	40	#include "stm32f4xx_ll_tim.h"
ganlikun	0:13413ea9a877	41	#include "stm32f4xx_ll_bus.h"
ganlikun	0:13413ea9a877	42
ganlikun	0:13413ea9a877	43	#ifdef USE_FULL_ASSERT
ganlikun	0:13413ea9a877	44	#include "stm32_assert.h"
ganlikun	0:13413ea9a877	45	#else
ganlikun	0:13413ea9a877	46	#define assert_param(expr) ((void)0U)
ganlikun	0:13413ea9a877	47	#endif
ganlikun	0:13413ea9a877	48
ganlikun	0:13413ea9a877	49	/** @addtogroup STM32F4xx_LL_Driver
ganlikun	0:13413ea9a877	50	* @{
ganlikun	0:13413ea9a877	51	*/
ganlikun	0:13413ea9a877	52
ganlikun	0:13413ea9a877	53	#if defined (TIM1) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM6) \|\| defined (TIM7) \|\| defined (TIM8) \|\| defined (TIM9) \|\| defined (TIM10) \|\| defined (TIM11) \|\| defined (TIM12) \|\| defined (TIM13) \|\| defined (TIM14)
ganlikun	0:13413ea9a877	54
ganlikun	0:13413ea9a877	55	/** @addtogroup TIM_LL
ganlikun	0:13413ea9a877	56	* @{
ganlikun	0:13413ea9a877	57	*/
ganlikun	0:13413ea9a877	58
ganlikun	0:13413ea9a877	59	/* Private types -------------------------------------------------------------*/
ganlikun	0:13413ea9a877	60	/* Private variables ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	61	/* Private constants ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	62	/* Private macros ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	63	/** @addtogroup TIM_LL_Private_Macros
ganlikun	0:13413ea9a877	64	* @{
ganlikun	0:13413ea9a877	65	*/
ganlikun	0:13413ea9a877	66	#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
ganlikun	0:13413ea9a877	67	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
ganlikun	0:13413ea9a877	68	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
ganlikun	0:13413ea9a877	69	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
ganlikun	0:13413ea9a877	70	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
ganlikun	0:13413ea9a877	71
ganlikun	0:13413ea9a877	72	#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
ganlikun	0:13413ea9a877	73	\|\| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
ganlikun	0:13413ea9a877	74	\|\| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
ganlikun	0:13413ea9a877	75
ganlikun	0:13413ea9a877	76	#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
ganlikun	0:13413ea9a877	77	\|\| ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
ganlikun	0:13413ea9a877	78	\|\| ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
ganlikun	0:13413ea9a877	79	\|\| ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
ganlikun	0:13413ea9a877	80	\|\| ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
ganlikun	0:13413ea9a877	81	\|\| ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
ganlikun	0:13413ea9a877	82	\|\| ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
ganlikun	0:13413ea9a877	83	\|\| ((__VALUE__) == LL_TIM_OCMODE_PWM2))
ganlikun	0:13413ea9a877	84
ganlikun	0:13413ea9a877	85	#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
ganlikun	0:13413ea9a877	86	\|\| ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
ganlikun	0:13413ea9a877	87
ganlikun	0:13413ea9a877	88	#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
ganlikun	0:13413ea9a877	89	\|\| ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
ganlikun	0:13413ea9a877	90
ganlikun	0:13413ea9a877	91	#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
ganlikun	0:13413ea9a877	92	\|\| ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
ganlikun	0:13413ea9a877	93
ganlikun	0:13413ea9a877	94	#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
ganlikun	0:13413ea9a877	95	\|\| ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
ganlikun	0:13413ea9a877	96	\|\| ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
ganlikun	0:13413ea9a877	97
ganlikun	0:13413ea9a877	98	#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
ganlikun	0:13413ea9a877	99	\|\| ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
ganlikun	0:13413ea9a877	100	\|\| ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
ganlikun	0:13413ea9a877	101	\|\| ((__VALUE__) == LL_TIM_ICPSC_DIV8))
ganlikun	0:13413ea9a877	102
ganlikun	0:13413ea9a877	103	#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
ganlikun	0:13413ea9a877	104	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
ganlikun	0:13413ea9a877	105	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
ganlikun	0:13413ea9a877	106	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
ganlikun	0:13413ea9a877	107	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
ganlikun	0:13413ea9a877	108	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
ganlikun	0:13413ea9a877	109	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
ganlikun	0:13413ea9a877	110	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
ganlikun	0:13413ea9a877	111	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
ganlikun	0:13413ea9a877	112	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
ganlikun	0:13413ea9a877	113	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
ganlikun	0:13413ea9a877	114	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
ganlikun	0:13413ea9a877	115	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
ganlikun	0:13413ea9a877	116	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
ganlikun	0:13413ea9a877	117	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
ganlikun	0:13413ea9a877	118	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
ganlikun	0:13413ea9a877	119
ganlikun	0:13413ea9a877	120	#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
ganlikun	0:13413ea9a877	121	\|\| ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
ganlikun	0:13413ea9a877	122	\|\| ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
ganlikun	0:13413ea9a877	123
ganlikun	0:13413ea9a877	124	#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
ganlikun	0:13413ea9a877	125	\|\| ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
ganlikun	0:13413ea9a877	126	\|\| ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
ganlikun	0:13413ea9a877	127
ganlikun	0:13413ea9a877	128	#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
ganlikun	0:13413ea9a877	129	\|\| ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
ganlikun	0:13413ea9a877	130
ganlikun	0:13413ea9a877	131	#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
ganlikun	0:13413ea9a877	132	\|\| ((__VALUE__) == LL_TIM_OSSR_ENABLE))
ganlikun	0:13413ea9a877	133
ganlikun	0:13413ea9a877	134	#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
ganlikun	0:13413ea9a877	135	\|\| ((__VALUE__) == LL_TIM_OSSI_ENABLE))
ganlikun	0:13413ea9a877	136
ganlikun	0:13413ea9a877	137	#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
ganlikun	0:13413ea9a877	138	\|\| ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
ganlikun	0:13413ea9a877	139	\|\| ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
ganlikun	0:13413ea9a877	140	\|\| ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
ganlikun	0:13413ea9a877	141
ganlikun	0:13413ea9a877	142	#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
ganlikun	0:13413ea9a877	143	\|\| ((__VALUE__) == LL_TIM_BREAK_ENABLE))
ganlikun	0:13413ea9a877	144
ganlikun	0:13413ea9a877	145	#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
ganlikun	0:13413ea9a877	146	\|\| ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
ganlikun	0:13413ea9a877	147
ganlikun	0:13413ea9a877	148	#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
ganlikun	0:13413ea9a877	149	\|\| ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
ganlikun	0:13413ea9a877	150	/**
ganlikun	0:13413ea9a877	151	* @}
ganlikun	0:13413ea9a877	152	*/
ganlikun	0:13413ea9a877	153
ganlikun	0:13413ea9a877	154
ganlikun	0:13413ea9a877	155	/* Private function prototypes -----------------------------------------------*/
ganlikun	0:13413ea9a877	156	/** @defgroup TIM_LL_Private_Functions TIM Private Functions
ganlikun	0:13413ea9a877	157	* @{
ganlikun	0:13413ea9a877	158	*/
ganlikun	0:13413ea9a877	159	static ErrorStatus OC1Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
ganlikun	0:13413ea9a877	160	static ErrorStatus OC2Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
ganlikun	0:13413ea9a877	161	static ErrorStatus OC3Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
ganlikun	0:13413ea9a877	162	static ErrorStatus OC4Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
ganlikun	0:13413ea9a877	163	static ErrorStatus IC1Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
ganlikun	0:13413ea9a877	164	static ErrorStatus IC2Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
ganlikun	0:13413ea9a877	165	static ErrorStatus IC3Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
ganlikun	0:13413ea9a877	166	static ErrorStatus IC4Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
ganlikun	0:13413ea9a877	167	/**
ganlikun	0:13413ea9a877	168	* @}
ganlikun	0:13413ea9a877	169	*/
ganlikun	0:13413ea9a877	170
ganlikun	0:13413ea9a877	171	/* Exported functions --------------------------------------------------------*/
ganlikun	0:13413ea9a877	172	/** @addtogroup TIM_LL_Exported_Functions
ganlikun	0:13413ea9a877	173	* @{
ganlikun	0:13413ea9a877	174	*/
ganlikun	0:13413ea9a877	175
ganlikun	0:13413ea9a877	176	/** @addtogroup TIM_LL_EF_Init
ganlikun	0:13413ea9a877	177	* @{
ganlikun	0:13413ea9a877	178	*/
ganlikun	0:13413ea9a877	179
ganlikun	0:13413ea9a877	180	/**
ganlikun	0:13413ea9a877	181	* @brief Set TIMx registers to their reset values.
ganlikun	0:13413ea9a877	182	* @param TIMx Timer instance
ganlikun	0:13413ea9a877	183	* @retval An ErrorStatus enumeration value:
ganlikun	0:13413ea9a877	184	* - SUCCESS: TIMx registers are de-initialized
ganlikun	0:13413ea9a877	185	* - ERROR: invalid TIMx instance
ganlikun	0:13413ea9a877	186	*/
ganlikun	0:13413ea9a877	187	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
ganlikun	0:13413ea9a877	188	{
ganlikun	0:13413ea9a877	189	ErrorStatus result = SUCCESS;
ganlikun	0:13413ea9a877	190
ganlikun	0:13413ea9a877	191	/* Check the parameters */
ganlikun	0:13413ea9a877	192	assert_param(IS_TIM_INSTANCE(TIMx));
ganlikun	0:13413ea9a877	193
ganlikun	0:13413ea9a877	194	if (TIMx == TIM1)
ganlikun	0:13413ea9a877	195	{
ganlikun	0:13413ea9a877	196	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
ganlikun	0:13413ea9a877	197	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
ganlikun	0:13413ea9a877	198	}
ganlikun	0:13413ea9a877	199	#if defined(TIM2)
ganlikun	0:13413ea9a877	200	else if (TIMx == TIM2)
ganlikun	0:13413ea9a877	201	{
ganlikun	0:13413ea9a877	202	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
ganlikun	0:13413ea9a877	203	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
ganlikun	0:13413ea9a877	204	}
ganlikun	0:13413ea9a877	205	#endif
ganlikun	0:13413ea9a877	206	#if defined(TIM3)
ganlikun	0:13413ea9a877	207	else if (TIMx == TIM3)
ganlikun	0:13413ea9a877	208	{
ganlikun	0:13413ea9a877	209	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
ganlikun	0:13413ea9a877	210	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
ganlikun	0:13413ea9a877	211	}
ganlikun	0:13413ea9a877	212	#endif
ganlikun	0:13413ea9a877	213	#if defined(TIM4)
ganlikun	0:13413ea9a877	214	else if (TIMx == TIM4)
ganlikun	0:13413ea9a877	215	{
ganlikun	0:13413ea9a877	216	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
ganlikun	0:13413ea9a877	217	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
ganlikun	0:13413ea9a877	218	}
ganlikun	0:13413ea9a877	219	#endif
ganlikun	0:13413ea9a877	220	#if defined(TIM5)
ganlikun	0:13413ea9a877	221	else if (TIMx == TIM5)
ganlikun	0:13413ea9a877	222	{
ganlikun	0:13413ea9a877	223	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
ganlikun	0:13413ea9a877	224	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
ganlikun	0:13413ea9a877	225	}
ganlikun	0:13413ea9a877	226	#endif
ganlikun	0:13413ea9a877	227	#if defined(TIM6)
ganlikun	0:13413ea9a877	228	else if (TIMx == TIM6)
ganlikun	0:13413ea9a877	229	{
ganlikun	0:13413ea9a877	230	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
ganlikun	0:13413ea9a877	231	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
ganlikun	0:13413ea9a877	232	}
ganlikun	0:13413ea9a877	233	#endif
ganlikun	0:13413ea9a877	234	#if defined (TIM7)
ganlikun	0:13413ea9a877	235	else if (TIMx == TIM7)
ganlikun	0:13413ea9a877	236	{
ganlikun	0:13413ea9a877	237	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
ganlikun	0:13413ea9a877	238	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
ganlikun	0:13413ea9a877	239	}
ganlikun	0:13413ea9a877	240	#endif
ganlikun	0:13413ea9a877	241	#if defined(TIM8)
ganlikun	0:13413ea9a877	242	else if (TIMx == TIM8)
ganlikun	0:13413ea9a877	243	{
ganlikun	0:13413ea9a877	244	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
ganlikun	0:13413ea9a877	245	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
ganlikun	0:13413ea9a877	246	}
ganlikun	0:13413ea9a877	247	#endif
ganlikun	0:13413ea9a877	248	#if defined(TIM9)
ganlikun	0:13413ea9a877	249	else if (TIMx == TIM9)
ganlikun	0:13413ea9a877	250	{
ganlikun	0:13413ea9a877	251	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
ganlikun	0:13413ea9a877	252	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
ganlikun	0:13413ea9a877	253	}
ganlikun	0:13413ea9a877	254	#endif
ganlikun	0:13413ea9a877	255	#if defined(TIM10)
ganlikun	0:13413ea9a877	256	else if (TIMx == TIM10)
ganlikun	0:13413ea9a877	257	{
ganlikun	0:13413ea9a877	258	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
ganlikun	0:13413ea9a877	259	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
ganlikun	0:13413ea9a877	260	}
ganlikun	0:13413ea9a877	261	#endif
ganlikun	0:13413ea9a877	262	#if defined(TIM11)
ganlikun	0:13413ea9a877	263	else if (TIMx == TIM11)
ganlikun	0:13413ea9a877	264	{
ganlikun	0:13413ea9a877	265	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
ganlikun	0:13413ea9a877	266	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
ganlikun	0:13413ea9a877	267	}
ganlikun	0:13413ea9a877	268	#endif
ganlikun	0:13413ea9a877	269	#if defined(TIM12)
ganlikun	0:13413ea9a877	270	else if (TIMx == TIM12)
ganlikun	0:13413ea9a877	271	{
ganlikun	0:13413ea9a877	272	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
ganlikun	0:13413ea9a877	273	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
ganlikun	0:13413ea9a877	274	}
ganlikun	0:13413ea9a877	275	#endif
ganlikun	0:13413ea9a877	276	#if defined(TIM13)
ganlikun	0:13413ea9a877	277	else if (TIMx == TIM13)
ganlikun	0:13413ea9a877	278	{
ganlikun	0:13413ea9a877	279	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
ganlikun	0:13413ea9a877	280	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
ganlikun	0:13413ea9a877	281	}
ganlikun	0:13413ea9a877	282	#endif
ganlikun	0:13413ea9a877	283	#if defined(TIM14)
ganlikun	0:13413ea9a877	284	else if (TIMx == TIM14)
ganlikun	0:13413ea9a877	285	{
ganlikun	0:13413ea9a877	286	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
ganlikun	0:13413ea9a877	287	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
ganlikun	0:13413ea9a877	288	}
ganlikun	0:13413ea9a877	289	#endif
ganlikun	0:13413ea9a877	290	else
ganlikun	0:13413ea9a877	291	{
ganlikun	0:13413ea9a877	292	result = ERROR;
ganlikun	0:13413ea9a877	293	}
ganlikun	0:13413ea9a877	294
ganlikun	0:13413ea9a877	295	return result;
ganlikun	0:13413ea9a877	296	}
ganlikun	0:13413ea9a877	297
ganlikun	0:13413ea9a877	298	/**
ganlikun	0:13413ea9a877	299	* @brief Set the fields of the time base unit configuration data structure
ganlikun	0:13413ea9a877	300	* to their default values.
ganlikun	0:13413ea9a877	301	* @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
ganlikun	0:13413ea9a877	302	* @retval None
ganlikun	0:13413ea9a877	303	*/
ganlikun	0:13413ea9a877	304	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
ganlikun	0:13413ea9a877	305	{
ganlikun	0:13413ea9a877	306	/* Set the default configuration */
ganlikun	0:13413ea9a877	307	TIM_InitStruct->Prescaler = (uint16_t)0x0000U;
ganlikun	0:13413ea9a877	308	TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
ganlikun	0:13413ea9a877	309	TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
ganlikun	0:13413ea9a877	310	TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
ganlikun	0:13413ea9a877	311	TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
ganlikun	0:13413ea9a877	312	}
ganlikun	0:13413ea9a877	313
ganlikun	0:13413ea9a877	314	/**
ganlikun	0:13413ea9a877	315	* @brief Configure the TIMx time base unit.
ganlikun	0:13413ea9a877	316	* @param TIMx Timer Instance
ganlikun	0:13413ea9a877	317	* @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
ganlikun	0:13413ea9a877	318	* @retval An ErrorStatus enumeration value:
ganlikun	0:13413ea9a877	319	* - SUCCESS: TIMx registers are de-initialized
ganlikun	0:13413ea9a877	320	* - ERROR: not applicable
ganlikun	0:13413ea9a877	321	*/
ganlikun	0:13413ea9a877	322	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct)
ganlikun	0:13413ea9a877	323	{
ganlikun	0:13413ea9a877	324	uint32_t tmpcr1 = 0U;
ganlikun	0:13413ea9a877	325
ganlikun	0:13413ea9a877	326	/* Check the parameters */
ganlikun	0:13413ea9a877	327	assert_param(IS_TIM_INSTANCE(TIMx));
ganlikun	0:13413ea9a877	328	assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
ganlikun	0:13413ea9a877	329	assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
ganlikun	0:13413ea9a877	330
ganlikun	0:13413ea9a877	331	tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
ganlikun	0:13413ea9a877	332
ganlikun	0:13413ea9a877	333	if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
ganlikun	0:13413ea9a877	334	{
ganlikun	0:13413ea9a877	335	/* Select the Counter Mode */
ganlikun	0:13413ea9a877	336	MODIFY_REG(tmpcr1, (TIM_CR1_DIR \| TIM_CR1_CMS), TIM_InitStruct->CounterMode);
ganlikun	0:13413ea9a877	337	}
ganlikun	0:13413ea9a877	338
ganlikun	0:13413ea9a877	339	if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
ganlikun	0:13413ea9a877	340	{
ganlikun	0:13413ea9a877	341	/* Set the clock division */
ganlikun	0:13413ea9a877	342	MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
ganlikun	0:13413ea9a877	343	}
ganlikun	0:13413ea9a877	344
ganlikun	0:13413ea9a877	345	/* Write to TIMx CR1 */
ganlikun	0:13413ea9a877	346	LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
ganlikun	0:13413ea9a877	347
ganlikun	0:13413ea9a877	348	/* Set the Autoreload value */
ganlikun	0:13413ea9a877	349	LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
ganlikun	0:13413ea9a877	350
ganlikun	0:13413ea9a877	351	/* Set the Prescaler value */
ganlikun	0:13413ea9a877	352	LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
ganlikun	0:13413ea9a877	353
ganlikun	0:13413ea9a877	354	if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
ganlikun	0:13413ea9a877	355	{
ganlikun	0:13413ea9a877	356	/* Set the Repetition Counter value */
ganlikun	0:13413ea9a877	357	LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
ganlikun	0:13413ea9a877	358	}
ganlikun	0:13413ea9a877	359
ganlikun	0:13413ea9a877	360	/* Generate an update event to reload the Prescaler
ganlikun	0:13413ea9a877	361	and the repetition counter value (if applicable) immediately */
ganlikun	0:13413ea9a877	362	LL_TIM_GenerateEvent_UPDATE(TIMx);
ganlikun	0:13413ea9a877	363
ganlikun	0:13413ea9a877	364	return SUCCESS;
ganlikun	0:13413ea9a877	365	}
ganlikun	0:13413ea9a877	366
ganlikun	0:13413ea9a877	367	/**
ganlikun	0:13413ea9a877	368	* @brief Set the fields of the TIMx output channel configuration data
ganlikun	0:13413ea9a877	369	* structure to their default values.
ganlikun	0:13413ea9a877	370	* @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
ganlikun	0:13413ea9a877	371	* @retval None
ganlikun	0:13413ea9a877	372	*/
ganlikun	0:13413ea9a877	373	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
ganlikun	0:13413ea9a877	374	{
ganlikun	0:13413ea9a877	375	/* Set the default configuration */
ganlikun	0:13413ea9a877	376	TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
ganlikun	0:13413ea9a877	377	TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
ganlikun	0:13413ea9a877	378	TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
ganlikun	0:13413ea9a877	379	TIM_OC_InitStruct->CompareValue = 0x00000000U;
ganlikun	0:13413ea9a877	380	TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
ganlikun	0:13413ea9a877	381	TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
ganlikun	0:13413ea9a877	382	TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
ganlikun	0:13413ea9a877	383	TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
ganlikun	0:13413ea9a877	384	}
ganlikun	0:13413ea9a877	385
ganlikun	0:13413ea9a877	386	/**
ganlikun	0:13413ea9a877	387	* @brief Configure the TIMx output channel.
ganlikun	0:13413ea9a877	388	* @param TIMx Timer Instance
ganlikun	0:13413ea9a877	389	* @param Channel This parameter can be one of the following values:
ganlikun	0:13413ea9a877	390	* @arg @ref LL_TIM_CHANNEL_CH1
ganlikun	0:13413ea9a877	391	* @arg @ref LL_TIM_CHANNEL_CH2
ganlikun	0:13413ea9a877	392	* @arg @ref LL_TIM_CHANNEL_CH3
ganlikun	0:13413ea9a877	393	* @arg @ref LL_TIM_CHANNEL_CH4
ganlikun	0:13413ea9a877	394	* @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
ganlikun	0:13413ea9a877	395	* @retval An ErrorStatus enumeration value:
ganlikun	0:13413ea9a877	396	* - SUCCESS: TIMx output channel is initialized
ganlikun	0:13413ea9a877	397	* - ERROR: TIMx output channel is not initialized
ganlikun	0:13413ea9a877	398	*/
ganlikun	0:13413ea9a877	399	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct)
ganlikun	0:13413ea9a877	400	{
ganlikun	0:13413ea9a877	401	ErrorStatus result = ERROR;
ganlikun	0:13413ea9a877	402
ganlikun	0:13413ea9a877	403	switch (Channel)
ganlikun	0:13413ea9a877	404	{
ganlikun	0:13413ea9a877	405	case LL_TIM_CHANNEL_CH1:
ganlikun	0:13413ea9a877	406	result = OC1Config(TIMx, TIM_OC_InitStruct);
ganlikun	0:13413ea9a877	407	break;
ganlikun	0:13413ea9a877	408	case LL_TIM_CHANNEL_CH2:
ganlikun	0:13413ea9a877	409	result = OC2Config(TIMx, TIM_OC_InitStruct);
ganlikun	0:13413ea9a877	410	break;
ganlikun	0:13413ea9a877	411	case LL_TIM_CHANNEL_CH3:
ganlikun	0:13413ea9a877	412	result = OC3Config(TIMx, TIM_OC_InitStruct);
ganlikun	0:13413ea9a877	413	break;
ganlikun	0:13413ea9a877	414	case LL_TIM_CHANNEL_CH4:
ganlikun	0:13413ea9a877	415	result = OC4Config(TIMx, TIM_OC_InitStruct);
ganlikun	0:13413ea9a877	416	break;
ganlikun	0:13413ea9a877	417	default:
ganlikun	0:13413ea9a877	418	break;
ganlikun	0:13413ea9a877	419	}
ganlikun	0:13413ea9a877	420
ganlikun	0:13413ea9a877	421	return result;
ganlikun	0:13413ea9a877	422	}
ganlikun	0:13413ea9a877	423
ganlikun	0:13413ea9a877	424	/**
ganlikun	0:13413ea9a877	425	* @brief Set the fields of the TIMx input channel configuration data
ganlikun	0:13413ea9a877	426	* structure to their default values.
ganlikun	0:13413ea9a877	427	* @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
ganlikun	0:13413ea9a877	428	* @retval None
ganlikun	0:13413ea9a877	429	*/
ganlikun	0:13413ea9a877	430	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
ganlikun	0:13413ea9a877	431	{
ganlikun	0:13413ea9a877	432	/* Set the default configuration */
ganlikun	0:13413ea9a877	433	TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
ganlikun	0:13413ea9a877	434	TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
ganlikun	0:13413ea9a877	435	TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
ganlikun	0:13413ea9a877	436	TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
ganlikun	0:13413ea9a877	437	}
ganlikun	0:13413ea9a877	438
ganlikun	0:13413ea9a877	439	/**
ganlikun	0:13413ea9a877	440	* @brief Configure the TIMx input channel.
ganlikun	0:13413ea9a877	441	* @param TIMx Timer Instance
ganlikun	0:13413ea9a877	442	* @param Channel This parameter can be one of the following values:
ganlikun	0:13413ea9a877	443	* @arg @ref LL_TIM_CHANNEL_CH1
ganlikun	0:13413ea9a877	444	* @arg @ref LL_TIM_CHANNEL_CH2
ganlikun	0:13413ea9a877	445	* @arg @ref LL_TIM_CHANNEL_CH3
ganlikun	0:13413ea9a877	446	* @arg @ref LL_TIM_CHANNEL_CH4
ganlikun	0:13413ea9a877	447	* @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
ganlikun	0:13413ea9a877	448	* @retval An ErrorStatus enumeration value:
ganlikun	0:13413ea9a877	449	* - SUCCESS: TIMx output channel is initialized
ganlikun	0:13413ea9a877	450	* - ERROR: TIMx output channel is not initialized
ganlikun	0:13413ea9a877	451	*/
ganlikun	0:13413ea9a877	452	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct)
ganlikun	0:13413ea9a877	453	{
ganlikun	0:13413ea9a877	454	ErrorStatus result = ERROR;
ganlikun	0:13413ea9a877	455
ganlikun	0:13413ea9a877	456	switch (Channel)
ganlikun	0:13413ea9a877	457	{
ganlikun	0:13413ea9a877	458	case LL_TIM_CHANNEL_CH1:
ganlikun	0:13413ea9a877	459	result = IC1Config(TIMx, TIM_IC_InitStruct);
ganlikun	0:13413ea9a877	460	break;
ganlikun	0:13413ea9a877	461	case LL_TIM_CHANNEL_CH2:
ganlikun	0:13413ea9a877	462	result = IC2Config(TIMx, TIM_IC_InitStruct);
ganlikun	0:13413ea9a877	463	break;
ganlikun	0:13413ea9a877	464	case LL_TIM_CHANNEL_CH3:
ganlikun	0:13413ea9a877	465	result = IC3Config(TIMx, TIM_IC_InitStruct);
ganlikun	0:13413ea9a877	466	break;
ganlikun	0:13413ea9a877	467	case LL_TIM_CHANNEL_CH4:
ganlikun	0:13413ea9a877	468	result = IC4Config(TIMx, TIM_IC_InitStruct);
ganlikun	0:13413ea9a877	469	break;
ganlikun	0:13413ea9a877	470	default:
ganlikun	0:13413ea9a877	471	break;
ganlikun	0:13413ea9a877	472	}
ganlikun	0:13413ea9a877	473
ganlikun	0:13413ea9a877	474	return result;
ganlikun	0:13413ea9a877	475	}
ganlikun	0:13413ea9a877	476
ganlikun	0:13413ea9a877	477	/**
ganlikun	0:13413ea9a877	478	* @brief Fills each TIM_EncoderInitStruct field with its default value
ganlikun	0:13413ea9a877	479	* @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
ganlikun	0:13413ea9a877	480	* @retval None
ganlikun	0:13413ea9a877	481	*/
ganlikun	0:13413ea9a877	482	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
ganlikun	0:13413ea9a877	483	{
ganlikun	0:13413ea9a877	484	/* Set the default configuration */
ganlikun	0:13413ea9a877	485	TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
ganlikun	0:13413ea9a877	486	TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
ganlikun	0:13413ea9a877	487	TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
ganlikun	0:13413ea9a877	488	TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
ganlikun	0:13413ea9a877	489	TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
ganlikun	0:13413ea9a877	490	TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
ganlikun	0:13413ea9a877	491	TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
ganlikun	0:13413ea9a877	492	TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
ganlikun	0:13413ea9a877	493	TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
ganlikun	0:13413ea9a877	494	}
ganlikun	0:13413ea9a877	495
ganlikun	0:13413ea9a877	496	/**
ganlikun	0:13413ea9a877	497	* @brief Configure the encoder interface of the timer instance.
ganlikun	0:13413ea9a877	498	* @param TIMx Timer Instance
ganlikun	0:13413ea9a877	499	* @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
ganlikun	0:13413ea9a877	500	* @retval An ErrorStatus enumeration value:
ganlikun	0:13413ea9a877	501	* - SUCCESS: TIMx registers are de-initialized
ganlikun	0:13413ea9a877	502	* - ERROR: not applicable
ganlikun	0:13413ea9a877	503	*/
ganlikun	0:13413ea9a877	504	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct)
ganlikun	0:13413ea9a877	505	{
ganlikun	0:13413ea9a877	506	uint32_t tmpccmr1 = 0U;
ganlikun	0:13413ea9a877	507	uint32_t tmpccer = 0U;
ganlikun	0:13413ea9a877	508
ganlikun	0:13413ea9a877	509	/* Check the parameters */
ganlikun	0:13413ea9a877	510	assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
ganlikun	0:13413ea9a877	511	assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
ganlikun	0:13413ea9a877	512	assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
ganlikun	0:13413ea9a877	513	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
ganlikun	0:13413ea9a877	514	assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
ganlikun	0:13413ea9a877	515	assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
ganlikun	0:13413ea9a877	516	assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
ganlikun	0:13413ea9a877	517	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
ganlikun	0:13413ea9a877	518	assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
ganlikun	0:13413ea9a877	519	assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
ganlikun	0:13413ea9a877	520
ganlikun	0:13413ea9a877	521	/* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
ganlikun	0:13413ea9a877	522	TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E \| TIM_CCER_CC2E);
ganlikun	0:13413ea9a877	523
ganlikun	0:13413ea9a877	524	/* Get the TIMx CCMR1 register value */
ganlikun	0:13413ea9a877	525	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
ganlikun	0:13413ea9a877	526
ganlikun	0:13413ea9a877	527	/* Get the TIMx CCER register value */
ganlikun	0:13413ea9a877	528	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
ganlikun	0:13413ea9a877	529
ganlikun	0:13413ea9a877	530	/* Configure TI1 */
ganlikun	0:13413ea9a877	531	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S \| TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC);
ganlikun	0:13413ea9a877	532	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
ganlikun	0:13413ea9a877	533	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
ganlikun	0:13413ea9a877	534	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
ganlikun	0:13413ea9a877	535
ganlikun	0:13413ea9a877	536	/* Configure TI2 */
ganlikun	0:13413ea9a877	537	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S \| TIM_CCMR1_IC2F \| TIM_CCMR1_IC2PSC);
ganlikun	0:13413ea9a877	538	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
ganlikun	0:13413ea9a877	539	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
ganlikun	0:13413ea9a877	540	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
ganlikun	0:13413ea9a877	541
ganlikun	0:13413ea9a877	542	/* Set TI1 and TI2 polarity and enable TI1 and TI2 */
ganlikun	0:13413ea9a877	543	tmpccer &= (uint32_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP \| TIM_CCER_CC2P \| TIM_CCER_CC2NP);
ganlikun	0:13413ea9a877	544	tmpccer \|= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
ganlikun	0:13413ea9a877	545	tmpccer \|= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
ganlikun	0:13413ea9a877	546	tmpccer \|= (uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E);
ganlikun	0:13413ea9a877	547
ganlikun	0:13413ea9a877	548	/* Set encoder mode */
ganlikun	0:13413ea9a877	549	LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
ganlikun	0:13413ea9a877	550
ganlikun	0:13413ea9a877	551	/* Write to TIMx CCMR1 */
ganlikun	0:13413ea9a877	552	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
ganlikun	0:13413ea9a877	553
ganlikun	0:13413ea9a877	554	/* Write to TIMx CCER */
ganlikun	0:13413ea9a877	555	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
ganlikun	0:13413ea9a877	556
ganlikun	0:13413ea9a877	557	return SUCCESS;
ganlikun	0:13413ea9a877	558	}
ganlikun	0:13413ea9a877	559
ganlikun	0:13413ea9a877	560	/**
ganlikun	0:13413ea9a877	561	* @brief Set the fields of the TIMx Hall sensor interface configuration data
ganlikun	0:13413ea9a877	562	* structure to their default values.
ganlikun	0:13413ea9a877	563	* @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
ganlikun	0:13413ea9a877	564	* @retval None
ganlikun	0:13413ea9a877	565	*/
ganlikun	0:13413ea9a877	566	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
ganlikun	0:13413ea9a877	567	{
ganlikun	0:13413ea9a877	568	/* Set the default configuration */
ganlikun	0:13413ea9a877	569	TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
ganlikun	0:13413ea9a877	570	TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
ganlikun	0:13413ea9a877	571	TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
ganlikun	0:13413ea9a877	572	TIM_HallSensorInitStruct->CommutationDelay = 0U;
ganlikun	0:13413ea9a877	573	}
ganlikun	0:13413ea9a877	574
ganlikun	0:13413ea9a877	575	/**
ganlikun	0:13413ea9a877	576	* @brief Configure the Hall sensor interface of the timer instance.
ganlikun	0:13413ea9a877	577	* @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
ganlikun	0:13413ea9a877	578	* to the TI1 input channel
ganlikun	0:13413ea9a877	579	* @note TIMx slave mode controller is configured in reset mode.
ganlikun	0:13413ea9a877	580	Selected internal trigger is TI1F_ED.
ganlikun	0:13413ea9a877	581	* @note Channel 1 is configured as input, IC1 is mapped on TRC.
ganlikun	0:13413ea9a877	582	* @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
ganlikun	0:13413ea9a877	583	* between 2 changes on the inputs. It gives information about motor speed.
ganlikun	0:13413ea9a877	584	* @note Channel 2 is configured in output PWM 2 mode.
ganlikun	0:13413ea9a877	585	* @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
ganlikun	0:13413ea9a877	586	* @note OC2REF is selected as trigger output on TRGO.
ganlikun	0:13413ea9a877	587	* @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
ganlikun	0:13413ea9a877	588	* when TIMx operates in Hall sensor interface mode.
ganlikun	0:13413ea9a877	589	* @param TIMx Timer Instance
ganlikun	0:13413ea9a877	590	* @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
ganlikun	0:13413ea9a877	591	* @retval An ErrorStatus enumeration value:
ganlikun	0:13413ea9a877	592	* - SUCCESS: TIMx registers are de-initialized
ganlikun	0:13413ea9a877	593	* - ERROR: not applicable
ganlikun	0:13413ea9a877	594	*/
ganlikun	0:13413ea9a877	595	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct)
ganlikun	0:13413ea9a877	596	{
ganlikun	0:13413ea9a877	597	uint32_t tmpcr2 = 0U;
ganlikun	0:13413ea9a877	598	uint32_t tmpccmr1 = 0U;
ganlikun	0:13413ea9a877	599	uint32_t tmpccer = 0U;
ganlikun	0:13413ea9a877	600	uint32_t tmpsmcr = 0U;
ganlikun	0:13413ea9a877	601
ganlikun	0:13413ea9a877	602	/* Check the parameters */
ganlikun	0:13413ea9a877	603	assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
ganlikun	0:13413ea9a877	604	assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
ganlikun	0:13413ea9a877	605	assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
ganlikun	0:13413ea9a877	606	assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
ganlikun	0:13413ea9a877	607
ganlikun	0:13413ea9a877	608	/* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
ganlikun	0:13413ea9a877	609	TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E \| TIM_CCER_CC2E);
ganlikun	0:13413ea9a877	610
ganlikun	0:13413ea9a877	611	/* Get the TIMx CR2 register value */
ganlikun	0:13413ea9a877	612	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
ganlikun	0:13413ea9a877	613
ganlikun	0:13413ea9a877	614	/* Get the TIMx CCMR1 register value */
ganlikun	0:13413ea9a877	615	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
ganlikun	0:13413ea9a877	616
ganlikun	0:13413ea9a877	617	/* Get the TIMx CCER register value */
ganlikun	0:13413ea9a877	618	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
ganlikun	0:13413ea9a877	619
ganlikun	0:13413ea9a877	620	/* Get the TIMx SMCR register value */
ganlikun	0:13413ea9a877	621	tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
ganlikun	0:13413ea9a877	622
ganlikun	0:13413ea9a877	623	/* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
ganlikun	0:13413ea9a877	624	tmpcr2 \|= TIM_CR2_TI1S;
ganlikun	0:13413ea9a877	625
ganlikun	0:13413ea9a877	626	/* OC2REF signal is used as trigger output (TRGO) */
ganlikun	0:13413ea9a877	627	tmpcr2 \|= LL_TIM_TRGO_OC2REF;
ganlikun	0:13413ea9a877	628
ganlikun	0:13413ea9a877	629	/* Configure the slave mode controller */
ganlikun	0:13413ea9a877	630	tmpsmcr &= (uint32_t)~(TIM_SMCR_TS \| TIM_SMCR_SMS);
ganlikun	0:13413ea9a877	631	tmpsmcr \|= LL_TIM_TS_TI1F_ED;
ganlikun	0:13413ea9a877	632	tmpsmcr \|= LL_TIM_SLAVEMODE_RESET;
ganlikun	0:13413ea9a877	633
ganlikun	0:13413ea9a877	634	/* Configure input channel 1 */
ganlikun	0:13413ea9a877	635	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S \| TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC);
ganlikun	0:13413ea9a877	636	tmpccmr1 \|= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
ganlikun	0:13413ea9a877	637	tmpccmr1 \|= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
ganlikun	0:13413ea9a877	638	tmpccmr1 \|= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
ganlikun	0:13413ea9a877	639
ganlikun	0:13413ea9a877	640	/* Configure input channel 2 */
ganlikun	0:13413ea9a877	641	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M \| TIM_CCMR1_OC2FE \| TIM_CCMR1_OC2PE \| TIM_CCMR1_OC2CE);
ganlikun	0:13413ea9a877	642	tmpccmr1 \|= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
ganlikun	0:13413ea9a877	643
ganlikun	0:13413ea9a877	644	/* Set Channel 1 polarity and enable Channel 1 and Channel2 */
ganlikun	0:13413ea9a877	645	tmpccer &= (uint32_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP \| TIM_CCER_CC2P \| TIM_CCER_CC2NP);
ganlikun	0:13413ea9a877	646	tmpccer \|= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
ganlikun	0:13413ea9a877	647	tmpccer \|= (uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E);
ganlikun	0:13413ea9a877	648
ganlikun	0:13413ea9a877	649	/* Write to TIMx CR2 */
ganlikun	0:13413ea9a877	650	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
ganlikun	0:13413ea9a877	651
ganlikun	0:13413ea9a877	652	/* Write to TIMx SMCR */
ganlikun	0:13413ea9a877	653	LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
ganlikun	0:13413ea9a877	654
ganlikun	0:13413ea9a877	655	/* Write to TIMx CCMR1 */
ganlikun	0:13413ea9a877	656	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
ganlikun	0:13413ea9a877	657
ganlikun	0:13413ea9a877	658	/* Write to TIMx CCER */
ganlikun	0:13413ea9a877	659	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
ganlikun	0:13413ea9a877	660
ganlikun	0:13413ea9a877	661	/* Write to TIMx CCR2 */
ganlikun	0:13413ea9a877	662	LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
ganlikun	0:13413ea9a877	663
ganlikun	0:13413ea9a877	664	return SUCCESS;
ganlikun	0:13413ea9a877	665	}
ganlikun	0:13413ea9a877	666
ganlikun	0:13413ea9a877	667	/**
ganlikun	0:13413ea9a877	668	* @brief Set the fields of the Break and Dead Time configuration data structure
ganlikun	0:13413ea9a877	669	* to their default values.
ganlikun	0:13413ea9a877	670	* @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
ganlikun	0:13413ea9a877	671	* @retval None
ganlikun	0:13413ea9a877	672	*/
ganlikun	0:13413ea9a877	673	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
ganlikun	0:13413ea9a877	674	{
ganlikun	0:13413ea9a877	675	/* Set the default configuration */
ganlikun	0:13413ea9a877	676	TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
ganlikun	0:13413ea9a877	677	TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
ganlikun	0:13413ea9a877	678	TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
ganlikun	0:13413ea9a877	679	TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U;
ganlikun	0:13413ea9a877	680	TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
ganlikun	0:13413ea9a877	681	TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
ganlikun	0:13413ea9a877	682	TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
ganlikun	0:13413ea9a877	683	}
ganlikun	0:13413ea9a877	684
ganlikun	0:13413ea9a877	685	/**
ganlikun	0:13413ea9a877	686	* @brief Configure the Break and Dead Time feature of the timer instance.
ganlikun	0:13413ea9a877	687	* @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
ganlikun	0:13413ea9a877	688	* depending on the LOCK configuration, it can be necessary to configure all of
ganlikun	0:13413ea9a877	689	* them during the first write access to the TIMx_BDTR register.
ganlikun	0:13413ea9a877	690	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
ganlikun	0:13413ea9a877	691	* a timer instance provides a break input.
ganlikun	0:13413ea9a877	692	* @param TIMx Timer Instance
ganlikun	0:13413ea9a877	693	* @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
ganlikun	0:13413ea9a877	694	* @retval An ErrorStatus enumeration value:
ganlikun	0:13413ea9a877	695	* - SUCCESS: Break and Dead Time is initialized
ganlikun	0:13413ea9a877	696	* - ERROR: not applicable
ganlikun	0:13413ea9a877	697	*/
ganlikun	0:13413ea9a877	698	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct)
ganlikun	0:13413ea9a877	699	{
ganlikun	0:13413ea9a877	700	uint32_t tmpbdtr = 0;
ganlikun	0:13413ea9a877	701
ganlikun	0:13413ea9a877	702	/* Check the parameters */
ganlikun	0:13413ea9a877	703	assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
ganlikun	0:13413ea9a877	704	assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
ganlikun	0:13413ea9a877	705	assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
ganlikun	0:13413ea9a877	706	assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
ganlikun	0:13413ea9a877	707	assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
ganlikun	0:13413ea9a877	708	assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
ganlikun	0:13413ea9a877	709	assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
ganlikun	0:13413ea9a877	710
ganlikun	0:13413ea9a877	711	/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
ganlikun	0:13413ea9a877	712	the OSSI State, the dead time value and the Automatic Output Enable Bit */
ganlikun	0:13413ea9a877	713
ganlikun	0:13413ea9a877	714	/* Set the BDTR bits */
ganlikun	0:13413ea9a877	715	MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
ganlikun	0:13413ea9a877	716	MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
ganlikun	0:13413ea9a877	717	MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
ganlikun	0:13413ea9a877	718	MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
ganlikun	0:13413ea9a877	719	MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
ganlikun	0:13413ea9a877	720	MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
ganlikun	0:13413ea9a877	721	MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
ganlikun	0:13413ea9a877	722	MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
ganlikun	0:13413ea9a877	723
ganlikun	0:13413ea9a877	724	/* Set TIMx_BDTR */
ganlikun	0:13413ea9a877	725	LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
ganlikun	0:13413ea9a877	726
ganlikun	0:13413ea9a877	727	return SUCCESS;
ganlikun	0:13413ea9a877	728	}
ganlikun	0:13413ea9a877	729	/**
ganlikun	0:13413ea9a877	730	* @}
ganlikun	0:13413ea9a877	731	*/
ganlikun	0:13413ea9a877	732
ganlikun	0:13413ea9a877	733	/**
ganlikun	0:13413ea9a877	734	* @}
ganlikun	0:13413ea9a877	735	*/
ganlikun	0:13413ea9a877	736
ganlikun	0:13413ea9a877	737	/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
ganlikun	0:13413ea9a877	738	* @brief Private functions
ganlikun	0:13413ea9a877	739	* @{
ganlikun	0:13413ea9a877	740	*/
ganlikun	0:13413ea9a877	741	/**
ganlikun	0:13413ea9a877	742	* @brief Configure the TIMx output channel 1.
ganlikun	0:13413ea9a877	743	* @param TIMx Timer Instance
ganlikun	0:13413ea9a877	744	* @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
ganlikun	0:13413ea9a877	745	* @retval An ErrorStatus enumeration value:
ganlikun	0:13413ea9a877	746	* - SUCCESS: TIMx registers are de-initialized
ganlikun	0:13413ea9a877	747	* - ERROR: not applicable
ganlikun	0:13413ea9a877	748	*/
ganlikun	0:13413ea9a877	749	static ErrorStatus OC1Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
ganlikun	0:13413ea9a877	750	{
ganlikun	0:13413ea9a877	751	uint32_t tmpccmr1 = 0U;
ganlikun	0:13413ea9a877	752	uint32_t tmpccer = 0U;
ganlikun	0:13413ea9a877	753	uint32_t tmpcr2 = 0U;
ganlikun	0:13413ea9a877	754
ganlikun	0:13413ea9a877	755	/* Check the parameters */
ganlikun	0:13413ea9a877	756	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
ganlikun	0:13413ea9a877	757	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
ganlikun	0:13413ea9a877	758	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
ganlikun	0:13413ea9a877	759	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
ganlikun	0:13413ea9a877	760	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
ganlikun	0:13413ea9a877	761	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
ganlikun	0:13413ea9a877	762
ganlikun	0:13413ea9a877	763	/* Disable the Channel 1: Reset the CC1E Bit */
ganlikun	0:13413ea9a877	764	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
ganlikun	0:13413ea9a877	765
ganlikun	0:13413ea9a877	766	/* Get the TIMx CCER register value */
ganlikun	0:13413ea9a877	767	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
ganlikun	0:13413ea9a877	768
ganlikun	0:13413ea9a877	769	/* Get the TIMx CR2 register value */
ganlikun	0:13413ea9a877	770	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
ganlikun	0:13413ea9a877	771
ganlikun	0:13413ea9a877	772	/* Get the TIMx CCMR1 register value */
ganlikun	0:13413ea9a877	773	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
ganlikun	0:13413ea9a877	774
ganlikun	0:13413ea9a877	775	/* Reset Capture/Compare selection Bits */
ganlikun	0:13413ea9a877	776	CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
ganlikun	0:13413ea9a877	777
ganlikun	0:13413ea9a877	778	/* Set the Output Compare Mode */
ganlikun	0:13413ea9a877	779	MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
ganlikun	0:13413ea9a877	780
ganlikun	0:13413ea9a877	781	/* Set the Output Compare Polarity */
ganlikun	0:13413ea9a877	782	MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
ganlikun	0:13413ea9a877	783
ganlikun	0:13413ea9a877	784	/* Set the Output State */
ganlikun	0:13413ea9a877	785	MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
ganlikun	0:13413ea9a877	786
ganlikun	0:13413ea9a877	787	if (IS_TIM_BREAK_INSTANCE(TIMx))
ganlikun	0:13413ea9a877	788	{
ganlikun	0:13413ea9a877	789	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
ganlikun	0:13413ea9a877	790	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
ganlikun	0:13413ea9a877	791
ganlikun	0:13413ea9a877	792	/* Set the complementary output Polarity */
ganlikun	0:13413ea9a877	793	MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
ganlikun	0:13413ea9a877	794
ganlikun	0:13413ea9a877	795	/* Set the complementary output State */
ganlikun	0:13413ea9a877	796	MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
ganlikun	0:13413ea9a877	797
ganlikun	0:13413ea9a877	798	/* Set the Output Idle state */
ganlikun	0:13413ea9a877	799	MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
ganlikun	0:13413ea9a877	800
ganlikun	0:13413ea9a877	801	/* Set the complementary output Idle state */
ganlikun	0:13413ea9a877	802	MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
ganlikun	0:13413ea9a877	803	}
ganlikun	0:13413ea9a877	804
ganlikun	0:13413ea9a877	805	/* Write to TIMx CR2 */
ganlikun	0:13413ea9a877	806	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
ganlikun	0:13413ea9a877	807
ganlikun	0:13413ea9a877	808	/* Write to TIMx CCMR1 */
ganlikun	0:13413ea9a877	809	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
ganlikun	0:13413ea9a877	810
ganlikun	0:13413ea9a877	811	/* Set the Capture Compare Register value */
ganlikun	0:13413ea9a877	812	LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
ganlikun	0:13413ea9a877	813
ganlikun	0:13413ea9a877	814	/* Write to TIMx CCER */
ganlikun	0:13413ea9a877	815	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
ganlikun	0:13413ea9a877	816
ganlikun	0:13413ea9a877	817	return SUCCESS;
ganlikun	0:13413ea9a877	818	}
ganlikun	0:13413ea9a877	819
ganlikun	0:13413ea9a877	820	/**
ganlikun	0:13413ea9a877	821	* @brief Configure the TIMx output channel 2.
ganlikun	0:13413ea9a877	822	* @param TIMx Timer Instance
ganlikun	0:13413ea9a877	823	* @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
ganlikun	0:13413ea9a877	824	* @retval An ErrorStatus enumeration value:
ganlikun	0:13413ea9a877	825	* - SUCCESS: TIMx registers are de-initialized
ganlikun	0:13413ea9a877	826	* - ERROR: not applicable
ganlikun	0:13413ea9a877	827	*/
ganlikun	0:13413ea9a877	828	static ErrorStatus OC2Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
ganlikun	0:13413ea9a877	829	{
ganlikun	0:13413ea9a877	830	uint32_t tmpccmr1 = 0U;
ganlikun	0:13413ea9a877	831	uint32_t tmpccer = 0U;
ganlikun	0:13413ea9a877	832	uint32_t tmpcr2 = 0U;
ganlikun	0:13413ea9a877	833
ganlikun	0:13413ea9a877	834	/* Check the parameters */
ganlikun	0:13413ea9a877	835	assert_param(IS_TIM_CC2_INSTANCE(TIMx));
ganlikun	0:13413ea9a877	836	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
ganlikun	0:13413ea9a877	837	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
ganlikun	0:13413ea9a877	838	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
ganlikun	0:13413ea9a877	839	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
ganlikun	0:13413ea9a877	840	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
ganlikun	0:13413ea9a877	841
ganlikun	0:13413ea9a877	842	/* Disable the Channel 2: Reset the CC2E Bit */
ganlikun	0:13413ea9a877	843	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
ganlikun	0:13413ea9a877	844
ganlikun	0:13413ea9a877	845	/* Get the TIMx CCER register value */
ganlikun	0:13413ea9a877	846	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
ganlikun	0:13413ea9a877	847
ganlikun	0:13413ea9a877	848	/* Get the TIMx CR2 register value */
ganlikun	0:13413ea9a877	849	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
ganlikun	0:13413ea9a877	850
ganlikun	0:13413ea9a877	851	/* Get the TIMx CCMR1 register value */
ganlikun	0:13413ea9a877	852	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
ganlikun	0:13413ea9a877	853
ganlikun	0:13413ea9a877	854	/* Reset Capture/Compare selection Bits */
ganlikun	0:13413ea9a877	855	CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
ganlikun	0:13413ea9a877	856
ganlikun	0:13413ea9a877	857	/* Select the Output Compare Mode */
ganlikun	0:13413ea9a877	858	MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
ganlikun	0:13413ea9a877	859
ganlikun	0:13413ea9a877	860	/* Set the Output Compare Polarity */
ganlikun	0:13413ea9a877	861	MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
ganlikun	0:13413ea9a877	862
ganlikun	0:13413ea9a877	863	/* Set the Output State */
ganlikun	0:13413ea9a877	864	MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
ganlikun	0:13413ea9a877	865
ganlikun	0:13413ea9a877	866	if (IS_TIM_BREAK_INSTANCE(TIMx))
ganlikun	0:13413ea9a877	867	{
ganlikun	0:13413ea9a877	868	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
ganlikun	0:13413ea9a877	869	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
ganlikun	0:13413ea9a877	870
ganlikun	0:13413ea9a877	871	/* Set the complementary output Polarity */
ganlikun	0:13413ea9a877	872	MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
ganlikun	0:13413ea9a877	873
ganlikun	0:13413ea9a877	874	/* Set the complementary output State */
ganlikun	0:13413ea9a877	875	MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
ganlikun	0:13413ea9a877	876
ganlikun	0:13413ea9a877	877	/* Set the Output Idle state */
ganlikun	0:13413ea9a877	878	MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
ganlikun	0:13413ea9a877	879
ganlikun	0:13413ea9a877	880	/* Set the complementary output Idle state */
ganlikun	0:13413ea9a877	881	MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
ganlikun	0:13413ea9a877	882	}
ganlikun	0:13413ea9a877	883
ganlikun	0:13413ea9a877	884	/* Write to TIMx CR2 */
ganlikun	0:13413ea9a877	885	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
ganlikun	0:13413ea9a877	886
ganlikun	0:13413ea9a877	887	/* Write to TIMx CCMR1 */
ganlikun	0:13413ea9a877	888	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
ganlikun	0:13413ea9a877	889
ganlikun	0:13413ea9a877	890	/* Set the Capture Compare Register value */
ganlikun	0:13413ea9a877	891	LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
ganlikun	0:13413ea9a877	892
ganlikun	0:13413ea9a877	893	/* Write to TIMx CCER */
ganlikun	0:13413ea9a877	894	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
ganlikun	0:13413ea9a877	895
ganlikun	0:13413ea9a877	896	return SUCCESS;
ganlikun	0:13413ea9a877	897	}
ganlikun	0:13413ea9a877	898
ganlikun	0:13413ea9a877	899	/**
ganlikun	0:13413ea9a877	900	* @brief Configure the TIMx output channel 3.
ganlikun	0:13413ea9a877	901	* @param TIMx Timer Instance
ganlikun	0:13413ea9a877	902	* @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
ganlikun	0:13413ea9a877	903	* @retval An ErrorStatus enumeration value:
ganlikun	0:13413ea9a877	904	* - SUCCESS: TIMx registers are de-initialized
ganlikun	0:13413ea9a877	905	* - ERROR: not applicable
ganlikun	0:13413ea9a877	906	*/
ganlikun	0:13413ea9a877	907	static ErrorStatus OC3Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
ganlikun	0:13413ea9a877	908	{
ganlikun	0:13413ea9a877	909	uint32_t tmpccmr2 = 0U;
ganlikun	0:13413ea9a877	910	uint32_t tmpccer = 0U;
ganlikun	0:13413ea9a877	911	uint32_t tmpcr2 = 0U;
ganlikun	0:13413ea9a877	912
ganlikun	0:13413ea9a877	913	/* Check the parameters */
ganlikun	0:13413ea9a877	914	assert_param(IS_TIM_CC3_INSTANCE(TIMx));
ganlikun	0:13413ea9a877	915	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
ganlikun	0:13413ea9a877	916	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
ganlikun	0:13413ea9a877	917	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
ganlikun	0:13413ea9a877	918	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
ganlikun	0:13413ea9a877	919	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
ganlikun	0:13413ea9a877	920
ganlikun	0:13413ea9a877	921	/* Disable the Channel 3: Reset the CC3E Bit */
ganlikun	0:13413ea9a877	922	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
ganlikun	0:13413ea9a877	923
ganlikun	0:13413ea9a877	924	/* Get the TIMx CCER register value */
ganlikun	0:13413ea9a877	925	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
ganlikun	0:13413ea9a877	926
ganlikun	0:13413ea9a877	927	/* Get the TIMx CR2 register value */
ganlikun	0:13413ea9a877	928	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
ganlikun	0:13413ea9a877	929
ganlikun	0:13413ea9a877	930	/* Get the TIMx CCMR2 register value */
ganlikun	0:13413ea9a877	931	tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
ganlikun	0:13413ea9a877	932
ganlikun	0:13413ea9a877	933	/* Reset Capture/Compare selection Bits */
ganlikun	0:13413ea9a877	934	CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
ganlikun	0:13413ea9a877	935
ganlikun	0:13413ea9a877	936	/* Select the Output Compare Mode */
ganlikun	0:13413ea9a877	937	MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
ganlikun	0:13413ea9a877	938
ganlikun	0:13413ea9a877	939	/* Set the Output Compare Polarity */
ganlikun	0:13413ea9a877	940	MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
ganlikun	0:13413ea9a877	941
ganlikun	0:13413ea9a877	942	/* Set the Output State */
ganlikun	0:13413ea9a877	943	MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
ganlikun	0:13413ea9a877	944
ganlikun	0:13413ea9a877	945	if (IS_TIM_BREAK_INSTANCE(TIMx))
ganlikun	0:13413ea9a877	946	{
ganlikun	0:13413ea9a877	947	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
ganlikun	0:13413ea9a877	948	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
ganlikun	0:13413ea9a877	949
ganlikun	0:13413ea9a877	950	/* Set the complementary output Polarity */
ganlikun	0:13413ea9a877	951	MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
ganlikun	0:13413ea9a877	952
ganlikun	0:13413ea9a877	953	/* Set the complementary output State */
ganlikun	0:13413ea9a877	954	MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
ganlikun	0:13413ea9a877	955
ganlikun	0:13413ea9a877	956	/* Set the Output Idle state */
ganlikun	0:13413ea9a877	957	MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
ganlikun	0:13413ea9a877	958
ganlikun	0:13413ea9a877	959	/* Set the complementary output Idle state */
ganlikun	0:13413ea9a877	960	MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
ganlikun	0:13413ea9a877	961	}
ganlikun	0:13413ea9a877	962
ganlikun	0:13413ea9a877	963	/* Write to TIMx CR2 */
ganlikun	0:13413ea9a877	964	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
ganlikun	0:13413ea9a877	965
ganlikun	0:13413ea9a877	966	/* Write to TIMx CCMR2 */
ganlikun	0:13413ea9a877	967	LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
ganlikun	0:13413ea9a877	968
ganlikun	0:13413ea9a877	969	/* Set the Capture Compare Register value */
ganlikun	0:13413ea9a877	970	LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
ganlikun	0:13413ea9a877	971
ganlikun	0:13413ea9a877	972	/* Write to TIMx CCER */
ganlikun	0:13413ea9a877	973	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
ganlikun	0:13413ea9a877	974
ganlikun	0:13413ea9a877	975	return SUCCESS;
ganlikun	0:13413ea9a877	976	}
ganlikun	0:13413ea9a877	977
ganlikun	0:13413ea9a877	978	/**
ganlikun	0:13413ea9a877	979	* @brief Configure the TIMx output channel 4.
ganlikun	0:13413ea9a877	980	* @param TIMx Timer Instance
ganlikun	0:13413ea9a877	981	* @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
ganlikun	0:13413ea9a877	982	* @retval An ErrorStatus enumeration value:
ganlikun	0:13413ea9a877	983	* - SUCCESS: TIMx registers are de-initialized
ganlikun	0:13413ea9a877	984	* - ERROR: not applicable
ganlikun	0:13413ea9a877	985	*/
ganlikun	0:13413ea9a877	986	static ErrorStatus OC4Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
ganlikun	0:13413ea9a877	987	{
ganlikun	0:13413ea9a877	988	uint32_t tmpccmr2 = 0U;
ganlikun	0:13413ea9a877	989	uint32_t tmpccer = 0U;
ganlikun	0:13413ea9a877	990	uint32_t tmpcr2 = 0U;
ganlikun	0:13413ea9a877	991
ganlikun	0:13413ea9a877	992	/* Check the parameters */
ganlikun	0:13413ea9a877	993	assert_param(IS_TIM_CC4_INSTANCE(TIMx));
ganlikun	0:13413ea9a877	994	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
ganlikun	0:13413ea9a877	995	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
ganlikun	0:13413ea9a877	996	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
ganlikun	0:13413ea9a877	997	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
ganlikun	0:13413ea9a877	998	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
ganlikun	0:13413ea9a877	999
ganlikun	0:13413ea9a877	1000	/* Disable the Channel 4: Reset the CC4E Bit */
ganlikun	0:13413ea9a877	1001	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
ganlikun	0:13413ea9a877	1002
ganlikun	0:13413ea9a877	1003	/* Get the TIMx CCER register value */
ganlikun	0:13413ea9a877	1004	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
ganlikun	0:13413ea9a877	1005
ganlikun	0:13413ea9a877	1006	/* Get the TIMx CR2 register value */
ganlikun	0:13413ea9a877	1007	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
ganlikun	0:13413ea9a877	1008
ganlikun	0:13413ea9a877	1009	/* Get the TIMx CCMR2 register value */
ganlikun	0:13413ea9a877	1010	tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
ganlikun	0:13413ea9a877	1011
ganlikun	0:13413ea9a877	1012	/* Reset Capture/Compare selection Bits */
ganlikun	0:13413ea9a877	1013	CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
ganlikun	0:13413ea9a877	1014
ganlikun	0:13413ea9a877	1015	/* Select the Output Compare Mode */
ganlikun	0:13413ea9a877	1016	MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
ganlikun	0:13413ea9a877	1017
ganlikun	0:13413ea9a877	1018	/* Set the Output Compare Polarity */
ganlikun	0:13413ea9a877	1019	MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
ganlikun	0:13413ea9a877	1020
ganlikun	0:13413ea9a877	1021	/* Set the Output State */
ganlikun	0:13413ea9a877	1022	MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
ganlikun	0:13413ea9a877	1023
ganlikun	0:13413ea9a877	1024	if (IS_TIM_BREAK_INSTANCE(TIMx))
ganlikun	0:13413ea9a877	1025	{
ganlikun	0:13413ea9a877	1026	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
ganlikun	0:13413ea9a877	1027	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
ganlikun	0:13413ea9a877	1028
ganlikun	0:13413ea9a877	1029	/* Set the Output Idle state */
ganlikun	0:13413ea9a877	1030	MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
ganlikun	0:13413ea9a877	1031	}
ganlikun	0:13413ea9a877	1032
ganlikun	0:13413ea9a877	1033	/* Write to TIMx CR2 */
ganlikun	0:13413ea9a877	1034	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
ganlikun	0:13413ea9a877	1035
ganlikun	0:13413ea9a877	1036	/* Write to TIMx CCMR2 */
ganlikun	0:13413ea9a877	1037	LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
ganlikun	0:13413ea9a877	1038
ganlikun	0:13413ea9a877	1039	/* Set the Capture Compare Register value */
ganlikun	0:13413ea9a877	1040	LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
ganlikun	0:13413ea9a877	1041
ganlikun	0:13413ea9a877	1042	/* Write to TIMx CCER */
ganlikun	0:13413ea9a877	1043	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
ganlikun	0:13413ea9a877	1044
ganlikun	0:13413ea9a877	1045	return SUCCESS;
ganlikun	0:13413ea9a877	1046	}
ganlikun	0:13413ea9a877	1047
ganlikun	0:13413ea9a877	1048
ganlikun	0:13413ea9a877	1049	/**
ganlikun	0:13413ea9a877	1050	* @brief Configure the TIMx input channel 1.
ganlikun	0:13413ea9a877	1051	* @param TIMx Timer Instance
ganlikun	0:13413ea9a877	1052	* @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
ganlikun	0:13413ea9a877	1053	* @retval An ErrorStatus enumeration value:
ganlikun	0:13413ea9a877	1054	* - SUCCESS: TIMx registers are de-initialized
ganlikun	0:13413ea9a877	1055	* - ERROR: not applicable
ganlikun	0:13413ea9a877	1056	*/
ganlikun	0:13413ea9a877	1057	static ErrorStatus IC1Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
ganlikun	0:13413ea9a877	1058	{
ganlikun	0:13413ea9a877	1059	/* Check the parameters */
ganlikun	0:13413ea9a877	1060	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
ganlikun	0:13413ea9a877	1061	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
ganlikun	0:13413ea9a877	1062	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
ganlikun	0:13413ea9a877	1063	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
ganlikun	0:13413ea9a877	1064	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
ganlikun	0:13413ea9a877	1065
ganlikun	0:13413ea9a877	1066	/* Disable the Channel 1: Reset the CC1E Bit */
ganlikun	0:13413ea9a877	1067	TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
ganlikun	0:13413ea9a877	1068
ganlikun	0:13413ea9a877	1069	/* Select the Input and set the filter and the prescaler value */
ganlikun	0:13413ea9a877	1070	MODIFY_REG(TIMx->CCMR1,
ganlikun	0:13413ea9a877	1071	(TIM_CCMR1_CC1S \| TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC),
ganlikun	0:13413ea9a877	1072	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 16U);
ganlikun	0:13413ea9a877	1073
ganlikun	0:13413ea9a877	1074	/* Select the Polarity and set the CC1E Bit */
ganlikun	0:13413ea9a877	1075	MODIFY_REG(TIMx->CCER,
ganlikun	0:13413ea9a877	1076	(TIM_CCER_CC1P \| TIM_CCER_CC1NP),
ganlikun	0:13413ea9a877	1077	(TIM_ICInitStruct->ICPolarity \| TIM_CCER_CC1E));
ganlikun	0:13413ea9a877	1078
ganlikun	0:13413ea9a877	1079	return SUCCESS;
ganlikun	0:13413ea9a877	1080	}
ganlikun	0:13413ea9a877	1081
ganlikun	0:13413ea9a877	1082	/**
ganlikun	0:13413ea9a877	1083	* @brief Configure the TIMx input channel 2.
ganlikun	0:13413ea9a877	1084	* @param TIMx Timer Instance
ganlikun	0:13413ea9a877	1085	* @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
ganlikun	0:13413ea9a877	1086	* @retval An ErrorStatus enumeration value:
ganlikun	0:13413ea9a877	1087	* - SUCCESS: TIMx registers are de-initialized
ganlikun	0:13413ea9a877	1088	* - ERROR: not applicable
ganlikun	0:13413ea9a877	1089	*/
ganlikun	0:13413ea9a877	1090	static ErrorStatus IC2Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
ganlikun	0:13413ea9a877	1091	{
ganlikun	0:13413ea9a877	1092	/* Check the parameters */
ganlikun	0:13413ea9a877	1093	assert_param(IS_TIM_CC2_INSTANCE(TIMx));
ganlikun	0:13413ea9a877	1094	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
ganlikun	0:13413ea9a877	1095	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
ganlikun	0:13413ea9a877	1096	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
ganlikun	0:13413ea9a877	1097	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
ganlikun	0:13413ea9a877	1098
ganlikun	0:13413ea9a877	1099	/* Disable the Channel 2: Reset the CC2E Bit */
ganlikun	0:13413ea9a877	1100	TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
ganlikun	0:13413ea9a877	1101
ganlikun	0:13413ea9a877	1102	/* Select the Input and set the filter and the prescaler value */
ganlikun	0:13413ea9a877	1103	MODIFY_REG(TIMx->CCMR1,
ganlikun	0:13413ea9a877	1104	(TIM_CCMR1_CC2S \| TIM_CCMR1_IC2F \| TIM_CCMR1_IC2PSC),
ganlikun	0:13413ea9a877	1105	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 8U);
ganlikun	0:13413ea9a877	1106
ganlikun	0:13413ea9a877	1107	/* Select the Polarity and set the CC2E Bit */
ganlikun	0:13413ea9a877	1108	MODIFY_REG(TIMx->CCER,
ganlikun	0:13413ea9a877	1109	(TIM_CCER_CC2P \| TIM_CCER_CC2NP),
ganlikun	0:13413ea9a877	1110	((TIM_ICInitStruct->ICPolarity << 4U) \| TIM_CCER_CC2E));
ganlikun	0:13413ea9a877	1111
ganlikun	0:13413ea9a877	1112	return SUCCESS;
ganlikun	0:13413ea9a877	1113	}
ganlikun	0:13413ea9a877	1114
ganlikun	0:13413ea9a877	1115	/**
ganlikun	0:13413ea9a877	1116	* @brief Configure the TIMx input channel 3.
ganlikun	0:13413ea9a877	1117	* @param TIMx Timer Instance
ganlikun	0:13413ea9a877	1118	* @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
ganlikun	0:13413ea9a877	1119	* @retval An ErrorStatus enumeration value:
ganlikun	0:13413ea9a877	1120	* - SUCCESS: TIMx registers are de-initialized
ganlikun	0:13413ea9a877	1121	* - ERROR: not applicable
ganlikun	0:13413ea9a877	1122	*/
ganlikun	0:13413ea9a877	1123	static ErrorStatus IC3Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
ganlikun	0:13413ea9a877	1124	{
ganlikun	0:13413ea9a877	1125	/* Check the parameters */
ganlikun	0:13413ea9a877	1126	assert_param(IS_TIM_CC3_INSTANCE(TIMx));
ganlikun	0:13413ea9a877	1127	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
ganlikun	0:13413ea9a877	1128	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
ganlikun	0:13413ea9a877	1129	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
ganlikun	0:13413ea9a877	1130	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
ganlikun	0:13413ea9a877	1131
ganlikun	0:13413ea9a877	1132	/* Disable the Channel 3: Reset the CC3E Bit */
ganlikun	0:13413ea9a877	1133	TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
ganlikun	0:13413ea9a877	1134
ganlikun	0:13413ea9a877	1135	/* Select the Input and set the filter and the prescaler value */
ganlikun	0:13413ea9a877	1136	MODIFY_REG(TIMx->CCMR2,
ganlikun	0:13413ea9a877	1137	(TIM_CCMR2_CC3S \| TIM_CCMR2_IC3F \| TIM_CCMR2_IC3PSC),
ganlikun	0:13413ea9a877	1138	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 16U);
ganlikun	0:13413ea9a877	1139
ganlikun	0:13413ea9a877	1140	/* Select the Polarity and set the CC3E Bit */
ganlikun	0:13413ea9a877	1141	MODIFY_REG(TIMx->CCER,
ganlikun	0:13413ea9a877	1142	(TIM_CCER_CC3P \| TIM_CCER_CC3NP),
ganlikun	0:13413ea9a877	1143	((TIM_ICInitStruct->ICPolarity << 8U) \| TIM_CCER_CC3E));
ganlikun	0:13413ea9a877	1144
ganlikun	0:13413ea9a877	1145	return SUCCESS;
ganlikun	0:13413ea9a877	1146	}
ganlikun	0:13413ea9a877	1147
ganlikun	0:13413ea9a877	1148	/**
ganlikun	0:13413ea9a877	1149	* @brief Configure the TIMx input channel 4.
ganlikun	0:13413ea9a877	1150	* @param TIMx Timer Instance
ganlikun	0:13413ea9a877	1151	* @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
ganlikun	0:13413ea9a877	1152	* @retval An ErrorStatus enumeration value:
ganlikun	0:13413ea9a877	1153	* - SUCCESS: TIMx registers are de-initialized
ganlikun	0:13413ea9a877	1154	* - ERROR: not applicable
ganlikun	0:13413ea9a877	1155	*/
ganlikun	0:13413ea9a877	1156	static ErrorStatus IC4Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
ganlikun	0:13413ea9a877	1157	{
ganlikun	0:13413ea9a877	1158	/* Check the parameters */
ganlikun	0:13413ea9a877	1159	assert_param(IS_TIM_CC4_INSTANCE(TIMx));
ganlikun	0:13413ea9a877	1160	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
ganlikun	0:13413ea9a877	1161	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
ganlikun	0:13413ea9a877	1162	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
ganlikun	0:13413ea9a877	1163	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
ganlikun	0:13413ea9a877	1164
ganlikun	0:13413ea9a877	1165	/* Disable the Channel 4: Reset the CC4E Bit */
ganlikun	0:13413ea9a877	1166	TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
ganlikun	0:13413ea9a877	1167
ganlikun	0:13413ea9a877	1168	/* Select the Input and set the filter and the prescaler value */
ganlikun	0:13413ea9a877	1169	MODIFY_REG(TIMx->CCMR2,
ganlikun	0:13413ea9a877	1170	(TIM_CCMR2_CC4S \| TIM_CCMR2_IC4F \| TIM_CCMR2_IC4PSC),
ganlikun	0:13413ea9a877	1171	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 8U);
ganlikun	0:13413ea9a877	1172
ganlikun	0:13413ea9a877	1173	/* Select the Polarity and set the CC2E Bit */
ganlikun	0:13413ea9a877	1174	MODIFY_REG(TIMx->CCER,
ganlikun	0:13413ea9a877	1175	(TIM_CCER_CC4P \| TIM_CCER_CC4NP),
ganlikun	0:13413ea9a877	1176	((TIM_ICInitStruct->ICPolarity << 12U) \| TIM_CCER_CC4E));
ganlikun	0:13413ea9a877	1177
ganlikun	0:13413ea9a877	1178	return SUCCESS;
ganlikun	0:13413ea9a877	1179	}
ganlikun	0:13413ea9a877	1180
ganlikun	0:13413ea9a877	1181
ganlikun	0:13413ea9a877	1182	/**
ganlikun	0:13413ea9a877	1183	* @}
ganlikun	0:13413ea9a877	1184	*/
ganlikun	0:13413ea9a877	1185
ganlikun	0:13413ea9a877	1186	/**
ganlikun	0:13413ea9a877	1187	* @}
ganlikun	0:13413ea9a877	1188	*/
ganlikun	0:13413ea9a877	1189
ganlikun	0:13413ea9a877	1190	#endif /* TIM1 \|\| TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\| TIM6 \|\| TIM7 \|\| TIM8 \|\| TIM9 \|\| TIM10 \|\| TIM11 \|\| TIM12 \|\| TIM13 \|\| TIM14 */
ganlikun	0:13413ea9a877	1191
ganlikun	0:13413ea9a877	1192	/**
ganlikun	0:13413ea9a877	1193	* @}
ganlikun	0:13413ea9a877	1194	*/
ganlikun	0:13413ea9a877	1195
ganlikun	0:13413ea9a877	1196	#endif /* USE_FULL_LL_DRIVER */
ganlikun	0:13413ea9a877	1197
ganlikun	0:13413ea9a877	1198	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
ganlikun	0:13413ea9a877	1199

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Type:	Library
Created:	05 Jul 2022
Imports:	1
Forks:	0
Commits:	1
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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.c@0:13413ea9a877, 2022-06-12 (annotated)

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