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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_system.h@0:13413ea9a877, 2022-06-12 (annotated)

Committer:: ganlikun
Date:: Sun Jun 12 14:02:44 2022 +0000
Revision:: 0:13413ea9a877

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User	Revision	Line number	New contents of line
ganlikun	0:13413ea9a877	1	/**
ganlikun	0:13413ea9a877	2	******************************************************************************
ganlikun	0:13413ea9a877	3	* @file stm32f4xx_ll_system.h
ganlikun	0:13413ea9a877	4	* @author MCD Application Team
ganlikun	0:13413ea9a877	5	* @version V1.7.1
ganlikun	0:13413ea9a877	6	* @date 14-April-2017
ganlikun	0:13413ea9a877	7	* @brief Header file of SYSTEM LL module.
ganlikun	0:13413ea9a877	8	@verbatim
ganlikun	0:13413ea9a877	9	==============================================================================
ganlikun	0:13413ea9a877	10	##### How to use this driver #####
ganlikun	0:13413ea9a877	11	==============================================================================
ganlikun	0:13413ea9a877	12	[..]
ganlikun	0:13413ea9a877	13	The LL SYSTEM driver contains a set of generic APIs that can be
ganlikun	0:13413ea9a877	14	used by user:
ganlikun	0:13413ea9a877	15	(+) Some of the FLASH features need to be handled in the SYSTEM file.
ganlikun	0:13413ea9a877	16	(+) Access to DBGCMU registers
ganlikun	0:13413ea9a877	17	(+) Access to SYSCFG registers
ganlikun	0:13413ea9a877	18
ganlikun	0:13413ea9a877	19	@endverbatim
ganlikun	0:13413ea9a877	20	******************************************************************************
ganlikun	0:13413ea9a877	21	* @attention
ganlikun	0:13413ea9a877	22	*
ganlikun	0:13413ea9a877	23	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun	0:13413ea9a877	24	*
ganlikun	0:13413ea9a877	25	* Redistribution and use in source and binary forms, with or without modification,
ganlikun	0:13413ea9a877	26	* are permitted provided that the following conditions are met:
ganlikun	0:13413ea9a877	27	* 1. Redistributions of source code must retain the above copyright notice,
ganlikun	0:13413ea9a877	28	* this list of conditions and the following disclaimer.
ganlikun	0:13413ea9a877	29	* 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun	0:13413ea9a877	30	* this list of conditions and the following disclaimer in the documentation
ganlikun	0:13413ea9a877	31	* and/or other materials provided with the distribution.
ganlikun	0:13413ea9a877	32	* 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun	0:13413ea9a877	33	* may be used to endorse or promote products derived from this software
ganlikun	0:13413ea9a877	34	* without specific prior written permission.
ganlikun	0:13413ea9a877	35	*
ganlikun	0:13413ea9a877	36	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun	0:13413ea9a877	37	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun	0:13413ea9a877	38	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun	0:13413ea9a877	39	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun	0:13413ea9a877	40	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun	0:13413ea9a877	41	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun	0:13413ea9a877	42	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun	0:13413ea9a877	43	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun	0:13413ea9a877	44	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun	0:13413ea9a877	45	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun	0:13413ea9a877	46	*
ganlikun	0:13413ea9a877	47	******************************************************************************
ganlikun	0:13413ea9a877	48	*/
ganlikun	0:13413ea9a877	49
ganlikun	0:13413ea9a877	50	/* Define to prevent recursive inclusion -------------------------------------*/
ganlikun	0:13413ea9a877	51	#ifndef __STM32F4xx_LL_SYSTEM_H
ganlikun	0:13413ea9a877	52	#define __STM32F4xx_LL_SYSTEM_H
ganlikun	0:13413ea9a877	53
ganlikun	0:13413ea9a877	54	#ifdef __cplusplus
ganlikun	0:13413ea9a877	55	extern "C" {
ganlikun	0:13413ea9a877	56	#endif
ganlikun	0:13413ea9a877	57
ganlikun	0:13413ea9a877	58	/* Includes ------------------------------------------------------------------*/
ganlikun	0:13413ea9a877	59	#include "stm32f4xx.h"
ganlikun	0:13413ea9a877	60
ganlikun	0:13413ea9a877	61	/** @addtogroup STM32F4xx_LL_Driver
ganlikun	0:13413ea9a877	62	* @{
ganlikun	0:13413ea9a877	63	*/
ganlikun	0:13413ea9a877	64
ganlikun	0:13413ea9a877	65	#if defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU)
ganlikun	0:13413ea9a877	66
ganlikun	0:13413ea9a877	67	/** @defgroup SYSTEM_LL SYSTEM
ganlikun	0:13413ea9a877	68	* @{
ganlikun	0:13413ea9a877	69	*/
ganlikun	0:13413ea9a877	70
ganlikun	0:13413ea9a877	71	/* Private types -------------------------------------------------------------*/
ganlikun	0:13413ea9a877	72	/* Private variables ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	73
ganlikun	0:13413ea9a877	74	/* Private constants ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	75	/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
ganlikun	0:13413ea9a877	76	* @{
ganlikun	0:13413ea9a877	77	*/
ganlikun	0:13413ea9a877	78
ganlikun	0:13413ea9a877	79	/**
ganlikun	0:13413ea9a877	80	* @}
ganlikun	0:13413ea9a877	81	*/
ganlikun	0:13413ea9a877	82
ganlikun	0:13413ea9a877	83	/* Private macros ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	84
ganlikun	0:13413ea9a877	85	/* Exported types ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	86	/* Exported constants --------------------------------------------------------*/
ganlikun	0:13413ea9a877	87	/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
ganlikun	0:13413ea9a877	88	* @{
ganlikun	0:13413ea9a877	89	*/
ganlikun	0:13413ea9a877	90
ganlikun	0:13413ea9a877	91	/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
ganlikun	0:13413ea9a877	92	* @{
ganlikun	0:13413ea9a877	93	*/
ganlikun	0:13413ea9a877	94	#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /!< Main Flash memory mapped at 0x00000000 /
ganlikun	0:13413ea9a877	95	#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /!< System Flash memory mapped at 0x00000000 /
ganlikun	0:13413ea9a877	96	#if defined(FSMC_Bank1)
ganlikun	0:13413ea9a877	97	#define LL_SYSCFG_REMAP_FSMC SYSCFG_MEMRMP_MEM_MODE_1 /!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 /
ganlikun	0:13413ea9a877	98	#endif /* FSMC_Bank1 */
ganlikun	0:13413ea9a877	99	#if defined(FMC_Bank1)
ganlikun	0:13413ea9a877	100	#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /!< FMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 /
ganlikun	0:13413ea9a877	101	#endif /* FMC_Bank1 */
ganlikun	0:13413ea9a877	102	#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 \| SYSCFG_MEMRMP_MEM_MODE_0) /!< SRAM1 mapped at 0x00000000 /
ganlikun	0:13413ea9a877	103	/**
ganlikun	0:13413ea9a877	104	* @}
ganlikun	0:13413ea9a877	105	*/
ganlikun	0:13413ea9a877	106
ganlikun	0:13413ea9a877	107	#if defined(SYSCFG_PMC_MII_RMII_SEL)
ganlikun	0:13413ea9a877	108	/** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC
ganlikun	0:13413ea9a877	109	* @{
ganlikun	0:13413ea9a877	110	*/
ganlikun	0:13413ea9a877	111	#define LL_SYSCFG_PMC_ETHMII (uint32_t)0x00000000 /!< ETH Media MII interface /
ganlikun	0:13413ea9a877	112	#define LL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SEL /!< ETH Media RMII interface /
ganlikun	0:13413ea9a877	113
ganlikun	0:13413ea9a877	114	/**
ganlikun	0:13413ea9a877	115	* @}
ganlikun	0:13413ea9a877	116	*/
ganlikun	0:13413ea9a877	117	#endif /* SYSCFG_PMC_MII_RMII_SEL */
ganlikun	0:13413ea9a877	118
ganlikun	0:13413ea9a877	119
ganlikun	0:13413ea9a877	120
ganlikun	0:13413ea9a877	121	#if defined(SYSCFG_MEMRMP_UFB_MODE)
ganlikun	0:13413ea9a877	122	/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
ganlikun	0:13413ea9a877	123	* @{
ganlikun	0:13413ea9a877	124	*/
ganlikun	0:13413ea9a877	125	#define LL_SYSCFG_BANKMODE_BANK1 (uint32_t)0x00000000 /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM)
ganlikun	0:13413ea9a877	126	and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/
ganlikun	0:13413ea9a877	127	#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_UFB_MODE /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM)
ganlikun	0:13413ea9a877	128	and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */
ganlikun	0:13413ea9a877	129	/**
ganlikun	0:13413ea9a877	130	* @}
ganlikun	0:13413ea9a877	131	*/
ganlikun	0:13413ea9a877	132	#endif /* SYSCFG_MEMRMP_UFB_MODE */
ganlikun	0:13413ea9a877	133	/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
ganlikun	0:13413ea9a877	134	* @{
ganlikun	0:13413ea9a877	135	*/
ganlikun	0:13413ea9a877	136	#if defined(SYSCFG_CFGR_FMPI2C1_SCL)
ganlikun	0:13413ea9a877	137	#define LL_SYSCFG_I2C_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL /!< Enable Fast Mode Plus on FMPI2C_SCL pin /
ganlikun	0:13413ea9a877	138	#define LL_SYSCFG_I2C_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA /!< Enable Fast Mode Plus on FMPI2C_SDA pin/
ganlikun	0:13413ea9a877	139	#endif /* SYSCFG_CFGR_FMPI2C1_SCL */
ganlikun	0:13413ea9a877	140	/**
ganlikun	0:13413ea9a877	141	* @}
ganlikun	0:13413ea9a877	142	*/
ganlikun	0:13413ea9a877	143
ganlikun	0:13413ea9a877	144	/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
ganlikun	0:13413ea9a877	145	* @{
ganlikun	0:13413ea9a877	146	*/
ganlikun	0:13413ea9a877	147	#define LL_SYSCFG_EXTI_PORTA (uint32_t)0 /!< EXTI PORT A /
ganlikun	0:13413ea9a877	148	#define LL_SYSCFG_EXTI_PORTB (uint32_t)1 /!< EXTI PORT B /
ganlikun	0:13413ea9a877	149	#define LL_SYSCFG_EXTI_PORTC (uint32_t)2 /!< EXTI PORT C /
ganlikun	0:13413ea9a877	150	#define LL_SYSCFG_EXTI_PORTD (uint32_t)3 /!< EXTI PORT D /
ganlikun	0:13413ea9a877	151	#define LL_SYSCFG_EXTI_PORTE (uint32_t)4 /!< EXTI PORT E /
ganlikun	0:13413ea9a877	152	#if defined(GPIOF)
ganlikun	0:13413ea9a877	153	#define LL_SYSCFG_EXTI_PORTF (uint32_t)5 /!< EXTI PORT F /
ganlikun	0:13413ea9a877	154	#endif /* GPIOF */
ganlikun	0:13413ea9a877	155	#if defined(GPIOG)
ganlikun	0:13413ea9a877	156	#define LL_SYSCFG_EXTI_PORTG (uint32_t)6 /!< EXTI PORT G /
ganlikun	0:13413ea9a877	157	#endif /* GPIOG */
ganlikun	0:13413ea9a877	158	#define LL_SYSCFG_EXTI_PORTH (uint32_t)7 /!< EXTI PORT H /
ganlikun	0:13413ea9a877	159	#if defined(GPIOI)
ganlikun	0:13413ea9a877	160	#define LL_SYSCFG_EXTI_PORTI (uint32_t)8 /!< EXTI PORT I /
ganlikun	0:13413ea9a877	161	#endif /* GPIOI */
ganlikun	0:13413ea9a877	162	#if defined(GPIOJ)
ganlikun	0:13413ea9a877	163	#define LL_SYSCFG_EXTI_PORTJ (uint32_t)9 /!< EXTI PORT J /
ganlikun	0:13413ea9a877	164	#endif /* GPIOJ */
ganlikun	0:13413ea9a877	165	#if defined(GPIOK)
ganlikun	0:13413ea9a877	166	#define LL_SYSCFG_EXTI_PORTK (uint32_t)10 /!< EXTI PORT k /
ganlikun	0:13413ea9a877	167	#endif /* GPIOK */
ganlikun	0:13413ea9a877	168	/**
ganlikun	0:13413ea9a877	169	* @}
ganlikun	0:13413ea9a877	170	*/
ganlikun	0:13413ea9a877	171
ganlikun	0:13413ea9a877	172	/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
ganlikun	0:13413ea9a877	173	* @{
ganlikun	0:13413ea9a877	174	*/
ganlikun	0:13413ea9a877	175	#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16 \| 0) /!< EXTI_POSITION_0 \| EXTICR[0] /
ganlikun	0:13413ea9a877	176	#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16 \| 0) /!< EXTI_POSITION_4 \| EXTICR[0] /
ganlikun	0:13413ea9a877	177	#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16 \| 0) /!< EXTI_POSITION_8 \| EXTICR[0] /
ganlikun	0:13413ea9a877	178	#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16 \| 0) /!< EXTI_POSITION_12 \| EXTICR[0] /
ganlikun	0:13413ea9a877	179	#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16 \| 1) /!< EXTI_POSITION_0 \| EXTICR[1] /
ganlikun	0:13413ea9a877	180	#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16 \| 1) /!< EXTI_POSITION_4 \| EXTICR[1] /
ganlikun	0:13413ea9a877	181	#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16 \| 1) /!< EXTI_POSITION_8 \| EXTICR[1] /
ganlikun	0:13413ea9a877	182	#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16 \| 1) /!< EXTI_POSITION_12 \| EXTICR[1] /
ganlikun	0:13413ea9a877	183	#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16 \| 2) /!< EXTI_POSITION_0 \| EXTICR[2] /
ganlikun	0:13413ea9a877	184	#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16 \| 2) /!< EXTI_POSITION_4 \| EXTICR[2] /
ganlikun	0:13413ea9a877	185	#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16 \| 2) /!< EXTI_POSITION_8 \| EXTICR[2] /
ganlikun	0:13413ea9a877	186	#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16 \| 2) /!< EXTI_POSITION_12 \| EXTICR[2] /
ganlikun	0:13413ea9a877	187	#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16 \| 3) /!< EXTI_POSITION_0 \| EXTICR[3] /
ganlikun	0:13413ea9a877	188	#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16 \| 3) /!< EXTI_POSITION_4 \| EXTICR[3] /
ganlikun	0:13413ea9a877	189	#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16 \| 3) /!< EXTI_POSITION_8 \| EXTICR[3] /
ganlikun	0:13413ea9a877	190	#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16 \| 3) /!< EXTI_POSITION_12 \| EXTICR[3] /
ganlikun	0:13413ea9a877	191	/**
ganlikun	0:13413ea9a877	192	* @}
ganlikun	0:13413ea9a877	193	*/
ganlikun	0:13413ea9a877	194
ganlikun	0:13413ea9a877	195	/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
ganlikun	0:13413ea9a877	196	* @{
ganlikun	0:13413ea9a877	197	*/
ganlikun	0:13413ea9a877	198	#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
ganlikun	0:13413ea9a877	199	#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM4
ganlikun	0:13413ea9a877	200	with Break Input of TIM1/8 */
ganlikun	0:13413ea9a877	201	#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8 Break Input
ganlikun	0:13413ea9a877	202	and also the PVDE and PLS bits of the Power Control Interface */
ganlikun	0:13413ea9a877	203	#endif /* SYSCFG_CFGR2_CLL */
ganlikun	0:13413ea9a877	204	/**
ganlikun	0:13413ea9a877	205	* @}
ganlikun	0:13413ea9a877	206	*/
ganlikun	0:13413ea9a877	207
ganlikun	0:13413ea9a877	208	#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
ganlikun	0:13413ea9a877	209	/** @defgroup SYSTEM_LL_DFSDM_BitStream_ClockSource SYSCFG MCHDLY BCKKSEL
ganlikun	0:13413ea9a877	210	* @{
ganlikun	0:13413ea9a877	211	*/
ganlikun	0:13413ea9a877	212	#define LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1 (uint32_t)0x00000000
ganlikun	0:13413ea9a877	213	#define LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_BSCKSEL
ganlikun	0:13413ea9a877	214	/**
ganlikun	0:13413ea9a877	215	* @}
ganlikun	0:13413ea9a877	216	*/
ganlikun	0:13413ea9a877	217	/** @defgroup SYSTEM_LL_DFSDM_MCHDLYEN SYSCFG MCHDLY MCHDLYEN
ganlikun	0:13413ea9a877	218	* @{
ganlikun	0:13413ea9a877	219	*/
ganlikun	0:13413ea9a877	220	#define LL_SYSCFG_DFSDM1_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY1EN
ganlikun	0:13413ea9a877	221	#define LL_SYSCFG_DFSDM2_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY2EN
ganlikun	0:13413ea9a877	222	/**
ganlikun	0:13413ea9a877	223	* @}
ganlikun	0:13413ea9a877	224	*/
ganlikun	0:13413ea9a877	225	/** @defgroup SYSTEM_LL_DFSDM_DataIn0_Source SYSCFG MCHDLY DFSDMD0SEL
ganlikun	0:13413ea9a877	226	* @{
ganlikun	0:13413ea9a877	227	*/
ganlikun	0:13413ea9a877	228	#define LL_SYSCFG_DFSDM1_DataIn0 SYSCFG_MCHDLYCR_DFSDM1D0SEL
ganlikun	0:13413ea9a877	229	#define LL_SYSCFG_DFSDM2_DataIn0 SYSCFG_MCHDLYCR_DFSDM2D0SEL
ganlikun	0:13413ea9a877	230
ganlikun	0:13413ea9a877	231	#define LL_SYSCFG_DFSDM1_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) \| 0x00000000)
ganlikun	0:13413ea9a877	232	#define LL_SYSCFG_DFSDM1_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) \| SYSCFG_MCHDLYCR_DFSDM1D0SEL)
ganlikun	0:13413ea9a877	233	#define LL_SYSCFG_DFSDM2_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) \| 0x00000000)
ganlikun	0:13413ea9a877	234	#define LL_SYSCFG_DFSDM2_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) \| SYSCFG_MCHDLYCR_DFSDM2D0SEL)
ganlikun	0:13413ea9a877	235	/**
ganlikun	0:13413ea9a877	236	* @}
ganlikun	0:13413ea9a877	237	*/
ganlikun	0:13413ea9a877	238	/** @defgroup SYSTEM_LL_DFSDM_DataIn2_Source SYSCFG MCHDLY DFSDMD2SEL
ganlikun	0:13413ea9a877	239	* @{
ganlikun	0:13413ea9a877	240	*/
ganlikun	0:13413ea9a877	241	#define LL_SYSCFG_DFSDM1_DataIn2 SYSCFG_MCHDLYCR_DFSDM1D2SEL
ganlikun	0:13413ea9a877	242	#define LL_SYSCFG_DFSDM2_DataIn2 SYSCFG_MCHDLYCR_DFSDM2D2SEL
ganlikun	0:13413ea9a877	243
ganlikun	0:13413ea9a877	244	#define LL_SYSCFG_DFSDM1_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) \| 0x00000000)
ganlikun	0:13413ea9a877	245	#define LL_SYSCFG_DFSDM1_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) \| SYSCFG_MCHDLYCR_DFSDM1D2SEL)
ganlikun	0:13413ea9a877	246	#define LL_SYSCFG_DFSDM2_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) \| 0x00000000)
ganlikun	0:13413ea9a877	247	#define LL_SYSCFG_DFSDM2_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) \| SYSCFG_MCHDLYCR_DFSDM2D2SEL)
ganlikun	0:13413ea9a877	248	/**
ganlikun	0:13413ea9a877	249	* @}
ganlikun	0:13413ea9a877	250	*/
ganlikun	0:13413ea9a877	251	/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK02SEL
ganlikun	0:13413ea9a877	252	* @{
ganlikun	0:13413ea9a877	253	*/
ganlikun	0:13413ea9a877	254	#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0 (uint32_t)0x00000000
ganlikun	0:13413ea9a877	255	#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL
ganlikun	0:13413ea9a877	256	/**
ganlikun	0:13413ea9a877	257	* @}
ganlikun	0:13413ea9a877	258	*/
ganlikun	0:13413ea9a877	259	/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK13SEL
ganlikun	0:13413ea9a877	260	* @{
ganlikun	0:13413ea9a877	261	*/
ganlikun	0:13413ea9a877	262	#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1 (uint32_t)0x00000000
ganlikun	0:13413ea9a877	263	#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL
ganlikun	0:13413ea9a877	264	/**
ganlikun	0:13413ea9a877	265	* @}
ganlikun	0:13413ea9a877	266	*/
ganlikun	0:13413ea9a877	267	/** @defgroup SYSTEM_LL_DFSDM1_CLKIN_SourceSelection SYSCFG MCHDLY DFSDMCFG
ganlikun	0:13413ea9a877	268	* @{
ganlikun	0:13413ea9a877	269	*/
ganlikun	0:13413ea9a877	270	#define LL_SYSCFG_DFSDM1_CKIN_PAD (uint32_t)0x00000000
ganlikun	0:13413ea9a877	271	#define LL_SYSCFG_DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG
ganlikun	0:13413ea9a877	272	/**
ganlikun	0:13413ea9a877	273	* @}
ganlikun	0:13413ea9a877	274	*/
ganlikun	0:13413ea9a877	275	/** @defgroup SYSTEM_LL_DFSDM1_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM1CKOSEL
ganlikun	0:13413ea9a877	276	* @{
ganlikun	0:13413ea9a877	277	*/
ganlikun	0:13413ea9a877	278	#define LL_SYSCFG_DFSDM1_CKOUT (uint32_t)0x00000000
ganlikun	0:13413ea9a877	279	#define LL_SYSCFG_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL
ganlikun	0:13413ea9a877	280	/**
ganlikun	0:13413ea9a877	281	* @}
ganlikun	0:13413ea9a877	282	*/
ganlikun	0:13413ea9a877	283
ganlikun	0:13413ea9a877	284	/** @defgroup SYSTEM_LL_DFSDM2_DataIn4_SourceSelection SYSCFG MCHDLY DFSDM2D4SEL
ganlikun	0:13413ea9a877	285	* @{
ganlikun	0:13413ea9a877	286	*/
ganlikun	0:13413ea9a877	287	#define LL_SYSCFG_DFSDM2_DataIn4_PAD (uint32_t)0x00000000
ganlikun	0:13413ea9a877	288	#define LL_SYSCFG_DFSDM2_DataIn4_DM SYSCFG_MCHDLYCR_DFSDM2D4SEL
ganlikun	0:13413ea9a877	289	/**
ganlikun	0:13413ea9a877	290	* @}
ganlikun	0:13413ea9a877	291	*/
ganlikun	0:13413ea9a877	292	/** @defgroup SYSTEM_LL_DFSDM2_DataIn6_SourceSelection SYSCFG MCHDLY DFSDM2D6SEL
ganlikun	0:13413ea9a877	293	* @{
ganlikun	0:13413ea9a877	294	*/
ganlikun	0:13413ea9a877	295	#define LL_SYSCFG_DFSDM2_DataIn6_PAD (uint32_t)0x00000000
ganlikun	0:13413ea9a877	296	#define LL_SYSCFG_DFSDM2_DataIn6_DM SYSCFG_MCHDLYCR_DFSDM2D6SEL
ganlikun	0:13413ea9a877	297	/**
ganlikun	0:13413ea9a877	298	* @}
ganlikun	0:13413ea9a877	299	*/
ganlikun	0:13413ea9a877	300	/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC4_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK04SEL
ganlikun	0:13413ea9a877	301	* @{
ganlikun	0:13413ea9a877	302	*/
ganlikun	0:13413ea9a877	303	#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0 (uint32_t)0x00000000
ganlikun	0:13413ea9a877	304	#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL
ganlikun	0:13413ea9a877	305	/**
ganlikun	0:13413ea9a877	306	* @}
ganlikun	0:13413ea9a877	307	*/
ganlikun	0:13413ea9a877	308	/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC3_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK15SEL
ganlikun	0:13413ea9a877	309	* @{
ganlikun	0:13413ea9a877	310	*/
ganlikun	0:13413ea9a877	311	#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1 (uint32_t)0x00000000
ganlikun	0:13413ea9a877	312	#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL
ganlikun	0:13413ea9a877	313	/**
ganlikun	0:13413ea9a877	314	* @}
ganlikun	0:13413ea9a877	315	*/
ganlikun	0:13413ea9a877	316	/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK26SEL
ganlikun	0:13413ea9a877	317	* @{
ganlikun	0:13413ea9a877	318	*/
ganlikun	0:13413ea9a877	319	#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2 (uint32_t)0x00000000
ganlikun	0:13413ea9a877	320	#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL
ganlikun	0:13413ea9a877	321	/**
ganlikun	0:13413ea9a877	322	* @}
ganlikun	0:13413ea9a877	323	*/
ganlikun	0:13413ea9a877	324	/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK37SEL
ganlikun	0:13413ea9a877	325	* @{
ganlikun	0:13413ea9a877	326	*/
ganlikun	0:13413ea9a877	327	#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3 (uint32_t)0x00000000
ganlikun	0:13413ea9a877	328	#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL
ganlikun	0:13413ea9a877	329	/**
ganlikun	0:13413ea9a877	330	* @}
ganlikun	0:13413ea9a877	331	*/
ganlikun	0:13413ea9a877	332	/** @defgroup SYSTEM_LL_DFSDM2_CLKIN_SourceSelection SYSCFG MCHDLY DFSDM2CFG
ganlikun	0:13413ea9a877	333	* @{
ganlikun	0:13413ea9a877	334	*/
ganlikun	0:13413ea9a877	335	#define LL_SYSCFG_DFSDM2_CKIN_PAD (uint32_t)0x00000000
ganlikun	0:13413ea9a877	336	#define LL_SYSCFG_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG
ganlikun	0:13413ea9a877	337	/**
ganlikun	0:13413ea9a877	338	* @}
ganlikun	0:13413ea9a877	339	*/
ganlikun	0:13413ea9a877	340	/** @defgroup SYSTEM_LL_DFSDM2_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM2CKOSEL
ganlikun	0:13413ea9a877	341	* @{
ganlikun	0:13413ea9a877	342	*/
ganlikun	0:13413ea9a877	343	#define LL_SYSCFG_DFSDM2_CKOUT (uint32_t)0x00000000
ganlikun	0:13413ea9a877	344	#define LL_SYSCFG_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL
ganlikun	0:13413ea9a877	345	/**
ganlikun	0:13413ea9a877	346	* @}
ganlikun	0:13413ea9a877	347	*/
ganlikun	0:13413ea9a877	348	#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
ganlikun	0:13413ea9a877	349
ganlikun	0:13413ea9a877	350	/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
ganlikun	0:13413ea9a877	351	* @{
ganlikun	0:13413ea9a877	352	*/
ganlikun	0:13413ea9a877	353	#define LL_DBGMCU_TRACE_NONE 0x00000000U /!< TRACE pins not assigned (default state) /
ganlikun	0:13413ea9a877	354	#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /!< TRACE pin assignment for Asynchronous Mode /
ganlikun	0:13413ea9a877	355	#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_0) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 /
ganlikun	0:13413ea9a877	356	#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_1) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 /
ganlikun	0:13413ea9a877	357	#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 /
ganlikun	0:13413ea9a877	358	/**
ganlikun	0:13413ea9a877	359	* @}
ganlikun	0:13413ea9a877	360	*/
ganlikun	0:13413ea9a877	361
ganlikun	0:13413ea9a877	362	/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
ganlikun	0:13413ea9a877	363	* @{
ganlikun	0:13413ea9a877	364	*/
ganlikun	0:13413ea9a877	365	#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
ganlikun	0:13413ea9a877	366	#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /!< TIM2 counter stopped when core is halted /
ganlikun	0:13413ea9a877	367	#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
ganlikun	0:13413ea9a877	368	#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
ganlikun	0:13413ea9a877	369	#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /!< TIM3 counter stopped when core is halted /
ganlikun	0:13413ea9a877	370	#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
ganlikun	0:13413ea9a877	371	#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
ganlikun	0:13413ea9a877	372	#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /!< TIM4 counter stopped when core is halted /
ganlikun	0:13413ea9a877	373	#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
ganlikun	0:13413ea9a877	374	#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /!< TIM5 counter stopped when core is halted /
ganlikun	0:13413ea9a877	375	#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
ganlikun	0:13413ea9a877	376	#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /!< TIM6 counter stopped when core is halted /
ganlikun	0:13413ea9a877	377	#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
ganlikun	0:13413ea9a877	378	#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
ganlikun	0:13413ea9a877	379	#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /!< TIM7 counter stopped when core is halted /
ganlikun	0:13413ea9a877	380	#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
ganlikun	0:13413ea9a877	381	#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
ganlikun	0:13413ea9a877	382	#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /!< TIM12 counter stopped when core is halted /
ganlikun	0:13413ea9a877	383	#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
ganlikun	0:13413ea9a877	384	#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
ganlikun	0:13413ea9a877	385	#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /!< TIM13 counter stopped when core is halted /
ganlikun	0:13413ea9a877	386	#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
ganlikun	0:13413ea9a877	387	#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
ganlikun	0:13413ea9a877	388	#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /!< TIM14 counter stopped when core is halted /
ganlikun	0:13413ea9a877	389	#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
ganlikun	0:13413ea9a877	390	#if defined(DBGMCU_APB1_FZ_DBG_LPTIM_STOP)
ganlikun	0:13413ea9a877	391	#define LL_DBGMCU_APB1_GRP1_LPTIM_STOP DBGMCU_APB1_FZ_DBG_LPTIM_STOP /!< LPTIM counter stopped when core is halted /
ganlikun	0:13413ea9a877	392	#endif /* DBGMCU_APB1_FZ_DBG_LPTIM_STOP */
ganlikun	0:13413ea9a877	393	#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /!< RTC counter stopped when core is halted /
ganlikun	0:13413ea9a877	394	#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /!< Debug Window Watchdog stopped when Core is halted /
ganlikun	0:13413ea9a877	395	#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /!< Debug Independent Watchdog stopped when Core is halted /
ganlikun	0:13413ea9a877	396	#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /!< I2C1 SMBUS timeout mode stopped when Core is halted /
ganlikun	0:13413ea9a877	397	#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /!< I2C2 SMBUS timeout mode stopped when Core is halted /
ganlikun	0:13413ea9a877	398	#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
ganlikun	0:13413ea9a877	399	#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /!< I2C3 SMBUS timeout mode stopped when Core is halted /
ganlikun	0:13413ea9a877	400	#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
ganlikun	0:13413ea9a877	401	#if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)
ganlikun	0:13413ea9a877	402	#define LL_DBGMCU_APB1_GRP1_I2C4_STOP DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /!< I2C4 SMBUS timeout mode stopped when Core is halted /
ganlikun	0:13413ea9a877	403	#endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */
ganlikun	0:13413ea9a877	404	#if defined(DBGMCU_APB1_FZ_DBG_CAN1_STOP)
ganlikun	0:13413ea9a877	405	#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /!< CAN1 debug stopped when Core is halted /
ganlikun	0:13413ea9a877	406	#endif /* DBGMCU_APB1_FZ_DBG_CAN1_STOP */
ganlikun	0:13413ea9a877	407	#if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP)
ganlikun	0:13413ea9a877	408	#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP /!< CAN2 debug stopped when Core is halted /
ganlikun	0:13413ea9a877	409	#endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */
ganlikun	0:13413ea9a877	410	#if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP)
ganlikun	0:13413ea9a877	411	#define LL_DBGMCU_APB1_GRP1_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP /!< CAN3 debug stopped when Core is halted /
ganlikun	0:13413ea9a877	412	#endif /* DBGMCU_APB1_FZ_DBG_CAN3_STOP */
ganlikun	0:13413ea9a877	413	/**
ganlikun	0:13413ea9a877	414	* @}
ganlikun	0:13413ea9a877	415	*/
ganlikun	0:13413ea9a877	416
ganlikun	0:13413ea9a877	417	/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
ganlikun	0:13413ea9a877	418	* @{
ganlikun	0:13413ea9a877	419	*/
ganlikun	0:13413ea9a877	420	#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /!< TIM1 counter stopped when core is halted /
ganlikun	0:13413ea9a877	421	#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
ganlikun	0:13413ea9a877	422	#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /!< TIM8 counter stopped when core is halted /
ganlikun	0:13413ea9a877	423	#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
ganlikun	0:13413ea9a877	424	#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /!< TIM9 counter stopped when core is halted /
ganlikun	0:13413ea9a877	425	#if defined(DBGMCU_APB2_FZ_DBG_TIM10_STOP)
ganlikun	0:13413ea9a877	426	#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /!< TIM10 counter stopped when core is halted /
ganlikun	0:13413ea9a877	427	#endif /* DBGMCU_APB2_FZ_DBG_TIM10_STOP */
ganlikun	0:13413ea9a877	428	#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /!< TIM11 counter stopped when core is halted /
ganlikun	0:13413ea9a877	429	/**
ganlikun	0:13413ea9a877	430	* @}
ganlikun	0:13413ea9a877	431	*/
ganlikun	0:13413ea9a877	432
ganlikun	0:13413ea9a877	433	/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
ganlikun	0:13413ea9a877	434	* @{
ganlikun	0:13413ea9a877	435	*/
ganlikun	0:13413ea9a877	436	#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /!< FLASH Zero wait state /
ganlikun	0:13413ea9a877	437	#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /!< FLASH One wait state /
ganlikun	0:13413ea9a877	438	#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /!< FLASH Two wait states /
ganlikun	0:13413ea9a877	439	#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /!< FLASH Three wait states /
ganlikun	0:13413ea9a877	440	#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /!< FLASH Four wait states /
ganlikun	0:13413ea9a877	441	#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /!< FLASH five wait state /
ganlikun	0:13413ea9a877	442	#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /!< FLASH six wait state /
ganlikun	0:13413ea9a877	443	#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /!< FLASH seven wait states /
ganlikun	0:13413ea9a877	444	#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /!< FLASH eight wait states /
ganlikun	0:13413ea9a877	445	#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /!< FLASH nine wait states /
ganlikun	0:13413ea9a877	446	#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /!< FLASH ten wait states /
ganlikun	0:13413ea9a877	447	#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /!< FLASH eleven wait states /
ganlikun	0:13413ea9a877	448	#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /!< FLASH twelve wait states /
ganlikun	0:13413ea9a877	449	#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /!< FLASH thirteen wait states /
ganlikun	0:13413ea9a877	450	#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /!< FLASH fourteen wait states /
ganlikun	0:13413ea9a877	451	#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /!< FLASH fifteen wait states /
ganlikun	0:13413ea9a877	452	/**
ganlikun	0:13413ea9a877	453	* @}
ganlikun	0:13413ea9a877	454	*/
ganlikun	0:13413ea9a877	455
ganlikun	0:13413ea9a877	456	/**
ganlikun	0:13413ea9a877	457	* @}
ganlikun	0:13413ea9a877	458	*/
ganlikun	0:13413ea9a877	459
ganlikun	0:13413ea9a877	460	/* Exported macro ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	461
ganlikun	0:13413ea9a877	462	/* Exported functions --------------------------------------------------------*/
ganlikun	0:13413ea9a877	463	/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
ganlikun	0:13413ea9a877	464	* @{
ganlikun	0:13413ea9a877	465	*/
ganlikun	0:13413ea9a877	466
ganlikun	0:13413ea9a877	467	/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
ganlikun	0:13413ea9a877	468	* @{
ganlikun	0:13413ea9a877	469	*/
ganlikun	0:13413ea9a877	470	/**
ganlikun	0:13413ea9a877	471	* @brief Set memory mapping at address 0x00000000
ganlikun	0:13413ea9a877	472	* @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
ganlikun	0:13413ea9a877	473	* @param Memory This parameter can be one of the following values:
ganlikun	0:13413ea9a877	474	* @arg @ref LL_SYSCFG_REMAP_FLASH
ganlikun	0:13413ea9a877	475	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
ganlikun	0:13413ea9a877	476	* @arg @ref LL_SYSCFG_REMAP_SRAM
ganlikun	0:13413ea9a877	477	* @arg @ref LL_SYSCFG_REMAP_FSMC (*)
ganlikun	0:13413ea9a877	478	* @arg @ref LL_SYSCFG_REMAP_FMC (*)
ganlikun	0:13413ea9a877	479	* @retval None
ganlikun	0:13413ea9a877	480	*/
ganlikun	0:13413ea9a877	481	__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
ganlikun	0:13413ea9a877	482	{
ganlikun	0:13413ea9a877	483	MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
ganlikun	0:13413ea9a877	484	}
ganlikun	0:13413ea9a877	485
ganlikun	0:13413ea9a877	486	/**
ganlikun	0:13413ea9a877	487	* @brief Get memory mapping at address 0x00000000
ganlikun	0:13413ea9a877	488	* @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
ganlikun	0:13413ea9a877	489	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	490	* @arg @ref LL_SYSCFG_REMAP_FLASH
ganlikun	0:13413ea9a877	491	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
ganlikun	0:13413ea9a877	492	* @arg @ref LL_SYSCFG_REMAP_SRAM
ganlikun	0:13413ea9a877	493	* @arg @ref LL_SYSCFG_REMAP_FSMC (*)
ganlikun	0:13413ea9a877	494	* @arg @ref LL_SYSCFG_REMAP_FMC (*)
ganlikun	0:13413ea9a877	495	*/
ganlikun	0:13413ea9a877	496	__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
ganlikun	0:13413ea9a877	497	{
ganlikun	0:13413ea9a877	498	return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
ganlikun	0:13413ea9a877	499	}
ganlikun	0:13413ea9a877	500
ganlikun	0:13413ea9a877	501	#if defined(SYSCFG_MEMRMP_SWP_FMC)
ganlikun	0:13413ea9a877	502	/**
ganlikun	0:13413ea9a877	503	* @brief Enables the FMC Memory Mapping Swapping
ganlikun	0:13413ea9a877	504	* @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_EnableFMCMemorySwapping
ganlikun	0:13413ea9a877	505	* @note SDRAM is accessible at 0x60000000 and NOR/RAM
ganlikun	0:13413ea9a877	506	* is accessible at 0xC0000000
ganlikun	0:13413ea9a877	507	* @retval None
ganlikun	0:13413ea9a877	508	*/
ganlikun	0:13413ea9a877	509	__STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void)
ganlikun	0:13413ea9a877	510	{
ganlikun	0:13413ea9a877	511	SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0);
ganlikun	0:13413ea9a877	512	}
ganlikun	0:13413ea9a877	513
ganlikun	0:13413ea9a877	514	/**
ganlikun	0:13413ea9a877	515	* @brief Disables the FMC Memory Mapping Swapping
ganlikun	0:13413ea9a877	516	* @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_DisableFMCMemorySwapping
ganlikun	0:13413ea9a877	517	* @note SDRAM is accessible at 0xC0000000 (default mapping)
ganlikun	0:13413ea9a877	518	* and NOR/RAM is accessible at 0x60000000 (default mapping)
ganlikun	0:13413ea9a877	519	* @retval None
ganlikun	0:13413ea9a877	520	*/
ganlikun	0:13413ea9a877	521	__STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void)
ganlikun	0:13413ea9a877	522	{
ganlikun	0:13413ea9a877	523	CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC);
ganlikun	0:13413ea9a877	524	}
ganlikun	0:13413ea9a877	525
ganlikun	0:13413ea9a877	526	#endif /* SYSCFG_MEMRMP_SWP_FMC */
ganlikun	0:13413ea9a877	527	/**
ganlikun	0:13413ea9a877	528	* @brief Enables the Compensation cell Power Down
ganlikun	0:13413ea9a877	529	* @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_EnableCompensationCell
ganlikun	0:13413ea9a877	530	* @note The I/O compensation cell can be used only when the device supply
ganlikun	0:13413ea9a877	531	* voltage ranges from 2.4 to 3.6 V
ganlikun	0:13413ea9a877	532	* @retval None
ganlikun	0:13413ea9a877	533	*/
ganlikun	0:13413ea9a877	534	__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
ganlikun	0:13413ea9a877	535	{
ganlikun	0:13413ea9a877	536	SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
ganlikun	0:13413ea9a877	537	}
ganlikun	0:13413ea9a877	538
ganlikun	0:13413ea9a877	539	/**
ganlikun	0:13413ea9a877	540	* @brief Disables the Compensation cell Power Down
ganlikun	0:13413ea9a877	541	* @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_DisableCompensationCell
ganlikun	0:13413ea9a877	542	* @note The I/O compensation cell can be used only when the device supply
ganlikun	0:13413ea9a877	543	* voltage ranges from 2.4 to 3.6 V
ganlikun	0:13413ea9a877	544	* @retval None
ganlikun	0:13413ea9a877	545	*/
ganlikun	0:13413ea9a877	546	__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
ganlikun	0:13413ea9a877	547	{
ganlikun	0:13413ea9a877	548	CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
ganlikun	0:13413ea9a877	549	}
ganlikun	0:13413ea9a877	550
ganlikun	0:13413ea9a877	551	/**
ganlikun	0:13413ea9a877	552	* @brief Get Compensation Cell ready Flag
ganlikun	0:13413ea9a877	553	* @rmtoll SYSCFG_CMPCR READY LL_SYSCFG_IsActiveFlag_CMPCR
ganlikun	0:13413ea9a877	554	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	555	*/
ganlikun	0:13413ea9a877	556	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
ganlikun	0:13413ea9a877	557	{
ganlikun	0:13413ea9a877	558	return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY));
ganlikun	0:13413ea9a877	559	}
ganlikun	0:13413ea9a877	560
ganlikun	0:13413ea9a877	561	#if defined(SYSCFG_PMC_MII_RMII_SEL)
ganlikun	0:13413ea9a877	562	/**
ganlikun	0:13413ea9a877	563	* @brief Select Ethernet PHY interface
ganlikun	0:13413ea9a877	564	* @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface
ganlikun	0:13413ea9a877	565	* @param Interface This parameter can be one of the following values:
ganlikun	0:13413ea9a877	566	* @arg @ref LL_SYSCFG_PMC_ETHMII
ganlikun	0:13413ea9a877	567	* @arg @ref LL_SYSCFG_PMC_ETHRMII
ganlikun	0:13413ea9a877	568	* @retval None
ganlikun	0:13413ea9a877	569	*/
ganlikun	0:13413ea9a877	570	__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
ganlikun	0:13413ea9a877	571	{
ganlikun	0:13413ea9a877	572	MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface);
ganlikun	0:13413ea9a877	573	}
ganlikun	0:13413ea9a877	574
ganlikun	0:13413ea9a877	575	/**
ganlikun	0:13413ea9a877	576	* @brief Get Ethernet PHY interface
ganlikun	0:13413ea9a877	577	* @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface
ganlikun	0:13413ea9a877	578	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	579	* @arg @ref LL_SYSCFG_PMC_ETHMII
ganlikun	0:13413ea9a877	580	* @arg @ref LL_SYSCFG_PMC_ETHRMII
ganlikun	0:13413ea9a877	581	* @retval None
ganlikun	0:13413ea9a877	582	*/
ganlikun	0:13413ea9a877	583	__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
ganlikun	0:13413ea9a877	584	{
ganlikun	0:13413ea9a877	585	return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL));
ganlikun	0:13413ea9a877	586	}
ganlikun	0:13413ea9a877	587	#endif /* SYSCFG_PMC_MII_RMII_SEL */
ganlikun	0:13413ea9a877	588
ganlikun	0:13413ea9a877	589
ganlikun	0:13413ea9a877	590
ganlikun	0:13413ea9a877	591	#if defined(SYSCFG_MEMRMP_UFB_MODE)
ganlikun	0:13413ea9a877	592	/**
ganlikun	0:13413ea9a877	593	* @brief Select Flash bank mode (Bank flashed at 0x08000000)
ganlikun	0:13413ea9a877	594	* @rmtoll SYSCFG_MEMRMP UFB_MODE LL_SYSCFG_SetFlashBankMode
ganlikun	0:13413ea9a877	595	* @param Bank This parameter can be one of the following values:
ganlikun	0:13413ea9a877	596	* @arg @ref LL_SYSCFG_BANKMODE_BANK1
ganlikun	0:13413ea9a877	597	* @arg @ref LL_SYSCFG_BANKMODE_BANK2
ganlikun	0:13413ea9a877	598	* @retval None
ganlikun	0:13413ea9a877	599	*/
ganlikun	0:13413ea9a877	600	__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
ganlikun	0:13413ea9a877	601	{
ganlikun	0:13413ea9a877	602	MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE, Bank);
ganlikun	0:13413ea9a877	603	}
ganlikun	0:13413ea9a877	604
ganlikun	0:13413ea9a877	605	/**
ganlikun	0:13413ea9a877	606	* @brief Get Flash bank mode (Bank flashed at 0x08000000)
ganlikun	0:13413ea9a877	607	* @rmtoll SYSCFG_MEMRMP UFB_MODE LL_SYSCFG_GetFlashBankMode
ganlikun	0:13413ea9a877	608	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	609	* @arg @ref LL_SYSCFG_BANKMODE_BANK1
ganlikun	0:13413ea9a877	610	* @arg @ref LL_SYSCFG_BANKMODE_BANK2
ganlikun	0:13413ea9a877	611	*/
ganlikun	0:13413ea9a877	612	__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
ganlikun	0:13413ea9a877	613	{
ganlikun	0:13413ea9a877	614	return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE));
ganlikun	0:13413ea9a877	615	}
ganlikun	0:13413ea9a877	616	#endif /* SYSCFG_MEMRMP_UFB_MODE */
ganlikun	0:13413ea9a877	617
ganlikun	0:13413ea9a877	618	#if defined(SYSCFG_CFGR_FMPI2C1_SCL)
ganlikun	0:13413ea9a877	619	/**
ganlikun	0:13413ea9a877	620	* @brief Enable the I2C fast mode plus driving capability.
ganlikun	0:13413ea9a877	621	* @rmtoll SYSCFG_CFGR FMPI2C1_SCL LL_SYSCFG_EnableFastModePlus\n
ganlikun	0:13413ea9a877	622	* SYSCFG_CFGR FMPI2C1_SDA LL_SYSCFG_EnableFastModePlus
ganlikun	0:13413ea9a877	623	* @param ConfigFastModePlus This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	624	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
ganlikun	0:13413ea9a877	625	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
ganlikun	0:13413ea9a877	626	* (*) value not defined in all devices
ganlikun	0:13413ea9a877	627	* @retval None
ganlikun	0:13413ea9a877	628	*/
ganlikun	0:13413ea9a877	629	__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
ganlikun	0:13413ea9a877	630	{
ganlikun	0:13413ea9a877	631	SET_BIT(SYSCFG->CFGR, ConfigFastModePlus);
ganlikun	0:13413ea9a877	632	}
ganlikun	0:13413ea9a877	633
ganlikun	0:13413ea9a877	634	/**
ganlikun	0:13413ea9a877	635	* @brief Disable the I2C fast mode plus driving capability.
ganlikun	0:13413ea9a877	636	* @rmtoll SYSCFG_CFGR FMPI2C1_SCL LL_SYSCFG_DisableFastModePlus\n
ganlikun	0:13413ea9a877	637	* SYSCFG_CFGR FMPI2C1_SDA LL_SYSCFG_DisableFastModePlus\n
ganlikun	0:13413ea9a877	638	* @param ConfigFastModePlus This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	639	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
ganlikun	0:13413ea9a877	640	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
ganlikun	0:13413ea9a877	641	* (*) value not defined in all devices
ganlikun	0:13413ea9a877	642	* @retval None
ganlikun	0:13413ea9a877	643	*/
ganlikun	0:13413ea9a877	644	__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
ganlikun	0:13413ea9a877	645	{
ganlikun	0:13413ea9a877	646	CLEAR_BIT(SYSCFG->CFGR, ConfigFastModePlus);
ganlikun	0:13413ea9a877	647	}
ganlikun	0:13413ea9a877	648	#endif /* SYSCFG_CFGR_FMPI2C1_SCL */
ganlikun	0:13413ea9a877	649
ganlikun	0:13413ea9a877	650	/**
ganlikun	0:13413ea9a877	651	* @brief Configure source input for the EXTI external interrupt.
ganlikun	0:13413ea9a877	652	* @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
ganlikun	0:13413ea9a877	653	* SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
ganlikun	0:13413ea9a877	654	* SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
ganlikun	0:13413ea9a877	655	* SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
ganlikun	0:13413ea9a877	656	* @param Port This parameter can be one of the following values:
ganlikun	0:13413ea9a877	657	* @arg @ref LL_SYSCFG_EXTI_PORTA
ganlikun	0:13413ea9a877	658	* @arg @ref LL_SYSCFG_EXTI_PORTB
ganlikun	0:13413ea9a877	659	* @arg @ref LL_SYSCFG_EXTI_PORTC
ganlikun	0:13413ea9a877	660	* @arg @ref LL_SYSCFG_EXTI_PORTD
ganlikun	0:13413ea9a877	661	* @arg @ref LL_SYSCFG_EXTI_PORTE
ganlikun	0:13413ea9a877	662	* @arg @ref LL_SYSCFG_EXTI_PORTF (*)
ganlikun	0:13413ea9a877	663	* @arg @ref LL_SYSCFG_EXTI_PORTG (*)
ganlikun	0:13413ea9a877	664	* @arg @ref LL_SYSCFG_EXTI_PORTH
ganlikun	0:13413ea9a877	665	*
ganlikun	0:13413ea9a877	666	* (*) value not defined in all devices
ganlikun	0:13413ea9a877	667	* @param Line This parameter can be one of the following values:
ganlikun	0:13413ea9a877	668	* @arg @ref LL_SYSCFG_EXTI_LINE0
ganlikun	0:13413ea9a877	669	* @arg @ref LL_SYSCFG_EXTI_LINE1
ganlikun	0:13413ea9a877	670	* @arg @ref LL_SYSCFG_EXTI_LINE2
ganlikun	0:13413ea9a877	671	* @arg @ref LL_SYSCFG_EXTI_LINE3
ganlikun	0:13413ea9a877	672	* @arg @ref LL_SYSCFG_EXTI_LINE4
ganlikun	0:13413ea9a877	673	* @arg @ref LL_SYSCFG_EXTI_LINE5
ganlikun	0:13413ea9a877	674	* @arg @ref LL_SYSCFG_EXTI_LINE6
ganlikun	0:13413ea9a877	675	* @arg @ref LL_SYSCFG_EXTI_LINE7
ganlikun	0:13413ea9a877	676	* @arg @ref LL_SYSCFG_EXTI_LINE8
ganlikun	0:13413ea9a877	677	* @arg @ref LL_SYSCFG_EXTI_LINE9
ganlikun	0:13413ea9a877	678	* @arg @ref LL_SYSCFG_EXTI_LINE10
ganlikun	0:13413ea9a877	679	* @arg @ref LL_SYSCFG_EXTI_LINE11
ganlikun	0:13413ea9a877	680	* @arg @ref LL_SYSCFG_EXTI_LINE12
ganlikun	0:13413ea9a877	681	* @arg @ref LL_SYSCFG_EXTI_LINE13
ganlikun	0:13413ea9a877	682	* @arg @ref LL_SYSCFG_EXTI_LINE14
ganlikun	0:13413ea9a877	683	* @arg @ref LL_SYSCFG_EXTI_LINE15
ganlikun	0:13413ea9a877	684	* @retval None
ganlikun	0:13413ea9a877	685	*/
ganlikun	0:13413ea9a877	686	__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
ganlikun	0:13413ea9a877	687	{
ganlikun	0:13413ea9a877	688	MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
ganlikun	0:13413ea9a877	689	}
ganlikun	0:13413ea9a877	690
ganlikun	0:13413ea9a877	691	/**
ganlikun	0:13413ea9a877	692	* @brief Get the configured defined for specific EXTI Line
ganlikun	0:13413ea9a877	693	* @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
ganlikun	0:13413ea9a877	694	* SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
ganlikun	0:13413ea9a877	695	* SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
ganlikun	0:13413ea9a877	696	* SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
ganlikun	0:13413ea9a877	697	* @param Line This parameter can be one of the following values:
ganlikun	0:13413ea9a877	698	* @arg @ref LL_SYSCFG_EXTI_LINE0
ganlikun	0:13413ea9a877	699	* @arg @ref LL_SYSCFG_EXTI_LINE1
ganlikun	0:13413ea9a877	700	* @arg @ref LL_SYSCFG_EXTI_LINE2
ganlikun	0:13413ea9a877	701	* @arg @ref LL_SYSCFG_EXTI_LINE3
ganlikun	0:13413ea9a877	702	* @arg @ref LL_SYSCFG_EXTI_LINE4
ganlikun	0:13413ea9a877	703	* @arg @ref LL_SYSCFG_EXTI_LINE5
ganlikun	0:13413ea9a877	704	* @arg @ref LL_SYSCFG_EXTI_LINE6
ganlikun	0:13413ea9a877	705	* @arg @ref LL_SYSCFG_EXTI_LINE7
ganlikun	0:13413ea9a877	706	* @arg @ref LL_SYSCFG_EXTI_LINE8
ganlikun	0:13413ea9a877	707	* @arg @ref LL_SYSCFG_EXTI_LINE9
ganlikun	0:13413ea9a877	708	* @arg @ref LL_SYSCFG_EXTI_LINE10
ganlikun	0:13413ea9a877	709	* @arg @ref LL_SYSCFG_EXTI_LINE11
ganlikun	0:13413ea9a877	710	* @arg @ref LL_SYSCFG_EXTI_LINE12
ganlikun	0:13413ea9a877	711	* @arg @ref LL_SYSCFG_EXTI_LINE13
ganlikun	0:13413ea9a877	712	* @arg @ref LL_SYSCFG_EXTI_LINE14
ganlikun	0:13413ea9a877	713	* @arg @ref LL_SYSCFG_EXTI_LINE15
ganlikun	0:13413ea9a877	714	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	715	* @arg @ref LL_SYSCFG_EXTI_PORTA
ganlikun	0:13413ea9a877	716	* @arg @ref LL_SYSCFG_EXTI_PORTB
ganlikun	0:13413ea9a877	717	* @arg @ref LL_SYSCFG_EXTI_PORTC
ganlikun	0:13413ea9a877	718	* @arg @ref LL_SYSCFG_EXTI_PORTD
ganlikun	0:13413ea9a877	719	* @arg @ref LL_SYSCFG_EXTI_PORTE
ganlikun	0:13413ea9a877	720	* @arg @ref LL_SYSCFG_EXTI_PORTF (*)
ganlikun	0:13413ea9a877	721	* @arg @ref LL_SYSCFG_EXTI_PORTG (*)
ganlikun	0:13413ea9a877	722	* @arg @ref LL_SYSCFG_EXTI_PORTH
ganlikun	0:13413ea9a877	723	* (*) value not defined in all devices
ganlikun	0:13413ea9a877	724	*/
ganlikun	0:13413ea9a877	725	__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
ganlikun	0:13413ea9a877	726	{
ganlikun	0:13413ea9a877	727	return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
ganlikun	0:13413ea9a877	728	}
ganlikun	0:13413ea9a877	729
ganlikun	0:13413ea9a877	730	#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
ganlikun	0:13413ea9a877	731	/**
ganlikun	0:13413ea9a877	732	* @brief Set connections to TIM1/8 break inputs
ganlikun	0:13413ea9a877	733	* @rmtoll SYSCFG_CFGR2 LockUp Lock LL_SYSCFG_SetTIMBreakInputs \n
ganlikun	0:13413ea9a877	734	* SYSCFG_CFGR2 PVD Lock LL_SYSCFG_SetTIMBreakInputs
ganlikun	0:13413ea9a877	735	* @param Break This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	736	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
ganlikun	0:13413ea9a877	737	* @arg @ref LL_SYSCFG_TIMBREAK_PVD
ganlikun	0:13413ea9a877	738	* @retval None
ganlikun	0:13413ea9a877	739	*/
ganlikun	0:13413ea9a877	740	__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
ganlikun	0:13413ea9a877	741	{
ganlikun	0:13413ea9a877	742	MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_PVD_LOCK, Break);
ganlikun	0:13413ea9a877	743	}
ganlikun	0:13413ea9a877	744
ganlikun	0:13413ea9a877	745	/**
ganlikun	0:13413ea9a877	746	* @brief Get connections to TIM1/8 Break inputs
ganlikun	0:13413ea9a877	747	* @rmtoll SYSCFG_CFGR2 LockUp Lock LL_SYSCFG_SetTIMBreakInputs \n
ganlikun	0:13413ea9a877	748	* SYSCFG_CFGR2 PVD Lock LL_SYSCFG_SetTIMBreakInputs
ganlikun	0:13413ea9a877	749	* @retval Returned value can be can be a combination of the following values:
ganlikun	0:13413ea9a877	750	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
ganlikun	0:13413ea9a877	751	* @arg @ref LL_SYSCFG_TIMBREAK_PVD
ganlikun	0:13413ea9a877	752	*/
ganlikun	0:13413ea9a877	753	__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
ganlikun	0:13413ea9a877	754	{
ganlikun	0:13413ea9a877	755	return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_PVD_LOCK));
ganlikun	0:13413ea9a877	756	}
ganlikun	0:13413ea9a877	757	#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
ganlikun	0:13413ea9a877	758	#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
ganlikun	0:13413ea9a877	759	/**
ganlikun	0:13413ea9a877	760	* @brief Select the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
ganlikun	0:13413ea9a877	761	* @rmtoll SYSCFG_MCHDLYCR BSCKSEL LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection
ganlikun	0:13413ea9a877	762	* @param ClockSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	763	* @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
ganlikun	0:13413ea9a877	764	* @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
ganlikun	0:13413ea9a877	765	* @retval None
ganlikun	0:13413ea9a877	766	*/
ganlikun	0:13413ea9a877	767	__STATIC_INLINE void LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection(uint32_t ClockSource)
ganlikun	0:13413ea9a877	768	{
ganlikun	0:13413ea9a877	769	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL, ClockSource);
ganlikun	0:13413ea9a877	770	}
ganlikun	0:13413ea9a877	771	/**
ganlikun	0:13413ea9a877	772	* @brief Get the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
ganlikun	0:13413ea9a877	773	* @rmtoll SYSCFG_MCHDLYCR BSCKSEL LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection
ganlikun	0:13413ea9a877	774	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	775	* @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
ganlikun	0:13413ea9a877	776	* @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
ganlikun	0:13413ea9a877	777	* @retval None
ganlikun	0:13413ea9a877	778	*/
ganlikun	0:13413ea9a877	779	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection(void)
ganlikun	0:13413ea9a877	780	{
ganlikun	0:13413ea9a877	781	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL));
ganlikun	0:13413ea9a877	782	}
ganlikun	0:13413ea9a877	783	/**
ganlikun	0:13413ea9a877	784	* @brief Enables the DFSDM1 or DFSDM2 Delay clock
ganlikun	0:13413ea9a877	785	* @rmtoll SYSCFG_MCHDLYCR MCHDLYEN LL_SYSCFG_DFSDM_EnableDelayClock
ganlikun	0:13413ea9a877	786	* @param MCHDLY This paramater can be one of the following values
ganlikun	0:13413ea9a877	787	* @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
ganlikun	0:13413ea9a877	788	* @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
ganlikun	0:13413ea9a877	789	* @retval None
ganlikun	0:13413ea9a877	790	*/
ganlikun	0:13413ea9a877	791	__STATIC_INLINE void LL_SYSCFG_DFSDM_EnableDelayClock(uint32_t MCHDLY)
ganlikun	0:13413ea9a877	792	{
ganlikun	0:13413ea9a877	793	SET_BIT(SYSCFG->MCHDLYCR, MCHDLY);
ganlikun	0:13413ea9a877	794	}
ganlikun	0:13413ea9a877	795
ganlikun	0:13413ea9a877	796	/**
ganlikun	0:13413ea9a877	797	* @brief Disables the DFSDM1 or the DFSDM2 Delay clock
ganlikun	0:13413ea9a877	798	* @rmtoll SYSCFG_MCHDLYCR MCHDLY1EN LL_SYSCFG_DFSDM1_DisableDelayClock
ganlikun	0:13413ea9a877	799	* @param MCHDLY This paramater can be one of the following values
ganlikun	0:13413ea9a877	800	* @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
ganlikun	0:13413ea9a877	801	* @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
ganlikun	0:13413ea9a877	802	* @retval None
ganlikun	0:13413ea9a877	803	*/
ganlikun	0:13413ea9a877	804	__STATIC_INLINE void LL_SYSCFG_DFSDM_DisableDelayClock(uint32_t MCHDLY)
ganlikun	0:13413ea9a877	805	{
ganlikun	0:13413ea9a877	806	CLEAR_BIT(SYSCFG->MCHDLYCR, MCHDLY);
ganlikun	0:13413ea9a877	807	}
ganlikun	0:13413ea9a877	808
ganlikun	0:13413ea9a877	809	/**
ganlikun	0:13413ea9a877	810	* @brief Select the source for DFSDM1 or DFSDM2 DatIn0
ganlikun	0:13413ea9a877	811	* @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_SetDataIn0Source
ganlikun	0:13413ea9a877	812	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	813	* @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
ganlikun	0:13413ea9a877	814	* @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
ganlikun	0:13413ea9a877	815	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
ganlikun	0:13413ea9a877	816	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
ganlikun	0:13413ea9a877	817	* @retval None
ganlikun	0:13413ea9a877	818	*/
ganlikun	0:13413ea9a877	819	__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn0Source(uint32_t Source)
ganlikun	0:13413ea9a877	820	{
ganlikun	0:13413ea9a877	821	MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
ganlikun	0:13413ea9a877	822	}
ganlikun	0:13413ea9a877	823	/**
ganlikun	0:13413ea9a877	824	* @brief Get the source for DFSDM1 or DFSDM2 DatIn0.
ganlikun	0:13413ea9a877	825	* @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_GetDataIn0Source
ganlikun	0:13413ea9a877	826	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	827	* @arg @ref LL_SYSCFG_DFSDM1_DataIn0
ganlikun	0:13413ea9a877	828	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0
ganlikun	0:13413ea9a877	829	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	830	* @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
ganlikun	0:13413ea9a877	831	* @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
ganlikun	0:13413ea9a877	832	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
ganlikun	0:13413ea9a877	833	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
ganlikun	0:13413ea9a877	834	* @retval None
ganlikun	0:13413ea9a877	835	*/
ganlikun	0:13413ea9a877	836	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn0Source(uint32_t Source)
ganlikun	0:13413ea9a877	837	{
ganlikun	0:13413ea9a877	838	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
ganlikun	0:13413ea9a877	839	}
ganlikun	0:13413ea9a877	840	/**
ganlikun	0:13413ea9a877	841	* @brief Select the source for DFSDM1 or DFSDM2 DatIn2
ganlikun	0:13413ea9a877	842	* @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_SetDataIn2Source
ganlikun	0:13413ea9a877	843	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	844	* @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
ganlikun	0:13413ea9a877	845	* @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
ganlikun	0:13413ea9a877	846	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
ganlikun	0:13413ea9a877	847	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
ganlikun	0:13413ea9a877	848	* @retval None
ganlikun	0:13413ea9a877	849	*/
ganlikun	0:13413ea9a877	850	__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn2Source(uint32_t Source)
ganlikun	0:13413ea9a877	851	{
ganlikun	0:13413ea9a877	852	MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
ganlikun	0:13413ea9a877	853	}
ganlikun	0:13413ea9a877	854	/**
ganlikun	0:13413ea9a877	855	* @brief Get the source for DFSDM1 or DFSDM2 DatIn2.
ganlikun	0:13413ea9a877	856	* @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_GetDataIn2Source
ganlikun	0:13413ea9a877	857	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	858	* @arg @ref LL_SYSCFG_DFSDM1_DataIn2
ganlikun	0:13413ea9a877	859	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2
ganlikun	0:13413ea9a877	860	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	861	* @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
ganlikun	0:13413ea9a877	862	* @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
ganlikun	0:13413ea9a877	863	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
ganlikun	0:13413ea9a877	864	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
ganlikun	0:13413ea9a877	865	* @retval None
ganlikun	0:13413ea9a877	866	*/
ganlikun	0:13413ea9a877	867	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn2Source(uint32_t Source)
ganlikun	0:13413ea9a877	868	{
ganlikun	0:13413ea9a877	869	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
ganlikun	0:13413ea9a877	870	}
ganlikun	0:13413ea9a877	871
ganlikun	0:13413ea9a877	872	/**
ganlikun	0:13413ea9a877	873	* @brief Select the distribution of the bitsream lock gated by TIM4 OC2
ganlikun	0:13413ea9a877	874	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CK02SEL LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution
ganlikun	0:13413ea9a877	875	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	876	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
ganlikun	0:13413ea9a877	877	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
ganlikun	0:13413ea9a877	878	* @retval None
ganlikun	0:13413ea9a877	879	*/
ganlikun	0:13413ea9a877	880	__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution(uint32_t Source)
ganlikun	0:13413ea9a877	881	{
ganlikun	0:13413ea9a877	882	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL, Source);
ganlikun	0:13413ea9a877	883	}
ganlikun	0:13413ea9a877	884	/**
ganlikun	0:13413ea9a877	885	* @brief Get the distribution of the bitsream lock gated by TIM4 OC2
ganlikun	0:13413ea9a877	886	* @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution
ganlikun	0:13413ea9a877	887	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	888	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
ganlikun	0:13413ea9a877	889	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
ganlikun	0:13413ea9a877	890	* @retval None
ganlikun	0:13413ea9a877	891	*/
ganlikun	0:13413ea9a877	892	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution(void)
ganlikun	0:13413ea9a877	893	{
ganlikun	0:13413ea9a877	894	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL));
ganlikun	0:13413ea9a877	895	}
ganlikun	0:13413ea9a877	896
ganlikun	0:13413ea9a877	897	/**
ganlikun	0:13413ea9a877	898	* @brief Select the distribution of the bitsream lock gated by TIM4 OC1
ganlikun	0:13413ea9a877	899	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CK13SEL LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution
ganlikun	0:13413ea9a877	900	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	901	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
ganlikun	0:13413ea9a877	902	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
ganlikun	0:13413ea9a877	903	* @retval None
ganlikun	0:13413ea9a877	904	*/
ganlikun	0:13413ea9a877	905	__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution(uint32_t Source)
ganlikun	0:13413ea9a877	906	{
ganlikun	0:13413ea9a877	907	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL, Source);
ganlikun	0:13413ea9a877	908	}
ganlikun	0:13413ea9a877	909	/**
ganlikun	0:13413ea9a877	910	* @brief Get the distribution of the bitsream lock gated by TIM4 OC1
ganlikun	0:13413ea9a877	911	* @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution
ganlikun	0:13413ea9a877	912	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	913	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
ganlikun	0:13413ea9a877	914	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
ganlikun	0:13413ea9a877	915	* @retval None
ganlikun	0:13413ea9a877	916	*/
ganlikun	0:13413ea9a877	917	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution(void)
ganlikun	0:13413ea9a877	918	{
ganlikun	0:13413ea9a877	919	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL));
ganlikun	0:13413ea9a877	920	}
ganlikun	0:13413ea9a877	921
ganlikun	0:13413ea9a877	922	/**
ganlikun	0:13413ea9a877	923	* @brief Select the DFSDM1 Clock In
ganlikun	0:13413ea9a877	924	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_SetClockInSourceSelection
ganlikun	0:13413ea9a877	925	* @param ClockSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	926	* @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
ganlikun	0:13413ea9a877	927	* @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
ganlikun	0:13413ea9a877	928	* @retval None
ganlikun	0:13413ea9a877	929	*/
ganlikun	0:13413ea9a877	930	__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockInSourceSelection(uint32_t ClockSource)
ganlikun	0:13413ea9a877	931	{
ganlikun	0:13413ea9a877	932	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG, ClockSource);
ganlikun	0:13413ea9a877	933	}
ganlikun	0:13413ea9a877	934	/**
ganlikun	0:13413ea9a877	935	* @brief GET the DFSDM1 Clock In
ganlikun	0:13413ea9a877	936	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_GetClockInSourceSelection
ganlikun	0:13413ea9a877	937	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	938	* @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
ganlikun	0:13413ea9a877	939	* @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
ganlikun	0:13413ea9a877	940	* @retval None
ganlikun	0:13413ea9a877	941	*/
ganlikun	0:13413ea9a877	942	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockInSourceSelection(void)
ganlikun	0:13413ea9a877	943	{
ganlikun	0:13413ea9a877	944	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG));
ganlikun	0:13413ea9a877	945	}
ganlikun	0:13413ea9a877	946
ganlikun	0:13413ea9a877	947	/**
ganlikun	0:13413ea9a877	948	* @brief Select the DFSDM1 Clock Out
ganlikun	0:13413ea9a877	949	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_SetClockOutSourceSelection
ganlikun	0:13413ea9a877	950	* @param ClockSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	951	* @arg @ref LL_SYSCFG_DFSDM1_CKOUT
ganlikun	0:13413ea9a877	952	* @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
ganlikun	0:13413ea9a877	953	* @retval None
ganlikun	0:13413ea9a877	954	*/
ganlikun	0:13413ea9a877	955	__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockOutSourceSelection(uint32_t ClockSource)
ganlikun	0:13413ea9a877	956	{
ganlikun	0:13413ea9a877	957	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL, ClockSource);
ganlikun	0:13413ea9a877	958	}
ganlikun	0:13413ea9a877	959	/**
ganlikun	0:13413ea9a877	960	* @brief GET the DFSDM1 Clock Out
ganlikun	0:13413ea9a877	961	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_GetClockOutSourceSelection
ganlikun	0:13413ea9a877	962	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	963	* @arg @ref LL_SYSCFG_DFSDM1_CKOUT
ganlikun	0:13413ea9a877	964	* @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
ganlikun	0:13413ea9a877	965	* @retval None
ganlikun	0:13413ea9a877	966	*/
ganlikun	0:13413ea9a877	967	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockOutSourceSelection(void)
ganlikun	0:13413ea9a877	968	{
ganlikun	0:13413ea9a877	969	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL));
ganlikun	0:13413ea9a877	970	}
ganlikun	0:13413ea9a877	971
ganlikun	0:13413ea9a877	972	/**
ganlikun	0:13413ea9a877	973	* @brief Enables the DFSDM2 Delay clock
ganlikun	0:13413ea9a877	974	* @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN LL_SYSCFG_DFSDM2_EnableDelayClock
ganlikun	0:13413ea9a877	975	* @retval None
ganlikun	0:13413ea9a877	976	*/
ganlikun	0:13413ea9a877	977	__STATIC_INLINE void LL_SYSCFG_DFSDM2_EnableDelayClock(void)
ganlikun	0:13413ea9a877	978	{
ganlikun	0:13413ea9a877	979	SET_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
ganlikun	0:13413ea9a877	980	}
ganlikun	0:13413ea9a877	981
ganlikun	0:13413ea9a877	982	/**
ganlikun	0:13413ea9a877	983	* @brief Disables the DFSDM2 Delay clock
ganlikun	0:13413ea9a877	984	* @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN LL_SYSCFG_DFSDM2_DisableDelayClock
ganlikun	0:13413ea9a877	985	* @retval None
ganlikun	0:13413ea9a877	986	*/
ganlikun	0:13413ea9a877	987	__STATIC_INLINE void LL_SYSCFG_DFSDM2_DisableDelayClock(void)
ganlikun	0:13413ea9a877	988	{
ganlikun	0:13413ea9a877	989	CLEAR_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
ganlikun	0:13413ea9a877	990	}
ganlikun	0:13413ea9a877	991	/**
ganlikun	0:13413ea9a877	992	* @brief Select the source for DFSDM2 DatIn0
ganlikun	0:13413ea9a877	993	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_SetDataIn0Source
ganlikun	0:13413ea9a877	994	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	995	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
ganlikun	0:13413ea9a877	996	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
ganlikun	0:13413ea9a877	997	* @retval None
ganlikun	0:13413ea9a877	998	*/
ganlikun	0:13413ea9a877	999	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn0Source(uint32_t Source)
ganlikun	0:13413ea9a877	1000	{
ganlikun	0:13413ea9a877	1001	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL, Source);
ganlikun	0:13413ea9a877	1002	}
ganlikun	0:13413ea9a877	1003	/**
ganlikun	0:13413ea9a877	1004	* @brief Get the source for DFSDM2 DatIn0.
ganlikun	0:13413ea9a877	1005	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_GetDataIn0Source
ganlikun	0:13413ea9a877	1006	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	1007	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
ganlikun	0:13413ea9a877	1008	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
ganlikun	0:13413ea9a877	1009	* @retval None
ganlikun	0:13413ea9a877	1010	*/
ganlikun	0:13413ea9a877	1011	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn0Source(void)
ganlikun	0:13413ea9a877	1012	{
ganlikun	0:13413ea9a877	1013	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL));
ganlikun	0:13413ea9a877	1014	}
ganlikun	0:13413ea9a877	1015
ganlikun	0:13413ea9a877	1016	/**
ganlikun	0:13413ea9a877	1017	* @brief Select the source for DFSDM2 DatIn2
ganlikun	0:13413ea9a877	1018	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_SetDataIn2Source
ganlikun	0:13413ea9a877	1019	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1020	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
ganlikun	0:13413ea9a877	1021	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
ganlikun	0:13413ea9a877	1022	* @retval None
ganlikun	0:13413ea9a877	1023	*/
ganlikun	0:13413ea9a877	1024	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn2Source(uint32_t Source)
ganlikun	0:13413ea9a877	1025	{
ganlikun	0:13413ea9a877	1026	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL, Source);
ganlikun	0:13413ea9a877	1027	}
ganlikun	0:13413ea9a877	1028	/**
ganlikun	0:13413ea9a877	1029	* @brief Get the source for DFSDM2 DatIn2.
ganlikun	0:13413ea9a877	1030	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_GetDataIn2Source
ganlikun	0:13413ea9a877	1031	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	1032	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
ganlikun	0:13413ea9a877	1033	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
ganlikun	0:13413ea9a877	1034	* @retval None
ganlikun	0:13413ea9a877	1035	*/
ganlikun	0:13413ea9a877	1036	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn2Source(void)
ganlikun	0:13413ea9a877	1037	{
ganlikun	0:13413ea9a877	1038	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL));
ganlikun	0:13413ea9a877	1039	}
ganlikun	0:13413ea9a877	1040
ganlikun	0:13413ea9a877	1041	/**
ganlikun	0:13413ea9a877	1042	* @brief Select the source for DFSDM2 DatIn4
ganlikun	0:13413ea9a877	1043	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_SetDataIn4Source
ganlikun	0:13413ea9a877	1044	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1045	* @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
ganlikun	0:13413ea9a877	1046	* @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
ganlikun	0:13413ea9a877	1047	* @retval None
ganlikun	0:13413ea9a877	1048	*/
ganlikun	0:13413ea9a877	1049	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn4Source(uint32_t Source)
ganlikun	0:13413ea9a877	1050	{
ganlikun	0:13413ea9a877	1051	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL, Source);
ganlikun	0:13413ea9a877	1052	}
ganlikun	0:13413ea9a877	1053	/**
ganlikun	0:13413ea9a877	1054	* @brief Get the source for DFSDM2 DatIn4.
ganlikun	0:13413ea9a877	1055	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_GetDataIn4Source
ganlikun	0:13413ea9a877	1056	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	1057	* @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
ganlikun	0:13413ea9a877	1058	* @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
ganlikun	0:13413ea9a877	1059	* @retval None
ganlikun	0:13413ea9a877	1060	*/
ganlikun	0:13413ea9a877	1061	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn4Source(void)
ganlikun	0:13413ea9a877	1062	{
ganlikun	0:13413ea9a877	1063	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL));
ganlikun	0:13413ea9a877	1064	}
ganlikun	0:13413ea9a877	1065
ganlikun	0:13413ea9a877	1066	/**
ganlikun	0:13413ea9a877	1067	* @brief Select the source for DFSDM2 DatIn6
ganlikun	0:13413ea9a877	1068	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_SetDataIn6Source
ganlikun	0:13413ea9a877	1069	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1070	* @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
ganlikun	0:13413ea9a877	1071	* @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
ganlikun	0:13413ea9a877	1072	* @retval None
ganlikun	0:13413ea9a877	1073	*/
ganlikun	0:13413ea9a877	1074	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn6Source(uint32_t Source)
ganlikun	0:13413ea9a877	1075	{
ganlikun	0:13413ea9a877	1076	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL, Source);
ganlikun	0:13413ea9a877	1077	}
ganlikun	0:13413ea9a877	1078	/**
ganlikun	0:13413ea9a877	1079	* @brief Get the source for DFSDM2 DatIn6.
ganlikun	0:13413ea9a877	1080	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_GetDataIn6Source
ganlikun	0:13413ea9a877	1081	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	1082	* @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
ganlikun	0:13413ea9a877	1083	* @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
ganlikun	0:13413ea9a877	1084	* @retval None
ganlikun	0:13413ea9a877	1085	*/
ganlikun	0:13413ea9a877	1086	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn6Source(void)
ganlikun	0:13413ea9a877	1087	{
ganlikun	0:13413ea9a877	1088	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL));
ganlikun	0:13413ea9a877	1089	}
ganlikun	0:13413ea9a877	1090
ganlikun	0:13413ea9a877	1091	/**
ganlikun	0:13413ea9a877	1092	* @brief Select the distribution of the bitsream lock gated by TIM3 OC4
ganlikun	0:13413ea9a877	1093	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution
ganlikun	0:13413ea9a877	1094	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1095	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
ganlikun	0:13413ea9a877	1096	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
ganlikun	0:13413ea9a877	1097	* @retval None
ganlikun	0:13413ea9a877	1098	*/
ganlikun	0:13413ea9a877	1099	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution(uint32_t Source)
ganlikun	0:13413ea9a877	1100	{
ganlikun	0:13413ea9a877	1101	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL, Source);
ganlikun	0:13413ea9a877	1102	}
ganlikun	0:13413ea9a877	1103	/**
ganlikun	0:13413ea9a877	1104	* @brief Get the distribution of the bitsream lock gated by TIM3 OC4
ganlikun	0:13413ea9a877	1105	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution
ganlikun	0:13413ea9a877	1106	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	1107	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
ganlikun	0:13413ea9a877	1108	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
ganlikun	0:13413ea9a877	1109	* @retval None
ganlikun	0:13413ea9a877	1110	*/
ganlikun	0:13413ea9a877	1111	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution(void)
ganlikun	0:13413ea9a877	1112	{
ganlikun	0:13413ea9a877	1113	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL));
ganlikun	0:13413ea9a877	1114	}
ganlikun	0:13413ea9a877	1115
ganlikun	0:13413ea9a877	1116	/**
ganlikun	0:13413ea9a877	1117	* @brief Select the distribution of the bitsream lock gated by TIM3 OC3
ganlikun	0:13413ea9a877	1118	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK15SEL LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution
ganlikun	0:13413ea9a877	1119	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1120	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
ganlikun	0:13413ea9a877	1121	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
ganlikun	0:13413ea9a877	1122	* @retval None
ganlikun	0:13413ea9a877	1123	*/
ganlikun	0:13413ea9a877	1124	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution(uint32_t Source)
ganlikun	0:13413ea9a877	1125	{
ganlikun	0:13413ea9a877	1126	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL, Source);
ganlikun	0:13413ea9a877	1127	}
ganlikun	0:13413ea9a877	1128	/**
ganlikun	0:13413ea9a877	1129	* @brief Get the distribution of the bitsream lock gated by TIM3 OC4
ganlikun	0:13413ea9a877	1130	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution
ganlikun	0:13413ea9a877	1131	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	1132	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
ganlikun	0:13413ea9a877	1133	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
ganlikun	0:13413ea9a877	1134	* @retval None
ganlikun	0:13413ea9a877	1135	*/
ganlikun	0:13413ea9a877	1136	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution(void)
ganlikun	0:13413ea9a877	1137	{
ganlikun	0:13413ea9a877	1138	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL));
ganlikun	0:13413ea9a877	1139	}
ganlikun	0:13413ea9a877	1140
ganlikun	0:13413ea9a877	1141	/**
ganlikun	0:13413ea9a877	1142	* @brief Select the distribution of the bitsream lock gated by TIM3 OC2
ganlikun	0:13413ea9a877	1143	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK26SEL LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution
ganlikun	0:13413ea9a877	1144	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1145	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
ganlikun	0:13413ea9a877	1146	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
ganlikun	0:13413ea9a877	1147	* @retval None
ganlikun	0:13413ea9a877	1148	*/
ganlikun	0:13413ea9a877	1149	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution(uint32_t Source)
ganlikun	0:13413ea9a877	1150	{
ganlikun	0:13413ea9a877	1151	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL, Source);
ganlikun	0:13413ea9a877	1152	}
ganlikun	0:13413ea9a877	1153	/**
ganlikun	0:13413ea9a877	1154	* @brief Get the distribution of the bitsream lock gated by TIM3 OC2
ganlikun	0:13413ea9a877	1155	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution
ganlikun	0:13413ea9a877	1156	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	1157	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
ganlikun	0:13413ea9a877	1158	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
ganlikun	0:13413ea9a877	1159	* @retval None
ganlikun	0:13413ea9a877	1160	*/
ganlikun	0:13413ea9a877	1161	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution(void)
ganlikun	0:13413ea9a877	1162	{
ganlikun	0:13413ea9a877	1163	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL));
ganlikun	0:13413ea9a877	1164	}
ganlikun	0:13413ea9a877	1165
ganlikun	0:13413ea9a877	1166	/**
ganlikun	0:13413ea9a877	1167	* @brief Select the distribution of the bitsream lock gated by TIM3 OC1
ganlikun	0:13413ea9a877	1168	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution
ganlikun	0:13413ea9a877	1169	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1170	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
ganlikun	0:13413ea9a877	1171	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
ganlikun	0:13413ea9a877	1172	* @retval None
ganlikun	0:13413ea9a877	1173	*/
ganlikun	0:13413ea9a877	1174	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution(uint32_t Source)
ganlikun	0:13413ea9a877	1175	{
ganlikun	0:13413ea9a877	1176	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL, Source);
ganlikun	0:13413ea9a877	1177	}
ganlikun	0:13413ea9a877	1178	/**
ganlikun	0:13413ea9a877	1179	* @brief Get the distribution of the bitsream lock gated by TIM3 OC1
ganlikun	0:13413ea9a877	1180	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution
ganlikun	0:13413ea9a877	1181	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	1182	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
ganlikun	0:13413ea9a877	1183	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
ganlikun	0:13413ea9a877	1184	* @retval None
ganlikun	0:13413ea9a877	1185	*/
ganlikun	0:13413ea9a877	1186	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution(void)
ganlikun	0:13413ea9a877	1187	{
ganlikun	0:13413ea9a877	1188	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL));
ganlikun	0:13413ea9a877	1189	}
ganlikun	0:13413ea9a877	1190
ganlikun	0:13413ea9a877	1191	/**
ganlikun	0:13413ea9a877	1192	* @brief Select the DFSDM2 Clock In
ganlikun	0:13413ea9a877	1193	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_SetClockInSourceSelection
ganlikun	0:13413ea9a877	1194	* @param ClockSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1195	* @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
ganlikun	0:13413ea9a877	1196	* @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
ganlikun	0:13413ea9a877	1197	* @retval None
ganlikun	0:13413ea9a877	1198	*/
ganlikun	0:13413ea9a877	1199	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockInSourceSelection(uint32_t ClockSource)
ganlikun	0:13413ea9a877	1200	{
ganlikun	0:13413ea9a877	1201	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG, ClockSource);
ganlikun	0:13413ea9a877	1202	}
ganlikun	0:13413ea9a877	1203	/**
ganlikun	0:13413ea9a877	1204	* @brief GET the DFSDM2 Clock In
ganlikun	0:13413ea9a877	1205	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_GetClockInSourceSelection
ganlikun	0:13413ea9a877	1206	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	1207	* @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
ganlikun	0:13413ea9a877	1208	* @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
ganlikun	0:13413ea9a877	1209	* @retval None
ganlikun	0:13413ea9a877	1210	*/
ganlikun	0:13413ea9a877	1211	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockInSourceSelection(void)
ganlikun	0:13413ea9a877	1212	{
ganlikun	0:13413ea9a877	1213	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG));
ganlikun	0:13413ea9a877	1214	}
ganlikun	0:13413ea9a877	1215
ganlikun	0:13413ea9a877	1216	/**
ganlikun	0:13413ea9a877	1217	* @brief Select the DFSDM2 Clock Out
ganlikun	0:13413ea9a877	1218	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_SetClockOutSourceSelection
ganlikun	0:13413ea9a877	1219	* @param ClockSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1220	* @arg @ref LL_SYSCFG_DFSDM2_CKOUT
ganlikun	0:13413ea9a877	1221	* @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
ganlikun	0:13413ea9a877	1222	* @retval None
ganlikun	0:13413ea9a877	1223	*/
ganlikun	0:13413ea9a877	1224	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockOutSourceSelection(uint32_t ClockSource)
ganlikun	0:13413ea9a877	1225	{
ganlikun	0:13413ea9a877	1226	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL, ClockSource);
ganlikun	0:13413ea9a877	1227	}
ganlikun	0:13413ea9a877	1228	/**
ganlikun	0:13413ea9a877	1229	* @brief GET the DFSDM2 Clock Out
ganlikun	0:13413ea9a877	1230	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_GetClockOutSourceSelection
ganlikun	0:13413ea9a877	1231	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	1232	* @arg @ref LL_SYSCFG_DFSDM2_CKOUT
ganlikun	0:13413ea9a877	1233	* @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
ganlikun	0:13413ea9a877	1234	* @retval None
ganlikun	0:13413ea9a877	1235	*/
ganlikun	0:13413ea9a877	1236	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockOutSourceSelection(void)
ganlikun	0:13413ea9a877	1237	{
ganlikun	0:13413ea9a877	1238	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL));
ganlikun	0:13413ea9a877	1239	}
ganlikun	0:13413ea9a877	1240
ganlikun	0:13413ea9a877	1241	#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
ganlikun	0:13413ea9a877	1242	/**
ganlikun	0:13413ea9a877	1243	* @}
ganlikun	0:13413ea9a877	1244	*/
ganlikun	0:13413ea9a877	1245
ganlikun	0:13413ea9a877	1246
ganlikun	0:13413ea9a877	1247	/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
ganlikun	0:13413ea9a877	1248	* @{
ganlikun	0:13413ea9a877	1249	*/
ganlikun	0:13413ea9a877	1250
ganlikun	0:13413ea9a877	1251	/**
ganlikun	0:13413ea9a877	1252	* @brief Return the device identifier
ganlikun	0:13413ea9a877	1253	* @note For STM32F405/407xx and STM32F415/417xx devices, the device ID is 0x413
ganlikun	0:13413ea9a877	1254	* @note For STM32F42xxx and STM32F43xxx devices, the device ID is 0x419
ganlikun	0:13413ea9a877	1255	* @note For STM32F401xx devices, the device ID is 0x423
ganlikun	0:13413ea9a877	1256	* @note For STM32F401xx devices, the device ID is 0x433
ganlikun	0:13413ea9a877	1257	* @note For STM32F411xx devices, the device ID is 0x431
ganlikun	0:13413ea9a877	1258	* @note For STM32F410xx devices, the device ID is 0x458
ganlikun	0:13413ea9a877	1259	* @note For STM32F412xx devices, the device ID is 0x441
ganlikun	0:13413ea9a877	1260	* @note For STM32F413xx and STM32423xx devices, the device ID is 0x463
ganlikun	0:13413ea9a877	1261	* @note For STM32F446xx devices, the device ID is 0x421
ganlikun	0:13413ea9a877	1262	* @note For STM32F469xx and STM32F479xx devices, the device ID is 0x434
ganlikun	0:13413ea9a877	1263	* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
ganlikun	0:13413ea9a877	1264	* @retval Values between Min_Data=0x00 and Max_Data=0xFFF
ganlikun	0:13413ea9a877	1265	*/
ganlikun	0:13413ea9a877	1266	__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
ganlikun	0:13413ea9a877	1267	{
ganlikun	0:13413ea9a877	1268	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
ganlikun	0:13413ea9a877	1269	}
ganlikun	0:13413ea9a877	1270
ganlikun	0:13413ea9a877	1271	/**
ganlikun	0:13413ea9a877	1272	* @brief Return the device revision identifier
ganlikun	0:13413ea9a877	1273	* @note This field indicates the revision of the device.
ganlikun	0:13413ea9a877	1274	For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001, rev1 -> 0x1003, rev2 ->0x1007, revY -> 0x100F for STM32F405/407xx and STM32F415/417xx devices
ganlikun	0:13413ea9a877	1275	For example, it is read as RevA -> 0x1000, Cat 2 revY -> 0x1003, rev1 -> 0x1007, rev3 ->0x2001 for STM32F42xxx and STM32F43xxx devices
ganlikun	0:13413ea9a877	1276	For example, it is read as RevZ -> 0x1000, Cat 2 revA -> 0x1001 for STM32F401xB/C devices
ganlikun	0:13413ea9a877	1277	For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 for STM32F401xD/E devices
ganlikun	0:13413ea9a877	1278	For example, it is read as RevA -> 0x1000 for STM32F411xx,STM32F413/423xx,STM32F469/423xx, STM32F446xx and STM32F410xx devices
ganlikun	0:13413ea9a877	1279	For example, it is read as RevZ -> 0x1001, Cat 2 revB -> 0x2000, revC -> 0x3000 for STM32F412xx devices
ganlikun	0:13413ea9a877	1280	* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
ganlikun	0:13413ea9a877	1281	* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
ganlikun	0:13413ea9a877	1282	*/
ganlikun	0:13413ea9a877	1283	__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
ganlikun	0:13413ea9a877	1284	{
ganlikun	0:13413ea9a877	1285	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
ganlikun	0:13413ea9a877	1286	}
ganlikun	0:13413ea9a877	1287
ganlikun	0:13413ea9a877	1288	/**
ganlikun	0:13413ea9a877	1289	* @brief Enable the Debug Module during SLEEP mode
ganlikun	0:13413ea9a877	1290	* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
ganlikun	0:13413ea9a877	1291	* @retval None
ganlikun	0:13413ea9a877	1292	*/
ganlikun	0:13413ea9a877	1293	__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
ganlikun	0:13413ea9a877	1294	{
ganlikun	0:13413ea9a877	1295	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
ganlikun	0:13413ea9a877	1296	}
ganlikun	0:13413ea9a877	1297
ganlikun	0:13413ea9a877	1298	/**
ganlikun	0:13413ea9a877	1299	* @brief Disable the Debug Module during SLEEP mode
ganlikun	0:13413ea9a877	1300	* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
ganlikun	0:13413ea9a877	1301	* @retval None
ganlikun	0:13413ea9a877	1302	*/
ganlikun	0:13413ea9a877	1303	__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
ganlikun	0:13413ea9a877	1304	{
ganlikun	0:13413ea9a877	1305	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
ganlikun	0:13413ea9a877	1306	}
ganlikun	0:13413ea9a877	1307
ganlikun	0:13413ea9a877	1308	/**
ganlikun	0:13413ea9a877	1309	* @brief Enable the Debug Module during STOP mode
ganlikun	0:13413ea9a877	1310	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
ganlikun	0:13413ea9a877	1311	* @retval None
ganlikun	0:13413ea9a877	1312	*/
ganlikun	0:13413ea9a877	1313	__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
ganlikun	0:13413ea9a877	1314	{
ganlikun	0:13413ea9a877	1315	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
ganlikun	0:13413ea9a877	1316	}
ganlikun	0:13413ea9a877	1317
ganlikun	0:13413ea9a877	1318	/**
ganlikun	0:13413ea9a877	1319	* @brief Disable the Debug Module during STOP mode
ganlikun	0:13413ea9a877	1320	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
ganlikun	0:13413ea9a877	1321	* @retval None
ganlikun	0:13413ea9a877	1322	*/
ganlikun	0:13413ea9a877	1323	__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
ganlikun	0:13413ea9a877	1324	{
ganlikun	0:13413ea9a877	1325	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
ganlikun	0:13413ea9a877	1326	}
ganlikun	0:13413ea9a877	1327
ganlikun	0:13413ea9a877	1328	/**
ganlikun	0:13413ea9a877	1329	* @brief Enable the Debug Module during STANDBY mode
ganlikun	0:13413ea9a877	1330	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
ganlikun	0:13413ea9a877	1331	* @retval None
ganlikun	0:13413ea9a877	1332	*/
ganlikun	0:13413ea9a877	1333	__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
ganlikun	0:13413ea9a877	1334	{
ganlikun	0:13413ea9a877	1335	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
ganlikun	0:13413ea9a877	1336	}
ganlikun	0:13413ea9a877	1337
ganlikun	0:13413ea9a877	1338	/**
ganlikun	0:13413ea9a877	1339	* @brief Disable the Debug Module during STANDBY mode
ganlikun	0:13413ea9a877	1340	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
ganlikun	0:13413ea9a877	1341	* @retval None
ganlikun	0:13413ea9a877	1342	*/
ganlikun	0:13413ea9a877	1343	__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
ganlikun	0:13413ea9a877	1344	{
ganlikun	0:13413ea9a877	1345	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
ganlikun	0:13413ea9a877	1346	}
ganlikun	0:13413ea9a877	1347
ganlikun	0:13413ea9a877	1348	/**
ganlikun	0:13413ea9a877	1349	* @brief Set Trace pin assignment control
ganlikun	0:13413ea9a877	1350	* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
ganlikun	0:13413ea9a877	1351	* DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
ganlikun	0:13413ea9a877	1352	* @param PinAssignment This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1353	* @arg @ref LL_DBGMCU_TRACE_NONE
ganlikun	0:13413ea9a877	1354	* @arg @ref LL_DBGMCU_TRACE_ASYNCH
ganlikun	0:13413ea9a877	1355	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
ganlikun	0:13413ea9a877	1356	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
ganlikun	0:13413ea9a877	1357	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
ganlikun	0:13413ea9a877	1358	* @retval None
ganlikun	0:13413ea9a877	1359	*/
ganlikun	0:13413ea9a877	1360	__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
ganlikun	0:13413ea9a877	1361	{
ganlikun	0:13413ea9a877	1362	MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE, PinAssignment);
ganlikun	0:13413ea9a877	1363	}
ganlikun	0:13413ea9a877	1364
ganlikun	0:13413ea9a877	1365	/**
ganlikun	0:13413ea9a877	1366	* @brief Get Trace pin assignment control
ganlikun	0:13413ea9a877	1367	* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
ganlikun	0:13413ea9a877	1368	* DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
ganlikun	0:13413ea9a877	1369	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	1370	* @arg @ref LL_DBGMCU_TRACE_NONE
ganlikun	0:13413ea9a877	1371	* @arg @ref LL_DBGMCU_TRACE_ASYNCH
ganlikun	0:13413ea9a877	1372	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
ganlikun	0:13413ea9a877	1373	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
ganlikun	0:13413ea9a877	1374	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
ganlikun	0:13413ea9a877	1375	*/
ganlikun	0:13413ea9a877	1376	__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
ganlikun	0:13413ea9a877	1377	{
ganlikun	0:13413ea9a877	1378	return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE));
ganlikun	0:13413ea9a877	1379	}
ganlikun	0:13413ea9a877	1380
ganlikun	0:13413ea9a877	1381	/**
ganlikun	0:13413ea9a877	1382	* @brief Freeze APB1 peripherals (group1 peripherals)
ganlikun	0:13413ea9a877	1383	* @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1384	* DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1385	* DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1386	* DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1387	* DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1388	* DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1389	* DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1390	* DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1391	* DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1392	* DBGMCU_APB1_FZ DBG_LPTIM_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1393	* DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1394	* DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1395	* DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1396	* DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1397	* DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1398	* DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1399	* DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1400	* DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1401	* DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1402	* DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
ganlikun	0:13413ea9a877	1403	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1404	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
ganlikun	0:13413ea9a877	1405	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
ganlikun	0:13413ea9a877	1406	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
ganlikun	0:13413ea9a877	1407	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
ganlikun	0:13413ea9a877	1408	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
ganlikun	0:13413ea9a877	1409	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
ganlikun	0:13413ea9a877	1410	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
ganlikun	0:13413ea9a877	1411	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
ganlikun	0:13413ea9a877	1412	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
ganlikun	0:13413ea9a877	1413	* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
ganlikun	0:13413ea9a877	1414	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
ganlikun	0:13413ea9a877	1415	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
ganlikun	0:13413ea9a877	1416	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
ganlikun	0:13413ea9a877	1417	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
ganlikun	0:13413ea9a877	1418	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
ganlikun	0:13413ea9a877	1419	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
ganlikun	0:13413ea9a877	1420	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
ganlikun	0:13413ea9a877	1421	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
ganlikun	0:13413ea9a877	1422	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
ganlikun	0:13413ea9a877	1423	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
ganlikun	0:13413ea9a877	1424	*
ganlikun	0:13413ea9a877	1425	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1426	* @retval None
ganlikun	0:13413ea9a877	1427	*/
ganlikun	0:13413ea9a877	1428	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
ganlikun	0:13413ea9a877	1429	{
ganlikun	0:13413ea9a877	1430	SET_BIT(DBGMCU->APB1FZ, Periphs);
ganlikun	0:13413ea9a877	1431	}
ganlikun	0:13413ea9a877	1432
ganlikun	0:13413ea9a877	1433	/**
ganlikun	0:13413ea9a877	1434	* @brief Unfreeze APB1 peripherals (group1 peripherals)
ganlikun	0:13413ea9a877	1435	* @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1436	* DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1437	* DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1438	* DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1439	* DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1440	* DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1441	* DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1442	* DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1443	* DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1444	* DBGMCU_APB1_FZ DBG_LPTIM_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1445	* DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1446	* DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1447	* DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1448	* DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1449	* DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1450	* DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1451	* DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1452	* DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1453	* DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1454	* DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
ganlikun	0:13413ea9a877	1455	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1456	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
ganlikun	0:13413ea9a877	1457	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
ganlikun	0:13413ea9a877	1458	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
ganlikun	0:13413ea9a877	1459	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
ganlikun	0:13413ea9a877	1460	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
ganlikun	0:13413ea9a877	1461	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
ganlikun	0:13413ea9a877	1462	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
ganlikun	0:13413ea9a877	1463	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
ganlikun	0:13413ea9a877	1464	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
ganlikun	0:13413ea9a877	1465	* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
ganlikun	0:13413ea9a877	1466	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
ganlikun	0:13413ea9a877	1467	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
ganlikun	0:13413ea9a877	1468	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
ganlikun	0:13413ea9a877	1469	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
ganlikun	0:13413ea9a877	1470	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
ganlikun	0:13413ea9a877	1471	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
ganlikun	0:13413ea9a877	1472	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
ganlikun	0:13413ea9a877	1473	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
ganlikun	0:13413ea9a877	1474	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
ganlikun	0:13413ea9a877	1475	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
ganlikun	0:13413ea9a877	1476	*
ganlikun	0:13413ea9a877	1477	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1478	* @retval None
ganlikun	0:13413ea9a877	1479	*/
ganlikun	0:13413ea9a877	1480	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
ganlikun	0:13413ea9a877	1481	{
ganlikun	0:13413ea9a877	1482	CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
ganlikun	0:13413ea9a877	1483	}
ganlikun	0:13413ea9a877	1484
ganlikun	0:13413ea9a877	1485	/**
ganlikun	0:13413ea9a877	1486	* @brief Freeze APB2 peripherals
ganlikun	0:13413ea9a877	1487	* @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1488	* DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1489	* DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1490	* DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
ganlikun	0:13413ea9a877	1491	* DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
ganlikun	0:13413ea9a877	1492	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1493	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
ganlikun	0:13413ea9a877	1494	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
ganlikun	0:13413ea9a877	1495	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
ganlikun	0:13413ea9a877	1496	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
ganlikun	0:13413ea9a877	1497	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
ganlikun	0:13413ea9a877	1498	*
ganlikun	0:13413ea9a877	1499	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1500	* @retval None
ganlikun	0:13413ea9a877	1501	*/
ganlikun	0:13413ea9a877	1502	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
ganlikun	0:13413ea9a877	1503	{
ganlikun	0:13413ea9a877	1504	SET_BIT(DBGMCU->APB2FZ, Periphs);
ganlikun	0:13413ea9a877	1505	}
ganlikun	0:13413ea9a877	1506
ganlikun	0:13413ea9a877	1507	/**
ganlikun	0:13413ea9a877	1508	* @brief Unfreeze APB2 peripherals
ganlikun	0:13413ea9a877	1509	* @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1510	* DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1511	* DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1512	* DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
ganlikun	0:13413ea9a877	1513	* DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
ganlikun	0:13413ea9a877	1514	* @param Periphs This parameter can be a combination of the following values:
ganlikun	0:13413ea9a877	1515	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
ganlikun	0:13413ea9a877	1516	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
ganlikun	0:13413ea9a877	1517	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
ganlikun	0:13413ea9a877	1518	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
ganlikun	0:13413ea9a877	1519	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
ganlikun	0:13413ea9a877	1520	*
ganlikun	0:13413ea9a877	1521	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1522	* @retval None
ganlikun	0:13413ea9a877	1523	*/
ganlikun	0:13413ea9a877	1524	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
ganlikun	0:13413ea9a877	1525	{
ganlikun	0:13413ea9a877	1526	CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
ganlikun	0:13413ea9a877	1527	}
ganlikun	0:13413ea9a877	1528	/**
ganlikun	0:13413ea9a877	1529	* @}
ganlikun	0:13413ea9a877	1530	*/
ganlikun	0:13413ea9a877	1531
ganlikun	0:13413ea9a877	1532	/** @defgroup SYSTEM_LL_EF_FLASH FLASH
ganlikun	0:13413ea9a877	1533	* @{
ganlikun	0:13413ea9a877	1534	*/
ganlikun	0:13413ea9a877	1535
ganlikun	0:13413ea9a877	1536	/**
ganlikun	0:13413ea9a877	1537	* @brief Set FLASH Latency
ganlikun	0:13413ea9a877	1538	* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
ganlikun	0:13413ea9a877	1539	* @param Latency This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1540	* @arg @ref LL_FLASH_LATENCY_0
ganlikun	0:13413ea9a877	1541	* @arg @ref LL_FLASH_LATENCY_1
ganlikun	0:13413ea9a877	1542	* @arg @ref LL_FLASH_LATENCY_2
ganlikun	0:13413ea9a877	1543	* @arg @ref LL_FLASH_LATENCY_3
ganlikun	0:13413ea9a877	1544	* @arg @ref LL_FLASH_LATENCY_4
ganlikun	0:13413ea9a877	1545	* @arg @ref LL_FLASH_LATENCY_5
ganlikun	0:13413ea9a877	1546	* @arg @ref LL_FLASH_LATENCY_6
ganlikun	0:13413ea9a877	1547	* @arg @ref LL_FLASH_LATENCY_7
ganlikun	0:13413ea9a877	1548	* @arg @ref LL_FLASH_LATENCY_8
ganlikun	0:13413ea9a877	1549	* @arg @ref LL_FLASH_LATENCY_9
ganlikun	0:13413ea9a877	1550	* @arg @ref LL_FLASH_LATENCY_10
ganlikun	0:13413ea9a877	1551	* @arg @ref LL_FLASH_LATENCY_11
ganlikun	0:13413ea9a877	1552	* @arg @ref LL_FLASH_LATENCY_12
ganlikun	0:13413ea9a877	1553	* @arg @ref LL_FLASH_LATENCY_13
ganlikun	0:13413ea9a877	1554	* @arg @ref LL_FLASH_LATENCY_14
ganlikun	0:13413ea9a877	1555	* @arg @ref LL_FLASH_LATENCY_15
ganlikun	0:13413ea9a877	1556	* @retval None
ganlikun	0:13413ea9a877	1557	*/
ganlikun	0:13413ea9a877	1558	__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
ganlikun	0:13413ea9a877	1559	{
ganlikun	0:13413ea9a877	1560	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
ganlikun	0:13413ea9a877	1561	}
ganlikun	0:13413ea9a877	1562
ganlikun	0:13413ea9a877	1563	/**
ganlikun	0:13413ea9a877	1564	* @brief Get FLASH Latency
ganlikun	0:13413ea9a877	1565	* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
ganlikun	0:13413ea9a877	1566	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	1567	* @arg @ref LL_FLASH_LATENCY_0
ganlikun	0:13413ea9a877	1568	* @arg @ref LL_FLASH_LATENCY_1
ganlikun	0:13413ea9a877	1569	* @arg @ref LL_FLASH_LATENCY_2
ganlikun	0:13413ea9a877	1570	* @arg @ref LL_FLASH_LATENCY_3
ganlikun	0:13413ea9a877	1571	* @arg @ref LL_FLASH_LATENCY_4
ganlikun	0:13413ea9a877	1572	* @arg @ref LL_FLASH_LATENCY_5
ganlikun	0:13413ea9a877	1573	* @arg @ref LL_FLASH_LATENCY_6
ganlikun	0:13413ea9a877	1574	* @arg @ref LL_FLASH_LATENCY_7
ganlikun	0:13413ea9a877	1575	* @arg @ref LL_FLASH_LATENCY_8
ganlikun	0:13413ea9a877	1576	* @arg @ref LL_FLASH_LATENCY_9
ganlikun	0:13413ea9a877	1577	* @arg @ref LL_FLASH_LATENCY_10
ganlikun	0:13413ea9a877	1578	* @arg @ref LL_FLASH_LATENCY_11
ganlikun	0:13413ea9a877	1579	* @arg @ref LL_FLASH_LATENCY_12
ganlikun	0:13413ea9a877	1580	* @arg @ref LL_FLASH_LATENCY_13
ganlikun	0:13413ea9a877	1581	* @arg @ref LL_FLASH_LATENCY_14
ganlikun	0:13413ea9a877	1582	* @arg @ref LL_FLASH_LATENCY_15
ganlikun	0:13413ea9a877	1583	*/
ganlikun	0:13413ea9a877	1584	__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
ganlikun	0:13413ea9a877	1585	{
ganlikun	0:13413ea9a877	1586	return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
ganlikun	0:13413ea9a877	1587	}
ganlikun	0:13413ea9a877	1588
ganlikun	0:13413ea9a877	1589	/**
ganlikun	0:13413ea9a877	1590	* @brief Enable Prefetch
ganlikun	0:13413ea9a877	1591	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
ganlikun	0:13413ea9a877	1592	* @retval None
ganlikun	0:13413ea9a877	1593	*/
ganlikun	0:13413ea9a877	1594	__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
ganlikun	0:13413ea9a877	1595	{
ganlikun	0:13413ea9a877	1596	SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
ganlikun	0:13413ea9a877	1597	}
ganlikun	0:13413ea9a877	1598
ganlikun	0:13413ea9a877	1599	/**
ganlikun	0:13413ea9a877	1600	* @brief Disable Prefetch
ganlikun	0:13413ea9a877	1601	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
ganlikun	0:13413ea9a877	1602	* @retval None
ganlikun	0:13413ea9a877	1603	*/
ganlikun	0:13413ea9a877	1604	__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
ganlikun	0:13413ea9a877	1605	{
ganlikun	0:13413ea9a877	1606	CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
ganlikun	0:13413ea9a877	1607	}
ganlikun	0:13413ea9a877	1608
ganlikun	0:13413ea9a877	1609	/**
ganlikun	0:13413ea9a877	1610	* @brief Check if Prefetch buffer is enabled
ganlikun	0:13413ea9a877	1611	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
ganlikun	0:13413ea9a877	1612	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1613	*/
ganlikun	0:13413ea9a877	1614	__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
ganlikun	0:13413ea9a877	1615	{
ganlikun	0:13413ea9a877	1616	return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
ganlikun	0:13413ea9a877	1617	}
ganlikun	0:13413ea9a877	1618
ganlikun	0:13413ea9a877	1619	/**
ganlikun	0:13413ea9a877	1620	* @brief Enable Instruction cache
ganlikun	0:13413ea9a877	1621	* @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
ganlikun	0:13413ea9a877	1622	* @retval None
ganlikun	0:13413ea9a877	1623	*/
ganlikun	0:13413ea9a877	1624	__STATIC_INLINE void LL_FLASH_EnableInstCache(void)
ganlikun	0:13413ea9a877	1625	{
ganlikun	0:13413ea9a877	1626	SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
ganlikun	0:13413ea9a877	1627	}
ganlikun	0:13413ea9a877	1628
ganlikun	0:13413ea9a877	1629	/**
ganlikun	0:13413ea9a877	1630	* @brief Disable Instruction cache
ganlikun	0:13413ea9a877	1631	* @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
ganlikun	0:13413ea9a877	1632	* @retval None
ganlikun	0:13413ea9a877	1633	*/
ganlikun	0:13413ea9a877	1634	__STATIC_INLINE void LL_FLASH_DisableInstCache(void)
ganlikun	0:13413ea9a877	1635	{
ganlikun	0:13413ea9a877	1636	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
ganlikun	0:13413ea9a877	1637	}
ganlikun	0:13413ea9a877	1638
ganlikun	0:13413ea9a877	1639	/**
ganlikun	0:13413ea9a877	1640	* @brief Enable Data cache
ganlikun	0:13413ea9a877	1641	* @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
ganlikun	0:13413ea9a877	1642	* @retval None
ganlikun	0:13413ea9a877	1643	*/
ganlikun	0:13413ea9a877	1644	__STATIC_INLINE void LL_FLASH_EnableDataCache(void)
ganlikun	0:13413ea9a877	1645	{
ganlikun	0:13413ea9a877	1646	SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
ganlikun	0:13413ea9a877	1647	}
ganlikun	0:13413ea9a877	1648
ganlikun	0:13413ea9a877	1649	/**
ganlikun	0:13413ea9a877	1650	* @brief Disable Data cache
ganlikun	0:13413ea9a877	1651	* @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
ganlikun	0:13413ea9a877	1652	* @retval None
ganlikun	0:13413ea9a877	1653	*/
ganlikun	0:13413ea9a877	1654	__STATIC_INLINE void LL_FLASH_DisableDataCache(void)
ganlikun	0:13413ea9a877	1655	{
ganlikun	0:13413ea9a877	1656	CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
ganlikun	0:13413ea9a877	1657	}
ganlikun	0:13413ea9a877	1658
ganlikun	0:13413ea9a877	1659	/**
ganlikun	0:13413ea9a877	1660	* @brief Enable Instruction cache reset
ganlikun	0:13413ea9a877	1661	* @note bit can be written only when the instruction cache is disabled
ganlikun	0:13413ea9a877	1662	* @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
ganlikun	0:13413ea9a877	1663	* @retval None
ganlikun	0:13413ea9a877	1664	*/
ganlikun	0:13413ea9a877	1665	__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
ganlikun	0:13413ea9a877	1666	{
ganlikun	0:13413ea9a877	1667	SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
ganlikun	0:13413ea9a877	1668	}
ganlikun	0:13413ea9a877	1669
ganlikun	0:13413ea9a877	1670	/**
ganlikun	0:13413ea9a877	1671	* @brief Disable Instruction cache reset
ganlikun	0:13413ea9a877	1672	* @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
ganlikun	0:13413ea9a877	1673	* @retval None
ganlikun	0:13413ea9a877	1674	*/
ganlikun	0:13413ea9a877	1675	__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
ganlikun	0:13413ea9a877	1676	{
ganlikun	0:13413ea9a877	1677	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
ganlikun	0:13413ea9a877	1678	}
ganlikun	0:13413ea9a877	1679
ganlikun	0:13413ea9a877	1680	/**
ganlikun	0:13413ea9a877	1681	* @brief Enable Data cache reset
ganlikun	0:13413ea9a877	1682	* @note bit can be written only when the data cache is disabled
ganlikun	0:13413ea9a877	1683	* @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
ganlikun	0:13413ea9a877	1684	* @retval None
ganlikun	0:13413ea9a877	1685	*/
ganlikun	0:13413ea9a877	1686	__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
ganlikun	0:13413ea9a877	1687	{
ganlikun	0:13413ea9a877	1688	SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
ganlikun	0:13413ea9a877	1689	}
ganlikun	0:13413ea9a877	1690
ganlikun	0:13413ea9a877	1691	/**
ganlikun	0:13413ea9a877	1692	* @brief Disable Data cache reset
ganlikun	0:13413ea9a877	1693	* @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
ganlikun	0:13413ea9a877	1694	* @retval None
ganlikun	0:13413ea9a877	1695	*/
ganlikun	0:13413ea9a877	1696	__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
ganlikun	0:13413ea9a877	1697	{
ganlikun	0:13413ea9a877	1698	CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
ganlikun	0:13413ea9a877	1699	}
ganlikun	0:13413ea9a877	1700
ganlikun	0:13413ea9a877	1701
ganlikun	0:13413ea9a877	1702	/**
ganlikun	0:13413ea9a877	1703	* @}
ganlikun	0:13413ea9a877	1704	*/
ganlikun	0:13413ea9a877	1705
ganlikun	0:13413ea9a877	1706	/**
ganlikun	0:13413ea9a877	1707	* @}
ganlikun	0:13413ea9a877	1708	*/
ganlikun	0:13413ea9a877	1709
ganlikun	0:13413ea9a877	1710	/**
ganlikun	0:13413ea9a877	1711	* @}
ganlikun	0:13413ea9a877	1712	*/
ganlikun	0:13413ea9a877	1713
ganlikun	0:13413ea9a877	1714	#endif /* defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU) */
ganlikun	0:13413ea9a877	1715
ganlikun	0:13413ea9a877	1716	/**
ganlikun	0:13413ea9a877	1717	* @}
ganlikun	0:13413ea9a877	1718	*/
ganlikun	0:13413ea9a877	1719
ganlikun	0:13413ea9a877	1720	#ifdef __cplusplus
ganlikun	0:13413ea9a877	1721	}
ganlikun	0:13413ea9a877	1722	#endif
ganlikun	0:13413ea9a877	1723
ganlikun	0:13413ea9a877	1724	#endif /* __STM32F4xx_LL_SYSTEM_H */
ganlikun	0:13413ea9a877	1725
ganlikun	0:13413ea9a877	1726	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
ganlikun	0:13413ea9a877	1727

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Type:	Library
Created:	05 Jul 2022
Imports:	1
Forks:	0
Commits:	1
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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_system.h@0:13413ea9a877, 2022-06-12 (annotated)

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