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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.h@0:13413ea9a877, 2022-06-12 (annotated)

Committer:: ganlikun
Date:: Sun Jun 12 14:02:44 2022 +0000
Revision:: 0:13413ea9a877

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User	Revision	Line number	New contents of line
ganlikun	0:13413ea9a877	1	/**
ganlikun	0:13413ea9a877	2	******************************************************************************
ganlikun	0:13413ea9a877	3	* @file stm32f4xx_ll_spi.h
ganlikun	0:13413ea9a877	4	* @author MCD Application Team
ganlikun	0:13413ea9a877	5	* @version V1.7.1
ganlikun	0:13413ea9a877	6	* @date 14-April-2017
ganlikun	0:13413ea9a877	7	* @brief Header file of SPI LL module.
ganlikun	0:13413ea9a877	8	******************************************************************************
ganlikun	0:13413ea9a877	9	* @attention
ganlikun	0:13413ea9a877	10	*
ganlikun	0:13413ea9a877	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun	0:13413ea9a877	12	*
ganlikun	0:13413ea9a877	13	* Redistribution and use in source and binary forms, with or without modification,
ganlikun	0:13413ea9a877	14	* are permitted provided that the following conditions are met:
ganlikun	0:13413ea9a877	15	* 1. Redistributions of source code must retain the above copyright notice,
ganlikun	0:13413ea9a877	16	* this list of conditions and the following disclaimer.
ganlikun	0:13413ea9a877	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun	0:13413ea9a877	18	* this list of conditions and the following disclaimer in the documentation
ganlikun	0:13413ea9a877	19	* and/or other materials provided with the distribution.
ganlikun	0:13413ea9a877	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun	0:13413ea9a877	21	* may be used to endorse or promote products derived from this software
ganlikun	0:13413ea9a877	22	* without specific prior written permission.
ganlikun	0:13413ea9a877	23	*
ganlikun	0:13413ea9a877	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun	0:13413ea9a877	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun	0:13413ea9a877	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun	0:13413ea9a877	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun	0:13413ea9a877	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun	0:13413ea9a877	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun	0:13413ea9a877	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun	0:13413ea9a877	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun	0:13413ea9a877	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun	0:13413ea9a877	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun	0:13413ea9a877	34	*
ganlikun	0:13413ea9a877	35	******************************************************************************
ganlikun	0:13413ea9a877	36	*/
ganlikun	0:13413ea9a877	37
ganlikun	0:13413ea9a877	38	/* Define to prevent recursive inclusion -------------------------------------*/
ganlikun	0:13413ea9a877	39	#ifndef __STM32F4xx_LL_SPI_H
ganlikun	0:13413ea9a877	40	#define __STM32F4xx_LL_SPI_H
ganlikun	0:13413ea9a877	41
ganlikun	0:13413ea9a877	42	#ifdef __cplusplus
ganlikun	0:13413ea9a877	43	extern "C" {
ganlikun	0:13413ea9a877	44	#endif
ganlikun	0:13413ea9a877	45
ganlikun	0:13413ea9a877	46	/* Includes ------------------------------------------------------------------*/
ganlikun	0:13413ea9a877	47	#include "stm32f4xx.h"
ganlikun	0:13413ea9a877	48
ganlikun	0:13413ea9a877	49	/** @addtogroup STM32F4xx_LL_Driver
ganlikun	0:13413ea9a877	50	* @{
ganlikun	0:13413ea9a877	51	*/
ganlikun	0:13413ea9a877	52
ganlikun	0:13413ea9a877	53	#if defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3) \|\| defined (SPI4) \|\| defined (SPI5) \|\| defined(SPI6)
ganlikun	0:13413ea9a877	54
ganlikun	0:13413ea9a877	55	/** @defgroup SPI_LL SPI
ganlikun	0:13413ea9a877	56	* @{
ganlikun	0:13413ea9a877	57	*/
ganlikun	0:13413ea9a877	58
ganlikun	0:13413ea9a877	59	/* Private types -------------------------------------------------------------*/
ganlikun	0:13413ea9a877	60	/* Private variables ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	61	/* Private macros ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	62
ganlikun	0:13413ea9a877	63	/* Exported types ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	64	#if defined(USE_FULL_LL_DRIVER)
ganlikun	0:13413ea9a877	65	/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
ganlikun	0:13413ea9a877	66	* @{
ganlikun	0:13413ea9a877	67	*/
ganlikun	0:13413ea9a877	68
ganlikun	0:13413ea9a877	69	/**
ganlikun	0:13413ea9a877	70	* @brief SPI Init structures definition
ganlikun	0:13413ea9a877	71	*/
ganlikun	0:13413ea9a877	72	typedef struct
ganlikun	0:13413ea9a877	73	{
ganlikun	0:13413ea9a877	74	uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
ganlikun	0:13413ea9a877	75	This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
ganlikun	0:13413ea9a877	76
ganlikun	0:13413ea9a877	77	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
ganlikun	0:13413ea9a877	78
ganlikun	0:13413ea9a877	79	uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
ganlikun	0:13413ea9a877	80	This parameter can be a value of @ref SPI_LL_EC_MODE.
ganlikun	0:13413ea9a877	81
ganlikun	0:13413ea9a877	82	This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
ganlikun	0:13413ea9a877	83
ganlikun	0:13413ea9a877	84	uint32_t DataWidth; /*!< Specifies the SPI data width.
ganlikun	0:13413ea9a877	85	This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
ganlikun	0:13413ea9a877	86
ganlikun	0:13413ea9a877	87	This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
ganlikun	0:13413ea9a877	88
ganlikun	0:13413ea9a877	89	uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
ganlikun	0:13413ea9a877	90	This parameter can be a value of @ref SPI_LL_EC_POLARITY.
ganlikun	0:13413ea9a877	91
ganlikun	0:13413ea9a877	92	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
ganlikun	0:13413ea9a877	93
ganlikun	0:13413ea9a877	94	uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
ganlikun	0:13413ea9a877	95	This parameter can be a value of @ref SPI_LL_EC_PHASE.
ganlikun	0:13413ea9a877	96
ganlikun	0:13413ea9a877	97	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
ganlikun	0:13413ea9a877	98
ganlikun	0:13413ea9a877	99	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
ganlikun	0:13413ea9a877	100	This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
ganlikun	0:13413ea9a877	101
ganlikun	0:13413ea9a877	102	This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
ganlikun	0:13413ea9a877	103
ganlikun	0:13413ea9a877	104	uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
ganlikun	0:13413ea9a877	105	This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
ganlikun	0:13413ea9a877	106	@note The communication clock is derived from the master clock. The slave clock does not need to be set.
ganlikun	0:13413ea9a877	107
ganlikun	0:13413ea9a877	108	This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
ganlikun	0:13413ea9a877	109
ganlikun	0:13413ea9a877	110	uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
ganlikun	0:13413ea9a877	111	This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
ganlikun	0:13413ea9a877	112
ganlikun	0:13413ea9a877	113	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
ganlikun	0:13413ea9a877	114
ganlikun	0:13413ea9a877	115	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
ganlikun	0:13413ea9a877	116	This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
ganlikun	0:13413ea9a877	117
ganlikun	0:13413ea9a877	118	This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
ganlikun	0:13413ea9a877	119
ganlikun	0:13413ea9a877	120	uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
ganlikun	0:13413ea9a877	121	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
ganlikun	0:13413ea9a877	122
ganlikun	0:13413ea9a877	123	This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
ganlikun	0:13413ea9a877	124
ganlikun	0:13413ea9a877	125	} LL_SPI_InitTypeDef;
ganlikun	0:13413ea9a877	126
ganlikun	0:13413ea9a877	127	/**
ganlikun	0:13413ea9a877	128	* @}
ganlikun	0:13413ea9a877	129	*/
ganlikun	0:13413ea9a877	130	#endif /* USE_FULL_LL_DRIVER */
ganlikun	0:13413ea9a877	131
ganlikun	0:13413ea9a877	132	/* Exported constants --------------------------------------------------------*/
ganlikun	0:13413ea9a877	133	/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
ganlikun	0:13413ea9a877	134	* @{
ganlikun	0:13413ea9a877	135	*/
ganlikun	0:13413ea9a877	136
ganlikun	0:13413ea9a877	137	/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
ganlikun	0:13413ea9a877	138	* @brief Flags defines which can be used with LL_SPI_ReadReg function
ganlikun	0:13413ea9a877	139	* @{
ganlikun	0:13413ea9a877	140	*/
ganlikun	0:13413ea9a877	141	#define LL_SPI_SR_RXNE SPI_SR_RXNE /!< Rx buffer not empty flag /
ganlikun	0:13413ea9a877	142	#define LL_SPI_SR_TXE SPI_SR_TXE /!< Tx buffer empty flag /
ganlikun	0:13413ea9a877	143	#define LL_SPI_SR_BSY SPI_SR_BSY /!< Busy flag /
ganlikun	0:13413ea9a877	144	#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /!< CRC error flag /
ganlikun	0:13413ea9a877	145	#define LL_SPI_SR_MODF SPI_SR_MODF /!< Mode fault flag /
ganlikun	0:13413ea9a877	146	#define LL_SPI_SR_OVR SPI_SR_OVR /!< Overrun flag /
ganlikun	0:13413ea9a877	147	#define LL_SPI_SR_FRE SPI_SR_FRE /!< TI mode frame format error flag /
ganlikun	0:13413ea9a877	148	/**
ganlikun	0:13413ea9a877	149	* @}
ganlikun	0:13413ea9a877	150	*/
ganlikun	0:13413ea9a877	151
ganlikun	0:13413ea9a877	152	/** @defgroup SPI_LL_EC_IT IT Defines
ganlikun	0:13413ea9a877	153	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
ganlikun	0:13413ea9a877	154	* @{
ganlikun	0:13413ea9a877	155	*/
ganlikun	0:13413ea9a877	156	#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
ganlikun	0:13413ea9a877	157	#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
ganlikun	0:13413ea9a877	158	#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /!< Error interrupt enable /
ganlikun	0:13413ea9a877	159	/**
ganlikun	0:13413ea9a877	160	* @}
ganlikun	0:13413ea9a877	161	*/
ganlikun	0:13413ea9a877	162
ganlikun	0:13413ea9a877	163	/** @defgroup SPI_LL_EC_MODE Operation Mode
ganlikun	0:13413ea9a877	164	* @{
ganlikun	0:13413ea9a877	165	*/
ganlikun	0:13413ea9a877	166	#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI) /!< Master configuration /
ganlikun	0:13413ea9a877	167	#define LL_SPI_MODE_SLAVE 0x00000000U /!< Slave configuration /
ganlikun	0:13413ea9a877	168	/**
ganlikun	0:13413ea9a877	169	* @}
ganlikun	0:13413ea9a877	170	*/
ganlikun	0:13413ea9a877	171
ganlikun	0:13413ea9a877	172	/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
ganlikun	0:13413ea9a877	173	* @{
ganlikun	0:13413ea9a877	174	*/
ganlikun	0:13413ea9a877	175	#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /!< Motorola mode. Used as default value /
ganlikun	0:13413ea9a877	176	#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /!< TI mode /
ganlikun	0:13413ea9a877	177	/**
ganlikun	0:13413ea9a877	178	* @}
ganlikun	0:13413ea9a877	179	*/
ganlikun	0:13413ea9a877	180
ganlikun	0:13413ea9a877	181	/** @defgroup SPI_LL_EC_PHASE Clock Phase
ganlikun	0:13413ea9a877	182	* @{
ganlikun	0:13413ea9a877	183	*/
ganlikun	0:13413ea9a877	184	#define LL_SPI_PHASE_1EDGE 0x00000000U /!< First clock transition is the first data capture edge /
ganlikun	0:13413ea9a877	185	#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /!< Second clock transition is the first data capture edge /
ganlikun	0:13413ea9a877	186	/**
ganlikun	0:13413ea9a877	187	* @}
ganlikun	0:13413ea9a877	188	*/
ganlikun	0:13413ea9a877	189
ganlikun	0:13413ea9a877	190	/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
ganlikun	0:13413ea9a877	191	* @{
ganlikun	0:13413ea9a877	192	*/
ganlikun	0:13413ea9a877	193	#define LL_SPI_POLARITY_LOW 0x00000000U /!< Clock to 0 when idle /
ganlikun	0:13413ea9a877	194	#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /!< Clock to 1 when idle /
ganlikun	0:13413ea9a877	195	/**
ganlikun	0:13413ea9a877	196	* @}
ganlikun	0:13413ea9a877	197	*/
ganlikun	0:13413ea9a877	198
ganlikun	0:13413ea9a877	199	/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
ganlikun	0:13413ea9a877	200	* @{
ganlikun	0:13413ea9a877	201	*/
ganlikun	0:13413ea9a877	202	#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /!< BaudRate control equal to fPCLK/2 /
ganlikun	0:13413ea9a877	203	#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/4 /
ganlikun	0:13413ea9a877	204	#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/8 /
ganlikun	0:13413ea9a877	205	#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/16 /
ganlikun	0:13413ea9a877	206	#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /!< BaudRate control equal to fPCLK/32 /
ganlikun	0:13413ea9a877	207	#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/64 /
ganlikun	0:13413ea9a877	208	#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 \| SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/128 /
ganlikun	0:13413ea9a877	209	#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 \| SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/256 /
ganlikun	0:13413ea9a877	210	/**
ganlikun	0:13413ea9a877	211	* @}
ganlikun	0:13413ea9a877	212	*/
ganlikun	0:13413ea9a877	213
ganlikun	0:13413ea9a877	214	/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
ganlikun	0:13413ea9a877	215	* @{
ganlikun	0:13413ea9a877	216	*/
ganlikun	0:13413ea9a877	217	#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /!< Data is transmitted/received with the LSB first /
ganlikun	0:13413ea9a877	218	#define LL_SPI_MSB_FIRST 0x00000000U /!< Data is transmitted/received with the MSB first /
ganlikun	0:13413ea9a877	219	/**
ganlikun	0:13413ea9a877	220	* @}
ganlikun	0:13413ea9a877	221	*/
ganlikun	0:13413ea9a877	222
ganlikun	0:13413ea9a877	223	/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
ganlikun	0:13413ea9a877	224	* @{
ganlikun	0:13413ea9a877	225	*/
ganlikun	0:13413ea9a877	226	#define LL_SPI_FULL_DUPLEX 0x00000000U /!< Full-Duplex mode. Rx and Tx transfer on 2 lines /
ganlikun	0:13413ea9a877	227	#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /!< Simplex Rx mode. Rx transfer only on 1 line /
ganlikun	0:13413ea9a877	228	#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /!< Half-Duplex Rx mode. Rx transfer on 1 line /
ganlikun	0:13413ea9a877	229	#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE) /!< Half-Duplex Tx mode. Tx transfer on 1 line /
ganlikun	0:13413ea9a877	230	/**
ganlikun	0:13413ea9a877	231	* @}
ganlikun	0:13413ea9a877	232	*/
ganlikun	0:13413ea9a877	233
ganlikun	0:13413ea9a877	234	/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
ganlikun	0:13413ea9a877	235	* @{
ganlikun	0:13413ea9a877	236	*/
ganlikun	0:13413ea9a877	237	#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /!< NSS managed internally. NSS pin not used and free /
ganlikun	0:13413ea9a877	238	#define LL_SPI_NSS_HARD_INPUT 0x00000000U /!< NSS pin used in Input. Only used in Master mode /
ganlikun	0:13413ea9a877	239	#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /!< NSS pin used in Output. Only used in Slave mode as chip select /
ganlikun	0:13413ea9a877	240	/**
ganlikun	0:13413ea9a877	241	* @}
ganlikun	0:13413ea9a877	242	*/
ganlikun	0:13413ea9a877	243
ganlikun	0:13413ea9a877	244	/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
ganlikun	0:13413ea9a877	245	* @{
ganlikun	0:13413ea9a877	246	*/
ganlikun	0:13413ea9a877	247	#define LL_SPI_DATAWIDTH_8BIT 0x00000000U /!< Data length for SPI transfer: 8 bits /
ganlikun	0:13413ea9a877	248	#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /!< Data length for SPI transfer: 16 bits /
ganlikun	0:13413ea9a877	249	/**
ganlikun	0:13413ea9a877	250	* @}
ganlikun	0:13413ea9a877	251	*/
ganlikun	0:13413ea9a877	252	#if defined(USE_FULL_LL_DRIVER)
ganlikun	0:13413ea9a877	253
ganlikun	0:13413ea9a877	254	/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
ganlikun	0:13413ea9a877	255	* @{
ganlikun	0:13413ea9a877	256	*/
ganlikun	0:13413ea9a877	257	#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /!< CRC calculation disabled /
ganlikun	0:13413ea9a877	258	#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /!< CRC calculation enabled /
ganlikun	0:13413ea9a877	259	/**
ganlikun	0:13413ea9a877	260	* @}
ganlikun	0:13413ea9a877	261	*/
ganlikun	0:13413ea9a877	262	#endif /* USE_FULL_LL_DRIVER */
ganlikun	0:13413ea9a877	263
ganlikun	0:13413ea9a877	264	/**
ganlikun	0:13413ea9a877	265	* @}
ganlikun	0:13413ea9a877	266	*/
ganlikun	0:13413ea9a877	267
ganlikun	0:13413ea9a877	268	/* Exported macro ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	269	/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
ganlikun	0:13413ea9a877	270	* @{
ganlikun	0:13413ea9a877	271	*/
ganlikun	0:13413ea9a877	272
ganlikun	0:13413ea9a877	273	/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
ganlikun	0:13413ea9a877	274	* @{
ganlikun	0:13413ea9a877	275	*/
ganlikun	0:13413ea9a877	276
ganlikun	0:13413ea9a877	277	/**
ganlikun	0:13413ea9a877	278	* @brief Write a value in SPI register
ganlikun	0:13413ea9a877	279	* @param __INSTANCE__ SPI Instance
ganlikun	0:13413ea9a877	280	* @param __REG__ Register to be written
ganlikun	0:13413ea9a877	281	* @param __VALUE__ Value to be written in the register
ganlikun	0:13413ea9a877	282	* @retval None
ganlikun	0:13413ea9a877	283	*/
ganlikun	0:13413ea9a877	284	#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
ganlikun	0:13413ea9a877	285
ganlikun	0:13413ea9a877	286	/**
ganlikun	0:13413ea9a877	287	* @brief Read a value in SPI register
ganlikun	0:13413ea9a877	288	* @param __INSTANCE__ SPI Instance
ganlikun	0:13413ea9a877	289	* @param __REG__ Register to be read
ganlikun	0:13413ea9a877	290	* @retval Register value
ganlikun	0:13413ea9a877	291	*/
ganlikun	0:13413ea9a877	292	#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
ganlikun	0:13413ea9a877	293	/**
ganlikun	0:13413ea9a877	294	* @}
ganlikun	0:13413ea9a877	295	*/
ganlikun	0:13413ea9a877	296
ganlikun	0:13413ea9a877	297	/**
ganlikun	0:13413ea9a877	298	* @}
ganlikun	0:13413ea9a877	299	*/
ganlikun	0:13413ea9a877	300
ganlikun	0:13413ea9a877	301	/* Exported functions --------------------------------------------------------*/
ganlikun	0:13413ea9a877	302	/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
ganlikun	0:13413ea9a877	303	* @{
ganlikun	0:13413ea9a877	304	*/
ganlikun	0:13413ea9a877	305
ganlikun	0:13413ea9a877	306	/** @defgroup SPI_LL_EF_Configuration Configuration
ganlikun	0:13413ea9a877	307	* @{
ganlikun	0:13413ea9a877	308	*/
ganlikun	0:13413ea9a877	309
ganlikun	0:13413ea9a877	310	/**
ganlikun	0:13413ea9a877	311	* @brief Enable SPI peripheral
ganlikun	0:13413ea9a877	312	* @rmtoll CR1 SPE LL_SPI_Enable
ganlikun	0:13413ea9a877	313	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	314	* @retval None
ganlikun	0:13413ea9a877	315	*/
ganlikun	0:13413ea9a877	316	__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	317	{
ganlikun	0:13413ea9a877	318	SET_BIT(SPIx->CR1, SPI_CR1_SPE);
ganlikun	0:13413ea9a877	319	}
ganlikun	0:13413ea9a877	320
ganlikun	0:13413ea9a877	321	/**
ganlikun	0:13413ea9a877	322	* @brief Disable SPI peripheral
ganlikun	0:13413ea9a877	323	* @note When disabling the SPI, follow the procedure described in the Reference Manual.
ganlikun	0:13413ea9a877	324	* @rmtoll CR1 SPE LL_SPI_Disable
ganlikun	0:13413ea9a877	325	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	326	* @retval None
ganlikun	0:13413ea9a877	327	*/
ganlikun	0:13413ea9a877	328	__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	329	{
ganlikun	0:13413ea9a877	330	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
ganlikun	0:13413ea9a877	331	}
ganlikun	0:13413ea9a877	332
ganlikun	0:13413ea9a877	333	/**
ganlikun	0:13413ea9a877	334	* @brief Check if SPI peripheral is enabled
ganlikun	0:13413ea9a877	335	* @rmtoll CR1 SPE LL_SPI_IsEnabled
ganlikun	0:13413ea9a877	336	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	337	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	338	*/
ganlikun	0:13413ea9a877	339	__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	340	{
ganlikun	0:13413ea9a877	341	return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
ganlikun	0:13413ea9a877	342	}
ganlikun	0:13413ea9a877	343
ganlikun	0:13413ea9a877	344	/**
ganlikun	0:13413ea9a877	345	* @brief Set SPI operation mode to Master or Slave
ganlikun	0:13413ea9a877	346	* @note This bit should not be changed when communication is ongoing.
ganlikun	0:13413ea9a877	347	* @rmtoll CR1 MSTR LL_SPI_SetMode\n
ganlikun	0:13413ea9a877	348	* CR1 SSI LL_SPI_SetMode
ganlikun	0:13413ea9a877	349	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	350	* @param Mode This parameter can be one of the following values:
ganlikun	0:13413ea9a877	351	* @arg @ref LL_SPI_MODE_MASTER
ganlikun	0:13413ea9a877	352	* @arg @ref LL_SPI_MODE_SLAVE
ganlikun	0:13413ea9a877	353	* @retval None
ganlikun	0:13413ea9a877	354	*/
ganlikun	0:13413ea9a877	355	__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
ganlikun	0:13413ea9a877	356	{
ganlikun	0:13413ea9a877	357	MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI, Mode);
ganlikun	0:13413ea9a877	358	}
ganlikun	0:13413ea9a877	359
ganlikun	0:13413ea9a877	360	/**
ganlikun	0:13413ea9a877	361	* @brief Get SPI operation mode (Master or Slave)
ganlikun	0:13413ea9a877	362	* @rmtoll CR1 MSTR LL_SPI_GetMode\n
ganlikun	0:13413ea9a877	363	* CR1 SSI LL_SPI_GetMode
ganlikun	0:13413ea9a877	364	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	365	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	366	* @arg @ref LL_SPI_MODE_MASTER
ganlikun	0:13413ea9a877	367	* @arg @ref LL_SPI_MODE_SLAVE
ganlikun	0:13413ea9a877	368	*/
ganlikun	0:13413ea9a877	369	__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	370	{
ganlikun	0:13413ea9a877	371	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI));
ganlikun	0:13413ea9a877	372	}
ganlikun	0:13413ea9a877	373
ganlikun	0:13413ea9a877	374	/**
ganlikun	0:13413ea9a877	375	* @brief Set serial protocol used
ganlikun	0:13413ea9a877	376	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
ganlikun	0:13413ea9a877	377	* @rmtoll CR2 FRF LL_SPI_SetStandard
ganlikun	0:13413ea9a877	378	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	379	* @param Standard This parameter can be one of the following values:
ganlikun	0:13413ea9a877	380	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
ganlikun	0:13413ea9a877	381	* @arg @ref LL_SPI_PROTOCOL_TI
ganlikun	0:13413ea9a877	382	* @retval None
ganlikun	0:13413ea9a877	383	*/
ganlikun	0:13413ea9a877	384	__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
ganlikun	0:13413ea9a877	385	{
ganlikun	0:13413ea9a877	386	MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
ganlikun	0:13413ea9a877	387	}
ganlikun	0:13413ea9a877	388
ganlikun	0:13413ea9a877	389	/**
ganlikun	0:13413ea9a877	390	* @brief Get serial protocol used
ganlikun	0:13413ea9a877	391	* @rmtoll CR2 FRF LL_SPI_GetStandard
ganlikun	0:13413ea9a877	392	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	393	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	394	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
ganlikun	0:13413ea9a877	395	* @arg @ref LL_SPI_PROTOCOL_TI
ganlikun	0:13413ea9a877	396	*/
ganlikun	0:13413ea9a877	397	__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	398	{
ganlikun	0:13413ea9a877	399	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
ganlikun	0:13413ea9a877	400	}
ganlikun	0:13413ea9a877	401
ganlikun	0:13413ea9a877	402	/**
ganlikun	0:13413ea9a877	403	* @brief Set clock phase
ganlikun	0:13413ea9a877	404	* @note This bit should not be changed when communication is ongoing.
ganlikun	0:13413ea9a877	405	* This bit is not used in SPI TI mode.
ganlikun	0:13413ea9a877	406	* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
ganlikun	0:13413ea9a877	407	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	408	* @param ClockPhase This parameter can be one of the following values:
ganlikun	0:13413ea9a877	409	* @arg @ref LL_SPI_PHASE_1EDGE
ganlikun	0:13413ea9a877	410	* @arg @ref LL_SPI_PHASE_2EDGE
ganlikun	0:13413ea9a877	411	* @retval None
ganlikun	0:13413ea9a877	412	*/
ganlikun	0:13413ea9a877	413	__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
ganlikun	0:13413ea9a877	414	{
ganlikun	0:13413ea9a877	415	MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
ganlikun	0:13413ea9a877	416	}
ganlikun	0:13413ea9a877	417
ganlikun	0:13413ea9a877	418	/**
ganlikun	0:13413ea9a877	419	* @brief Get clock phase
ganlikun	0:13413ea9a877	420	* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
ganlikun	0:13413ea9a877	421	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	422	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	423	* @arg @ref LL_SPI_PHASE_1EDGE
ganlikun	0:13413ea9a877	424	* @arg @ref LL_SPI_PHASE_2EDGE
ganlikun	0:13413ea9a877	425	*/
ganlikun	0:13413ea9a877	426	__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	427	{
ganlikun	0:13413ea9a877	428	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
ganlikun	0:13413ea9a877	429	}
ganlikun	0:13413ea9a877	430
ganlikun	0:13413ea9a877	431	/**
ganlikun	0:13413ea9a877	432	* @brief Set clock polarity
ganlikun	0:13413ea9a877	433	* @note This bit should not be changed when communication is ongoing.
ganlikun	0:13413ea9a877	434	* This bit is not used in SPI TI mode.
ganlikun	0:13413ea9a877	435	* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
ganlikun	0:13413ea9a877	436	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	437	* @param ClockPolarity This parameter can be one of the following values:
ganlikun	0:13413ea9a877	438	* @arg @ref LL_SPI_POLARITY_LOW
ganlikun	0:13413ea9a877	439	* @arg @ref LL_SPI_POLARITY_HIGH
ganlikun	0:13413ea9a877	440	* @retval None
ganlikun	0:13413ea9a877	441	*/
ganlikun	0:13413ea9a877	442	__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
ganlikun	0:13413ea9a877	443	{
ganlikun	0:13413ea9a877	444	MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
ganlikun	0:13413ea9a877	445	}
ganlikun	0:13413ea9a877	446
ganlikun	0:13413ea9a877	447	/**
ganlikun	0:13413ea9a877	448	* @brief Get clock polarity
ganlikun	0:13413ea9a877	449	* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
ganlikun	0:13413ea9a877	450	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	451	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	452	* @arg @ref LL_SPI_POLARITY_LOW
ganlikun	0:13413ea9a877	453	* @arg @ref LL_SPI_POLARITY_HIGH
ganlikun	0:13413ea9a877	454	*/
ganlikun	0:13413ea9a877	455	__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	456	{
ganlikun	0:13413ea9a877	457	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
ganlikun	0:13413ea9a877	458	}
ganlikun	0:13413ea9a877	459
ganlikun	0:13413ea9a877	460	/**
ganlikun	0:13413ea9a877	461	* @brief Set baud rate prescaler
ganlikun	0:13413ea9a877	462	* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
ganlikun	0:13413ea9a877	463	* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
ganlikun	0:13413ea9a877	464	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	465	* @param BaudRate This parameter can be one of the following values:
ganlikun	0:13413ea9a877	466	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
ganlikun	0:13413ea9a877	467	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
ganlikun	0:13413ea9a877	468	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
ganlikun	0:13413ea9a877	469	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
ganlikun	0:13413ea9a877	470	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
ganlikun	0:13413ea9a877	471	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
ganlikun	0:13413ea9a877	472	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
ganlikun	0:13413ea9a877	473	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
ganlikun	0:13413ea9a877	474	* @retval None
ganlikun	0:13413ea9a877	475	*/
ganlikun	0:13413ea9a877	476	__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
ganlikun	0:13413ea9a877	477	{
ganlikun	0:13413ea9a877	478	MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
ganlikun	0:13413ea9a877	479	}
ganlikun	0:13413ea9a877	480
ganlikun	0:13413ea9a877	481	/**
ganlikun	0:13413ea9a877	482	* @brief Get baud rate prescaler
ganlikun	0:13413ea9a877	483	* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
ganlikun	0:13413ea9a877	484	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	485	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	486	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
ganlikun	0:13413ea9a877	487	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
ganlikun	0:13413ea9a877	488	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
ganlikun	0:13413ea9a877	489	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
ganlikun	0:13413ea9a877	490	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
ganlikun	0:13413ea9a877	491	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
ganlikun	0:13413ea9a877	492	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
ganlikun	0:13413ea9a877	493	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
ganlikun	0:13413ea9a877	494	*/
ganlikun	0:13413ea9a877	495	__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	496	{
ganlikun	0:13413ea9a877	497	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
ganlikun	0:13413ea9a877	498	}
ganlikun	0:13413ea9a877	499
ganlikun	0:13413ea9a877	500	/**
ganlikun	0:13413ea9a877	501	* @brief Set transfer bit order
ganlikun	0:13413ea9a877	502	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
ganlikun	0:13413ea9a877	503	* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
ganlikun	0:13413ea9a877	504	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	505	* @param BitOrder This parameter can be one of the following values:
ganlikun	0:13413ea9a877	506	* @arg @ref LL_SPI_LSB_FIRST
ganlikun	0:13413ea9a877	507	* @arg @ref LL_SPI_MSB_FIRST
ganlikun	0:13413ea9a877	508	* @retval None
ganlikun	0:13413ea9a877	509	*/
ganlikun	0:13413ea9a877	510	__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
ganlikun	0:13413ea9a877	511	{
ganlikun	0:13413ea9a877	512	MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
ganlikun	0:13413ea9a877	513	}
ganlikun	0:13413ea9a877	514
ganlikun	0:13413ea9a877	515	/**
ganlikun	0:13413ea9a877	516	* @brief Get transfer bit order
ganlikun	0:13413ea9a877	517	* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
ganlikun	0:13413ea9a877	518	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	519	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	520	* @arg @ref LL_SPI_LSB_FIRST
ganlikun	0:13413ea9a877	521	* @arg @ref LL_SPI_MSB_FIRST
ganlikun	0:13413ea9a877	522	*/
ganlikun	0:13413ea9a877	523	__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	524	{
ganlikun	0:13413ea9a877	525	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
ganlikun	0:13413ea9a877	526	}
ganlikun	0:13413ea9a877	527
ganlikun	0:13413ea9a877	528	/**
ganlikun	0:13413ea9a877	529	* @brief Set transfer direction mode
ganlikun	0:13413ea9a877	530	* @note For Half-Duplex mode, Rx Direction is set by default.
ganlikun	0:13413ea9a877	531	* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
ganlikun	0:13413ea9a877	532	* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
ganlikun	0:13413ea9a877	533	* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
ganlikun	0:13413ea9a877	534	* CR1 BIDIOE LL_SPI_SetTransferDirection
ganlikun	0:13413ea9a877	535	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	536	* @param TransferDirection This parameter can be one of the following values:
ganlikun	0:13413ea9a877	537	* @arg @ref LL_SPI_FULL_DUPLEX
ganlikun	0:13413ea9a877	538	* @arg @ref LL_SPI_SIMPLEX_RX
ganlikun	0:13413ea9a877	539	* @arg @ref LL_SPI_HALF_DUPLEX_RX
ganlikun	0:13413ea9a877	540	* @arg @ref LL_SPI_HALF_DUPLEX_TX
ganlikun	0:13413ea9a877	541	* @retval None
ganlikun	0:13413ea9a877	542	*/
ganlikun	0:13413ea9a877	543	__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
ganlikun	0:13413ea9a877	544	{
ganlikun	0:13413ea9a877	545	MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE, TransferDirection);
ganlikun	0:13413ea9a877	546	}
ganlikun	0:13413ea9a877	547
ganlikun	0:13413ea9a877	548	/**
ganlikun	0:13413ea9a877	549	* @brief Get transfer direction mode
ganlikun	0:13413ea9a877	550	* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
ganlikun	0:13413ea9a877	551	* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
ganlikun	0:13413ea9a877	552	* CR1 BIDIOE LL_SPI_GetTransferDirection
ganlikun	0:13413ea9a877	553	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	554	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	555	* @arg @ref LL_SPI_FULL_DUPLEX
ganlikun	0:13413ea9a877	556	* @arg @ref LL_SPI_SIMPLEX_RX
ganlikun	0:13413ea9a877	557	* @arg @ref LL_SPI_HALF_DUPLEX_RX
ganlikun	0:13413ea9a877	558	* @arg @ref LL_SPI_HALF_DUPLEX_TX
ganlikun	0:13413ea9a877	559	*/
ganlikun	0:13413ea9a877	560	__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	561	{
ganlikun	0:13413ea9a877	562	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE));
ganlikun	0:13413ea9a877	563	}
ganlikun	0:13413ea9a877	564
ganlikun	0:13413ea9a877	565	/**
ganlikun	0:13413ea9a877	566	* @brief Set frame data width
ganlikun	0:13413ea9a877	567	* @rmtoll CR1 DFF LL_SPI_SetDataWidth
ganlikun	0:13413ea9a877	568	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	569	* @param DataWidth This parameter can be one of the following values:
ganlikun	0:13413ea9a877	570	* @arg @ref LL_SPI_DATAWIDTH_8BIT
ganlikun	0:13413ea9a877	571	* @arg @ref LL_SPI_DATAWIDTH_16BIT
ganlikun	0:13413ea9a877	572	* @retval None
ganlikun	0:13413ea9a877	573	*/
ganlikun	0:13413ea9a877	574	__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
ganlikun	0:13413ea9a877	575	{
ganlikun	0:13413ea9a877	576	MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
ganlikun	0:13413ea9a877	577	}
ganlikun	0:13413ea9a877	578
ganlikun	0:13413ea9a877	579	/**
ganlikun	0:13413ea9a877	580	* @brief Get frame data width
ganlikun	0:13413ea9a877	581	* @rmtoll CR1 DFF LL_SPI_GetDataWidth
ganlikun	0:13413ea9a877	582	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	583	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	584	* @arg @ref LL_SPI_DATAWIDTH_8BIT
ganlikun	0:13413ea9a877	585	* @arg @ref LL_SPI_DATAWIDTH_16BIT
ganlikun	0:13413ea9a877	586	*/
ganlikun	0:13413ea9a877	587	__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	588	{
ganlikun	0:13413ea9a877	589	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
ganlikun	0:13413ea9a877	590	}
ganlikun	0:13413ea9a877	591
ganlikun	0:13413ea9a877	592	/**
ganlikun	0:13413ea9a877	593	* @}
ganlikun	0:13413ea9a877	594	*/
ganlikun	0:13413ea9a877	595
ganlikun	0:13413ea9a877	596	/** @defgroup SPI_LL_EF_CRC_Management CRC Management
ganlikun	0:13413ea9a877	597	* @{
ganlikun	0:13413ea9a877	598	*/
ganlikun	0:13413ea9a877	599
ganlikun	0:13413ea9a877	600	/**
ganlikun	0:13413ea9a877	601	* @brief Enable CRC
ganlikun	0:13413ea9a877	602	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
ganlikun	0:13413ea9a877	603	* @rmtoll CR1 CRCEN LL_SPI_EnableCRC
ganlikun	0:13413ea9a877	604	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	605	* @retval None
ganlikun	0:13413ea9a877	606	*/
ganlikun	0:13413ea9a877	607	__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	608	{
ganlikun	0:13413ea9a877	609	SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
ganlikun	0:13413ea9a877	610	}
ganlikun	0:13413ea9a877	611
ganlikun	0:13413ea9a877	612	/**
ganlikun	0:13413ea9a877	613	* @brief Disable CRC
ganlikun	0:13413ea9a877	614	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
ganlikun	0:13413ea9a877	615	* @rmtoll CR1 CRCEN LL_SPI_DisableCRC
ganlikun	0:13413ea9a877	616	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	617	* @retval None
ganlikun	0:13413ea9a877	618	*/
ganlikun	0:13413ea9a877	619	__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	620	{
ganlikun	0:13413ea9a877	621	CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
ganlikun	0:13413ea9a877	622	}
ganlikun	0:13413ea9a877	623
ganlikun	0:13413ea9a877	624	/**
ganlikun	0:13413ea9a877	625	* @brief Check if CRC is enabled
ganlikun	0:13413ea9a877	626	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
ganlikun	0:13413ea9a877	627	* @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
ganlikun	0:13413ea9a877	628	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	629	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	630	*/
ganlikun	0:13413ea9a877	631	__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	632	{
ganlikun	0:13413ea9a877	633	return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
ganlikun	0:13413ea9a877	634	}
ganlikun	0:13413ea9a877	635
ganlikun	0:13413ea9a877	636	/**
ganlikun	0:13413ea9a877	637	* @brief Set CRCNext to transfer CRC on the line
ganlikun	0:13413ea9a877	638	* @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
ganlikun	0:13413ea9a877	639	* @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
ganlikun	0:13413ea9a877	640	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	641	* @retval None
ganlikun	0:13413ea9a877	642	*/
ganlikun	0:13413ea9a877	643	__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	644	{
ganlikun	0:13413ea9a877	645	SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
ganlikun	0:13413ea9a877	646	}
ganlikun	0:13413ea9a877	647
ganlikun	0:13413ea9a877	648	/**
ganlikun	0:13413ea9a877	649	* @brief Set polynomial for CRC calculation
ganlikun	0:13413ea9a877	650	* @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
ganlikun	0:13413ea9a877	651	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	652	* @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
ganlikun	0:13413ea9a877	653	* @retval None
ganlikun	0:13413ea9a877	654	*/
ganlikun	0:13413ea9a877	655	__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
ganlikun	0:13413ea9a877	656	{
ganlikun	0:13413ea9a877	657	WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
ganlikun	0:13413ea9a877	658	}
ganlikun	0:13413ea9a877	659
ganlikun	0:13413ea9a877	660	/**
ganlikun	0:13413ea9a877	661	* @brief Get polynomial for CRC calculation
ganlikun	0:13413ea9a877	662	* @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
ganlikun	0:13413ea9a877	663	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	664	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
ganlikun	0:13413ea9a877	665	*/
ganlikun	0:13413ea9a877	666	__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	667	{
ganlikun	0:13413ea9a877	668	return (uint32_t)(READ_REG(SPIx->CRCPR));
ganlikun	0:13413ea9a877	669	}
ganlikun	0:13413ea9a877	670
ganlikun	0:13413ea9a877	671	/**
ganlikun	0:13413ea9a877	672	* @brief Get Rx CRC
ganlikun	0:13413ea9a877	673	* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
ganlikun	0:13413ea9a877	674	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	675	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
ganlikun	0:13413ea9a877	676	*/
ganlikun	0:13413ea9a877	677	__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	678	{
ganlikun	0:13413ea9a877	679	return (uint32_t)(READ_REG(SPIx->RXCRCR));
ganlikun	0:13413ea9a877	680	}
ganlikun	0:13413ea9a877	681
ganlikun	0:13413ea9a877	682	/**
ganlikun	0:13413ea9a877	683	* @brief Get Tx CRC
ganlikun	0:13413ea9a877	684	* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
ganlikun	0:13413ea9a877	685	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	686	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
ganlikun	0:13413ea9a877	687	*/
ganlikun	0:13413ea9a877	688	__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	689	{
ganlikun	0:13413ea9a877	690	return (uint32_t)(READ_REG(SPIx->TXCRCR));
ganlikun	0:13413ea9a877	691	}
ganlikun	0:13413ea9a877	692
ganlikun	0:13413ea9a877	693	/**
ganlikun	0:13413ea9a877	694	* @}
ganlikun	0:13413ea9a877	695	*/
ganlikun	0:13413ea9a877	696
ganlikun	0:13413ea9a877	697	/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
ganlikun	0:13413ea9a877	698	* @{
ganlikun	0:13413ea9a877	699	*/
ganlikun	0:13413ea9a877	700
ganlikun	0:13413ea9a877	701	/**
ganlikun	0:13413ea9a877	702	* @brief Set NSS mode
ganlikun	0:13413ea9a877	703	* @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
ganlikun	0:13413ea9a877	704	* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
ganlikun	0:13413ea9a877	705	* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
ganlikun	0:13413ea9a877	706	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	707	* @param NSS This parameter can be one of the following values:
ganlikun	0:13413ea9a877	708	* @arg @ref LL_SPI_NSS_SOFT
ganlikun	0:13413ea9a877	709	* @arg @ref LL_SPI_NSS_HARD_INPUT
ganlikun	0:13413ea9a877	710	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
ganlikun	0:13413ea9a877	711	* @retval None
ganlikun	0:13413ea9a877	712	*/
ganlikun	0:13413ea9a877	713	__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
ganlikun	0:13413ea9a877	714	{
ganlikun	0:13413ea9a877	715	MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
ganlikun	0:13413ea9a877	716	MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
ganlikun	0:13413ea9a877	717	}
ganlikun	0:13413ea9a877	718
ganlikun	0:13413ea9a877	719	/**
ganlikun	0:13413ea9a877	720	* @brief Get NSS mode
ganlikun	0:13413ea9a877	721	* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
ganlikun	0:13413ea9a877	722	* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
ganlikun	0:13413ea9a877	723	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	724	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	725	* @arg @ref LL_SPI_NSS_SOFT
ganlikun	0:13413ea9a877	726	* @arg @ref LL_SPI_NSS_HARD_INPUT
ganlikun	0:13413ea9a877	727	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
ganlikun	0:13413ea9a877	728	*/
ganlikun	0:13413ea9a877	729	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	730	{
ganlikun	0:13413ea9a877	731	register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
ganlikun	0:13413ea9a877	732	register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
ganlikun	0:13413ea9a877	733	return (Ssm \| Ssoe);
ganlikun	0:13413ea9a877	734	}
ganlikun	0:13413ea9a877	735
ganlikun	0:13413ea9a877	736	/**
ganlikun	0:13413ea9a877	737	* @}
ganlikun	0:13413ea9a877	738	*/
ganlikun	0:13413ea9a877	739
ganlikun	0:13413ea9a877	740	/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
ganlikun	0:13413ea9a877	741	* @{
ganlikun	0:13413ea9a877	742	*/
ganlikun	0:13413ea9a877	743
ganlikun	0:13413ea9a877	744	/**
ganlikun	0:13413ea9a877	745	* @brief Check if Rx buffer is not empty
ganlikun	0:13413ea9a877	746	* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
ganlikun	0:13413ea9a877	747	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	748	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	749	*/
ganlikun	0:13413ea9a877	750	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	751	{
ganlikun	0:13413ea9a877	752	return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
ganlikun	0:13413ea9a877	753	}
ganlikun	0:13413ea9a877	754
ganlikun	0:13413ea9a877	755	/**
ganlikun	0:13413ea9a877	756	* @brief Check if Tx buffer is empty
ganlikun	0:13413ea9a877	757	* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
ganlikun	0:13413ea9a877	758	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	759	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	760	*/
ganlikun	0:13413ea9a877	761	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	762	{
ganlikun	0:13413ea9a877	763	return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
ganlikun	0:13413ea9a877	764	}
ganlikun	0:13413ea9a877	765
ganlikun	0:13413ea9a877	766	/**
ganlikun	0:13413ea9a877	767	* @brief Get CRC error flag
ganlikun	0:13413ea9a877	768	* @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
ganlikun	0:13413ea9a877	769	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	770	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	771	*/
ganlikun	0:13413ea9a877	772	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	773	{
ganlikun	0:13413ea9a877	774	return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
ganlikun	0:13413ea9a877	775	}
ganlikun	0:13413ea9a877	776
ganlikun	0:13413ea9a877	777	/**
ganlikun	0:13413ea9a877	778	* @brief Get mode fault error flag
ganlikun	0:13413ea9a877	779	* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
ganlikun	0:13413ea9a877	780	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	781	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	782	*/
ganlikun	0:13413ea9a877	783	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	784	{
ganlikun	0:13413ea9a877	785	return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
ganlikun	0:13413ea9a877	786	}
ganlikun	0:13413ea9a877	787
ganlikun	0:13413ea9a877	788	/**
ganlikun	0:13413ea9a877	789	* @brief Get overrun error flag
ganlikun	0:13413ea9a877	790	* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
ganlikun	0:13413ea9a877	791	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	792	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	793	*/
ganlikun	0:13413ea9a877	794	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	795	{
ganlikun	0:13413ea9a877	796	return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
ganlikun	0:13413ea9a877	797	}
ganlikun	0:13413ea9a877	798
ganlikun	0:13413ea9a877	799	/**
ganlikun	0:13413ea9a877	800	* @brief Get busy flag
ganlikun	0:13413ea9a877	801	* @note The BSY flag is cleared under any one of the following conditions:
ganlikun	0:13413ea9a877	802	* -When the SPI is correctly disabled
ganlikun	0:13413ea9a877	803	* -When a fault is detected in Master mode (MODF bit set to 1)
ganlikun	0:13413ea9a877	804	* -In Master mode, when it finishes a data transmission and no new data is ready to be
ganlikun	0:13413ea9a877	805	* sent
ganlikun	0:13413ea9a877	806	* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
ganlikun	0:13413ea9a877	807	* each data transfer.
ganlikun	0:13413ea9a877	808	* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
ganlikun	0:13413ea9a877	809	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	810	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	811	*/
ganlikun	0:13413ea9a877	812	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	813	{
ganlikun	0:13413ea9a877	814	return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
ganlikun	0:13413ea9a877	815	}
ganlikun	0:13413ea9a877	816
ganlikun	0:13413ea9a877	817	/**
ganlikun	0:13413ea9a877	818	* @brief Get frame format error flag
ganlikun	0:13413ea9a877	819	* @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
ganlikun	0:13413ea9a877	820	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	821	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	822	*/
ganlikun	0:13413ea9a877	823	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	824	{
ganlikun	0:13413ea9a877	825	return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
ganlikun	0:13413ea9a877	826	}
ganlikun	0:13413ea9a877	827
ganlikun	0:13413ea9a877	828	/**
ganlikun	0:13413ea9a877	829	* @brief Clear CRC error flag
ganlikun	0:13413ea9a877	830	* @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
ganlikun	0:13413ea9a877	831	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	832	* @retval None
ganlikun	0:13413ea9a877	833	*/
ganlikun	0:13413ea9a877	834	__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	835	{
ganlikun	0:13413ea9a877	836	CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
ganlikun	0:13413ea9a877	837	}
ganlikun	0:13413ea9a877	838
ganlikun	0:13413ea9a877	839	/**
ganlikun	0:13413ea9a877	840	* @brief Clear mode fault error flag
ganlikun	0:13413ea9a877	841	* @note Clearing this flag is done by a read access to the SPIx_SR
ganlikun	0:13413ea9a877	842	* register followed by a write access to the SPIx_CR1 register
ganlikun	0:13413ea9a877	843	* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
ganlikun	0:13413ea9a877	844	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	845	* @retval None
ganlikun	0:13413ea9a877	846	*/
ganlikun	0:13413ea9a877	847	__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	848	{
ganlikun	0:13413ea9a877	849	__IO uint32_t tmpreg;
ganlikun	0:13413ea9a877	850	tmpreg = SPIx->SR;
ganlikun	0:13413ea9a877	851	(void) tmpreg;
ganlikun	0:13413ea9a877	852	tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
ganlikun	0:13413ea9a877	853	(void) tmpreg;
ganlikun	0:13413ea9a877	854	}
ganlikun	0:13413ea9a877	855
ganlikun	0:13413ea9a877	856	/**
ganlikun	0:13413ea9a877	857	* @brief Clear overrun error flag
ganlikun	0:13413ea9a877	858	* @note Clearing this flag is done by a read access to the SPIx_DR
ganlikun	0:13413ea9a877	859	* register followed by a read access to the SPIx_SR register
ganlikun	0:13413ea9a877	860	* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
ganlikun	0:13413ea9a877	861	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	862	* @retval None
ganlikun	0:13413ea9a877	863	*/
ganlikun	0:13413ea9a877	864	__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	865	{
ganlikun	0:13413ea9a877	866	__IO uint32_t tmpreg;
ganlikun	0:13413ea9a877	867	tmpreg = SPIx->DR;
ganlikun	0:13413ea9a877	868	(void) tmpreg;
ganlikun	0:13413ea9a877	869	tmpreg = SPIx->SR;
ganlikun	0:13413ea9a877	870	(void) tmpreg;
ganlikun	0:13413ea9a877	871	}
ganlikun	0:13413ea9a877	872
ganlikun	0:13413ea9a877	873	/**
ganlikun	0:13413ea9a877	874	* @brief Clear frame format error flag
ganlikun	0:13413ea9a877	875	* @note Clearing this flag is done by reading SPIx_SR register
ganlikun	0:13413ea9a877	876	* @rmtoll SR FRE LL_SPI_ClearFlag_FRE
ganlikun	0:13413ea9a877	877	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	878	* @retval None
ganlikun	0:13413ea9a877	879	*/
ganlikun	0:13413ea9a877	880	__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	881	{
ganlikun	0:13413ea9a877	882	__IO uint32_t tmpreg;
ganlikun	0:13413ea9a877	883	tmpreg = SPIx->SR;
ganlikun	0:13413ea9a877	884	(void) tmpreg;
ganlikun	0:13413ea9a877	885	}
ganlikun	0:13413ea9a877	886
ganlikun	0:13413ea9a877	887	/**
ganlikun	0:13413ea9a877	888	* @}
ganlikun	0:13413ea9a877	889	*/
ganlikun	0:13413ea9a877	890
ganlikun	0:13413ea9a877	891	/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
ganlikun	0:13413ea9a877	892	* @{
ganlikun	0:13413ea9a877	893	*/
ganlikun	0:13413ea9a877	894
ganlikun	0:13413ea9a877	895	/**
ganlikun	0:13413ea9a877	896	* @brief Enable error interrupt
ganlikun	0:13413ea9a877	897	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
ganlikun	0:13413ea9a877	898	* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
ganlikun	0:13413ea9a877	899	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	900	* @retval None
ganlikun	0:13413ea9a877	901	*/
ganlikun	0:13413ea9a877	902	__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	903	{
ganlikun	0:13413ea9a877	904	SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
ganlikun	0:13413ea9a877	905	}
ganlikun	0:13413ea9a877	906
ganlikun	0:13413ea9a877	907	/**
ganlikun	0:13413ea9a877	908	* @brief Enable Rx buffer not empty interrupt
ganlikun	0:13413ea9a877	909	* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
ganlikun	0:13413ea9a877	910	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	911	* @retval None
ganlikun	0:13413ea9a877	912	*/
ganlikun	0:13413ea9a877	913	__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	914	{
ganlikun	0:13413ea9a877	915	SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
ganlikun	0:13413ea9a877	916	}
ganlikun	0:13413ea9a877	917
ganlikun	0:13413ea9a877	918	/**
ganlikun	0:13413ea9a877	919	* @brief Enable Tx buffer empty interrupt
ganlikun	0:13413ea9a877	920	* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
ganlikun	0:13413ea9a877	921	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	922	* @retval None
ganlikun	0:13413ea9a877	923	*/
ganlikun	0:13413ea9a877	924	__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	925	{
ganlikun	0:13413ea9a877	926	SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
ganlikun	0:13413ea9a877	927	}
ganlikun	0:13413ea9a877	928
ganlikun	0:13413ea9a877	929	/**
ganlikun	0:13413ea9a877	930	* @brief Disable error interrupt
ganlikun	0:13413ea9a877	931	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
ganlikun	0:13413ea9a877	932	* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
ganlikun	0:13413ea9a877	933	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	934	* @retval None
ganlikun	0:13413ea9a877	935	*/
ganlikun	0:13413ea9a877	936	__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	937	{
ganlikun	0:13413ea9a877	938	CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
ganlikun	0:13413ea9a877	939	}
ganlikun	0:13413ea9a877	940
ganlikun	0:13413ea9a877	941	/**
ganlikun	0:13413ea9a877	942	* @brief Disable Rx buffer not empty interrupt
ganlikun	0:13413ea9a877	943	* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
ganlikun	0:13413ea9a877	944	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	945	* @retval None
ganlikun	0:13413ea9a877	946	*/
ganlikun	0:13413ea9a877	947	__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	948	{
ganlikun	0:13413ea9a877	949	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
ganlikun	0:13413ea9a877	950	}
ganlikun	0:13413ea9a877	951
ganlikun	0:13413ea9a877	952	/**
ganlikun	0:13413ea9a877	953	* @brief Disable Tx buffer empty interrupt
ganlikun	0:13413ea9a877	954	* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
ganlikun	0:13413ea9a877	955	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	956	* @retval None
ganlikun	0:13413ea9a877	957	*/
ganlikun	0:13413ea9a877	958	__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	959	{
ganlikun	0:13413ea9a877	960	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
ganlikun	0:13413ea9a877	961	}
ganlikun	0:13413ea9a877	962
ganlikun	0:13413ea9a877	963	/**
ganlikun	0:13413ea9a877	964	* @brief Check if error interrupt is enabled
ganlikun	0:13413ea9a877	965	* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
ganlikun	0:13413ea9a877	966	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	967	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	968	*/
ganlikun	0:13413ea9a877	969	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	970	{
ganlikun	0:13413ea9a877	971	return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
ganlikun	0:13413ea9a877	972	}
ganlikun	0:13413ea9a877	973
ganlikun	0:13413ea9a877	974	/**
ganlikun	0:13413ea9a877	975	* @brief Check if Rx buffer not empty interrupt is enabled
ganlikun	0:13413ea9a877	976	* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
ganlikun	0:13413ea9a877	977	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	978	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	979	*/
ganlikun	0:13413ea9a877	980	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	981	{
ganlikun	0:13413ea9a877	982	return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
ganlikun	0:13413ea9a877	983	}
ganlikun	0:13413ea9a877	984
ganlikun	0:13413ea9a877	985	/**
ganlikun	0:13413ea9a877	986	* @brief Check if Tx buffer empty interrupt
ganlikun	0:13413ea9a877	987	* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
ganlikun	0:13413ea9a877	988	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	989	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	990	*/
ganlikun	0:13413ea9a877	991	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	992	{
ganlikun	0:13413ea9a877	993	return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
ganlikun	0:13413ea9a877	994	}
ganlikun	0:13413ea9a877	995
ganlikun	0:13413ea9a877	996	/**
ganlikun	0:13413ea9a877	997	* @}
ganlikun	0:13413ea9a877	998	*/
ganlikun	0:13413ea9a877	999
ganlikun	0:13413ea9a877	1000	/** @defgroup SPI_LL_EF_DMA_Management DMA Management
ganlikun	0:13413ea9a877	1001	* @{
ganlikun	0:13413ea9a877	1002	*/
ganlikun	0:13413ea9a877	1003
ganlikun	0:13413ea9a877	1004	/**
ganlikun	0:13413ea9a877	1005	* @brief Enable DMA Rx
ganlikun	0:13413ea9a877	1006	* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
ganlikun	0:13413ea9a877	1007	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1008	* @retval None
ganlikun	0:13413ea9a877	1009	*/
ganlikun	0:13413ea9a877	1010	__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1011	{
ganlikun	0:13413ea9a877	1012	SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
ganlikun	0:13413ea9a877	1013	}
ganlikun	0:13413ea9a877	1014
ganlikun	0:13413ea9a877	1015	/**
ganlikun	0:13413ea9a877	1016	* @brief Disable DMA Rx
ganlikun	0:13413ea9a877	1017	* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
ganlikun	0:13413ea9a877	1018	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1019	* @retval None
ganlikun	0:13413ea9a877	1020	*/
ganlikun	0:13413ea9a877	1021	__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1022	{
ganlikun	0:13413ea9a877	1023	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
ganlikun	0:13413ea9a877	1024	}
ganlikun	0:13413ea9a877	1025
ganlikun	0:13413ea9a877	1026	/**
ganlikun	0:13413ea9a877	1027	* @brief Check if DMA Rx is enabled
ganlikun	0:13413ea9a877	1028	* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
ganlikun	0:13413ea9a877	1029	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1030	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1031	*/
ganlikun	0:13413ea9a877	1032	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1033	{
ganlikun	0:13413ea9a877	1034	return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
ganlikun	0:13413ea9a877	1035	}
ganlikun	0:13413ea9a877	1036
ganlikun	0:13413ea9a877	1037	/**
ganlikun	0:13413ea9a877	1038	* @brief Enable DMA Tx
ganlikun	0:13413ea9a877	1039	* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
ganlikun	0:13413ea9a877	1040	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1041	* @retval None
ganlikun	0:13413ea9a877	1042	*/
ganlikun	0:13413ea9a877	1043	__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1044	{
ganlikun	0:13413ea9a877	1045	SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
ganlikun	0:13413ea9a877	1046	}
ganlikun	0:13413ea9a877	1047
ganlikun	0:13413ea9a877	1048	/**
ganlikun	0:13413ea9a877	1049	* @brief Disable DMA Tx
ganlikun	0:13413ea9a877	1050	* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
ganlikun	0:13413ea9a877	1051	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1052	* @retval None
ganlikun	0:13413ea9a877	1053	*/
ganlikun	0:13413ea9a877	1054	__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1055	{
ganlikun	0:13413ea9a877	1056	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
ganlikun	0:13413ea9a877	1057	}
ganlikun	0:13413ea9a877	1058
ganlikun	0:13413ea9a877	1059	/**
ganlikun	0:13413ea9a877	1060	* @brief Check if DMA Tx is enabled
ganlikun	0:13413ea9a877	1061	* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
ganlikun	0:13413ea9a877	1062	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1063	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1064	*/
ganlikun	0:13413ea9a877	1065	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1066	{
ganlikun	0:13413ea9a877	1067	return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
ganlikun	0:13413ea9a877	1068	}
ganlikun	0:13413ea9a877	1069
ganlikun	0:13413ea9a877	1070	/**
ganlikun	0:13413ea9a877	1071	* @brief Get the data register address used for DMA transfer
ganlikun	0:13413ea9a877	1072	* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
ganlikun	0:13413ea9a877	1073	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1074	* @retval Address of data register
ganlikun	0:13413ea9a877	1075	*/
ganlikun	0:13413ea9a877	1076	__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1077	{
ganlikun	0:13413ea9a877	1078	return (uint32_t) & (SPIx->DR);
ganlikun	0:13413ea9a877	1079	}
ganlikun	0:13413ea9a877	1080
ganlikun	0:13413ea9a877	1081	/**
ganlikun	0:13413ea9a877	1082	* @}
ganlikun	0:13413ea9a877	1083	*/
ganlikun	0:13413ea9a877	1084
ganlikun	0:13413ea9a877	1085	/** @defgroup SPI_LL_EF_DATA_Management DATA Management
ganlikun	0:13413ea9a877	1086	* @{
ganlikun	0:13413ea9a877	1087	*/
ganlikun	0:13413ea9a877	1088
ganlikun	0:13413ea9a877	1089	/**
ganlikun	0:13413ea9a877	1090	* @brief Read 8-Bits in the data register
ganlikun	0:13413ea9a877	1091	* @rmtoll DR DR LL_SPI_ReceiveData8
ganlikun	0:13413ea9a877	1092	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1093	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
ganlikun	0:13413ea9a877	1094	*/
ganlikun	0:13413ea9a877	1095	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1096	{
ganlikun	0:13413ea9a877	1097	return (uint8_t)(READ_REG(SPIx->DR));
ganlikun	0:13413ea9a877	1098	}
ganlikun	0:13413ea9a877	1099
ganlikun	0:13413ea9a877	1100	/**
ganlikun	0:13413ea9a877	1101	* @brief Read 16-Bits in the data register
ganlikun	0:13413ea9a877	1102	* @rmtoll DR DR LL_SPI_ReceiveData16
ganlikun	0:13413ea9a877	1103	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1104	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
ganlikun	0:13413ea9a877	1105	*/
ganlikun	0:13413ea9a877	1106	__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1107	{
ganlikun	0:13413ea9a877	1108	return (uint16_t)(READ_REG(SPIx->DR));
ganlikun	0:13413ea9a877	1109	}
ganlikun	0:13413ea9a877	1110
ganlikun	0:13413ea9a877	1111	/**
ganlikun	0:13413ea9a877	1112	* @brief Write 8-Bits in the data register
ganlikun	0:13413ea9a877	1113	* @rmtoll DR DR LL_SPI_TransmitData8
ganlikun	0:13413ea9a877	1114	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1115	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
ganlikun	0:13413ea9a877	1116	* @retval None
ganlikun	0:13413ea9a877	1117	*/
ganlikun	0:13413ea9a877	1118	__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
ganlikun	0:13413ea9a877	1119	{
ganlikun	0:13413ea9a877	1120	SPIx->DR = TxData;
ganlikun	0:13413ea9a877	1121	}
ganlikun	0:13413ea9a877	1122
ganlikun	0:13413ea9a877	1123	/**
ganlikun	0:13413ea9a877	1124	* @brief Write 16-Bits in the data register
ganlikun	0:13413ea9a877	1125	* @rmtoll DR DR LL_SPI_TransmitData16
ganlikun	0:13413ea9a877	1126	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1127	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
ganlikun	0:13413ea9a877	1128	* @retval None
ganlikun	0:13413ea9a877	1129	*/
ganlikun	0:13413ea9a877	1130	__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
ganlikun	0:13413ea9a877	1131	{
ganlikun	0:13413ea9a877	1132	SPIx->DR = TxData;
ganlikun	0:13413ea9a877	1133	}
ganlikun	0:13413ea9a877	1134
ganlikun	0:13413ea9a877	1135	/**
ganlikun	0:13413ea9a877	1136	* @}
ganlikun	0:13413ea9a877	1137	*/
ganlikun	0:13413ea9a877	1138	#if defined(USE_FULL_LL_DRIVER)
ganlikun	0:13413ea9a877	1139	/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
ganlikun	0:13413ea9a877	1140	* @{
ganlikun	0:13413ea9a877	1141	*/
ganlikun	0:13413ea9a877	1142
ganlikun	0:13413ea9a877	1143	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
ganlikun	0:13413ea9a877	1144	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct);
ganlikun	0:13413ea9a877	1145	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
ganlikun	0:13413ea9a877	1146
ganlikun	0:13413ea9a877	1147	/**
ganlikun	0:13413ea9a877	1148	* @}
ganlikun	0:13413ea9a877	1149	*/
ganlikun	0:13413ea9a877	1150	#endif /* USE_FULL_LL_DRIVER */
ganlikun	0:13413ea9a877	1151	/**
ganlikun	0:13413ea9a877	1152	* @}
ganlikun	0:13413ea9a877	1153	*/
ganlikun	0:13413ea9a877	1154
ganlikun	0:13413ea9a877	1155	/**
ganlikun	0:13413ea9a877	1156	* @}
ganlikun	0:13413ea9a877	1157	*/
ganlikun	0:13413ea9a877	1158
ganlikun	0:13413ea9a877	1159	/** @defgroup I2S_LL I2S
ganlikun	0:13413ea9a877	1160	* @{
ganlikun	0:13413ea9a877	1161	*/
ganlikun	0:13413ea9a877	1162
ganlikun	0:13413ea9a877	1163	/* Private variables ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	1164	/* Private constants ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	1165	/* Private macros ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	1166
ganlikun	0:13413ea9a877	1167	/* Exported types ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	1168	#if defined(USE_FULL_LL_DRIVER)
ganlikun	0:13413ea9a877	1169	/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
ganlikun	0:13413ea9a877	1170	* @{
ganlikun	0:13413ea9a877	1171	*/
ganlikun	0:13413ea9a877	1172
ganlikun	0:13413ea9a877	1173	/**
ganlikun	0:13413ea9a877	1174	* @brief I2S Init structure definition
ganlikun	0:13413ea9a877	1175	*/
ganlikun	0:13413ea9a877	1176
ganlikun	0:13413ea9a877	1177	typedef struct
ganlikun	0:13413ea9a877	1178	{
ganlikun	0:13413ea9a877	1179	uint32_t Mode; /*!< Specifies the I2S operating mode.
ganlikun	0:13413ea9a877	1180	This parameter can be a value of @ref I2S_LL_EC_MODE
ganlikun	0:13413ea9a877	1181
ganlikun	0:13413ea9a877	1182	This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
ganlikun	0:13413ea9a877	1183
ganlikun	0:13413ea9a877	1184	uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
ganlikun	0:13413ea9a877	1185	This parameter can be a value of @ref I2S_LL_EC_STANDARD
ganlikun	0:13413ea9a877	1186
ganlikun	0:13413ea9a877	1187	This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
ganlikun	0:13413ea9a877	1188
ganlikun	0:13413ea9a877	1189
ganlikun	0:13413ea9a877	1190	uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
ganlikun	0:13413ea9a877	1191	This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
ganlikun	0:13413ea9a877	1192
ganlikun	0:13413ea9a877	1193	This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
ganlikun	0:13413ea9a877	1194
ganlikun	0:13413ea9a877	1195
ganlikun	0:13413ea9a877	1196	uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
ganlikun	0:13413ea9a877	1197	This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
ganlikun	0:13413ea9a877	1198
ganlikun	0:13413ea9a877	1199	This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
ganlikun	0:13413ea9a877	1200
ganlikun	0:13413ea9a877	1201
ganlikun	0:13413ea9a877	1202	uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
ganlikun	0:13413ea9a877	1203	This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
ganlikun	0:13413ea9a877	1204
ganlikun	0:13413ea9a877	1205	Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
ganlikun	0:13413ea9a877	1206	and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
ganlikun	0:13413ea9a877	1207
ganlikun	0:13413ea9a877	1208
ganlikun	0:13413ea9a877	1209	uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
ganlikun	0:13413ea9a877	1210	This parameter can be a value of @ref I2S_LL_EC_POLARITY
ganlikun	0:13413ea9a877	1211
ganlikun	0:13413ea9a877	1212	This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
ganlikun	0:13413ea9a877	1213
ganlikun	0:13413ea9a877	1214	} LL_I2S_InitTypeDef;
ganlikun	0:13413ea9a877	1215
ganlikun	0:13413ea9a877	1216	/**
ganlikun	0:13413ea9a877	1217	* @}
ganlikun	0:13413ea9a877	1218	*/
ganlikun	0:13413ea9a877	1219	#endif /USE_FULL_LL_DRIVER/
ganlikun	0:13413ea9a877	1220
ganlikun	0:13413ea9a877	1221	/* Exported constants --------------------------------------------------------*/
ganlikun	0:13413ea9a877	1222	/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
ganlikun	0:13413ea9a877	1223	* @{
ganlikun	0:13413ea9a877	1224	*/
ganlikun	0:13413ea9a877	1225
ganlikun	0:13413ea9a877	1226	/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
ganlikun	0:13413ea9a877	1227	* @brief Flags defines which can be used with LL_I2S_ReadReg function
ganlikun	0:13413ea9a877	1228	* @{
ganlikun	0:13413ea9a877	1229	*/
ganlikun	0:13413ea9a877	1230	#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /!< Rx buffer not empty flag /
ganlikun	0:13413ea9a877	1231	#define LL_I2S_SR_TXE LL_SPI_SR_TXE /!< Tx buffer empty flag /
ganlikun	0:13413ea9a877	1232	#define LL_I2S_SR_BSY LL_SPI_SR_BSY /!< Busy flag /
ganlikun	0:13413ea9a877	1233	#define LL_I2S_SR_UDR SPI_SR_UDR /!< Underrun flag /
ganlikun	0:13413ea9a877	1234	#define LL_I2S_SR_OVR LL_SPI_SR_OVR /!< Overrun flag /
ganlikun	0:13413ea9a877	1235	#define LL_I2S_SR_FRE LL_SPI_SR_FRE /!< TI mode frame format error flag /
ganlikun	0:13413ea9a877	1236	/**
ganlikun	0:13413ea9a877	1237	* @}
ganlikun	0:13413ea9a877	1238	*/
ganlikun	0:13413ea9a877	1239
ganlikun	0:13413ea9a877	1240	/** @defgroup SPI_LL_EC_IT IT Defines
ganlikun	0:13413ea9a877	1241	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
ganlikun	0:13413ea9a877	1242	* @{
ganlikun	0:13413ea9a877	1243	*/
ganlikun	0:13413ea9a877	1244	#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
ganlikun	0:13413ea9a877	1245	#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
ganlikun	0:13413ea9a877	1246	#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /!< Error interrupt enable /
ganlikun	0:13413ea9a877	1247	/**
ganlikun	0:13413ea9a877	1248	* @}
ganlikun	0:13413ea9a877	1249	*/
ganlikun	0:13413ea9a877	1250
ganlikun	0:13413ea9a877	1251	/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
ganlikun	0:13413ea9a877	1252	* @{
ganlikun	0:13413ea9a877	1253	*/
ganlikun	0:13413ea9a877	1254	#define LL_I2S_DATAFORMAT_16B 0x00000000U /!< Data length 16 bits, Channel lenght 16bit /
ganlikun	0:13413ea9a877	1255	#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /!< Data length 16 bits, Channel lenght 32bit /
ganlikun	0:13413ea9a877	1256	#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_0) /!< Data length 24 bits, Channel lenght 32bit /
ganlikun	0:13413ea9a877	1257	#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_1) /!< Data length 16 bits, Channel lenght 32bit /
ganlikun	0:13413ea9a877	1258	/**
ganlikun	0:13413ea9a877	1259	* @}
ganlikun	0:13413ea9a877	1260	*/
ganlikun	0:13413ea9a877	1261
ganlikun	0:13413ea9a877	1262	/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
ganlikun	0:13413ea9a877	1263	* @{
ganlikun	0:13413ea9a877	1264	*/
ganlikun	0:13413ea9a877	1265	#define LL_I2S_POLARITY_LOW 0x00000000U /!< Clock steady state is low level /
ganlikun	0:13413ea9a877	1266	#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /!< Clock steady state is high level /
ganlikun	0:13413ea9a877	1267	/**
ganlikun	0:13413ea9a877	1268	* @}
ganlikun	0:13413ea9a877	1269	*/
ganlikun	0:13413ea9a877	1270
ganlikun	0:13413ea9a877	1271	/** @defgroup I2S_LL_EC_STANDARD I2s Standard
ganlikun	0:13413ea9a877	1272	* @{
ganlikun	0:13413ea9a877	1273	*/
ganlikun	0:13413ea9a877	1274	#define LL_I2S_STANDARD_PHILIPS 0x00000000U /!< I2S standard philips /
ganlikun	0:13413ea9a877	1275	#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /!< MSB justified standard (left justified) /
ganlikun	0:13413ea9a877	1276	#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /!< LSB justified standard (right justified) /
ganlikun	0:13413ea9a877	1277	#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1) /!< PCM standard, short frame synchronization /
ganlikun	0:13413ea9a877	1278	#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1 \| SPI_I2SCFGR_PCMSYNC) /!< PCM standard, long frame synchronization /
ganlikun	0:13413ea9a877	1279	/**
ganlikun	0:13413ea9a877	1280	* @}
ganlikun	0:13413ea9a877	1281	*/
ganlikun	0:13413ea9a877	1282
ganlikun	0:13413ea9a877	1283	/** @defgroup I2S_LL_EC_MODE Operation Mode
ganlikun	0:13413ea9a877	1284	* @{
ganlikun	0:13413ea9a877	1285	*/
ganlikun	0:13413ea9a877	1286	#define LL_I2S_MODE_SLAVE_TX 0x00000000U /!< Slave Tx configuration /
ganlikun	0:13413ea9a877	1287	#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /!< Slave Rx configuration /
ganlikun	0:13413ea9a877	1288	#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /!< Master Tx configuration /
ganlikun	0:13413ea9a877	1289	#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 \| SPI_I2SCFGR_I2SCFG_1) /!< Master Rx configuration /
ganlikun	0:13413ea9a877	1290	/**
ganlikun	0:13413ea9a877	1291	* @}
ganlikun	0:13413ea9a877	1292	*/
ganlikun	0:13413ea9a877	1293
ganlikun	0:13413ea9a877	1294	/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
ganlikun	0:13413ea9a877	1295	* @{
ganlikun	0:13413ea9a877	1296	*/
ganlikun	0:13413ea9a877	1297	#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /!< Odd factor: Real divider value is = I2SDIV 2 */
ganlikun	0:13413ea9a877	1298	#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /!< Odd factor: Real divider value is = (I2SDIV 2)+1 */
ganlikun	0:13413ea9a877	1299	/**
ganlikun	0:13413ea9a877	1300	* @}
ganlikun	0:13413ea9a877	1301	*/
ganlikun	0:13413ea9a877	1302
ganlikun	0:13413ea9a877	1303	#if defined(USE_FULL_LL_DRIVER)
ganlikun	0:13413ea9a877	1304
ganlikun	0:13413ea9a877	1305	/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
ganlikun	0:13413ea9a877	1306	* @{
ganlikun	0:13413ea9a877	1307	*/
ganlikun	0:13413ea9a877	1308	#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /!< Master clock output is disabled /
ganlikun	0:13413ea9a877	1309	#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /!< Master clock output is enabled /
ganlikun	0:13413ea9a877	1310	/**
ganlikun	0:13413ea9a877	1311	* @}
ganlikun	0:13413ea9a877	1312	*/
ganlikun	0:13413ea9a877	1313
ganlikun	0:13413ea9a877	1314	/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
ganlikun	0:13413ea9a877	1315	* @{
ganlikun	0:13413ea9a877	1316	*/
ganlikun	0:13413ea9a877	1317
ganlikun	0:13413ea9a877	1318	#define LL_I2S_AUDIOFREQ_192K 192000U /!< Audio Frequency configuration 192000 Hz /
ganlikun	0:13413ea9a877	1319	#define LL_I2S_AUDIOFREQ_96K 96000U /!< Audio Frequency configuration 96000 Hz /
ganlikun	0:13413ea9a877	1320	#define LL_I2S_AUDIOFREQ_48K 48000U /!< Audio Frequency configuration 48000 Hz /
ganlikun	0:13413ea9a877	1321	#define LL_I2S_AUDIOFREQ_44K 44100U /!< Audio Frequency configuration 44100 Hz /
ganlikun	0:13413ea9a877	1322	#define LL_I2S_AUDIOFREQ_32K 32000U /!< Audio Frequency configuration 32000 Hz /
ganlikun	0:13413ea9a877	1323	#define LL_I2S_AUDIOFREQ_22K 22050U /!< Audio Frequency configuration 22050 Hz /
ganlikun	0:13413ea9a877	1324	#define LL_I2S_AUDIOFREQ_16K 16000U /!< Audio Frequency configuration 16000 Hz /
ganlikun	0:13413ea9a877	1325	#define LL_I2S_AUDIOFREQ_11K 11025U /!< Audio Frequency configuration 11025 Hz /
ganlikun	0:13413ea9a877	1326	#define LL_I2S_AUDIOFREQ_8K 8000U /!< Audio Frequency configuration 8000 Hz /
ganlikun	0:13413ea9a877	1327	#define LL_I2S_AUDIOFREQ_DEFAULT 2U /!< Audio Freq not specified. Register I2SDIV = 2 /
ganlikun	0:13413ea9a877	1328	/**
ganlikun	0:13413ea9a877	1329	* @}
ganlikun	0:13413ea9a877	1330	*/
ganlikun	0:13413ea9a877	1331	#endif /* USE_FULL_LL_DRIVER */
ganlikun	0:13413ea9a877	1332
ganlikun	0:13413ea9a877	1333	/**
ganlikun	0:13413ea9a877	1334	* @}
ganlikun	0:13413ea9a877	1335	*/
ganlikun	0:13413ea9a877	1336
ganlikun	0:13413ea9a877	1337	/* Exported macro ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	1338	/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
ganlikun	0:13413ea9a877	1339	* @{
ganlikun	0:13413ea9a877	1340	*/
ganlikun	0:13413ea9a877	1341
ganlikun	0:13413ea9a877	1342	/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
ganlikun	0:13413ea9a877	1343	* @{
ganlikun	0:13413ea9a877	1344	*/
ganlikun	0:13413ea9a877	1345
ganlikun	0:13413ea9a877	1346	/**
ganlikun	0:13413ea9a877	1347	* @brief Write a value in I2S register
ganlikun	0:13413ea9a877	1348	* @param __INSTANCE__ I2S Instance
ganlikun	0:13413ea9a877	1349	* @param __REG__ Register to be written
ganlikun	0:13413ea9a877	1350	* @param __VALUE__ Value to be written in the register
ganlikun	0:13413ea9a877	1351	* @retval None
ganlikun	0:13413ea9a877	1352	*/
ganlikun	0:13413ea9a877	1353	#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
ganlikun	0:13413ea9a877	1354
ganlikun	0:13413ea9a877	1355	/**
ganlikun	0:13413ea9a877	1356	* @brief Read a value in I2S register
ganlikun	0:13413ea9a877	1357	* @param __INSTANCE__ I2S Instance
ganlikun	0:13413ea9a877	1358	* @param __REG__ Register to be read
ganlikun	0:13413ea9a877	1359	* @retval Register value
ganlikun	0:13413ea9a877	1360	*/
ganlikun	0:13413ea9a877	1361	#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
ganlikun	0:13413ea9a877	1362	/**
ganlikun	0:13413ea9a877	1363	* @}
ganlikun	0:13413ea9a877	1364	*/
ganlikun	0:13413ea9a877	1365
ganlikun	0:13413ea9a877	1366	/**
ganlikun	0:13413ea9a877	1367	* @}
ganlikun	0:13413ea9a877	1368	*/
ganlikun	0:13413ea9a877	1369
ganlikun	0:13413ea9a877	1370
ganlikun	0:13413ea9a877	1371	/* Exported functions --------------------------------------------------------*/
ganlikun	0:13413ea9a877	1372
ganlikun	0:13413ea9a877	1373	/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
ganlikun	0:13413ea9a877	1374	* @{
ganlikun	0:13413ea9a877	1375	*/
ganlikun	0:13413ea9a877	1376
ganlikun	0:13413ea9a877	1377	/** @defgroup I2S_LL_EF_Configuration Configuration
ganlikun	0:13413ea9a877	1378	* @{
ganlikun	0:13413ea9a877	1379	*/
ganlikun	0:13413ea9a877	1380
ganlikun	0:13413ea9a877	1381	/**
ganlikun	0:13413ea9a877	1382	* @brief Select I2S mode and Enable I2S peripheral
ganlikun	0:13413ea9a877	1383	* @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
ganlikun	0:13413ea9a877	1384	* I2SCFGR I2SE LL_I2S_Enable
ganlikun	0:13413ea9a877	1385	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1386	* @retval None
ganlikun	0:13413ea9a877	1387	*/
ganlikun	0:13413ea9a877	1388	__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1389	{
ganlikun	0:13413ea9a877	1390	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
ganlikun	0:13413ea9a877	1391	}
ganlikun	0:13413ea9a877	1392
ganlikun	0:13413ea9a877	1393	/**
ganlikun	0:13413ea9a877	1394	* @brief Disable I2S peripheral
ganlikun	0:13413ea9a877	1395	* @rmtoll I2SCFGR I2SE LL_I2S_Disable
ganlikun	0:13413ea9a877	1396	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1397	* @retval None
ganlikun	0:13413ea9a877	1398	*/
ganlikun	0:13413ea9a877	1399	__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1400	{
ganlikun	0:13413ea9a877	1401	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
ganlikun	0:13413ea9a877	1402	}
ganlikun	0:13413ea9a877	1403
ganlikun	0:13413ea9a877	1404	/**
ganlikun	0:13413ea9a877	1405	* @brief Check if I2S peripheral is enabled
ganlikun	0:13413ea9a877	1406	* @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
ganlikun	0:13413ea9a877	1407	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1408	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1409	*/
ganlikun	0:13413ea9a877	1410	__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1411	{
ganlikun	0:13413ea9a877	1412	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
ganlikun	0:13413ea9a877	1413	}
ganlikun	0:13413ea9a877	1414
ganlikun	0:13413ea9a877	1415	/**
ganlikun	0:13413ea9a877	1416	* @brief Set I2S data frame length
ganlikun	0:13413ea9a877	1417	* @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
ganlikun	0:13413ea9a877	1418	* I2SCFGR CHLEN LL_I2S_SetDataFormat
ganlikun	0:13413ea9a877	1419	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1420	* @param DataFormat This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1421	* @arg @ref LL_I2S_DATAFORMAT_16B
ganlikun	0:13413ea9a877	1422	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
ganlikun	0:13413ea9a877	1423	* @arg @ref LL_I2S_DATAFORMAT_24B
ganlikun	0:13413ea9a877	1424	* @arg @ref LL_I2S_DATAFORMAT_32B
ganlikun	0:13413ea9a877	1425	* @retval None
ganlikun	0:13413ea9a877	1426	*/
ganlikun	0:13413ea9a877	1427	__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
ganlikun	0:13413ea9a877	1428	{
ganlikun	0:13413ea9a877	1429	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN, DataFormat);
ganlikun	0:13413ea9a877	1430	}
ganlikun	0:13413ea9a877	1431
ganlikun	0:13413ea9a877	1432	/**
ganlikun	0:13413ea9a877	1433	* @brief Get I2S data frame length
ganlikun	0:13413ea9a877	1434	* @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
ganlikun	0:13413ea9a877	1435	* I2SCFGR CHLEN LL_I2S_GetDataFormat
ganlikun	0:13413ea9a877	1436	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1437	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	1438	* @arg @ref LL_I2S_DATAFORMAT_16B
ganlikun	0:13413ea9a877	1439	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
ganlikun	0:13413ea9a877	1440	* @arg @ref LL_I2S_DATAFORMAT_24B
ganlikun	0:13413ea9a877	1441	* @arg @ref LL_I2S_DATAFORMAT_32B
ganlikun	0:13413ea9a877	1442	*/
ganlikun	0:13413ea9a877	1443	__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1444	{
ganlikun	0:13413ea9a877	1445	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN));
ganlikun	0:13413ea9a877	1446	}
ganlikun	0:13413ea9a877	1447
ganlikun	0:13413ea9a877	1448	/**
ganlikun	0:13413ea9a877	1449	* @brief Set I2S clock polarity
ganlikun	0:13413ea9a877	1450	* @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
ganlikun	0:13413ea9a877	1451	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1452	* @param ClockPolarity This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1453	* @arg @ref LL_I2S_POLARITY_LOW
ganlikun	0:13413ea9a877	1454	* @arg @ref LL_I2S_POLARITY_HIGH
ganlikun	0:13413ea9a877	1455	* @retval None
ganlikun	0:13413ea9a877	1456	*/
ganlikun	0:13413ea9a877	1457	__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
ganlikun	0:13413ea9a877	1458	{
ganlikun	0:13413ea9a877	1459	SET_BIT(SPIx->I2SCFGR, ClockPolarity);
ganlikun	0:13413ea9a877	1460	}
ganlikun	0:13413ea9a877	1461
ganlikun	0:13413ea9a877	1462	/**
ganlikun	0:13413ea9a877	1463	* @brief Get I2S clock polarity
ganlikun	0:13413ea9a877	1464	* @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
ganlikun	0:13413ea9a877	1465	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1466	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	1467	* @arg @ref LL_I2S_POLARITY_LOW
ganlikun	0:13413ea9a877	1468	* @arg @ref LL_I2S_POLARITY_HIGH
ganlikun	0:13413ea9a877	1469	*/
ganlikun	0:13413ea9a877	1470	__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1471	{
ganlikun	0:13413ea9a877	1472	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
ganlikun	0:13413ea9a877	1473	}
ganlikun	0:13413ea9a877	1474
ganlikun	0:13413ea9a877	1475	/**
ganlikun	0:13413ea9a877	1476	* @brief Set I2S standard protocol
ganlikun	0:13413ea9a877	1477	* @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
ganlikun	0:13413ea9a877	1478	* I2SCFGR PCMSYNC LL_I2S_SetStandard
ganlikun	0:13413ea9a877	1479	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1480	* @param Standard This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1481	* @arg @ref LL_I2S_STANDARD_PHILIPS
ganlikun	0:13413ea9a877	1482	* @arg @ref LL_I2S_STANDARD_MSB
ganlikun	0:13413ea9a877	1483	* @arg @ref LL_I2S_STANDARD_LSB
ganlikun	0:13413ea9a877	1484	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
ganlikun	0:13413ea9a877	1485	* @arg @ref LL_I2S_STANDARD_PCM_LONG
ganlikun	0:13413ea9a877	1486	* @retval None
ganlikun	0:13413ea9a877	1487	*/
ganlikun	0:13413ea9a877	1488	__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
ganlikun	0:13413ea9a877	1489	{
ganlikun	0:13413ea9a877	1490	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC, Standard);
ganlikun	0:13413ea9a877	1491	}
ganlikun	0:13413ea9a877	1492
ganlikun	0:13413ea9a877	1493	/**
ganlikun	0:13413ea9a877	1494	* @brief Get I2S standard protocol
ganlikun	0:13413ea9a877	1495	* @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
ganlikun	0:13413ea9a877	1496	* I2SCFGR PCMSYNC LL_I2S_GetStandard
ganlikun	0:13413ea9a877	1497	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1498	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	1499	* @arg @ref LL_I2S_STANDARD_PHILIPS
ganlikun	0:13413ea9a877	1500	* @arg @ref LL_I2S_STANDARD_MSB
ganlikun	0:13413ea9a877	1501	* @arg @ref LL_I2S_STANDARD_LSB
ganlikun	0:13413ea9a877	1502	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
ganlikun	0:13413ea9a877	1503	* @arg @ref LL_I2S_STANDARD_PCM_LONG
ganlikun	0:13413ea9a877	1504	*/
ganlikun	0:13413ea9a877	1505	__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1506	{
ganlikun	0:13413ea9a877	1507	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC));
ganlikun	0:13413ea9a877	1508	}
ganlikun	0:13413ea9a877	1509
ganlikun	0:13413ea9a877	1510	/**
ganlikun	0:13413ea9a877	1511	* @brief Set I2S transfer mode
ganlikun	0:13413ea9a877	1512	* @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
ganlikun	0:13413ea9a877	1513	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1514	* @param Mode This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1515	* @arg @ref LL_I2S_MODE_SLAVE_TX
ganlikun	0:13413ea9a877	1516	* @arg @ref LL_I2S_MODE_SLAVE_RX
ganlikun	0:13413ea9a877	1517	* @arg @ref LL_I2S_MODE_MASTER_TX
ganlikun	0:13413ea9a877	1518	* @arg @ref LL_I2S_MODE_MASTER_RX
ganlikun	0:13413ea9a877	1519	* @retval None
ganlikun	0:13413ea9a877	1520	*/
ganlikun	0:13413ea9a877	1521	__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
ganlikun	0:13413ea9a877	1522	{
ganlikun	0:13413ea9a877	1523	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
ganlikun	0:13413ea9a877	1524	}
ganlikun	0:13413ea9a877	1525
ganlikun	0:13413ea9a877	1526	/**
ganlikun	0:13413ea9a877	1527	* @brief Get I2S transfer mode
ganlikun	0:13413ea9a877	1528	* @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
ganlikun	0:13413ea9a877	1529	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1530	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	1531	* @arg @ref LL_I2S_MODE_SLAVE_TX
ganlikun	0:13413ea9a877	1532	* @arg @ref LL_I2S_MODE_SLAVE_RX
ganlikun	0:13413ea9a877	1533	* @arg @ref LL_I2S_MODE_MASTER_TX
ganlikun	0:13413ea9a877	1534	* @arg @ref LL_I2S_MODE_MASTER_RX
ganlikun	0:13413ea9a877	1535	*/
ganlikun	0:13413ea9a877	1536	__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1537	{
ganlikun	0:13413ea9a877	1538	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
ganlikun	0:13413ea9a877	1539	}
ganlikun	0:13413ea9a877	1540
ganlikun	0:13413ea9a877	1541	/**
ganlikun	0:13413ea9a877	1542	* @brief Set I2S linear prescaler
ganlikun	0:13413ea9a877	1543	* @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
ganlikun	0:13413ea9a877	1544	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1545	* @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
ganlikun	0:13413ea9a877	1546	* @retval None
ganlikun	0:13413ea9a877	1547	*/
ganlikun	0:13413ea9a877	1548	__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
ganlikun	0:13413ea9a877	1549	{
ganlikun	0:13413ea9a877	1550	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
ganlikun	0:13413ea9a877	1551	}
ganlikun	0:13413ea9a877	1552
ganlikun	0:13413ea9a877	1553	/**
ganlikun	0:13413ea9a877	1554	* @brief Get I2S linear prescaler
ganlikun	0:13413ea9a877	1555	* @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
ganlikun	0:13413ea9a877	1556	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1557	* @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
ganlikun	0:13413ea9a877	1558	*/
ganlikun	0:13413ea9a877	1559	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1560	{
ganlikun	0:13413ea9a877	1561	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
ganlikun	0:13413ea9a877	1562	}
ganlikun	0:13413ea9a877	1563
ganlikun	0:13413ea9a877	1564	/**
ganlikun	0:13413ea9a877	1565	* @brief Set I2S parity prescaler
ganlikun	0:13413ea9a877	1566	* @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
ganlikun	0:13413ea9a877	1567	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1568	* @param PrescalerParity This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1569	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
ganlikun	0:13413ea9a877	1570	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
ganlikun	0:13413ea9a877	1571	* @retval None
ganlikun	0:13413ea9a877	1572	*/
ganlikun	0:13413ea9a877	1573	__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
ganlikun	0:13413ea9a877	1574	{
ganlikun	0:13413ea9a877	1575	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
ganlikun	0:13413ea9a877	1576	}
ganlikun	0:13413ea9a877	1577
ganlikun	0:13413ea9a877	1578	/**
ganlikun	0:13413ea9a877	1579	* @brief Get I2S parity prescaler
ganlikun	0:13413ea9a877	1580	* @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
ganlikun	0:13413ea9a877	1581	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1582	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	1583	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
ganlikun	0:13413ea9a877	1584	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
ganlikun	0:13413ea9a877	1585	*/
ganlikun	0:13413ea9a877	1586	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1587	{
ganlikun	0:13413ea9a877	1588	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
ganlikun	0:13413ea9a877	1589	}
ganlikun	0:13413ea9a877	1590
ganlikun	0:13413ea9a877	1591	/**
ganlikun	0:13413ea9a877	1592	* @brief Enable the master clock ouput (Pin MCK)
ganlikun	0:13413ea9a877	1593	* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
ganlikun	0:13413ea9a877	1594	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1595	* @retval None
ganlikun	0:13413ea9a877	1596	*/
ganlikun	0:13413ea9a877	1597	__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1598	{
ganlikun	0:13413ea9a877	1599	SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
ganlikun	0:13413ea9a877	1600	}
ganlikun	0:13413ea9a877	1601
ganlikun	0:13413ea9a877	1602	/**
ganlikun	0:13413ea9a877	1603	* @brief Disable the master clock ouput (Pin MCK)
ganlikun	0:13413ea9a877	1604	* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
ganlikun	0:13413ea9a877	1605	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1606	* @retval None
ganlikun	0:13413ea9a877	1607	*/
ganlikun	0:13413ea9a877	1608	__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1609	{
ganlikun	0:13413ea9a877	1610	CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
ganlikun	0:13413ea9a877	1611	}
ganlikun	0:13413ea9a877	1612
ganlikun	0:13413ea9a877	1613	/**
ganlikun	0:13413ea9a877	1614	* @brief Check if the master clock ouput (Pin MCK) is enabled
ganlikun	0:13413ea9a877	1615	* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
ganlikun	0:13413ea9a877	1616	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1617	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1618	*/
ganlikun	0:13413ea9a877	1619	__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1620	{
ganlikun	0:13413ea9a877	1621	return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
ganlikun	0:13413ea9a877	1622	}
ganlikun	0:13413ea9a877	1623
ganlikun	0:13413ea9a877	1624	#if defined(SPI_I2SCFGR_ASTRTEN)
ganlikun	0:13413ea9a877	1625	/**
ganlikun	0:13413ea9a877	1626	* @brief Enable asynchronous start
ganlikun	0:13413ea9a877	1627	* @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
ganlikun	0:13413ea9a877	1628	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1629	* @retval None
ganlikun	0:13413ea9a877	1630	*/
ganlikun	0:13413ea9a877	1631	__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1632	{
ganlikun	0:13413ea9a877	1633	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
ganlikun	0:13413ea9a877	1634	}
ganlikun	0:13413ea9a877	1635
ganlikun	0:13413ea9a877	1636	/**
ganlikun	0:13413ea9a877	1637	* @brief Disable asynchronous start
ganlikun	0:13413ea9a877	1638	* @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
ganlikun	0:13413ea9a877	1639	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1640	* @retval None
ganlikun	0:13413ea9a877	1641	*/
ganlikun	0:13413ea9a877	1642	__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1643	{
ganlikun	0:13413ea9a877	1644	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
ganlikun	0:13413ea9a877	1645	}
ganlikun	0:13413ea9a877	1646
ganlikun	0:13413ea9a877	1647	/**
ganlikun	0:13413ea9a877	1648	* @brief Check if asynchronous start is enabled
ganlikun	0:13413ea9a877	1649	* @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
ganlikun	0:13413ea9a877	1650	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1651	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1652	*/
ganlikun	0:13413ea9a877	1653	__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1654	{
ganlikun	0:13413ea9a877	1655	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN));
ganlikun	0:13413ea9a877	1656	}
ganlikun	0:13413ea9a877	1657	#endif /* SPI_I2SCFGR_ASTRTEN */
ganlikun	0:13413ea9a877	1658
ganlikun	0:13413ea9a877	1659	/**
ganlikun	0:13413ea9a877	1660	* @}
ganlikun	0:13413ea9a877	1661	*/
ganlikun	0:13413ea9a877	1662
ganlikun	0:13413ea9a877	1663	/** @defgroup I2S_LL_EF_FLAG FLAG Management
ganlikun	0:13413ea9a877	1664	* @{
ganlikun	0:13413ea9a877	1665	*/
ganlikun	0:13413ea9a877	1666
ganlikun	0:13413ea9a877	1667	/**
ganlikun	0:13413ea9a877	1668	* @brief Check if Rx buffer is not empty
ganlikun	0:13413ea9a877	1669	* @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
ganlikun	0:13413ea9a877	1670	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1671	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1672	*/
ganlikun	0:13413ea9a877	1673	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1674	{
ganlikun	0:13413ea9a877	1675	return LL_SPI_IsActiveFlag_RXNE(SPIx);
ganlikun	0:13413ea9a877	1676	}
ganlikun	0:13413ea9a877	1677
ganlikun	0:13413ea9a877	1678	/**
ganlikun	0:13413ea9a877	1679	* @brief Check if Tx buffer is empty
ganlikun	0:13413ea9a877	1680	* @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
ganlikun	0:13413ea9a877	1681	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1682	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1683	*/
ganlikun	0:13413ea9a877	1684	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1685	{
ganlikun	0:13413ea9a877	1686	return LL_SPI_IsActiveFlag_TXE(SPIx);
ganlikun	0:13413ea9a877	1687	}
ganlikun	0:13413ea9a877	1688
ganlikun	0:13413ea9a877	1689	/**
ganlikun	0:13413ea9a877	1690	* @brief Get busy flag
ganlikun	0:13413ea9a877	1691	* @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
ganlikun	0:13413ea9a877	1692	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1693	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1694	*/
ganlikun	0:13413ea9a877	1695	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1696	{
ganlikun	0:13413ea9a877	1697	return LL_SPI_IsActiveFlag_BSY(SPIx);
ganlikun	0:13413ea9a877	1698	}
ganlikun	0:13413ea9a877	1699
ganlikun	0:13413ea9a877	1700	/**
ganlikun	0:13413ea9a877	1701	* @brief Get overrun error flag
ganlikun	0:13413ea9a877	1702	* @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
ganlikun	0:13413ea9a877	1703	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1704	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1705	*/
ganlikun	0:13413ea9a877	1706	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1707	{
ganlikun	0:13413ea9a877	1708	return LL_SPI_IsActiveFlag_OVR(SPIx);
ganlikun	0:13413ea9a877	1709	}
ganlikun	0:13413ea9a877	1710
ganlikun	0:13413ea9a877	1711	/**
ganlikun	0:13413ea9a877	1712	* @brief Get underrun error flag
ganlikun	0:13413ea9a877	1713	* @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
ganlikun	0:13413ea9a877	1714	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1715	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1716	*/
ganlikun	0:13413ea9a877	1717	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1718	{
ganlikun	0:13413ea9a877	1719	return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
ganlikun	0:13413ea9a877	1720	}
ganlikun	0:13413ea9a877	1721
ganlikun	0:13413ea9a877	1722	/**
ganlikun	0:13413ea9a877	1723	* @brief Get frame format error flag
ganlikun	0:13413ea9a877	1724	* @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
ganlikun	0:13413ea9a877	1725	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1726	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1727	*/
ganlikun	0:13413ea9a877	1728	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1729	{
ganlikun	0:13413ea9a877	1730	return LL_SPI_IsActiveFlag_FRE(SPIx);
ganlikun	0:13413ea9a877	1731	}
ganlikun	0:13413ea9a877	1732
ganlikun	0:13413ea9a877	1733	/**
ganlikun	0:13413ea9a877	1734	* @brief Get channel side flag.
ganlikun	0:13413ea9a877	1735	* @note 0: Channel Left has to be transmitted or has been received\n
ganlikun	0:13413ea9a877	1736	* 1: Channel Right has to be transmitted or has been received\n
ganlikun	0:13413ea9a877	1737	* It has no significance in PCM mode.
ganlikun	0:13413ea9a877	1738	* @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
ganlikun	0:13413ea9a877	1739	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1740	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1741	*/
ganlikun	0:13413ea9a877	1742	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1743	{
ganlikun	0:13413ea9a877	1744	return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
ganlikun	0:13413ea9a877	1745	}
ganlikun	0:13413ea9a877	1746
ganlikun	0:13413ea9a877	1747	/**
ganlikun	0:13413ea9a877	1748	* @brief Clear overrun error flag
ganlikun	0:13413ea9a877	1749	* @rmtoll SR OVR LL_I2S_ClearFlag_OVR
ganlikun	0:13413ea9a877	1750	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1751	* @retval None
ganlikun	0:13413ea9a877	1752	*/
ganlikun	0:13413ea9a877	1753	__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1754	{
ganlikun	0:13413ea9a877	1755	LL_SPI_ClearFlag_OVR(SPIx);
ganlikun	0:13413ea9a877	1756	}
ganlikun	0:13413ea9a877	1757
ganlikun	0:13413ea9a877	1758	/**
ganlikun	0:13413ea9a877	1759	* @brief Clear underrun error flag
ganlikun	0:13413ea9a877	1760	* @rmtoll SR UDR LL_I2S_ClearFlag_UDR
ganlikun	0:13413ea9a877	1761	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1762	* @retval None
ganlikun	0:13413ea9a877	1763	*/
ganlikun	0:13413ea9a877	1764	__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1765	{
ganlikun	0:13413ea9a877	1766	__IO uint32_t tmpreg;
ganlikun	0:13413ea9a877	1767	tmpreg = SPIx->SR;
ganlikun	0:13413ea9a877	1768	(void)tmpreg;
ganlikun	0:13413ea9a877	1769	}
ganlikun	0:13413ea9a877	1770
ganlikun	0:13413ea9a877	1771	/**
ganlikun	0:13413ea9a877	1772	* @brief Clear frame format error flag
ganlikun	0:13413ea9a877	1773	* @rmtoll SR FRE LL_I2S_ClearFlag_FRE
ganlikun	0:13413ea9a877	1774	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1775	* @retval None
ganlikun	0:13413ea9a877	1776	*/
ganlikun	0:13413ea9a877	1777	__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1778	{
ganlikun	0:13413ea9a877	1779	LL_SPI_ClearFlag_FRE(SPIx);
ganlikun	0:13413ea9a877	1780	}
ganlikun	0:13413ea9a877	1781
ganlikun	0:13413ea9a877	1782	/**
ganlikun	0:13413ea9a877	1783	* @}
ganlikun	0:13413ea9a877	1784	*/
ganlikun	0:13413ea9a877	1785
ganlikun	0:13413ea9a877	1786	/** @defgroup I2S_LL_EF_IT Interrupt Management
ganlikun	0:13413ea9a877	1787	* @{
ganlikun	0:13413ea9a877	1788	*/
ganlikun	0:13413ea9a877	1789
ganlikun	0:13413ea9a877	1790	/**
ganlikun	0:13413ea9a877	1791	* @brief Enable error IT
ganlikun	0:13413ea9a877	1792	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
ganlikun	0:13413ea9a877	1793	* @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
ganlikun	0:13413ea9a877	1794	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1795	* @retval None
ganlikun	0:13413ea9a877	1796	*/
ganlikun	0:13413ea9a877	1797	__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1798	{
ganlikun	0:13413ea9a877	1799	LL_SPI_EnableIT_ERR(SPIx);
ganlikun	0:13413ea9a877	1800	}
ganlikun	0:13413ea9a877	1801
ganlikun	0:13413ea9a877	1802	/**
ganlikun	0:13413ea9a877	1803	* @brief Enable Rx buffer not empty IT
ganlikun	0:13413ea9a877	1804	* @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
ganlikun	0:13413ea9a877	1805	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1806	* @retval None
ganlikun	0:13413ea9a877	1807	*/
ganlikun	0:13413ea9a877	1808	__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1809	{
ganlikun	0:13413ea9a877	1810	LL_SPI_EnableIT_RXNE(SPIx);
ganlikun	0:13413ea9a877	1811	}
ganlikun	0:13413ea9a877	1812
ganlikun	0:13413ea9a877	1813	/**
ganlikun	0:13413ea9a877	1814	* @brief Enable Tx buffer empty IT
ganlikun	0:13413ea9a877	1815	* @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
ganlikun	0:13413ea9a877	1816	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1817	* @retval None
ganlikun	0:13413ea9a877	1818	*/
ganlikun	0:13413ea9a877	1819	__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1820	{
ganlikun	0:13413ea9a877	1821	LL_SPI_EnableIT_TXE(SPIx);
ganlikun	0:13413ea9a877	1822	}
ganlikun	0:13413ea9a877	1823
ganlikun	0:13413ea9a877	1824	/**
ganlikun	0:13413ea9a877	1825	* @brief Disable error IT
ganlikun	0:13413ea9a877	1826	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
ganlikun	0:13413ea9a877	1827	* @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
ganlikun	0:13413ea9a877	1828	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1829	* @retval None
ganlikun	0:13413ea9a877	1830	*/
ganlikun	0:13413ea9a877	1831	__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1832	{
ganlikun	0:13413ea9a877	1833	LL_SPI_DisableIT_ERR(SPIx);
ganlikun	0:13413ea9a877	1834	}
ganlikun	0:13413ea9a877	1835
ganlikun	0:13413ea9a877	1836	/**
ganlikun	0:13413ea9a877	1837	* @brief Disable Rx buffer not empty IT
ganlikun	0:13413ea9a877	1838	* @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
ganlikun	0:13413ea9a877	1839	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1840	* @retval None
ganlikun	0:13413ea9a877	1841	*/
ganlikun	0:13413ea9a877	1842	__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1843	{
ganlikun	0:13413ea9a877	1844	LL_SPI_DisableIT_RXNE(SPIx);
ganlikun	0:13413ea9a877	1845	}
ganlikun	0:13413ea9a877	1846
ganlikun	0:13413ea9a877	1847	/**
ganlikun	0:13413ea9a877	1848	* @brief Disable Tx buffer empty IT
ganlikun	0:13413ea9a877	1849	* @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
ganlikun	0:13413ea9a877	1850	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1851	* @retval None
ganlikun	0:13413ea9a877	1852	*/
ganlikun	0:13413ea9a877	1853	__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1854	{
ganlikun	0:13413ea9a877	1855	LL_SPI_DisableIT_TXE(SPIx);
ganlikun	0:13413ea9a877	1856	}
ganlikun	0:13413ea9a877	1857
ganlikun	0:13413ea9a877	1858	/**
ganlikun	0:13413ea9a877	1859	* @brief Check if ERR IT is enabled
ganlikun	0:13413ea9a877	1860	* @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
ganlikun	0:13413ea9a877	1861	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1862	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1863	*/
ganlikun	0:13413ea9a877	1864	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1865	{
ganlikun	0:13413ea9a877	1866	return LL_SPI_IsEnabledIT_ERR(SPIx);
ganlikun	0:13413ea9a877	1867	}
ganlikun	0:13413ea9a877	1868
ganlikun	0:13413ea9a877	1869	/**
ganlikun	0:13413ea9a877	1870	* @brief Check if RXNE IT is enabled
ganlikun	0:13413ea9a877	1871	* @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
ganlikun	0:13413ea9a877	1872	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1873	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1874	*/
ganlikun	0:13413ea9a877	1875	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1876	{
ganlikun	0:13413ea9a877	1877	return LL_SPI_IsEnabledIT_RXNE(SPIx);
ganlikun	0:13413ea9a877	1878	}
ganlikun	0:13413ea9a877	1879
ganlikun	0:13413ea9a877	1880	/**
ganlikun	0:13413ea9a877	1881	* @brief Check if TXE IT is enabled
ganlikun	0:13413ea9a877	1882	* @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
ganlikun	0:13413ea9a877	1883	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1884	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1885	*/
ganlikun	0:13413ea9a877	1886	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1887	{
ganlikun	0:13413ea9a877	1888	return LL_SPI_IsEnabledIT_TXE(SPIx);
ganlikun	0:13413ea9a877	1889	}
ganlikun	0:13413ea9a877	1890
ganlikun	0:13413ea9a877	1891	/**
ganlikun	0:13413ea9a877	1892	* @}
ganlikun	0:13413ea9a877	1893	*/
ganlikun	0:13413ea9a877	1894
ganlikun	0:13413ea9a877	1895	/** @defgroup I2S_LL_EF_DMA DMA Management
ganlikun	0:13413ea9a877	1896	* @{
ganlikun	0:13413ea9a877	1897	*/
ganlikun	0:13413ea9a877	1898
ganlikun	0:13413ea9a877	1899	/**
ganlikun	0:13413ea9a877	1900	* @brief Enable DMA Rx
ganlikun	0:13413ea9a877	1901	* @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
ganlikun	0:13413ea9a877	1902	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1903	* @retval None
ganlikun	0:13413ea9a877	1904	*/
ganlikun	0:13413ea9a877	1905	__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1906	{
ganlikun	0:13413ea9a877	1907	LL_SPI_EnableDMAReq_RX(SPIx);
ganlikun	0:13413ea9a877	1908	}
ganlikun	0:13413ea9a877	1909
ganlikun	0:13413ea9a877	1910	/**
ganlikun	0:13413ea9a877	1911	* @brief Disable DMA Rx
ganlikun	0:13413ea9a877	1912	* @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
ganlikun	0:13413ea9a877	1913	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1914	* @retval None
ganlikun	0:13413ea9a877	1915	*/
ganlikun	0:13413ea9a877	1916	__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1917	{
ganlikun	0:13413ea9a877	1918	LL_SPI_DisableDMAReq_RX(SPIx);
ganlikun	0:13413ea9a877	1919	}
ganlikun	0:13413ea9a877	1920
ganlikun	0:13413ea9a877	1921	/**
ganlikun	0:13413ea9a877	1922	* @brief Check if DMA Rx is enabled
ganlikun	0:13413ea9a877	1923	* @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
ganlikun	0:13413ea9a877	1924	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1925	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1926	*/
ganlikun	0:13413ea9a877	1927	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1928	{
ganlikun	0:13413ea9a877	1929	return LL_SPI_IsEnabledDMAReq_RX(SPIx);
ganlikun	0:13413ea9a877	1930	}
ganlikun	0:13413ea9a877	1931
ganlikun	0:13413ea9a877	1932	/**
ganlikun	0:13413ea9a877	1933	* @brief Enable DMA Tx
ganlikun	0:13413ea9a877	1934	* @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
ganlikun	0:13413ea9a877	1935	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1936	* @retval None
ganlikun	0:13413ea9a877	1937	*/
ganlikun	0:13413ea9a877	1938	__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1939	{
ganlikun	0:13413ea9a877	1940	LL_SPI_EnableDMAReq_TX(SPIx);
ganlikun	0:13413ea9a877	1941	}
ganlikun	0:13413ea9a877	1942
ganlikun	0:13413ea9a877	1943	/**
ganlikun	0:13413ea9a877	1944	* @brief Disable DMA Tx
ganlikun	0:13413ea9a877	1945	* @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
ganlikun	0:13413ea9a877	1946	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1947	* @retval None
ganlikun	0:13413ea9a877	1948	*/
ganlikun	0:13413ea9a877	1949	__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1950	{
ganlikun	0:13413ea9a877	1951	LL_SPI_DisableDMAReq_TX(SPIx);
ganlikun	0:13413ea9a877	1952	}
ganlikun	0:13413ea9a877	1953
ganlikun	0:13413ea9a877	1954	/**
ganlikun	0:13413ea9a877	1955	* @brief Check if DMA Tx is enabled
ganlikun	0:13413ea9a877	1956	* @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
ganlikun	0:13413ea9a877	1957	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1958	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1959	*/
ganlikun	0:13413ea9a877	1960	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1961	{
ganlikun	0:13413ea9a877	1962	return LL_SPI_IsEnabledDMAReq_TX(SPIx);
ganlikun	0:13413ea9a877	1963	}
ganlikun	0:13413ea9a877	1964
ganlikun	0:13413ea9a877	1965	/**
ganlikun	0:13413ea9a877	1966	* @}
ganlikun	0:13413ea9a877	1967	*/
ganlikun	0:13413ea9a877	1968
ganlikun	0:13413ea9a877	1969	/** @defgroup I2S_LL_EF_DATA DATA Management
ganlikun	0:13413ea9a877	1970	* @{
ganlikun	0:13413ea9a877	1971	*/
ganlikun	0:13413ea9a877	1972
ganlikun	0:13413ea9a877	1973	/**
ganlikun	0:13413ea9a877	1974	* @brief Read 16-Bits in data register
ganlikun	0:13413ea9a877	1975	* @rmtoll DR DR LL_I2S_ReceiveData16
ganlikun	0:13413ea9a877	1976	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1977	* @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
ganlikun	0:13413ea9a877	1978	*/
ganlikun	0:13413ea9a877	1979	__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
ganlikun	0:13413ea9a877	1980	{
ganlikun	0:13413ea9a877	1981	return LL_SPI_ReceiveData16(SPIx);
ganlikun	0:13413ea9a877	1982	}
ganlikun	0:13413ea9a877	1983
ganlikun	0:13413ea9a877	1984	/**
ganlikun	0:13413ea9a877	1985	* @brief Write 16-Bits in data register
ganlikun	0:13413ea9a877	1986	* @rmtoll DR DR LL_I2S_TransmitData16
ganlikun	0:13413ea9a877	1987	* @param SPIx SPI Instance
ganlikun	0:13413ea9a877	1988	* @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
ganlikun	0:13413ea9a877	1989	* @retval None
ganlikun	0:13413ea9a877	1990	*/
ganlikun	0:13413ea9a877	1991	__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
ganlikun	0:13413ea9a877	1992	{
ganlikun	0:13413ea9a877	1993	LL_SPI_TransmitData16(SPIx, TxData);
ganlikun	0:13413ea9a877	1994	}
ganlikun	0:13413ea9a877	1995
ganlikun	0:13413ea9a877	1996	/**
ganlikun	0:13413ea9a877	1997	* @}
ganlikun	0:13413ea9a877	1998	*/
ganlikun	0:13413ea9a877	1999
ganlikun	0:13413ea9a877	2000	#if defined(USE_FULL_LL_DRIVER)
ganlikun	0:13413ea9a877	2001	/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
ganlikun	0:13413ea9a877	2002	* @{
ganlikun	0:13413ea9a877	2003	*/
ganlikun	0:13413ea9a877	2004
ganlikun	0:13413ea9a877	2005	ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
ganlikun	0:13413ea9a877	2006	ErrorStatus LL_I2S_Init(SPI_TypeDef SPIx, LL_I2S_InitTypeDef I2S_InitStruct);
ganlikun	0:13413ea9a877	2007	void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
ganlikun	0:13413ea9a877	2008	void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
ganlikun	0:13413ea9a877	2009	#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
ganlikun	0:13413ea9a877	2010	ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef I2Sxext, LL_I2S_InitTypeDef I2S_InitStruct);
ganlikun	0:13413ea9a877	2011	#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
ganlikun	0:13413ea9a877	2012
ganlikun	0:13413ea9a877	2013	/**
ganlikun	0:13413ea9a877	2014	* @}
ganlikun	0:13413ea9a877	2015	*/
ganlikun	0:13413ea9a877	2016	#endif /* USE_FULL_LL_DRIVER */
ganlikun	0:13413ea9a877	2017
ganlikun	0:13413ea9a877	2018	/**
ganlikun	0:13413ea9a877	2019	* @}
ganlikun	0:13413ea9a877	2020	*/
ganlikun	0:13413ea9a877	2021
ganlikun	0:13413ea9a877	2022	/**
ganlikun	0:13413ea9a877	2023	* @}
ganlikun	0:13413ea9a877	2024	*/
ganlikun	0:13413ea9a877	2025
ganlikun	0:13413ea9a877	2026	#endif /* defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3) \|\| defined (SPI4) \|\| defined (SPI5) \|\| defined(SPI6) */
ganlikun	0:13413ea9a877	2027
ganlikun	0:13413ea9a877	2028	/**
ganlikun	0:13413ea9a877	2029	* @}
ganlikun	0:13413ea9a877	2030	*/
ganlikun	0:13413ea9a877	2031
ganlikun	0:13413ea9a877	2032	#ifdef __cplusplus
ganlikun	0:13413ea9a877	2033	}
ganlikun	0:13413ea9a877	2034	#endif
ganlikun	0:13413ea9a877	2035
ganlikun	0:13413ea9a877	2036	#endif /* __STM32F4xx_LL_SPI_H */
ganlikun	0:13413ea9a877	2037
ganlikun	0:13413ea9a877	2038	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
ganlikun	0:13413ea9a877	2039

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Type:	Library
Created:	05 Jul 2022
Imports:	1
Forks:	0
Commits:	1
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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.h@0:13413ea9a877, 2022-06-12 (annotated)

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