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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.h@0:13413ea9a877, 2022-06-12 (annotated)

Committer:: ganlikun
Date:: Sun Jun 12 14:02:44 2022 +0000
Revision:: 0:13413ea9a877

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User	Revision	Line number	New contents of line
ganlikun	0:13413ea9a877	1	/**
ganlikun	0:13413ea9a877	2	******************************************************************************
ganlikun	0:13413ea9a877	3	* @file stm32f4xx_ll_rcc.h
ganlikun	0:13413ea9a877	4	* @author MCD Application Team
ganlikun	0:13413ea9a877	5	* @version V1.7.1
ganlikun	0:13413ea9a877	6	* @date 14-April-2017
ganlikun	0:13413ea9a877	7	* @brief Header file of RCC LL module.
ganlikun	0:13413ea9a877	8	******************************************************************************
ganlikun	0:13413ea9a877	9	* @attention
ganlikun	0:13413ea9a877	10	*
ganlikun	0:13413ea9a877	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun	0:13413ea9a877	12	*
ganlikun	0:13413ea9a877	13	* Redistribution and use in source and binary forms, with or without modification,
ganlikun	0:13413ea9a877	14	* are permitted provided that the following conditions are met:
ganlikun	0:13413ea9a877	15	* 1. Redistributions of source code must retain the above copyright notice,
ganlikun	0:13413ea9a877	16	* this list of conditions and the following disclaimer.
ganlikun	0:13413ea9a877	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun	0:13413ea9a877	18	* this list of conditions and the following disclaimer in the documentation
ganlikun	0:13413ea9a877	19	* and/or other materials provided with the distribution.
ganlikun	0:13413ea9a877	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun	0:13413ea9a877	21	* may be used to endorse or promote products derived from this software
ganlikun	0:13413ea9a877	22	* without specific prior written permission.
ganlikun	0:13413ea9a877	23	*
ganlikun	0:13413ea9a877	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun	0:13413ea9a877	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun	0:13413ea9a877	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun	0:13413ea9a877	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun	0:13413ea9a877	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun	0:13413ea9a877	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun	0:13413ea9a877	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun	0:13413ea9a877	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun	0:13413ea9a877	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun	0:13413ea9a877	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun	0:13413ea9a877	34	*
ganlikun	0:13413ea9a877	35	******************************************************************************
ganlikun	0:13413ea9a877	36	*/
ganlikun	0:13413ea9a877	37
ganlikun	0:13413ea9a877	38	/* Define to prevent recursive inclusion -------------------------------------*/
ganlikun	0:13413ea9a877	39	#ifndef __STM32F4xx_LL_RCC_H
ganlikun	0:13413ea9a877	40	#define __STM32F4xx_LL_RCC_H
ganlikun	0:13413ea9a877	41
ganlikun	0:13413ea9a877	42	#ifdef __cplusplus
ganlikun	0:13413ea9a877	43	extern "C" {
ganlikun	0:13413ea9a877	44	#endif
ganlikun	0:13413ea9a877	45
ganlikun	0:13413ea9a877	46	/* Includes ------------------------------------------------------------------*/
ganlikun	0:13413ea9a877	47	#include "stm32f4xx.h"
ganlikun	0:13413ea9a877	48
ganlikun	0:13413ea9a877	49	/** @addtogroup STM32F4xx_LL_Driver
ganlikun	0:13413ea9a877	50	* @{
ganlikun	0:13413ea9a877	51	*/
ganlikun	0:13413ea9a877	52
ganlikun	0:13413ea9a877	53	#if defined(RCC)
ganlikun	0:13413ea9a877	54
ganlikun	0:13413ea9a877	55	/** @defgroup RCC_LL RCC
ganlikun	0:13413ea9a877	56	* @{
ganlikun	0:13413ea9a877	57	*/
ganlikun	0:13413ea9a877	58
ganlikun	0:13413ea9a877	59	/* Private types -------------------------------------------------------------*/
ganlikun	0:13413ea9a877	60	/* Private variables ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	61	/** @defgroup RCC_LL_Private_Variables RCC Private Variables
ganlikun	0:13413ea9a877	62	* @{
ganlikun	0:13413ea9a877	63	*/
ganlikun	0:13413ea9a877	64
ganlikun	0:13413ea9a877	65	#if defined(RCC_DCKCFGR_PLLSAIDIVR)
ganlikun	0:13413ea9a877	66	static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
ganlikun	0:13413ea9a877	67	#endif /* RCC_DCKCFGR_PLLSAIDIVR */
ganlikun	0:13413ea9a877	68
ganlikun	0:13413ea9a877	69	/**
ganlikun	0:13413ea9a877	70	* @}
ganlikun	0:13413ea9a877	71	*/
ganlikun	0:13413ea9a877	72	/* Private constants ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	73	/* Private macros ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	74	#if defined(USE_FULL_LL_DRIVER)
ganlikun	0:13413ea9a877	75	/** @defgroup RCC_LL_Private_Macros RCC Private Macros
ganlikun	0:13413ea9a877	76	* @{
ganlikun	0:13413ea9a877	77	*/
ganlikun	0:13413ea9a877	78	/**
ganlikun	0:13413ea9a877	79	* @}
ganlikun	0:13413ea9a877	80	*/
ganlikun	0:13413ea9a877	81	#endif /USE_FULL_LL_DRIVER/
ganlikun	0:13413ea9a877	82	/* Exported types ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	83	#if defined(USE_FULL_LL_DRIVER)
ganlikun	0:13413ea9a877	84	/** @defgroup RCC_LL_Exported_Types RCC Exported Types
ganlikun	0:13413ea9a877	85	* @{
ganlikun	0:13413ea9a877	86	*/
ganlikun	0:13413ea9a877	87
ganlikun	0:13413ea9a877	88	/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
ganlikun	0:13413ea9a877	89	* @{
ganlikun	0:13413ea9a877	90	*/
ganlikun	0:13413ea9a877	91
ganlikun	0:13413ea9a877	92	/**
ganlikun	0:13413ea9a877	93	* @brief RCC Clocks Frequency Structure
ganlikun	0:13413ea9a877	94	*/
ganlikun	0:13413ea9a877	95	typedef struct
ganlikun	0:13413ea9a877	96	{
ganlikun	0:13413ea9a877	97	uint32_t SYSCLK_Frequency; /!< SYSCLK clock frequency /
ganlikun	0:13413ea9a877	98	uint32_t HCLK_Frequency; /!< HCLK clock frequency /
ganlikun	0:13413ea9a877	99	uint32_t PCLK1_Frequency; /!< PCLK1 clock frequency /
ganlikun	0:13413ea9a877	100	uint32_t PCLK2_Frequency; /!< PCLK2 clock frequency /
ganlikun	0:13413ea9a877	101	} LL_RCC_ClocksTypeDef;
ganlikun	0:13413ea9a877	102
ganlikun	0:13413ea9a877	103	/**
ganlikun	0:13413ea9a877	104	* @}
ganlikun	0:13413ea9a877	105	*/
ganlikun	0:13413ea9a877	106
ganlikun	0:13413ea9a877	107	/**
ganlikun	0:13413ea9a877	108	* @}
ganlikun	0:13413ea9a877	109	*/
ganlikun	0:13413ea9a877	110	#endif /* USE_FULL_LL_DRIVER */
ganlikun	0:13413ea9a877	111
ganlikun	0:13413ea9a877	112	/* Exported constants --------------------------------------------------------*/
ganlikun	0:13413ea9a877	113	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
ganlikun	0:13413ea9a877	114	* @{
ganlikun	0:13413ea9a877	115	*/
ganlikun	0:13413ea9a877	116
ganlikun	0:13413ea9a877	117	/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
ganlikun	0:13413ea9a877	118	* @brief Defines used to adapt values of different oscillators
ganlikun	0:13413ea9a877	119	* @note These values could be modified in the user environment according to
ganlikun	0:13413ea9a877	120	* HW set-up.
ganlikun	0:13413ea9a877	121	* @{
ganlikun	0:13413ea9a877	122	*/
ganlikun	0:13413ea9a877	123	#if !defined (HSE_VALUE)
ganlikun	0:13413ea9a877	124	#define HSE_VALUE 25000000U /!< Value of the HSE oscillator in Hz /
ganlikun	0:13413ea9a877	125	#endif /* HSE_VALUE */
ganlikun	0:13413ea9a877	126
ganlikun	0:13413ea9a877	127	#if !defined (HSI_VALUE)
ganlikun	0:13413ea9a877	128	#define HSI_VALUE 16000000U /!< Value of the HSI oscillator in Hz /
ganlikun	0:13413ea9a877	129	#endif /* HSI_VALUE */
ganlikun	0:13413ea9a877	130
ganlikun	0:13413ea9a877	131	#if !defined (LSE_VALUE)
ganlikun	0:13413ea9a877	132	#define LSE_VALUE 32768U /!< Value of the LSE oscillator in Hz /
ganlikun	0:13413ea9a877	133	#endif /* LSE_VALUE */
ganlikun	0:13413ea9a877	134
ganlikun	0:13413ea9a877	135	#if !defined (LSI_VALUE)
ganlikun	0:13413ea9a877	136	#define LSI_VALUE 32000U /!< Value of the LSI oscillator in Hz /
ganlikun	0:13413ea9a877	137	#endif /* LSI_VALUE */
ganlikun	0:13413ea9a877	138
ganlikun	0:13413ea9a877	139	#if !defined (EXTERNAL_CLOCK_VALUE)
ganlikun	0:13413ea9a877	140	#define EXTERNAL_CLOCK_VALUE 12288000U /!< Value of the I2S_CKIN external oscillator in Hz /
ganlikun	0:13413ea9a877	141	#endif /* EXTERNAL_CLOCK_VALUE */
ganlikun	0:13413ea9a877	142	/**
ganlikun	0:13413ea9a877	143	* @}
ganlikun	0:13413ea9a877	144	*/
ganlikun	0:13413ea9a877	145
ganlikun	0:13413ea9a877	146	/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
ganlikun	0:13413ea9a877	147	* @brief Flags defines which can be used with LL_RCC_WriteReg function
ganlikun	0:13413ea9a877	148	* @{
ganlikun	0:13413ea9a877	149	*/
ganlikun	0:13413ea9a877	150	#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /!< LSI Ready Interrupt Clear /
ganlikun	0:13413ea9a877	151	#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /!< LSE Ready Interrupt Clear /
ganlikun	0:13413ea9a877	152	#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /!< HSI Ready Interrupt Clear /
ganlikun	0:13413ea9a877	153	#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /!< HSE Ready Interrupt Clear /
ganlikun	0:13413ea9a877	154	#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /!< PLL Ready Interrupt Clear /
ganlikun	0:13413ea9a877	155	#if defined(RCC_PLLI2S_SUPPORT)
ganlikun	0:13413ea9a877	156	#define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /!< PLLI2S Ready Interrupt Clear /
ganlikun	0:13413ea9a877	157	#endif /* RCC_PLLI2S_SUPPORT */
ganlikun	0:13413ea9a877	158	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	159	#define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /!< PLLSAI Ready Interrupt Clear /
ganlikun	0:13413ea9a877	160	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	161	#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /!< Clock Security System Interrupt Clear /
ganlikun	0:13413ea9a877	162	/**
ganlikun	0:13413ea9a877	163	* @}
ganlikun	0:13413ea9a877	164	*/
ganlikun	0:13413ea9a877	165
ganlikun	0:13413ea9a877	166	/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
ganlikun	0:13413ea9a877	167	* @brief Flags defines which can be used with LL_RCC_ReadReg function
ganlikun	0:13413ea9a877	168	* @{
ganlikun	0:13413ea9a877	169	*/
ganlikun	0:13413ea9a877	170	#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /!< LSI Ready Interrupt flag /
ganlikun	0:13413ea9a877	171	#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /!< LSE Ready Interrupt flag /
ganlikun	0:13413ea9a877	172	#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /!< HSI Ready Interrupt flag /
ganlikun	0:13413ea9a877	173	#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /!< HSE Ready Interrupt flag /
ganlikun	0:13413ea9a877	174	#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /!< PLL Ready Interrupt flag /
ganlikun	0:13413ea9a877	175	#if defined(RCC_PLLI2S_SUPPORT)
ganlikun	0:13413ea9a877	176	#define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /!< PLLI2S Ready Interrupt flag /
ganlikun	0:13413ea9a877	177	#endif /* RCC_PLLI2S_SUPPORT */
ganlikun	0:13413ea9a877	178	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	179	#define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /!< PLLSAI Ready Interrupt flag /
ganlikun	0:13413ea9a877	180	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	181	#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /!< Clock Security System Interrupt flag /
ganlikun	0:13413ea9a877	182	#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /!< Low-Power reset flag /
ganlikun	0:13413ea9a877	183	#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /!< PIN reset flag /
ganlikun	0:13413ea9a877	184	#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /!< POR/PDR reset flag /
ganlikun	0:13413ea9a877	185	#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /!< Software Reset flag /
ganlikun	0:13413ea9a877	186	#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /!< Independent Watchdog reset flag /
ganlikun	0:13413ea9a877	187	#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /!< Window watchdog reset flag /
ganlikun	0:13413ea9a877	188	#if defined(RCC_CSR_BORRSTF)
ganlikun	0:13413ea9a877	189	#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /!< BOR reset flag /
ganlikun	0:13413ea9a877	190	#endif /* RCC_CSR_BORRSTF */
ganlikun	0:13413ea9a877	191	/**
ganlikun	0:13413ea9a877	192	* @}
ganlikun	0:13413ea9a877	193	*/
ganlikun	0:13413ea9a877	194
ganlikun	0:13413ea9a877	195	/** @defgroup RCC_LL_EC_IT IT Defines
ganlikun	0:13413ea9a877	196	* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
ganlikun	0:13413ea9a877	197	* @{
ganlikun	0:13413ea9a877	198	*/
ganlikun	0:13413ea9a877	199	#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /!< LSI Ready Interrupt Enable /
ganlikun	0:13413ea9a877	200	#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /!< LSE Ready Interrupt Enable /
ganlikun	0:13413ea9a877	201	#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /!< HSI Ready Interrupt Enable /
ganlikun	0:13413ea9a877	202	#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /!< HSE Ready Interrupt Enable /
ganlikun	0:13413ea9a877	203	#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /!< PLL Ready Interrupt Enable /
ganlikun	0:13413ea9a877	204	#if defined(RCC_PLLI2S_SUPPORT)
ganlikun	0:13413ea9a877	205	#define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /!< PLLI2S Ready Interrupt Enable /
ganlikun	0:13413ea9a877	206	#endif /* RCC_PLLI2S_SUPPORT */
ganlikun	0:13413ea9a877	207	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	208	#define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /!< PLLSAI Ready Interrupt Enable /
ganlikun	0:13413ea9a877	209	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	210	/**
ganlikun	0:13413ea9a877	211	* @}
ganlikun	0:13413ea9a877	212	*/
ganlikun	0:13413ea9a877	213
ganlikun	0:13413ea9a877	214	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
ganlikun	0:13413ea9a877	215	* @{
ganlikun	0:13413ea9a877	216	*/
ganlikun	0:13413ea9a877	217	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
ganlikun	0:13413ea9a877	218	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
ganlikun	0:13413ea9a877	219	#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /!< PLL selection as system clock /
ganlikun	0:13413ea9a877	220	#if defined(RCC_CFGR_SW_PLLR)
ganlikun	0:13413ea9a877	221	#define LL_RCC_SYS_CLKSOURCE_PLLR RCC_CFGR_SW_PLLR /!< PLLR selection as system clock /
ganlikun	0:13413ea9a877	222	#endif /* RCC_CFGR_SW_PLLR */
ganlikun	0:13413ea9a877	223	/**
ganlikun	0:13413ea9a877	224	* @}
ganlikun	0:13413ea9a877	225	*/
ganlikun	0:13413ea9a877	226
ganlikun	0:13413ea9a877	227	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
ganlikun	0:13413ea9a877	228	* @{
ganlikun	0:13413ea9a877	229	*/
ganlikun	0:13413ea9a877	230	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
ganlikun	0:13413ea9a877	231	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
ganlikun	0:13413ea9a877	232	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /!< PLL used as system clock /
ganlikun	0:13413ea9a877	233	#if defined(RCC_PLLR_SYSCLK_SUPPORT)
ganlikun	0:13413ea9a877	234	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR RCC_CFGR_SWS_PLLR /!< PLLR used as system clock /
ganlikun	0:13413ea9a877	235	#endif /* RCC_PLLR_SYSCLK_SUPPORT */
ganlikun	0:13413ea9a877	236	/**
ganlikun	0:13413ea9a877	237	* @}
ganlikun	0:13413ea9a877	238	*/
ganlikun	0:13413ea9a877	239
ganlikun	0:13413ea9a877	240	/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
ganlikun	0:13413ea9a877	241	* @{
ganlikun	0:13413ea9a877	242	*/
ganlikun	0:13413ea9a877	243	#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
ganlikun	0:13413ea9a877	244	#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
ganlikun	0:13413ea9a877	245	#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
ganlikun	0:13413ea9a877	246	#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
ganlikun	0:13413ea9a877	247	#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
ganlikun	0:13413ea9a877	248	#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
ganlikun	0:13413ea9a877	249	#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
ganlikun	0:13413ea9a877	250	#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
ganlikun	0:13413ea9a877	251	#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
ganlikun	0:13413ea9a877	252	/**
ganlikun	0:13413ea9a877	253	* @}
ganlikun	0:13413ea9a877	254	*/
ganlikun	0:13413ea9a877	255
ganlikun	0:13413ea9a877	256	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
ganlikun	0:13413ea9a877	257	* @{
ganlikun	0:13413ea9a877	258	*/
ganlikun	0:13413ea9a877	259	#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
ganlikun	0:13413ea9a877	260	#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
ganlikun	0:13413ea9a877	261	#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
ganlikun	0:13413ea9a877	262	#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
ganlikun	0:13413ea9a877	263	#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
ganlikun	0:13413ea9a877	264	/**
ganlikun	0:13413ea9a877	265	* @}
ganlikun	0:13413ea9a877	266	*/
ganlikun	0:13413ea9a877	267
ganlikun	0:13413ea9a877	268	/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
ganlikun	0:13413ea9a877	269	* @{
ganlikun	0:13413ea9a877	270	*/
ganlikun	0:13413ea9a877	271	#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /!< HCLK not divided /
ganlikun	0:13413ea9a877	272	#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /!< HCLK divided by 2 /
ganlikun	0:13413ea9a877	273	#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /!< HCLK divided by 4 /
ganlikun	0:13413ea9a877	274	#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /!< HCLK divided by 8 /
ganlikun	0:13413ea9a877	275	#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /!< HCLK divided by 16 /
ganlikun	0:13413ea9a877	276	/**
ganlikun	0:13413ea9a877	277	* @}
ganlikun	0:13413ea9a877	278	*/
ganlikun	0:13413ea9a877	279
ganlikun	0:13413ea9a877	280	/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
ganlikun	0:13413ea9a877	281	* @{
ganlikun	0:13413ea9a877	282	*/
ganlikun	0:13413ea9a877	283	#define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1\|0x00000000U) /!< HSI selection as MCO1 source /
ganlikun	0:13413ea9a877	284	#define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1\|(RCC_CFGR_MCO1_0 >> 16U)) /!< LSE selection as MCO1 source /
ganlikun	0:13413ea9a877	285	#define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1\|(RCC_CFGR_MCO1_1 >> 16U)) /!< HSE selection as MCO1 source /
ganlikun	0:13413ea9a877	286	#define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1\|((RCC_CFGR_MCO1_1\|RCC_CFGR_MCO1_0) >> 16U)) /!< PLLCLK selection as MCO1 source /
ganlikun	0:13413ea9a877	287	#if defined(RCC_CFGR_MCO2)
ganlikun	0:13413ea9a877	288	#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2\|0x00000000U) /!< SYSCLK selection as MCO2 source /
ganlikun	0:13413ea9a877	289	#define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2\|(RCC_CFGR_MCO2_0 >> 16U)) /!< PLLI2S selection as MCO2 source /
ganlikun	0:13413ea9a877	290	#define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2\|(RCC_CFGR_MCO2_1 >> 16U)) /!< HSE selection as MCO2 source /
ganlikun	0:13413ea9a877	291	#define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2\|((RCC_CFGR_MCO2_1\|RCC_CFGR_MCO2_0) >> 16U)) /!< PLLCLK selection as MCO2 source /
ganlikun	0:13413ea9a877	292	#endif /* RCC_CFGR_MCO2 */
ganlikun	0:13413ea9a877	293	/**
ganlikun	0:13413ea9a877	294	* @}
ganlikun	0:13413ea9a877	295	*/
ganlikun	0:13413ea9a877	296
ganlikun	0:13413ea9a877	297	/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
ganlikun	0:13413ea9a877	298	* @{
ganlikun	0:13413ea9a877	299	*/
ganlikun	0:13413ea9a877	300	#define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE\|0x00000000U) /!< MCO1 not divided /
ganlikun	0:13413ea9a877	301	#define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE\|(RCC_CFGR_MCO1PRE_2 >> 16U)) /!< MCO1 divided by 2 /
ganlikun	0:13413ea9a877	302	#define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE\|((RCC_CFGR_MCO1PRE_2\|RCC_CFGR_MCO1PRE_0) >> 16U)) /!< MCO1 divided by 3 /
ganlikun	0:13413ea9a877	303	#define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE\|((RCC_CFGR_MCO1PRE_2\|RCC_CFGR_MCO1PRE_1) >> 16U)) /!< MCO1 divided by 4 /
ganlikun	0:13413ea9a877	304	#define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE\|(RCC_CFGR_MCO1PRE >> 16U)) /!< MCO1 divided by 5 /
ganlikun	0:13413ea9a877	305	#if defined(RCC_CFGR_MCO2PRE)
ganlikun	0:13413ea9a877	306	#define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE\|0x00000000U) /!< MCO2 not divided /
ganlikun	0:13413ea9a877	307	#define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE\|(RCC_CFGR_MCO2PRE_2 >> 16U)) /!< MCO2 divided by 2 /
ganlikun	0:13413ea9a877	308	#define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE\|((RCC_CFGR_MCO2PRE_2\|RCC_CFGR_MCO2PRE_0) >> 16U)) /!< MCO2 divided by 3 /
ganlikun	0:13413ea9a877	309	#define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE\|((RCC_CFGR_MCO2PRE_2\|RCC_CFGR_MCO2PRE_1) >> 16U)) /!< MCO2 divided by 4 /
ganlikun	0:13413ea9a877	310	#define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE\|(RCC_CFGR_MCO2PRE >> 16U)) /!< MCO2 divided by 5 /
ganlikun	0:13413ea9a877	311	#endif /* RCC_CFGR_MCO2PRE */
ganlikun	0:13413ea9a877	312	/**
ganlikun	0:13413ea9a877	313	* @}
ganlikun	0:13413ea9a877	314	*/
ganlikun	0:13413ea9a877	315
ganlikun	0:13413ea9a877	316	/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
ganlikun	0:13413ea9a877	317	* @{
ganlikun	0:13413ea9a877	318	*/
ganlikun	0:13413ea9a877	319	#define LL_RCC_RTC_NOCLOCK 0x00000000U /!< HSE not divided /
ganlikun	0:13413ea9a877	320	#define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /!< HSE clock divided by 2 /
ganlikun	0:13413ea9a877	321	#define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 3 /
ganlikun	0:13413ea9a877	322	#define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /!< HSE clock divided by 4 /
ganlikun	0:13413ea9a877	323	#define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 5 /
ganlikun	0:13413ea9a877	324	#define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 6 /
ganlikun	0:13413ea9a877	325	#define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 7 /
ganlikun	0:13413ea9a877	326	#define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /!< HSE clock divided by 8 /
ganlikun	0:13413ea9a877	327	#define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 9 /
ganlikun	0:13413ea9a877	328	#define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 10 /
ganlikun	0:13413ea9a877	329	#define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 11 /
ganlikun	0:13413ea9a877	330	#define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 12 /
ganlikun	0:13413ea9a877	331	#define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 13 /
ganlikun	0:13413ea9a877	332	#define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 14 /
ganlikun	0:13413ea9a877	333	#define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 15 /
ganlikun	0:13413ea9a877	334	#define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /!< HSE clock divided by 16 /
ganlikun	0:13413ea9a877	335	#define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 17 /
ganlikun	0:13413ea9a877	336	#define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 18 /
ganlikun	0:13413ea9a877	337	#define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 19 /
ganlikun	0:13413ea9a877	338	#define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 20 /
ganlikun	0:13413ea9a877	339	#define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 21 /
ganlikun	0:13413ea9a877	340	#define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 22 /
ganlikun	0:13413ea9a877	341	#define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 23 /
ganlikun	0:13413ea9a877	342	#define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3) /!< HSE clock divided by 24 /
ganlikun	0:13413ea9a877	343	#define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 25 /
ganlikun	0:13413ea9a877	344	#define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 26 /
ganlikun	0:13413ea9a877	345	#define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 27 /
ganlikun	0:13413ea9a877	346	#define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 28 /
ganlikun	0:13413ea9a877	347	#define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 29 /
ganlikun	0:13413ea9a877	348	#define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 30 /
ganlikun	0:13413ea9a877	349	#define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 31 /
ganlikun	0:13413ea9a877	350	/**
ganlikun	0:13413ea9a877	351	* @}
ganlikun	0:13413ea9a877	352	*/
ganlikun	0:13413ea9a877	353
ganlikun	0:13413ea9a877	354	#if defined(USE_FULL_LL_DRIVER)
ganlikun	0:13413ea9a877	355	/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
ganlikun	0:13413ea9a877	356	* @{
ganlikun	0:13413ea9a877	357	*/
ganlikun	0:13413ea9a877	358	#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /!< No clock enabled for the peripheral /
ganlikun	0:13413ea9a877	359	#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /!< Frequency cannot be provided as external clock /
ganlikun	0:13413ea9a877	360	/**
ganlikun	0:13413ea9a877	361	* @}
ganlikun	0:13413ea9a877	362	*/
ganlikun	0:13413ea9a877	363	#endif /* USE_FULL_LL_DRIVER */
ganlikun	0:13413ea9a877	364
ganlikun	0:13413ea9a877	365	#if defined(FMPI2C1)
ganlikun	0:13413ea9a877	366	/** @defgroup RCC_LL_EC_FMPI2C1_CLKSOURCE Peripheral FMPI2C clock source selection
ganlikun	0:13413ea9a877	367	* @{
ganlikun	0:13413ea9a877	368	*/
ganlikun	0:13413ea9a877	369	#define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 0x00000000U /!< PCLK1 clock used as FMPI2C1 clock source /
ganlikun	0:13413ea9a877	370	#define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK RCC_DCKCFGR2_FMPI2C1SEL_0 /!< SYSCLK clock used as FMPI2C1 clock source /
ganlikun	0:13413ea9a877	371	#define LL_RCC_FMPI2C1_CLKSOURCE_HSI RCC_DCKCFGR2_FMPI2C1SEL_1 /!< HSI clock used as FMPI2C1 clock source /
ganlikun	0:13413ea9a877	372	/**
ganlikun	0:13413ea9a877	373	* @}
ganlikun	0:13413ea9a877	374	*/
ganlikun	0:13413ea9a877	375	#endif /* FMPI2C1 */
ganlikun	0:13413ea9a877	376
ganlikun	0:13413ea9a877	377	#if defined(LPTIM1)
ganlikun	0:13413ea9a877	378	/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
ganlikun	0:13413ea9a877	379	* @{
ganlikun	0:13413ea9a877	380	*/
ganlikun	0:13413ea9a877	381	#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /!< PCLK1 clock used as LPTIM1 clock /
ganlikun	0:13413ea9a877	382	#define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_0 /!< LSI oscillator clock used as LPTIM1 clock /
ganlikun	0:13413ea9a877	383	#define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_1 /!< HSI oscillator clock used as LPTIM1 clock /
ganlikun	0:13413ea9a877	384	#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 \| RCC_DCKCFGR2_LPTIM1SEL_0) /!< LSE oscillator clock used as LPTIM1 clock /
ganlikun	0:13413ea9a877	385	/**
ganlikun	0:13413ea9a877	386	* @}
ganlikun	0:13413ea9a877	387	*/
ganlikun	0:13413ea9a877	388	#endif /* LPTIM1 */
ganlikun	0:13413ea9a877	389
ganlikun	0:13413ea9a877	390	#if defined(SAI1)
ganlikun	0:13413ea9a877	391	/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection
ganlikun	0:13413ea9a877	392	* @{
ganlikun	0:13413ea9a877	393	*/
ganlikun	0:13413ea9a877	394	#if defined(RCC_DCKCFGR_SAI1SRC)
ganlikun	0:13413ea9a877	395	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1SRC \| 0x00000000U) /!< PLLSAI clock used as SAI1 clock source /
ganlikun	0:13413ea9a877	396	#define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1SRC \| (RCC_DCKCFGR_SAI1SRC_0 >> 16)) /!< PLLI2S clock used as SAI1 clock source /
ganlikun	0:13413ea9a877	397	#define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1SRC \| (RCC_DCKCFGR_SAI1SRC_1 >> 16)) /!< PLL clock used as SAI1 clock source /
ganlikun	0:13413ea9a877	398	#define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1SRC \| (RCC_DCKCFGR_SAI1SRC >> 16)) /!< External pin clock used as SAI1 clock source /
ganlikun	0:13413ea9a877	399	#endif /* RCC_DCKCFGR_SAI1SRC */
ganlikun	0:13413ea9a877	400	#if defined(RCC_DCKCFGR_SAI2SRC)
ganlikun	0:13413ea9a877	401	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI2SRC \| 0x00000000U) /!< PLLSAI clock used as SAI2 clock source /
ganlikun	0:13413ea9a877	402	#define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI2SRC \| (RCC_DCKCFGR_SAI2SRC_0 >> 16)) /!< PLLI2S clock used as SAI2 clock source /
ganlikun	0:13413ea9a877	403	#define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI2SRC \| (RCC_DCKCFGR_SAI2SRC_1 >> 16)) /!< PLL clock used as SAI2 clock source /
ganlikun	0:13413ea9a877	404	#define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI2SRC \| (RCC_DCKCFGR_SAI2SRC >> 16)) /!< PLL Main clock used as SAI2 clock source /
ganlikun	0:13413ea9a877	405	#endif /* RCC_DCKCFGR_SAI2SRC */
ganlikun	0:13413ea9a877	406	#if defined(RCC_DCKCFGR_SAI1ASRC)
ganlikun	0:13413ea9a877	407	#if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
ganlikun	0:13413ea9a877	408	#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| 0x00000000U) /!< PLLI2S clock used as SAI1 block A clock source /
ganlikun	0:13413ea9a877	409	#define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /!< External pin used as SAI1 block A clock source /
ganlikun	0:13413ea9a877	410	#define LL_RCC_SAI1_A_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /!< PLL clock used as SAI1 block A clock source /
ganlikun	0:13413ea9a877	411	#define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| (RCC_DCKCFGR_SAI1ASRC >> 16)) /!< PLL Main clock used as SAI1 block A clock source /
ganlikun	0:13413ea9a877	412	#else
ganlikun	0:13413ea9a877	413	#define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| 0x00000000U) /!< PLLSAI clock used as SAI1 block A clock source /
ganlikun	0:13413ea9a877	414	#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /!< PLLI2S clock used as SAI1 block A clock source /
ganlikun	0:13413ea9a877	415	#define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /!< External pin clock used as SAI1 block A clock source /
ganlikun	0:13413ea9a877	416	#endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
ganlikun	0:13413ea9a877	417	#endif /* RCC_DCKCFGR_SAI1ASRC */
ganlikun	0:13413ea9a877	418	#if defined(RCC_DCKCFGR_SAI1BSRC)
ganlikun	0:13413ea9a877	419	#if defined(RCC_SAI1B_PLLSOURCE_SUPPORT)
ganlikun	0:13413ea9a877	420	#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| 0x00000000U) /!< PLLI2S clock used as SAI1 block B clock source /
ganlikun	0:13413ea9a877	421	#define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /!< External pin used as SAI1 block B clock source /
ganlikun	0:13413ea9a877	422	#define LL_RCC_SAI1_B_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /!< PLL clock used as SAI1 block B clock source /
ganlikun	0:13413ea9a877	423	#define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| (RCC_DCKCFGR_SAI1BSRC >> 16)) /!< PLL Main clock used as SAI1 block B clock source /
ganlikun	0:13413ea9a877	424	#else
ganlikun	0:13413ea9a877	425	#define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| 0x00000000U) /!< PLLSAI clock used as SAI1 block B clock source /
ganlikun	0:13413ea9a877	426	#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /!< PLLI2S clock used as SAI1 block B clock source /
ganlikun	0:13413ea9a877	427	#define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /!< External pin clock used as SAI1 block B clock source /
ganlikun	0:13413ea9a877	428	#endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */
ganlikun	0:13413ea9a877	429	#endif /* RCC_DCKCFGR_SAI1BSRC */
ganlikun	0:13413ea9a877	430	/**
ganlikun	0:13413ea9a877	431	* @}
ganlikun	0:13413ea9a877	432	*/
ganlikun	0:13413ea9a877	433	#endif /* SAI1 */
ganlikun	0:13413ea9a877	434
ganlikun	0:13413ea9a877	435	#if defined(RCC_DCKCFGR_SDIOSEL) \|\| defined(RCC_DCKCFGR2_SDIOSEL)
ganlikun	0:13413ea9a877	436	/** @defgroup RCC_LL_EC_SDIOx_CLKSOURCE Peripheral SDIO clock source selection
ganlikun	0:13413ea9a877	437	* @{
ganlikun	0:13413ea9a877	438	*/
ganlikun	0:13413ea9a877	439	#define LL_RCC_SDIO_CLKSOURCE_PLL48CLK 0x00000000U /!< PLL 48M domain clock used as SDIO clock /
ganlikun	0:13413ea9a877	440	#if defined(RCC_DCKCFGR_SDIOSEL)
ganlikun	0:13413ea9a877	441	#define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR_SDIOSEL /!< System clock clock used as SDIO clock /
ganlikun	0:13413ea9a877	442	#else
ganlikun	0:13413ea9a877	443	#define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDIOSEL /!< System clock clock used as SDIO clock /
ganlikun	0:13413ea9a877	444	#endif /* RCC_DCKCFGR_SDIOSEL */
ganlikun	0:13413ea9a877	445	/**
ganlikun	0:13413ea9a877	446	* @}
ganlikun	0:13413ea9a877	447	*/
ganlikun	0:13413ea9a877	448	#endif /* RCC_DCKCFGR_SDIOSEL \|\| RCC_DCKCFGR2_SDIOSEL */
ganlikun	0:13413ea9a877	449
ganlikun	0:13413ea9a877	450	#if defined(DSI)
ganlikun	0:13413ea9a877	451	/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
ganlikun	0:13413ea9a877	452	* @{
ganlikun	0:13413ea9a877	453	*/
ganlikun	0:13413ea9a877	454	#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /!< DSI-PHY clock used as DSI byte lane clock source /
ganlikun	0:13413ea9a877	455	#define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR_DSISEL /!< PLL clock used as DSI byte lane clock source /
ganlikun	0:13413ea9a877	456	/**
ganlikun	0:13413ea9a877	457	* @}
ganlikun	0:13413ea9a877	458	*/
ganlikun	0:13413ea9a877	459	#endif /* DSI */
ganlikun	0:13413ea9a877	460
ganlikun	0:13413ea9a877	461	#if defined(CEC)
ganlikun	0:13413ea9a877	462	/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
ganlikun	0:13413ea9a877	463	* @{
ganlikun	0:13413ea9a877	464	*/
ganlikun	0:13413ea9a877	465	#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U /!< HSI oscillator clock divided by 488 used as CEC clock /
ganlikun	0:13413ea9a877	466	#define LL_RCC_CEC_CLKSOURCE_LSE RCC_DCKCFGR2_CECSEL /!< LSE oscillator clock used as CEC clock /
ganlikun	0:13413ea9a877	467	/**
ganlikun	0:13413ea9a877	468	* @}
ganlikun	0:13413ea9a877	469	*/
ganlikun	0:13413ea9a877	470	#endif /* CEC */
ganlikun	0:13413ea9a877	471
ganlikun	0:13413ea9a877	472	/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
ganlikun	0:13413ea9a877	473	* @{
ganlikun	0:13413ea9a877	474	*/
ganlikun	0:13413ea9a877	475	#if defined(RCC_CFGR_I2SSRC)
ganlikun	0:13413ea9a877	476	#define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /!< I2S oscillator clock used as I2S1 clock /
ganlikun	0:13413ea9a877	477	#define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /!< External pin clock used as I2S1 clock /
ganlikun	0:13413ea9a877	478	#endif /* RCC_CFGR_I2SSRC */
ganlikun	0:13413ea9a877	479	#if defined(RCC_DCKCFGR_I2SSRC)
ganlikun	0:13413ea9a877	480	#define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2SSRC \| 0x00000000U) /!< PLL clock used as I2S1 clock source /
ganlikun	0:13413ea9a877	481	#define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2SSRC \| (RCC_DCKCFGR_I2SSRC_0 >> 16)) /!< External pin used as I2S1 clock source /
ganlikun	0:13413ea9a877	482	#define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2SSRC \| (RCC_DCKCFGR_I2SSRC_1 >> 16)) /!< PLL Main clock used as I2S1 clock source /
ganlikun	0:13413ea9a877	483	#endif /* RCC_DCKCFGR_I2SSRC */
ganlikun	0:13413ea9a877	484	#if defined(RCC_DCKCFGR_I2S1SRC)
ganlikun	0:13413ea9a877	485	#define LL_RCC_I2S1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S1SRC \| 0x00000000U) /!< PLLI2S clock used as I2S1 clock source /
ganlikun	0:13413ea9a877	486	#define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S1SRC \| (RCC_DCKCFGR_I2S1SRC_0 >> 16)) /!< External pin used as I2S1 clock source /
ganlikun	0:13413ea9a877	487	#define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S1SRC \| (RCC_DCKCFGR_I2S1SRC_1 >> 16)) /!< PLL clock used as I2S1 clock source /
ganlikun	0:13413ea9a877	488	#define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S1SRC \| (RCC_DCKCFGR_I2S1SRC >> 16)) /!< PLL Main clock used as I2S1 clock source /
ganlikun	0:13413ea9a877	489	#endif /* RCC_DCKCFGR_I2S1SRC */
ganlikun	0:13413ea9a877	490	#if defined(RCC_DCKCFGR_I2S2SRC)
ganlikun	0:13413ea9a877	491	#define LL_RCC_I2S2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S2SRC \| 0x00000000U) /!< PLLI2S clock used as I2S2 clock source /
ganlikun	0:13413ea9a877	492	#define LL_RCC_I2S2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S2SRC \| (RCC_DCKCFGR_I2S2SRC_0 >> 16)) /!< External pin used as I2S2 clock source /
ganlikun	0:13413ea9a877	493	#define LL_RCC_I2S2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S2SRC \| (RCC_DCKCFGR_I2S2SRC_1 >> 16)) /!< PLL clock used as I2S2 clock source /
ganlikun	0:13413ea9a877	494	#define LL_RCC_I2S2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S2SRC \| (RCC_DCKCFGR_I2S2SRC >> 16)) /!< PLL Main clock used as I2S2 clock source /
ganlikun	0:13413ea9a877	495	#endif /* RCC_DCKCFGR_I2S2SRC */
ganlikun	0:13413ea9a877	496	/**
ganlikun	0:13413ea9a877	497	* @}
ganlikun	0:13413ea9a877	498	*/
ganlikun	0:13413ea9a877	499
ganlikun	0:13413ea9a877	500	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
ganlikun	0:13413ea9a877	501	/** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection
ganlikun	0:13413ea9a877	502	* @{
ganlikun	0:13413ea9a877	503	*/
ganlikun	0:13413ea9a877	504	#if defined(RCC_DCKCFGR_CK48MSEL)
ganlikun	0:13413ea9a877	505	#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /!< PLL oscillator clock used as 48Mhz domain clock /
ganlikun	0:13413ea9a877	506	#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR_CK48MSEL /!< PLLSAI oscillator clock used as 48Mhz domain clock /
ganlikun	0:13413ea9a877	507	#endif /* RCC_DCKCFGR_CK48MSEL */
ganlikun	0:13413ea9a877	508	#if defined(RCC_DCKCFGR2_CK48MSEL)
ganlikun	0:13413ea9a877	509	#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /!< PLL oscillator clock used as 48Mhz domain clock /
ganlikun	0:13413ea9a877	510	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	511	#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /!< PLLSAI oscillator clock used as 48Mhz domain clock /
ganlikun	0:13413ea9a877	512	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	513	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
ganlikun	0:13413ea9a877	514	#define LL_RCC_CK48M_CLKSOURCE_PLLI2S RCC_DCKCFGR2_CK48MSEL /!< PLLI2S oscillator clock used as 48Mhz domain clock /
ganlikun	0:13413ea9a877	515	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
ganlikun	0:13413ea9a877	516	#endif /* RCC_DCKCFGR2_CK48MSEL */
ganlikun	0:13413ea9a877	517	/**
ganlikun	0:13413ea9a877	518	* @}
ganlikun	0:13413ea9a877	519	*/
ganlikun	0:13413ea9a877	520
ganlikun	0:13413ea9a877	521	#if defined(RNG)
ganlikun	0:13413ea9a877	522	/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
ganlikun	0:13413ea9a877	523	* @{
ganlikun	0:13413ea9a877	524	*/
ganlikun	0:13413ea9a877	525	#define LL_RCC_RNG_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /!< PLL clock used as RNG clock source /
ganlikun	0:13413ea9a877	526	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	527	#define LL_RCC_RNG_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /!< PLLSAI clock used as RNG clock source /
ganlikun	0:13413ea9a877	528	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	529	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
ganlikun	0:13413ea9a877	530	#define LL_RCC_RNG_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /!< PLLI2S clock used as RNG clock source /
ganlikun	0:13413ea9a877	531	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
ganlikun	0:13413ea9a877	532	/**
ganlikun	0:13413ea9a877	533	* @}
ganlikun	0:13413ea9a877	534	*/
ganlikun	0:13413ea9a877	535	#endif /* RNG */
ganlikun	0:13413ea9a877	536
ganlikun	0:13413ea9a877	537	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
ganlikun	0:13413ea9a877	538	/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
ganlikun	0:13413ea9a877	539	* @{
ganlikun	0:13413ea9a877	540	*/
ganlikun	0:13413ea9a877	541	#define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /!< PLL clock used as USB clock source /
ganlikun	0:13413ea9a877	542	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	543	#define LL_RCC_USB_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /!< PLLSAI clock used as USB clock source /
ganlikun	0:13413ea9a877	544	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	545	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
ganlikun	0:13413ea9a877	546	#define LL_RCC_USB_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /!< PLLI2S clock used as USB clock source /
ganlikun	0:13413ea9a877	547	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
ganlikun	0:13413ea9a877	548	/**
ganlikun	0:13413ea9a877	549	* @}
ganlikun	0:13413ea9a877	550	*/
ganlikun	0:13413ea9a877	551	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
ganlikun	0:13413ea9a877	552
ganlikun	0:13413ea9a877	553	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
ganlikun	0:13413ea9a877	554
ganlikun	0:13413ea9a877	555	#if defined(DFSDM1_Channel0) \|\| defined(DFSDM2_Channel0)
ganlikun	0:13413ea9a877	556	/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection
ganlikun	0:13413ea9a877	557	* @{
ganlikun	0:13413ea9a877	558	*/
ganlikun	0:13413ea9a877	559	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL \| 0x00000000U) /!< I2S1 clock used as DFSDM1 Audio clock source /
ganlikun	0:13413ea9a877	560	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL \| (RCC_DCKCFGR_CKDFSDM1ASEL << 16)) /!< I2S2 clock used as DFSDM1 Audio clock source /
ganlikun	0:13413ea9a877	561	#if defined(DFSDM2_Channel0)
ganlikun	0:13413ea9a877	562	#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL \| 0x00000000U) /!< I2S1 clock used as DFSDM2 Audio clock source /
ganlikun	0:13413ea9a877	563	#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL \| (RCC_DCKCFGR_CKDFSDM2ASEL << 16)) /!< I2S2 clock used as DFSDM2 Audio clock source /
ganlikun	0:13413ea9a877	564	#endif /* DFSDM2_Channel0 */
ganlikun	0:13413ea9a877	565	/**
ganlikun	0:13413ea9a877	566	* @}
ganlikun	0:13413ea9a877	567	*/
ganlikun	0:13413ea9a877	568
ganlikun	0:13413ea9a877	569	/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection
ganlikun	0:13413ea9a877	570	* @{
ganlikun	0:13413ea9a877	571	*/
ganlikun	0:13413ea9a877	572	#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /!< PCLK2 clock used as DFSDM1 clock /
ganlikun	0:13413ea9a877	573	#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /!< System clock used as DFSDM1 clock /
ganlikun	0:13413ea9a877	574	#if defined(DFSDM2_Channel0)
ganlikun	0:13413ea9a877	575	#define LL_RCC_DFSDM2_CLKSOURCE_PCLK2 0x00000000U /!< PCLK2 clock used as DFSDM2 clock /
ganlikun	0:13413ea9a877	576	#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /!< System clock used as DFSDM2 clock /
ganlikun	0:13413ea9a877	577	#endif /* DFSDM2_Channel0 */
ganlikun	0:13413ea9a877	578	/**
ganlikun	0:13413ea9a877	579	* @}
ganlikun	0:13413ea9a877	580	*/
ganlikun	0:13413ea9a877	581	#endif /* DFSDM1_Channel0 \|\| DFSDM2_Channel0 */
ganlikun	0:13413ea9a877	582
ganlikun	0:13413ea9a877	583	#if defined(FMPI2C1)
ganlikun	0:13413ea9a877	584	/** @defgroup RCC_LL_EC_FMPI2C1 Peripheral FMPI2C get clock source
ganlikun	0:13413ea9a877	585	* @{
ganlikun	0:13413ea9a877	586	*/
ganlikun	0:13413ea9a877	587	#define LL_RCC_FMPI2C1_CLKSOURCE RCC_DCKCFGR2_FMPI2C1SEL /!< FMPI2C1 Clock source selection /
ganlikun	0:13413ea9a877	588	/**
ganlikun	0:13413ea9a877	589	* @}
ganlikun	0:13413ea9a877	590	*/
ganlikun	0:13413ea9a877	591	#endif /* FMPI2C1 */
ganlikun	0:13413ea9a877	592
ganlikun	0:13413ea9a877	593	#if defined(SPDIFRX)
ganlikun	0:13413ea9a877	594	/** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE Peripheral SPDIFRX clock source selection
ganlikun	0:13413ea9a877	595	* @{
ganlikun	0:13413ea9a877	596	*/
ganlikun	0:13413ea9a877	597	#define LL_RCC_SPDIFRX1_CLKSOURCE_PLL 0x00000000U /!< PLL clock used as SPDIFRX clock source /
ganlikun	0:13413ea9a877	598	#define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S RCC_DCKCFGR2_SPDIFRXSEL /!< PLLI2S clock used as SPDIFRX clock source /
ganlikun	0:13413ea9a877	599	/**
ganlikun	0:13413ea9a877	600	* @}
ganlikun	0:13413ea9a877	601	*/
ganlikun	0:13413ea9a877	602	#endif /* SPDIFRX */
ganlikun	0:13413ea9a877	603
ganlikun	0:13413ea9a877	604	#if defined(LPTIM1)
ganlikun	0:13413ea9a877	605	/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
ganlikun	0:13413ea9a877	606	* @{
ganlikun	0:13413ea9a877	607	*/
ganlikun	0:13413ea9a877	608	#define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /!< LPTIM1 Clock source selection /
ganlikun	0:13413ea9a877	609	/**
ganlikun	0:13413ea9a877	610	* @}
ganlikun	0:13413ea9a877	611	*/
ganlikun	0:13413ea9a877	612	#endif /* LPTIM1 */
ganlikun	0:13413ea9a877	613
ganlikun	0:13413ea9a877	614	#if defined(SAI1)
ganlikun	0:13413ea9a877	615	/** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source
ganlikun	0:13413ea9a877	616	* @{
ganlikun	0:13413ea9a877	617	*/
ganlikun	0:13413ea9a877	618	#if defined(RCC_DCKCFGR_SAI1ASRC)
ganlikun	0:13413ea9a877	619	#define LL_RCC_SAI1_A_CLKSOURCE RCC_DCKCFGR_SAI1ASRC /!< SAI1 block A Clock source selection /
ganlikun	0:13413ea9a877	620	#endif /* RCC_DCKCFGR_SAI1ASRC */
ganlikun	0:13413ea9a877	621	#if defined(RCC_DCKCFGR_SAI1BSRC)
ganlikun	0:13413ea9a877	622	#define LL_RCC_SAI1_B_CLKSOURCE RCC_DCKCFGR_SAI1BSRC /!< SAI1 block B Clock source selection /
ganlikun	0:13413ea9a877	623	#endif /* RCC_DCKCFGR_SAI1BSRC */
ganlikun	0:13413ea9a877	624	#if defined(RCC_DCKCFGR_SAI1SRC)
ganlikun	0:13413ea9a877	625	#define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR_SAI1SRC /!< SAI1 Clock source selection /
ganlikun	0:13413ea9a877	626	#endif /* RCC_DCKCFGR_SAI1SRC */
ganlikun	0:13413ea9a877	627	#if defined(RCC_DCKCFGR_SAI2SRC)
ganlikun	0:13413ea9a877	628	#define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR_SAI2SRC /!< SAI2 Clock source selection /
ganlikun	0:13413ea9a877	629	#endif /* RCC_DCKCFGR_SAI2SRC */
ganlikun	0:13413ea9a877	630	/**
ganlikun	0:13413ea9a877	631	* @}
ganlikun	0:13413ea9a877	632	*/
ganlikun	0:13413ea9a877	633	#endif /* SAI1 */
ganlikun	0:13413ea9a877	634
ganlikun	0:13413ea9a877	635	#if defined(SDIO)
ganlikun	0:13413ea9a877	636	/** @defgroup RCC_LL_EC_SDIOx Peripheral SDIO get clock source
ganlikun	0:13413ea9a877	637	* @{
ganlikun	0:13413ea9a877	638	*/
ganlikun	0:13413ea9a877	639	#if defined(RCC_DCKCFGR_SDIOSEL)
ganlikun	0:13413ea9a877	640	#define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR_SDIOSEL /!< SDIO Clock source selection /
ganlikun	0:13413ea9a877	641	#elif defined(RCC_DCKCFGR2_SDIOSEL)
ganlikun	0:13413ea9a877	642	#define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR2_SDIOSEL /!< SDIO Clock source selection /
ganlikun	0:13413ea9a877	643	#else
ganlikun	0:13413ea9a877	644	#define LL_RCC_SDIO_CLKSOURCE RCC_PLLCFGR_PLLQ /!< SDIO Clock source selection /
ganlikun	0:13413ea9a877	645	#endif
ganlikun	0:13413ea9a877	646	/**
ganlikun	0:13413ea9a877	647	* @}
ganlikun	0:13413ea9a877	648	*/
ganlikun	0:13413ea9a877	649	#endif /* SDIO */
ganlikun	0:13413ea9a877	650
ganlikun	0:13413ea9a877	651	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
ganlikun	0:13413ea9a877	652	/** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source
ganlikun	0:13413ea9a877	653	* @{
ganlikun	0:13413ea9a877	654	*/
ganlikun	0:13413ea9a877	655	#if defined(RCC_DCKCFGR_CK48MSEL)
ganlikun	0:13413ea9a877	656	#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR_CK48MSEL /!< CK48M Domain clock source selection /
ganlikun	0:13413ea9a877	657	#endif /* RCC_DCKCFGR_CK48MSEL */
ganlikun	0:13413ea9a877	658	#if defined(RCC_DCKCFGR2_CK48MSEL)
ganlikun	0:13413ea9a877	659	#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /!< CK48M Domain clock source selection /
ganlikun	0:13413ea9a877	660	#endif /* RCC_DCKCFGR_CK48MSEL */
ganlikun	0:13413ea9a877	661	/**
ganlikun	0:13413ea9a877	662	* @}
ganlikun	0:13413ea9a877	663	*/
ganlikun	0:13413ea9a877	664	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
ganlikun	0:13413ea9a877	665
ganlikun	0:13413ea9a877	666	#if defined(RNG)
ganlikun	0:13413ea9a877	667	/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
ganlikun	0:13413ea9a877	668	* @{
ganlikun	0:13413ea9a877	669	*/
ganlikun	0:13413ea9a877	670	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
ganlikun	0:13413ea9a877	671	#define LL_RCC_RNG_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /!< RNG Clock source selection /
ganlikun	0:13413ea9a877	672	#else
ganlikun	0:13413ea9a877	673	#define LL_RCC_RNG_CLKSOURCE RCC_PLLCFGR_PLLQ /!< RNG Clock source selection /
ganlikun	0:13413ea9a877	674	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
ganlikun	0:13413ea9a877	675	/**
ganlikun	0:13413ea9a877	676	* @}
ganlikun	0:13413ea9a877	677	*/
ganlikun	0:13413ea9a877	678	#endif /* RNG */
ganlikun	0:13413ea9a877	679
ganlikun	0:13413ea9a877	680	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
ganlikun	0:13413ea9a877	681	/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
ganlikun	0:13413ea9a877	682	* @{
ganlikun	0:13413ea9a877	683	*/
ganlikun	0:13413ea9a877	684	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
ganlikun	0:13413ea9a877	685	#define LL_RCC_USB_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /!< USB Clock source selection /
ganlikun	0:13413ea9a877	686	#else
ganlikun	0:13413ea9a877	687	#define LL_RCC_USB_CLKSOURCE RCC_PLLCFGR_PLLQ /!< USB Clock source selection /
ganlikun	0:13413ea9a877	688	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
ganlikun	0:13413ea9a877	689	/**
ganlikun	0:13413ea9a877	690	* @}
ganlikun	0:13413ea9a877	691	*/
ganlikun	0:13413ea9a877	692	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
ganlikun	0:13413ea9a877	693
ganlikun	0:13413ea9a877	694	#if defined(CEC)
ganlikun	0:13413ea9a877	695	/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
ganlikun	0:13413ea9a877	696	* @{
ganlikun	0:13413ea9a877	697	*/
ganlikun	0:13413ea9a877	698	#define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /!< CEC Clock source selection /
ganlikun	0:13413ea9a877	699	/**
ganlikun	0:13413ea9a877	700	* @}
ganlikun	0:13413ea9a877	701	*/
ganlikun	0:13413ea9a877	702	#endif /* CEC */
ganlikun	0:13413ea9a877	703
ganlikun	0:13413ea9a877	704	/** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
ganlikun	0:13413ea9a877	705	* @{
ganlikun	0:13413ea9a877	706	*/
ganlikun	0:13413ea9a877	707	#if defined(RCC_CFGR_I2SSRC)
ganlikun	0:13413ea9a877	708	#define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /!< I2S1 Clock source selection /
ganlikun	0:13413ea9a877	709	#endif /* RCC_CFGR_I2SSRC */
ganlikun	0:13413ea9a877	710	#if defined(RCC_DCKCFGR_I2SSRC)
ganlikun	0:13413ea9a877	711	#define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2SSRC /!< I2S1 Clock source selection /
ganlikun	0:13413ea9a877	712	#endif /* RCC_DCKCFGR_I2SSRC */
ganlikun	0:13413ea9a877	713	#if defined(RCC_DCKCFGR_I2S1SRC)
ganlikun	0:13413ea9a877	714	#define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2S1SRC /!< I2S1 Clock source selection /
ganlikun	0:13413ea9a877	715	#endif /* RCC_DCKCFGR_I2S1SRC */
ganlikun	0:13413ea9a877	716	#if defined(RCC_DCKCFGR_I2S2SRC)
ganlikun	0:13413ea9a877	717	#define LL_RCC_I2S2_CLKSOURCE RCC_DCKCFGR_I2S2SRC /!< I2S2 Clock source selection /
ganlikun	0:13413ea9a877	718	#endif /* RCC_DCKCFGR_I2S2SRC */
ganlikun	0:13413ea9a877	719	/**
ganlikun	0:13413ea9a877	720	* @}
ganlikun	0:13413ea9a877	721	*/
ganlikun	0:13413ea9a877	722
ganlikun	0:13413ea9a877	723	#if defined(DFSDM1_Channel0) \|\| defined(DFSDM2_Channel0)
ganlikun	0:13413ea9a877	724	/** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source
ganlikun	0:13413ea9a877	725	* @{
ganlikun	0:13413ea9a877	726	*/
ganlikun	0:13413ea9a877	727	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM1ASEL /!< DFSDM1 Audio Clock source selection /
ganlikun	0:13413ea9a877	728	#if defined(DFSDM2_Channel0)
ganlikun	0:13413ea9a877	729	#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM2ASEL /!< DFSDM2 Audio Clock source selection /
ganlikun	0:13413ea9a877	730	#endif /* DFSDM2_Channel0 */
ganlikun	0:13413ea9a877	731	/**
ganlikun	0:13413ea9a877	732	* @}
ganlikun	0:13413ea9a877	733	*/
ganlikun	0:13413ea9a877	734
ganlikun	0:13413ea9a877	735	/** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
ganlikun	0:13413ea9a877	736	* @{
ganlikun	0:13413ea9a877	737	*/
ganlikun	0:13413ea9a877	738	#define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /!< DFSDM1 Clock source selection /
ganlikun	0:13413ea9a877	739	#if defined(DFSDM2_Channel0)
ganlikun	0:13413ea9a877	740	#define LL_RCC_DFSDM2_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /!< DFSDM2 Clock source selection /
ganlikun	0:13413ea9a877	741	#endif /* DFSDM2_Channel0 */
ganlikun	0:13413ea9a877	742	/**
ganlikun	0:13413ea9a877	743	* @}
ganlikun	0:13413ea9a877	744	*/
ganlikun	0:13413ea9a877	745	#endif /* DFSDM1_Channel0 \|\| DFSDM2_Channel0 */
ganlikun	0:13413ea9a877	746
ganlikun	0:13413ea9a877	747	#if defined(SPDIFRX)
ganlikun	0:13413ea9a877	748	/** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source
ganlikun	0:13413ea9a877	749	* @{
ganlikun	0:13413ea9a877	750	*/
ganlikun	0:13413ea9a877	751	#define LL_RCC_SPDIFRX1_CLKSOURCE RCC_DCKCFGR2_SPDIFRXSEL /!< SPDIFRX Clock source selection /
ganlikun	0:13413ea9a877	752	/**
ganlikun	0:13413ea9a877	753	* @}
ganlikun	0:13413ea9a877	754	*/
ganlikun	0:13413ea9a877	755	#endif /* SPDIFRX */
ganlikun	0:13413ea9a877	756
ganlikun	0:13413ea9a877	757	#if defined(DSI)
ganlikun	0:13413ea9a877	758	/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
ganlikun	0:13413ea9a877	759	* @{
ganlikun	0:13413ea9a877	760	*/
ganlikun	0:13413ea9a877	761	#define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR_DSISEL /!< DSI Clock source selection /
ganlikun	0:13413ea9a877	762	/**
ganlikun	0:13413ea9a877	763	* @}
ganlikun	0:13413ea9a877	764	*/
ganlikun	0:13413ea9a877	765	#endif /* DSI */
ganlikun	0:13413ea9a877	766
ganlikun	0:13413ea9a877	767	#if defined(LTDC)
ganlikun	0:13413ea9a877	768	/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
ganlikun	0:13413ea9a877	769	* @{
ganlikun	0:13413ea9a877	770	*/
ganlikun	0:13413ea9a877	771	#define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR_PLLSAIDIVR /!< LTDC Clock source selection /
ganlikun	0:13413ea9a877	772	/**
ganlikun	0:13413ea9a877	773	* @}
ganlikun	0:13413ea9a877	774	*/
ganlikun	0:13413ea9a877	775	#endif /* LTDC */
ganlikun	0:13413ea9a877	776
ganlikun	0:13413ea9a877	777
ganlikun	0:13413ea9a877	778	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
ganlikun	0:13413ea9a877	779	* @{
ganlikun	0:13413ea9a877	780	*/
ganlikun	0:13413ea9a877	781	#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /!< No clock used as RTC clock /
ganlikun	0:13413ea9a877	782	#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
ganlikun	0:13413ea9a877	783	#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
ganlikun	0:13413ea9a877	784	#define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by HSE prescaler used as RTC clock /
ganlikun	0:13413ea9a877	785	/**
ganlikun	0:13413ea9a877	786	* @}
ganlikun	0:13413ea9a877	787	*/
ganlikun	0:13413ea9a877	788
ganlikun	0:13413ea9a877	789	#if defined(RCC_DCKCFGR_TIMPRE)
ganlikun	0:13413ea9a877	790	/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
ganlikun	0:13413ea9a877	791	* @{
ganlikun	0:13413ea9a877	792	*/
ganlikun	0:13413ea9a877	793	#define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /!< Timers clock to twice PCLK /
ganlikun	0:13413ea9a877	794	#define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR_TIMPRE /!< Timers clock to four time PCLK /
ganlikun	0:13413ea9a877	795	/**
ganlikun	0:13413ea9a877	796	* @}
ganlikun	0:13413ea9a877	797	*/
ganlikun	0:13413ea9a877	798	#endif /* RCC_DCKCFGR_TIMPRE */
ganlikun	0:13413ea9a877	799
ganlikun	0:13413ea9a877	800	/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source
ganlikun	0:13413ea9a877	801	* @{
ganlikun	0:13413ea9a877	802	*/
ganlikun	0:13413ea9a877	803	#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /!< HSI16 clock selected as PLL entry clock source /
ganlikun	0:13413ea9a877	804	#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
ganlikun	0:13413ea9a877	805	#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
ganlikun	0:13413ea9a877	806	#define LL_RCC_PLLI2SSOURCE_PIN (RCC_PLLI2SCFGR_PLLI2SSRC \| 0x80U) /!< I2S External pin input clock selected as PLLI2S entry clock source /
ganlikun	0:13413ea9a877	807	#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
ganlikun	0:13413ea9a877	808	/**
ganlikun	0:13413ea9a877	809	* @}
ganlikun	0:13413ea9a877	810	*/
ganlikun	0:13413ea9a877	811
ganlikun	0:13413ea9a877	812	/** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor
ganlikun	0:13413ea9a877	813	* @{
ganlikun	0:13413ea9a877	814	*/
ganlikun	0:13413ea9a877	815	#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 2 /
ganlikun	0:13413ea9a877	816	#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 3 /
ganlikun	0:13413ea9a877	817	#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 4 /
ganlikun	0:13413ea9a877	818	#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 5 /
ganlikun	0:13413ea9a877	819	#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 6 /
ganlikun	0:13413ea9a877	820	#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 7 /
ganlikun	0:13413ea9a877	821	#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 8 /
ganlikun	0:13413ea9a877	822	#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 9 /
ganlikun	0:13413ea9a877	823	#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 10 /
ganlikun	0:13413ea9a877	824	#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 11 /
ganlikun	0:13413ea9a877	825	#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 12 /
ganlikun	0:13413ea9a877	826	#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 13 /
ganlikun	0:13413ea9a877	827	#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 14 /
ganlikun	0:13413ea9a877	828	#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 15 /
ganlikun	0:13413ea9a877	829	#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /!< PLL, PLLI2S and PLLSAI division factor by 16 /
ganlikun	0:13413ea9a877	830	#define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 17 /
ganlikun	0:13413ea9a877	831	#define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 18 /
ganlikun	0:13413ea9a877	832	#define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 19 /
ganlikun	0:13413ea9a877	833	#define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 20 /
ganlikun	0:13413ea9a877	834	#define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 21 /
ganlikun	0:13413ea9a877	835	#define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 22 /
ganlikun	0:13413ea9a877	836	#define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 23 /
ganlikun	0:13413ea9a877	837	#define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 24 /
ganlikun	0:13413ea9a877	838	#define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 25 /
ganlikun	0:13413ea9a877	839	#define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 26 /
ganlikun	0:13413ea9a877	840	#define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 27 /
ganlikun	0:13413ea9a877	841	#define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 28 /
ganlikun	0:13413ea9a877	842	#define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 29 /
ganlikun	0:13413ea9a877	843	#define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 30 /
ganlikun	0:13413ea9a877	844	#define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 31 /
ganlikun	0:13413ea9a877	845	#define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /!< PLL, PLLI2S and PLLSAI division factor by 32 /
ganlikun	0:13413ea9a877	846	#define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 33 /
ganlikun	0:13413ea9a877	847	#define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 34 /
ganlikun	0:13413ea9a877	848	#define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 35 /
ganlikun	0:13413ea9a877	849	#define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 36 /
ganlikun	0:13413ea9a877	850	#define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 37 /
ganlikun	0:13413ea9a877	851	#define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 38 /
ganlikun	0:13413ea9a877	852	#define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 39 /
ganlikun	0:13413ea9a877	853	#define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 40 /
ganlikun	0:13413ea9a877	854	#define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 41 /
ganlikun	0:13413ea9a877	855	#define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 42 /
ganlikun	0:13413ea9a877	856	#define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 43 /
ganlikun	0:13413ea9a877	857	#define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 44 /
ganlikun	0:13413ea9a877	858	#define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 45 /
ganlikun	0:13413ea9a877	859	#define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 46 /
ganlikun	0:13413ea9a877	860	#define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 47 /
ganlikun	0:13413ea9a877	861	#define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4) /!< PLL, PLLI2S and PLLSAI division factor by 48 /
ganlikun	0:13413ea9a877	862	#define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 49 /
ganlikun	0:13413ea9a877	863	#define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 50 /
ganlikun	0:13413ea9a877	864	#define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 51 /
ganlikun	0:13413ea9a877	865	#define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 52 /
ganlikun	0:13413ea9a877	866	#define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 53 /
ganlikun	0:13413ea9a877	867	#define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 54 /
ganlikun	0:13413ea9a877	868	#define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 55 /
ganlikun	0:13413ea9a877	869	#define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 56 /
ganlikun	0:13413ea9a877	870	#define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 57 /
ganlikun	0:13413ea9a877	871	#define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 58 /
ganlikun	0:13413ea9a877	872	#define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 59 /
ganlikun	0:13413ea9a877	873	#define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 60 /
ganlikun	0:13413ea9a877	874	#define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 61 /
ganlikun	0:13413ea9a877	875	#define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 62 /
ganlikun	0:13413ea9a877	876	#define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 63 /
ganlikun	0:13413ea9a877	877	/**
ganlikun	0:13413ea9a877	878	* @}
ganlikun	0:13413ea9a877	879	*/
ganlikun	0:13413ea9a877	880
ganlikun	0:13413ea9a877	881	#if defined(RCC_PLLCFGR_PLLR)
ganlikun	0:13413ea9a877	882	/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
ganlikun	0:13413ea9a877	883	* @{
ganlikun	0:13413ea9a877	884	*/
ganlikun	0:13413ea9a877	885	#define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /!< Main PLL division factor for PLLCLK (system clock) by 2 /
ganlikun	0:13413ea9a877	886	#define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1\|RCC_PLLCFGR_PLLR_0) /!< Main PLL division factor for PLLCLK (system clock) by 3 /
ganlikun	0:13413ea9a877	887	#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /!< Main PLL division factor for PLLCLK (system clock) by 4 /
ganlikun	0:13413ea9a877	888	#define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2\|RCC_PLLCFGR_PLLR_0) /!< Main PLL division factor for PLLCLK (system clock) by 5 /
ganlikun	0:13413ea9a877	889	#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2\|RCC_PLLCFGR_PLLR_1) /!< Main PLL division factor for PLLCLK (system clock) by 6 /
ganlikun	0:13413ea9a877	890	#define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /!< Main PLL division factor for PLLCLK (system clock) by 7 /
ganlikun	0:13413ea9a877	891	/**
ganlikun	0:13413ea9a877	892	* @}
ganlikun	0:13413ea9a877	893	*/
ganlikun	0:13413ea9a877	894	#endif /* RCC_PLLCFGR_PLLR */
ganlikun	0:13413ea9a877	895
ganlikun	0:13413ea9a877	896	#if defined(RCC_DCKCFGR_PLLDIVR)
ganlikun	0:13413ea9a877	897	/** @defgroup RCC_LL_EC_PLLDIVR PLLDIVR division factor (PLLDIVR)
ganlikun	0:13413ea9a877	898	* @{
ganlikun	0:13413ea9a877	899	*/
ganlikun	0:13413ea9a877	900	#define LL_RCC_PLLDIVR_DIV_1 (RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 1 /
ganlikun	0:13413ea9a877	901	#define LL_RCC_PLLDIVR_DIV_2 (RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 2 /
ganlikun	0:13413ea9a877	902	#define LL_RCC_PLLDIVR_DIV_3 (RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 3 /
ganlikun	0:13413ea9a877	903	#define LL_RCC_PLLDIVR_DIV_4 (RCC_DCKCFGR_PLLDIVR_2) /!< PLL division factor for PLLDIVR output by 4 /
ganlikun	0:13413ea9a877	904	#define LL_RCC_PLLDIVR_DIV_5 (RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 5 /
ganlikun	0:13413ea9a877	905	#define LL_RCC_PLLDIVR_DIV_6 (RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 6 /
ganlikun	0:13413ea9a877	906	#define LL_RCC_PLLDIVR_DIV_7 (RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 7 /
ganlikun	0:13413ea9a877	907	#define LL_RCC_PLLDIVR_DIV_8 (RCC_DCKCFGR_PLLDIVR_3) /!< PLL division factor for PLLDIVR output by 8 /
ganlikun	0:13413ea9a877	908	#define LL_RCC_PLLDIVR_DIV_9 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 9 /
ganlikun	0:13413ea9a877	909	#define LL_RCC_PLLDIVR_DIV_10 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 10 /
ganlikun	0:13413ea9a877	910	#define LL_RCC_PLLDIVR_DIV_11 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 11 /
ganlikun	0:13413ea9a877	911	#define LL_RCC_PLLDIVR_DIV_12 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2) /!< PLL division factor for PLLDIVR output by 12 /
ganlikun	0:13413ea9a877	912	#define LL_RCC_PLLDIVR_DIV_13 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 13 /
ganlikun	0:13413ea9a877	913	#define LL_RCC_PLLDIVR_DIV_14 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 14 /
ganlikun	0:13413ea9a877	914	#define LL_RCC_PLLDIVR_DIV_15 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 15 /
ganlikun	0:13413ea9a877	915	#define LL_RCC_PLLDIVR_DIV_16 (RCC_DCKCFGR_PLLDIVR_4) /!< PLL division factor for PLLDIVR output by 16 /
ganlikun	0:13413ea9a877	916	#define LL_RCC_PLLDIVR_DIV_17 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 17 /
ganlikun	0:13413ea9a877	917	#define LL_RCC_PLLDIVR_DIV_18 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 18 /
ganlikun	0:13413ea9a877	918	#define LL_RCC_PLLDIVR_DIV_19 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 19 /
ganlikun	0:13413ea9a877	919	#define LL_RCC_PLLDIVR_DIV_20 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_2) /!< PLL division factor for PLLDIVR output by 20 /
ganlikun	0:13413ea9a877	920	#define LL_RCC_PLLDIVR_DIV_21 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 21 /
ganlikun	0:13413ea9a877	921	#define LL_RCC_PLLDIVR_DIV_22 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 22 /
ganlikun	0:13413ea9a877	922	#define LL_RCC_PLLDIVR_DIV_23 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 23 /
ganlikun	0:13413ea9a877	923	#define LL_RCC_PLLDIVR_DIV_24 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3) /!< PLL division factor for PLLDIVR output by 24 /
ganlikun	0:13413ea9a877	924	#define LL_RCC_PLLDIVR_DIV_25 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 25 /
ganlikun	0:13413ea9a877	925	#define LL_RCC_PLLDIVR_DIV_26 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 26 /
ganlikun	0:13413ea9a877	926	#define LL_RCC_PLLDIVR_DIV_27 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 27 /
ganlikun	0:13413ea9a877	927	#define LL_RCC_PLLDIVR_DIV_28 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2) /!< PLL division factor for PLLDIVR output by 28 /
ganlikun	0:13413ea9a877	928	#define LL_RCC_PLLDIVR_DIV_29 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 29 /
ganlikun	0:13413ea9a877	929	#define LL_RCC_PLLDIVR_DIV_30 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 30 /
ganlikun	0:13413ea9a877	930	#define LL_RCC_PLLDIVR_DIV_31 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 31 /
ganlikun	0:13413ea9a877	931	/**
ganlikun	0:13413ea9a877	932	* @}
ganlikun	0:13413ea9a877	933	*/
ganlikun	0:13413ea9a877	934	#endif /* RCC_DCKCFGR_PLLDIVR */
ganlikun	0:13413ea9a877	935
ganlikun	0:13413ea9a877	936	/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
ganlikun	0:13413ea9a877	937	* @{
ganlikun	0:13413ea9a877	938	*/
ganlikun	0:13413ea9a877	939	#define LL_RCC_PLLP_DIV_2 0x00000000U /!< Main PLL division factor for PLLP output by 2 /
ganlikun	0:13413ea9a877	940	#define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /!< Main PLL division factor for PLLP output by 4 /
ganlikun	0:13413ea9a877	941	#define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /!< Main PLL division factor for PLLP output by 6 /
ganlikun	0:13413ea9a877	942	#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 \| RCC_PLLCFGR_PLLP_0) /!< Main PLL division factor for PLLP output by 8 /
ganlikun	0:13413ea9a877	943	/**
ganlikun	0:13413ea9a877	944	* @}
ganlikun	0:13413ea9a877	945	*/
ganlikun	0:13413ea9a877	946
ganlikun	0:13413ea9a877	947	/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
ganlikun	0:13413ea9a877	948	* @{
ganlikun	0:13413ea9a877	949	*/
ganlikun	0:13413ea9a877	950	#define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /!< Main PLL division factor for PLLQ output by 2 /
ganlikun	0:13413ea9a877	951	#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 3 /
ganlikun	0:13413ea9a877	952	#define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /!< Main PLL division factor for PLLQ output by 4 /
ganlikun	0:13413ea9a877	953	#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 5 /
ganlikun	0:13413ea9a877	954	#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 6 /
ganlikun	0:13413ea9a877	955	#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 7 /
ganlikun	0:13413ea9a877	956	#define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /!< Main PLL division factor for PLLQ output by 8 /
ganlikun	0:13413ea9a877	957	#define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 9 /
ganlikun	0:13413ea9a877	958	#define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 10 /
ganlikun	0:13413ea9a877	959	#define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 11 /
ganlikun	0:13413ea9a877	960	#define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2) /!< Main PLL division factor for PLLQ output by 12 /
ganlikun	0:13413ea9a877	961	#define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 13 /
ganlikun	0:13413ea9a877	962	#define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 14 /
ganlikun	0:13413ea9a877	963	#define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 15 /
ganlikun	0:13413ea9a877	964	/**
ganlikun	0:13413ea9a877	965	* @}
ganlikun	0:13413ea9a877	966	*/
ganlikun	0:13413ea9a877	967
ganlikun	0:13413ea9a877	968	/** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection
ganlikun	0:13413ea9a877	969	* @{
ganlikun	0:13413ea9a877	970	*/
ganlikun	0:13413ea9a877	971	#define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /!< PLL center spread spectrum selection /
ganlikun	0:13413ea9a877	972	#define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /!< PLL down spread spectrum selection /
ganlikun	0:13413ea9a877	973	/**
ganlikun	0:13413ea9a877	974	* @}
ganlikun	0:13413ea9a877	975	*/
ganlikun	0:13413ea9a877	976
ganlikun	0:13413ea9a877	977	#if defined(RCC_PLLI2S_SUPPORT)
ganlikun	0:13413ea9a877	978	/** @defgroup RCC_LL_EC_PLLI2SM PLLI2SM division factor (PLLI2SM)
ganlikun	0:13413ea9a877	979	* @{
ganlikun	0:13413ea9a877	980	*/
ganlikun	0:13413ea9a877	981	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
ganlikun	0:13413ea9a877	982	#define LL_RCC_PLLI2SM_DIV_2 (RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 2 /
ganlikun	0:13413ea9a877	983	#define LL_RCC_PLLI2SM_DIV_3 (RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 3 /
ganlikun	0:13413ea9a877	984	#define LL_RCC_PLLI2SM_DIV_4 (RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 4 /
ganlikun	0:13413ea9a877	985	#define LL_RCC_PLLI2SM_DIV_5 (RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 5 /
ganlikun	0:13413ea9a877	986	#define LL_RCC_PLLI2SM_DIV_6 (RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 6 /
ganlikun	0:13413ea9a877	987	#define LL_RCC_PLLI2SM_DIV_7 (RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 7 /
ganlikun	0:13413ea9a877	988	#define LL_RCC_PLLI2SM_DIV_8 (RCC_PLLI2SCFGR_PLLI2SM_3) /!< PLLI2S division factor for PLLI2SM output by 8 /
ganlikun	0:13413ea9a877	989	#define LL_RCC_PLLI2SM_DIV_9 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 9 /
ganlikun	0:13413ea9a877	990	#define LL_RCC_PLLI2SM_DIV_10 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 10 /
ganlikun	0:13413ea9a877	991	#define LL_RCC_PLLI2SM_DIV_11 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 11 /
ganlikun	0:13413ea9a877	992	#define LL_RCC_PLLI2SM_DIV_12 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 12 /
ganlikun	0:13413ea9a877	993	#define LL_RCC_PLLI2SM_DIV_13 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 13 /
ganlikun	0:13413ea9a877	994	#define LL_RCC_PLLI2SM_DIV_14 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 14 /
ganlikun	0:13413ea9a877	995	#define LL_RCC_PLLI2SM_DIV_15 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 15 /
ganlikun	0:13413ea9a877	996	#define LL_RCC_PLLI2SM_DIV_16 (RCC_PLLI2SCFGR_PLLI2SM_4) /!< PLLI2S division factor for PLLI2SM output by 16 /
ganlikun	0:13413ea9a877	997	#define LL_RCC_PLLI2SM_DIV_17 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 17 /
ganlikun	0:13413ea9a877	998	#define LL_RCC_PLLI2SM_DIV_18 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 18 /
ganlikun	0:13413ea9a877	999	#define LL_RCC_PLLI2SM_DIV_19 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 19 /
ganlikun	0:13413ea9a877	1000	#define LL_RCC_PLLI2SM_DIV_20 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 20 /
ganlikun	0:13413ea9a877	1001	#define LL_RCC_PLLI2SM_DIV_21 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 21 /
ganlikun	0:13413ea9a877	1002	#define LL_RCC_PLLI2SM_DIV_22 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 22 /
ganlikun	0:13413ea9a877	1003	#define LL_RCC_PLLI2SM_DIV_23 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 23 /
ganlikun	0:13413ea9a877	1004	#define LL_RCC_PLLI2SM_DIV_24 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3) /!< PLLI2S division factor for PLLI2SM output by 24 /
ganlikun	0:13413ea9a877	1005	#define LL_RCC_PLLI2SM_DIV_25 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 25 /
ganlikun	0:13413ea9a877	1006	#define LL_RCC_PLLI2SM_DIV_26 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 26 /
ganlikun	0:13413ea9a877	1007	#define LL_RCC_PLLI2SM_DIV_27 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 27 /
ganlikun	0:13413ea9a877	1008	#define LL_RCC_PLLI2SM_DIV_28 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 28 /
ganlikun	0:13413ea9a877	1009	#define LL_RCC_PLLI2SM_DIV_29 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 29 /
ganlikun	0:13413ea9a877	1010	#define LL_RCC_PLLI2SM_DIV_30 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 30 /
ganlikun	0:13413ea9a877	1011	#define LL_RCC_PLLI2SM_DIV_31 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 31 /
ganlikun	0:13413ea9a877	1012	#define LL_RCC_PLLI2SM_DIV_32 (RCC_PLLI2SCFGR_PLLI2SM_5) /!< PLLI2S division factor for PLLI2SM output by 32 /
ganlikun	0:13413ea9a877	1013	#define LL_RCC_PLLI2SM_DIV_33 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 33 /
ganlikun	0:13413ea9a877	1014	#define LL_RCC_PLLI2SM_DIV_34 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 34 /
ganlikun	0:13413ea9a877	1015	#define LL_RCC_PLLI2SM_DIV_35 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 35 /
ganlikun	0:13413ea9a877	1016	#define LL_RCC_PLLI2SM_DIV_36 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 36 /
ganlikun	0:13413ea9a877	1017	#define LL_RCC_PLLI2SM_DIV_37 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 37 /
ganlikun	0:13413ea9a877	1018	#define LL_RCC_PLLI2SM_DIV_38 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 38 /
ganlikun	0:13413ea9a877	1019	#define LL_RCC_PLLI2SM_DIV_39 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 39 /
ganlikun	0:13413ea9a877	1020	#define LL_RCC_PLLI2SM_DIV_40 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3) /!< PLLI2S division factor for PLLI2SM output by 40 /
ganlikun	0:13413ea9a877	1021	#define LL_RCC_PLLI2SM_DIV_41 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 41 /
ganlikun	0:13413ea9a877	1022	#define LL_RCC_PLLI2SM_DIV_42 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 42 /
ganlikun	0:13413ea9a877	1023	#define LL_RCC_PLLI2SM_DIV_43 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 43 /
ganlikun	0:13413ea9a877	1024	#define LL_RCC_PLLI2SM_DIV_44 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 44 /
ganlikun	0:13413ea9a877	1025	#define LL_RCC_PLLI2SM_DIV_45 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 45 /
ganlikun	0:13413ea9a877	1026	#define LL_RCC_PLLI2SM_DIV_46 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 46 /
ganlikun	0:13413ea9a877	1027	#define LL_RCC_PLLI2SM_DIV_47 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 47 /
ganlikun	0:13413ea9a877	1028	#define LL_RCC_PLLI2SM_DIV_48 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4) /!< PLLI2S division factor for PLLI2SM output by 48 /
ganlikun	0:13413ea9a877	1029	#define LL_RCC_PLLI2SM_DIV_49 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 49 /
ganlikun	0:13413ea9a877	1030	#define LL_RCC_PLLI2SM_DIV_50 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 50 /
ganlikun	0:13413ea9a877	1031	#define LL_RCC_PLLI2SM_DIV_51 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 51 /
ganlikun	0:13413ea9a877	1032	#define LL_RCC_PLLI2SM_DIV_52 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 52 /
ganlikun	0:13413ea9a877	1033	#define LL_RCC_PLLI2SM_DIV_53 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 53 /
ganlikun	0:13413ea9a877	1034	#define LL_RCC_PLLI2SM_DIV_54 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 54 /
ganlikun	0:13413ea9a877	1035	#define LL_RCC_PLLI2SM_DIV_55 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 55 /
ganlikun	0:13413ea9a877	1036	#define LL_RCC_PLLI2SM_DIV_56 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3) /!< PLLI2S division factor for PLLI2SM output by 56 /
ganlikun	0:13413ea9a877	1037	#define LL_RCC_PLLI2SM_DIV_57 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 57 /
ganlikun	0:13413ea9a877	1038	#define LL_RCC_PLLI2SM_DIV_58 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 58 /
ganlikun	0:13413ea9a877	1039	#define LL_RCC_PLLI2SM_DIV_59 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 59 /
ganlikun	0:13413ea9a877	1040	#define LL_RCC_PLLI2SM_DIV_60 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 60 /
ganlikun	0:13413ea9a877	1041	#define LL_RCC_PLLI2SM_DIV_61 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 61 /
ganlikun	0:13413ea9a877	1042	#define LL_RCC_PLLI2SM_DIV_62 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 62 /
ganlikun	0:13413ea9a877	1043	#define LL_RCC_PLLI2SM_DIV_63 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 63 /
ganlikun	0:13413ea9a877	1044	#else
ganlikun	0:13413ea9a877	1045	#define LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLM_DIV_2 /!< PLLI2S division factor for PLLI2SM output by 2 /
ganlikun	0:13413ea9a877	1046	#define LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLM_DIV_3 /!< PLLI2S division factor for PLLI2SM output by 3 /
ganlikun	0:13413ea9a877	1047	#define LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLM_DIV_4 /!< PLLI2S division factor for PLLI2SM output by 4 /
ganlikun	0:13413ea9a877	1048	#define LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLM_DIV_5 /!< PLLI2S division factor for PLLI2SM output by 5 /
ganlikun	0:13413ea9a877	1049	#define LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLM_DIV_6 /!< PLLI2S division factor for PLLI2SM output by 6 /
ganlikun	0:13413ea9a877	1050	#define LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLM_DIV_7 /!< PLLI2S division factor for PLLI2SM output by 7 /
ganlikun	0:13413ea9a877	1051	#define LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLM_DIV_8 /!< PLLI2S division factor for PLLI2SM output by 8 /
ganlikun	0:13413ea9a877	1052	#define LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLM_DIV_9 /!< PLLI2S division factor for PLLI2SM output by 9 /
ganlikun	0:13413ea9a877	1053	#define LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLM_DIV_10 /!< PLLI2S division factor for PLLI2SM output by 10 /
ganlikun	0:13413ea9a877	1054	#define LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLM_DIV_11 /!< PLLI2S division factor for PLLI2SM output by 11 /
ganlikun	0:13413ea9a877	1055	#define LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLM_DIV_12 /!< PLLI2S division factor for PLLI2SM output by 12 /
ganlikun	0:13413ea9a877	1056	#define LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLM_DIV_13 /!< PLLI2S division factor for PLLI2SM output by 13 /
ganlikun	0:13413ea9a877	1057	#define LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLM_DIV_14 /!< PLLI2S division factor for PLLI2SM output by 14 /
ganlikun	0:13413ea9a877	1058	#define LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLM_DIV_15 /!< PLLI2S division factor for PLLI2SM output by 15 /
ganlikun	0:13413ea9a877	1059	#define LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLM_DIV_16 /!< PLLI2S division factor for PLLI2SM output by 16 /
ganlikun	0:13413ea9a877	1060	#define LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLM_DIV_17 /!< PLLI2S division factor for PLLI2SM output by 17 /
ganlikun	0:13413ea9a877	1061	#define LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLM_DIV_18 /!< PLLI2S division factor for PLLI2SM output by 18 /
ganlikun	0:13413ea9a877	1062	#define LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLM_DIV_19 /!< PLLI2S division factor for PLLI2SM output by 19 /
ganlikun	0:13413ea9a877	1063	#define LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLM_DIV_20 /!< PLLI2S division factor for PLLI2SM output by 20 /
ganlikun	0:13413ea9a877	1064	#define LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLM_DIV_21 /!< PLLI2S division factor for PLLI2SM output by 21 /
ganlikun	0:13413ea9a877	1065	#define LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLM_DIV_22 /!< PLLI2S division factor for PLLI2SM output by 22 /
ganlikun	0:13413ea9a877	1066	#define LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLM_DIV_23 /!< PLLI2S division factor for PLLI2SM output by 23 /
ganlikun	0:13413ea9a877	1067	#define LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLM_DIV_24 /!< PLLI2S division factor for PLLI2SM output by 24 /
ganlikun	0:13413ea9a877	1068	#define LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLM_DIV_25 /!< PLLI2S division factor for PLLI2SM output by 25 /
ganlikun	0:13413ea9a877	1069	#define LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLM_DIV_26 /!< PLLI2S division factor for PLLI2SM output by 26 /
ganlikun	0:13413ea9a877	1070	#define LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLM_DIV_27 /!< PLLI2S division factor for PLLI2SM output by 27 /
ganlikun	0:13413ea9a877	1071	#define LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLM_DIV_28 /!< PLLI2S division factor for PLLI2SM output by 28 /
ganlikun	0:13413ea9a877	1072	#define LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLM_DIV_29 /!< PLLI2S division factor for PLLI2SM output by 29 /
ganlikun	0:13413ea9a877	1073	#define LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLM_DIV_30 /!< PLLI2S division factor for PLLI2SM output by 30 /
ganlikun	0:13413ea9a877	1074	#define LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLM_DIV_31 /!< PLLI2S division factor for PLLI2SM output by 31 /
ganlikun	0:13413ea9a877	1075	#define LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLM_DIV_32 /!< PLLI2S division factor for PLLI2SM output by 32 /
ganlikun	0:13413ea9a877	1076	#define LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLM_DIV_33 /!< PLLI2S division factor for PLLI2SM output by 33 /
ganlikun	0:13413ea9a877	1077	#define LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLM_DIV_34 /!< PLLI2S division factor for PLLI2SM output by 34 /
ganlikun	0:13413ea9a877	1078	#define LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLM_DIV_35 /!< PLLI2S division factor for PLLI2SM output by 35 /
ganlikun	0:13413ea9a877	1079	#define LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLM_DIV_36 /!< PLLI2S division factor for PLLI2SM output by 36 /
ganlikun	0:13413ea9a877	1080	#define LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLM_DIV_37 /!< PLLI2S division factor for PLLI2SM output by 37 /
ganlikun	0:13413ea9a877	1081	#define LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLM_DIV_38 /!< PLLI2S division factor for PLLI2SM output by 38 /
ganlikun	0:13413ea9a877	1082	#define LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLM_DIV_39 /!< PLLI2S division factor for PLLI2SM output by 39 /
ganlikun	0:13413ea9a877	1083	#define LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLM_DIV_40 /!< PLLI2S division factor for PLLI2SM output by 40 /
ganlikun	0:13413ea9a877	1084	#define LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLM_DIV_41 /!< PLLI2S division factor for PLLI2SM output by 41 /
ganlikun	0:13413ea9a877	1085	#define LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLM_DIV_42 /!< PLLI2S division factor for PLLI2SM output by 42 /
ganlikun	0:13413ea9a877	1086	#define LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLM_DIV_43 /!< PLLI2S division factor for PLLI2SM output by 43 /
ganlikun	0:13413ea9a877	1087	#define LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLM_DIV_44 /!< PLLI2S division factor for PLLI2SM output by 44 /
ganlikun	0:13413ea9a877	1088	#define LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLM_DIV_45 /!< PLLI2S division factor for PLLI2SM output by 45 /
ganlikun	0:13413ea9a877	1089	#define LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLM_DIV_46 /!< PLLI2S division factor for PLLI2SM output by 46 /
ganlikun	0:13413ea9a877	1090	#define LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLM_DIV_47 /!< PLLI2S division factor for PLLI2SM output by 47 /
ganlikun	0:13413ea9a877	1091	#define LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLM_DIV_48 /!< PLLI2S division factor for PLLI2SM output by 48 /
ganlikun	0:13413ea9a877	1092	#define LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLM_DIV_49 /!< PLLI2S division factor for PLLI2SM output by 49 /
ganlikun	0:13413ea9a877	1093	#define LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLM_DIV_50 /!< PLLI2S division factor for PLLI2SM output by 50 /
ganlikun	0:13413ea9a877	1094	#define LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLM_DIV_51 /!< PLLI2S division factor for PLLI2SM output by 51 /
ganlikun	0:13413ea9a877	1095	#define LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLM_DIV_52 /!< PLLI2S division factor for PLLI2SM output by 52 /
ganlikun	0:13413ea9a877	1096	#define LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLM_DIV_53 /!< PLLI2S division factor for PLLI2SM output by 53 /
ganlikun	0:13413ea9a877	1097	#define LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLM_DIV_54 /!< PLLI2S division factor for PLLI2SM output by 54 /
ganlikun	0:13413ea9a877	1098	#define LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLM_DIV_55 /!< PLLI2S division factor for PLLI2SM output by 55 /
ganlikun	0:13413ea9a877	1099	#define LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLM_DIV_56 /!< PLLI2S division factor for PLLI2SM output by 56 /
ganlikun	0:13413ea9a877	1100	#define LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLM_DIV_57 /!< PLLI2S division factor for PLLI2SM output by 57 /
ganlikun	0:13413ea9a877	1101	#define LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLM_DIV_58 /!< PLLI2S division factor for PLLI2SM output by 58 /
ganlikun	0:13413ea9a877	1102	#define LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLM_DIV_59 /!< PLLI2S division factor for PLLI2SM output by 59 /
ganlikun	0:13413ea9a877	1103	#define LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLM_DIV_60 /!< PLLI2S division factor for PLLI2SM output by 60 /
ganlikun	0:13413ea9a877	1104	#define LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLM_DIV_61 /!< PLLI2S division factor for PLLI2SM output by 61 /
ganlikun	0:13413ea9a877	1105	#define LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLM_DIV_62 /!< PLLI2S division factor for PLLI2SM output by 62 /
ganlikun	0:13413ea9a877	1106	#define LL_RCC_PLLI2SM_DIV_63 LL_RCC_PLLM_DIV_63 /!< PLLI2S division factor for PLLI2SM output by 63 /
ganlikun	0:13413ea9a877	1107	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
ganlikun	0:13413ea9a877	1108	/**
ganlikun	0:13413ea9a877	1109	* @}
ganlikun	0:13413ea9a877	1110	*/
ganlikun	0:13413ea9a877	1111
ganlikun	0:13413ea9a877	1112	#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
ganlikun	0:13413ea9a877	1113	/** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ)
ganlikun	0:13413ea9a877	1114	* @{
ganlikun	0:13413ea9a877	1115	*/
ganlikun	0:13413ea9a877	1116	#define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /!< PLLI2S division factor for PLLI2SQ output by 2 /
ganlikun	0:13413ea9a877	1117	#define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 3 /
ganlikun	0:13413ea9a877	1118	#define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /!< PLLI2S division factor for PLLI2SQ output by 4 /
ganlikun	0:13413ea9a877	1119	#define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 5 /
ganlikun	0:13413ea9a877	1120	#define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1) /!< PLLI2S division factor for PLLI2SQ output by 6 /
ganlikun	0:13413ea9a877	1121	#define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 7 /
ganlikun	0:13413ea9a877	1122	#define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /!< PLLI2S division factor for PLLI2SQ output by 8 /
ganlikun	0:13413ea9a877	1123	#define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 9 /
ganlikun	0:13413ea9a877	1124	#define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_1) /!< PLLI2S division factor for PLLI2SQ output by 10 /
ganlikun	0:13413ea9a877	1125	#define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 11 /
ganlikun	0:13413ea9a877	1126	#define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2) /!< PLLI2S division factor for PLLI2SQ output by 12 /
ganlikun	0:13413ea9a877	1127	#define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 13 /
ganlikun	0:13413ea9a877	1128	#define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1) /!< PLLI2S division factor for PLLI2SQ output by 14 /
ganlikun	0:13413ea9a877	1129	#define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 15 /
ganlikun	0:13413ea9a877	1130	/**
ganlikun	0:13413ea9a877	1131	* @}
ganlikun	0:13413ea9a877	1132	*/
ganlikun	0:13413ea9a877	1133	#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
ganlikun	0:13413ea9a877	1134
ganlikun	0:13413ea9a877	1135	#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
ganlikun	0:13413ea9a877	1136	/** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ)
ganlikun	0:13413ea9a877	1137	* @{
ganlikun	0:13413ea9a877	1138	*/
ganlikun	0:13413ea9a877	1139	#define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /!< PLLI2S division factor for PLLI2SDIVQ output by 1 /
ganlikun	0:13413ea9a877	1140	#define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR_PLLI2SDIVQ_0 /!< PLLI2S division factor for PLLI2SDIVQ output by 2 /
ganlikun	0:13413ea9a877	1141	#define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR_PLLI2SDIVQ_1 /!< PLLI2S division factor for PLLI2SDIVQ output by 3 /
ganlikun	0:13413ea9a877	1142	#define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 4 /
ganlikun	0:13413ea9a877	1143	#define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR_PLLI2SDIVQ_2 /!< PLLI2S division factor for PLLI2SDIVQ output by 5 /
ganlikun	0:13413ea9a877	1144	#define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 6 /
ganlikun	0:13413ea9a877	1145	#define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 7 /
ganlikun	0:13413ea9a877	1146	#define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 8 /
ganlikun	0:13413ea9a877	1147	#define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR_PLLI2SDIVQ_3 /!< PLLI2S division factor for PLLI2SDIVQ output by 9 /
ganlikun	0:13413ea9a877	1148	#define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 10 /
ganlikun	0:13413ea9a877	1149	#define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 11 /
ganlikun	0:13413ea9a877	1150	#define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 12 /
ganlikun	0:13413ea9a877	1151	#define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2) /!< PLLI2S division factor for PLLI2SDIVQ output by 13 /
ganlikun	0:13413ea9a877	1152	#define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 14 /
ganlikun	0:13413ea9a877	1153	#define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 15 /
ganlikun	0:13413ea9a877	1154	#define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 16 /
ganlikun	0:13413ea9a877	1155	#define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR_PLLI2SDIVQ_4 /!< PLLI2S division factor for PLLI2SDIVQ output by 17 /
ganlikun	0:13413ea9a877	1156	#define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 18 /
ganlikun	0:13413ea9a877	1157	#define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 19 /
ganlikun	0:13413ea9a877	1158	#define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 20 /
ganlikun	0:13413ea9a877	1159	#define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_2) /!< PLLI2S division factor for PLLI2SDIVQ output by 21 /
ganlikun	0:13413ea9a877	1160	#define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 22 /
ganlikun	0:13413ea9a877	1161	#define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 23 /
ganlikun	0:13413ea9a877	1162	#define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 24 /
ganlikun	0:13413ea9a877	1163	#define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3) /!< PLLI2S division factor for PLLI2SDIVQ output by 25 /
ganlikun	0:13413ea9a877	1164	#define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 26 /
ganlikun	0:13413ea9a877	1165	#define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 27 /
ganlikun	0:13413ea9a877	1166	#define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 28 /
ganlikun	0:13413ea9a877	1167	#define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2) /!< PLLI2S division factor for PLLI2SDIVQ output by 29 /
ganlikun	0:13413ea9a877	1168	#define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 30 /
ganlikun	0:13413ea9a877	1169	#define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 31 /
ganlikun	0:13413ea9a877	1170	#define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 32 /
ganlikun	0:13413ea9a877	1171	/**
ganlikun	0:13413ea9a877	1172	* @}
ganlikun	0:13413ea9a877	1173	*/
ganlikun	0:13413ea9a877	1174	#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
ganlikun	0:13413ea9a877	1175
ganlikun	0:13413ea9a877	1176	#if defined(RCC_DCKCFGR_PLLI2SDIVR)
ganlikun	0:13413ea9a877	1177	/** @defgroup RCC_LL_EC_PLLI2SDIVR PLLI2SDIVR division factor (PLLI2SDIVR)
ganlikun	0:13413ea9a877	1178	* @{
ganlikun	0:13413ea9a877	1179	*/
ganlikun	0:13413ea9a877	1180	#define LL_RCC_PLLI2SDIVR_DIV_1 (RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 1 /
ganlikun	0:13413ea9a877	1181	#define LL_RCC_PLLI2SDIVR_DIV_2 (RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 2 /
ganlikun	0:13413ea9a877	1182	#define LL_RCC_PLLI2SDIVR_DIV_3 (RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 3 /
ganlikun	0:13413ea9a877	1183	#define LL_RCC_PLLI2SDIVR_DIV_4 (RCC_DCKCFGR_PLLI2SDIVR_2) /!< PLLI2S division factor for PLLI2SDIVR output by 4 /
ganlikun	0:13413ea9a877	1184	#define LL_RCC_PLLI2SDIVR_DIV_5 (RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 5 /
ganlikun	0:13413ea9a877	1185	#define LL_RCC_PLLI2SDIVR_DIV_6 (RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 6 /
ganlikun	0:13413ea9a877	1186	#define LL_RCC_PLLI2SDIVR_DIV_7 (RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 7 /
ganlikun	0:13413ea9a877	1187	#define LL_RCC_PLLI2SDIVR_DIV_8 (RCC_DCKCFGR_PLLI2SDIVR_3) /!< PLLI2S division factor for PLLI2SDIVR output by 8 /
ganlikun	0:13413ea9a877	1188	#define LL_RCC_PLLI2SDIVR_DIV_9 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 9 /
ganlikun	0:13413ea9a877	1189	#define LL_RCC_PLLI2SDIVR_DIV_10 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 10 /
ganlikun	0:13413ea9a877	1190	#define LL_RCC_PLLI2SDIVR_DIV_11 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 11 /
ganlikun	0:13413ea9a877	1191	#define LL_RCC_PLLI2SDIVR_DIV_12 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2) /!< PLLI2S division factor for PLLI2SDIVR output by 12 /
ganlikun	0:13413ea9a877	1192	#define LL_RCC_PLLI2SDIVR_DIV_13 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 13 /
ganlikun	0:13413ea9a877	1193	#define LL_RCC_PLLI2SDIVR_DIV_14 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 14 /
ganlikun	0:13413ea9a877	1194	#define LL_RCC_PLLI2SDIVR_DIV_15 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 15 /
ganlikun	0:13413ea9a877	1195	#define LL_RCC_PLLI2SDIVR_DIV_16 (RCC_DCKCFGR_PLLI2SDIVR_4) /!< PLLI2S division factor for PLLI2SDIVR output by 16 /
ganlikun	0:13413ea9a877	1196	#define LL_RCC_PLLI2SDIVR_DIV_17 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 17 /
ganlikun	0:13413ea9a877	1197	#define LL_RCC_PLLI2SDIVR_DIV_18 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 18 /
ganlikun	0:13413ea9a877	1198	#define LL_RCC_PLLI2SDIVR_DIV_19 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 19 /
ganlikun	0:13413ea9a877	1199	#define LL_RCC_PLLI2SDIVR_DIV_20 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_2) /!< PLLI2S division factor for PLLI2SDIVR output by 20 /
ganlikun	0:13413ea9a877	1200	#define LL_RCC_PLLI2SDIVR_DIV_21 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 21 /
ganlikun	0:13413ea9a877	1201	#define LL_RCC_PLLI2SDIVR_DIV_22 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 22 /
ganlikun	0:13413ea9a877	1202	#define LL_RCC_PLLI2SDIVR_DIV_23 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 23 /
ganlikun	0:13413ea9a877	1203	#define LL_RCC_PLLI2SDIVR_DIV_24 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3) /!< PLLI2S division factor for PLLI2SDIVR output by 24 /
ganlikun	0:13413ea9a877	1204	#define LL_RCC_PLLI2SDIVR_DIV_25 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 25 /
ganlikun	0:13413ea9a877	1205	#define LL_RCC_PLLI2SDIVR_DIV_26 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 26 /
ganlikun	0:13413ea9a877	1206	#define LL_RCC_PLLI2SDIVR_DIV_27 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 27 /
ganlikun	0:13413ea9a877	1207	#define LL_RCC_PLLI2SDIVR_DIV_28 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2) /!< PLLI2S division factor for PLLI2SDIVR output by 28 /
ganlikun	0:13413ea9a877	1208	#define LL_RCC_PLLI2SDIVR_DIV_29 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 29 /
ganlikun	0:13413ea9a877	1209	#define LL_RCC_PLLI2SDIVR_DIV_30 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 30 /
ganlikun	0:13413ea9a877	1210	#define LL_RCC_PLLI2SDIVR_DIV_31 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 31 /
ganlikun	0:13413ea9a877	1211	/**
ganlikun	0:13413ea9a877	1212	* @}
ganlikun	0:13413ea9a877	1213	*/
ganlikun	0:13413ea9a877	1214	#endif /* RCC_DCKCFGR_PLLI2SDIVR */
ganlikun	0:13413ea9a877	1215
ganlikun	0:13413ea9a877	1216	/** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR)
ganlikun	0:13413ea9a877	1217	* @{
ganlikun	0:13413ea9a877	1218	*/
ganlikun	0:13413ea9a877	1219	#define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /!< PLLI2S division factor for PLLI2SR output by 2 /
ganlikun	0:13413ea9a877	1220	#define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 3 /
ganlikun	0:13413ea9a877	1221	#define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /!< PLLI2S division factor for PLLI2SR output by 4 /
ganlikun	0:13413ea9a877	1222	#define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 5 /
ganlikun	0:13413ea9a877	1223	#define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_1) /!< PLLI2S division factor for PLLI2SR output by 6 /
ganlikun	0:13413ea9a877	1224	#define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_1 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 7 /
ganlikun	0:13413ea9a877	1225	/**
ganlikun	0:13413ea9a877	1226	* @}
ganlikun	0:13413ea9a877	1227	*/
ganlikun	0:13413ea9a877	1228
ganlikun	0:13413ea9a877	1229	#if defined(RCC_PLLI2SCFGR_PLLI2SP)
ganlikun	0:13413ea9a877	1230	/** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP)
ganlikun	0:13413ea9a877	1231	* @{
ganlikun	0:13413ea9a877	1232	*/
ganlikun	0:13413ea9a877	1233	#define LL_RCC_PLLI2SP_DIV_2 0x00000000U /!< PLLI2S division factor for PLLI2SP output by 2 /
ganlikun	0:13413ea9a877	1234	#define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /!< PLLI2S division factor for PLLI2SP output by 4 /
ganlikun	0:13413ea9a877	1235	#define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /!< PLLI2S division factor for PLLI2SP output by 6 /
ganlikun	0:13413ea9a877	1236	#define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 \| RCC_PLLI2SCFGR_PLLI2SP_0) /!< PLLI2S division factor for PLLI2SP output by 8 /
ganlikun	0:13413ea9a877	1237	/**
ganlikun	0:13413ea9a877	1238	* @}
ganlikun	0:13413ea9a877	1239	*/
ganlikun	0:13413ea9a877	1240	#endif /* RCC_PLLI2SCFGR_PLLI2SP */
ganlikun	0:13413ea9a877	1241	#endif /* RCC_PLLI2S_SUPPORT */
ganlikun	0:13413ea9a877	1242
ganlikun	0:13413ea9a877	1243	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	1244	/** @defgroup RCC_LL_EC_PLLSAIM PLLSAIM division factor (PLLSAIM or PLLM)
ganlikun	0:13413ea9a877	1245	* @{
ganlikun	0:13413ea9a877	1246	*/
ganlikun	0:13413ea9a877	1247	#if defined(RCC_PLLSAICFGR_PLLSAIM)
ganlikun	0:13413ea9a877	1248	#define LL_RCC_PLLSAIM_DIV_2 (RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 2 /
ganlikun	0:13413ea9a877	1249	#define LL_RCC_PLLSAIM_DIV_3 (RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 3 /
ganlikun	0:13413ea9a877	1250	#define LL_RCC_PLLSAIM_DIV_4 (RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 4 /
ganlikun	0:13413ea9a877	1251	#define LL_RCC_PLLSAIM_DIV_5 (RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 5 /
ganlikun	0:13413ea9a877	1252	#define LL_RCC_PLLSAIM_DIV_6 (RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 6 /
ganlikun	0:13413ea9a877	1253	#define LL_RCC_PLLSAIM_DIV_7 (RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 7 /
ganlikun	0:13413ea9a877	1254	#define LL_RCC_PLLSAIM_DIV_8 (RCC_PLLSAICFGR_PLLSAIM_3) /!< PLLSAI division factor for PLLSAIM output by 8 /
ganlikun	0:13413ea9a877	1255	#define LL_RCC_PLLSAIM_DIV_9 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 9 /
ganlikun	0:13413ea9a877	1256	#define LL_RCC_PLLSAIM_DIV_10 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 10 /
ganlikun	0:13413ea9a877	1257	#define LL_RCC_PLLSAIM_DIV_11 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 11 /
ganlikun	0:13413ea9a877	1258	#define LL_RCC_PLLSAIM_DIV_12 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 12 /
ganlikun	0:13413ea9a877	1259	#define LL_RCC_PLLSAIM_DIV_13 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 13 /
ganlikun	0:13413ea9a877	1260	#define LL_RCC_PLLSAIM_DIV_14 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 14 /
ganlikun	0:13413ea9a877	1261	#define LL_RCC_PLLSAIM_DIV_15 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 15 /
ganlikun	0:13413ea9a877	1262	#define LL_RCC_PLLSAIM_DIV_16 (RCC_PLLSAICFGR_PLLSAIM_4) /!< PLLSAI division factor for PLLSAIM output by 16 /
ganlikun	0:13413ea9a877	1263	#define LL_RCC_PLLSAIM_DIV_17 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 17 /
ganlikun	0:13413ea9a877	1264	#define LL_RCC_PLLSAIM_DIV_18 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 18 /
ganlikun	0:13413ea9a877	1265	#define LL_RCC_PLLSAIM_DIV_19 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 19 /
ganlikun	0:13413ea9a877	1266	#define LL_RCC_PLLSAIM_DIV_20 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 20 /
ganlikun	0:13413ea9a877	1267	#define LL_RCC_PLLSAIM_DIV_21 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 21 /
ganlikun	0:13413ea9a877	1268	#define LL_RCC_PLLSAIM_DIV_22 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 22 /
ganlikun	0:13413ea9a877	1269	#define LL_RCC_PLLSAIM_DIV_23 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 23 /
ganlikun	0:13413ea9a877	1270	#define LL_RCC_PLLSAIM_DIV_24 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3) /!< PLLSAI division factor for PLLSAIM output by 24 /
ganlikun	0:13413ea9a877	1271	#define LL_RCC_PLLSAIM_DIV_25 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 25 /
ganlikun	0:13413ea9a877	1272	#define LL_RCC_PLLSAIM_DIV_26 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 26 /
ganlikun	0:13413ea9a877	1273	#define LL_RCC_PLLSAIM_DIV_27 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 27 /
ganlikun	0:13413ea9a877	1274	#define LL_RCC_PLLSAIM_DIV_28 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 28 /
ganlikun	0:13413ea9a877	1275	#define LL_RCC_PLLSAIM_DIV_29 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 29 /
ganlikun	0:13413ea9a877	1276	#define LL_RCC_PLLSAIM_DIV_30 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 30 /
ganlikun	0:13413ea9a877	1277	#define LL_RCC_PLLSAIM_DIV_31 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 31 /
ganlikun	0:13413ea9a877	1278	#define LL_RCC_PLLSAIM_DIV_32 (RCC_PLLSAICFGR_PLLSAIM_5) /!< PLLSAI division factor for PLLSAIM output by 32 /
ganlikun	0:13413ea9a877	1279	#define LL_RCC_PLLSAIM_DIV_33 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 33 /
ganlikun	0:13413ea9a877	1280	#define LL_RCC_PLLSAIM_DIV_34 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 34 /
ganlikun	0:13413ea9a877	1281	#define LL_RCC_PLLSAIM_DIV_35 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 35 /
ganlikun	0:13413ea9a877	1282	#define LL_RCC_PLLSAIM_DIV_36 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 36 /
ganlikun	0:13413ea9a877	1283	#define LL_RCC_PLLSAIM_DIV_37 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 37 /
ganlikun	0:13413ea9a877	1284	#define LL_RCC_PLLSAIM_DIV_38 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 38 /
ganlikun	0:13413ea9a877	1285	#define LL_RCC_PLLSAIM_DIV_39 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 39 /
ganlikun	0:13413ea9a877	1286	#define LL_RCC_PLLSAIM_DIV_40 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3) /!< PLLSAI division factor for PLLSAIM output by 40 /
ganlikun	0:13413ea9a877	1287	#define LL_RCC_PLLSAIM_DIV_41 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 41 /
ganlikun	0:13413ea9a877	1288	#define LL_RCC_PLLSAIM_DIV_42 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 42 /
ganlikun	0:13413ea9a877	1289	#define LL_RCC_PLLSAIM_DIV_43 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 43 /
ganlikun	0:13413ea9a877	1290	#define LL_RCC_PLLSAIM_DIV_44 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 44 /
ganlikun	0:13413ea9a877	1291	#define LL_RCC_PLLSAIM_DIV_45 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 45 /
ganlikun	0:13413ea9a877	1292	#define LL_RCC_PLLSAIM_DIV_46 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 46 /
ganlikun	0:13413ea9a877	1293	#define LL_RCC_PLLSAIM_DIV_47 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 47 /
ganlikun	0:13413ea9a877	1294	#define LL_RCC_PLLSAIM_DIV_48 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4) /!< PLLSAI division factor for PLLSAIM output by 48 /
ganlikun	0:13413ea9a877	1295	#define LL_RCC_PLLSAIM_DIV_49 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 49 /
ganlikun	0:13413ea9a877	1296	#define LL_RCC_PLLSAIM_DIV_50 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 50 /
ganlikun	0:13413ea9a877	1297	#define LL_RCC_PLLSAIM_DIV_51 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 51 /
ganlikun	0:13413ea9a877	1298	#define LL_RCC_PLLSAIM_DIV_52 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 52 /
ganlikun	0:13413ea9a877	1299	#define LL_RCC_PLLSAIM_DIV_53 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 53 /
ganlikun	0:13413ea9a877	1300	#define LL_RCC_PLLSAIM_DIV_54 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 54 /
ganlikun	0:13413ea9a877	1301	#define LL_RCC_PLLSAIM_DIV_55 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 55 /
ganlikun	0:13413ea9a877	1302	#define LL_RCC_PLLSAIM_DIV_56 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3) /!< PLLSAI division factor for PLLSAIM output by 56 /
ganlikun	0:13413ea9a877	1303	#define LL_RCC_PLLSAIM_DIV_57 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 57 /
ganlikun	0:13413ea9a877	1304	#define LL_RCC_PLLSAIM_DIV_58 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 58 /
ganlikun	0:13413ea9a877	1305	#define LL_RCC_PLLSAIM_DIV_59 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 59 /
ganlikun	0:13413ea9a877	1306	#define LL_RCC_PLLSAIM_DIV_60 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 60 /
ganlikun	0:13413ea9a877	1307	#define LL_RCC_PLLSAIM_DIV_61 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 61 /
ganlikun	0:13413ea9a877	1308	#define LL_RCC_PLLSAIM_DIV_62 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 62 /
ganlikun	0:13413ea9a877	1309	#define LL_RCC_PLLSAIM_DIV_63 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 63 /
ganlikun	0:13413ea9a877	1310	#else
ganlikun	0:13413ea9a877	1311	#define LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLM_DIV_2 /!< PLLSAI division factor for PLLSAIM output by 2 /
ganlikun	0:13413ea9a877	1312	#define LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLM_DIV_3 /!< PLLSAI division factor for PLLSAIM output by 3 /
ganlikun	0:13413ea9a877	1313	#define LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLM_DIV_4 /!< PLLSAI division factor for PLLSAIM output by 4 /
ganlikun	0:13413ea9a877	1314	#define LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLM_DIV_5 /!< PLLSAI division factor for PLLSAIM output by 5 /
ganlikun	0:13413ea9a877	1315	#define LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLM_DIV_6 /!< PLLSAI division factor for PLLSAIM output by 6 /
ganlikun	0:13413ea9a877	1316	#define LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLM_DIV_7 /!< PLLSAI division factor for PLLSAIM output by 7 /
ganlikun	0:13413ea9a877	1317	#define LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLM_DIV_8 /!< PLLSAI division factor for PLLSAIM output by 8 /
ganlikun	0:13413ea9a877	1318	#define LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLM_DIV_9 /!< PLLSAI division factor for PLLSAIM output by 9 /
ganlikun	0:13413ea9a877	1319	#define LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLM_DIV_10 /!< PLLSAI division factor for PLLSAIM output by 10 /
ganlikun	0:13413ea9a877	1320	#define LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLM_DIV_11 /!< PLLSAI division factor for PLLSAIM output by 11 /
ganlikun	0:13413ea9a877	1321	#define LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLM_DIV_12 /!< PLLSAI division factor for PLLSAIM output by 12 /
ganlikun	0:13413ea9a877	1322	#define LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLM_DIV_13 /!< PLLSAI division factor for PLLSAIM output by 13 /
ganlikun	0:13413ea9a877	1323	#define LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLM_DIV_14 /!< PLLSAI division factor for PLLSAIM output by 14 /
ganlikun	0:13413ea9a877	1324	#define LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLM_DIV_15 /!< PLLSAI division factor for PLLSAIM output by 15 /
ganlikun	0:13413ea9a877	1325	#define LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLM_DIV_16 /!< PLLSAI division factor for PLLSAIM output by 16 /
ganlikun	0:13413ea9a877	1326	#define LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLM_DIV_17 /!< PLLSAI division factor for PLLSAIM output by 17 /
ganlikun	0:13413ea9a877	1327	#define LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLM_DIV_18 /!< PLLSAI division factor for PLLSAIM output by 18 /
ganlikun	0:13413ea9a877	1328	#define LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLM_DIV_19 /!< PLLSAI division factor for PLLSAIM output by 19 /
ganlikun	0:13413ea9a877	1329	#define LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLM_DIV_20 /!< PLLSAI division factor for PLLSAIM output by 20 /
ganlikun	0:13413ea9a877	1330	#define LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLM_DIV_21 /!< PLLSAI division factor for PLLSAIM output by 21 /
ganlikun	0:13413ea9a877	1331	#define LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLM_DIV_22 /!< PLLSAI division factor for PLLSAIM output by 22 /
ganlikun	0:13413ea9a877	1332	#define LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLM_DIV_23 /!< PLLSAI division factor for PLLSAIM output by 23 /
ganlikun	0:13413ea9a877	1333	#define LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLM_DIV_24 /!< PLLSAI division factor for PLLSAIM output by 24 /
ganlikun	0:13413ea9a877	1334	#define LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLM_DIV_25 /!< PLLSAI division factor for PLLSAIM output by 25 /
ganlikun	0:13413ea9a877	1335	#define LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLM_DIV_26 /!< PLLSAI division factor for PLLSAIM output by 26 /
ganlikun	0:13413ea9a877	1336	#define LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLM_DIV_27 /!< PLLSAI division factor for PLLSAIM output by 27 /
ganlikun	0:13413ea9a877	1337	#define LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLM_DIV_28 /!< PLLSAI division factor for PLLSAIM output by 28 /
ganlikun	0:13413ea9a877	1338	#define LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLM_DIV_29 /!< PLLSAI division factor for PLLSAIM output by 29 /
ganlikun	0:13413ea9a877	1339	#define LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLM_DIV_30 /!< PLLSAI division factor for PLLSAIM output by 30 /
ganlikun	0:13413ea9a877	1340	#define LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLM_DIV_31 /!< PLLSAI division factor for PLLSAIM output by 31 /
ganlikun	0:13413ea9a877	1341	#define LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLM_DIV_32 /!< PLLSAI division factor for PLLSAIM output by 32 /
ganlikun	0:13413ea9a877	1342	#define LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLM_DIV_33 /!< PLLSAI division factor for PLLSAIM output by 33 /
ganlikun	0:13413ea9a877	1343	#define LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLM_DIV_34 /!< PLLSAI division factor for PLLSAIM output by 34 /
ganlikun	0:13413ea9a877	1344	#define LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLM_DIV_35 /!< PLLSAI division factor for PLLSAIM output by 35 /
ganlikun	0:13413ea9a877	1345	#define LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLM_DIV_36 /!< PLLSAI division factor for PLLSAIM output by 36 /
ganlikun	0:13413ea9a877	1346	#define LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLM_DIV_37 /!< PLLSAI division factor for PLLSAIM output by 37 /
ganlikun	0:13413ea9a877	1347	#define LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLM_DIV_38 /!< PLLSAI division factor for PLLSAIM output by 38 /
ganlikun	0:13413ea9a877	1348	#define LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLM_DIV_39 /!< PLLSAI division factor for PLLSAIM output by 39 /
ganlikun	0:13413ea9a877	1349	#define LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLM_DIV_40 /!< PLLSAI division factor for PLLSAIM output by 40 /
ganlikun	0:13413ea9a877	1350	#define LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLM_DIV_41 /!< PLLSAI division factor for PLLSAIM output by 41 /
ganlikun	0:13413ea9a877	1351	#define LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLM_DIV_42 /!< PLLSAI division factor for PLLSAIM output by 42 /
ganlikun	0:13413ea9a877	1352	#define LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLM_DIV_43 /!< PLLSAI division factor for PLLSAIM output by 43 /
ganlikun	0:13413ea9a877	1353	#define LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLM_DIV_44 /!< PLLSAI division factor for PLLSAIM output by 44 /
ganlikun	0:13413ea9a877	1354	#define LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLM_DIV_45 /!< PLLSAI division factor for PLLSAIM output by 45 /
ganlikun	0:13413ea9a877	1355	#define LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLM_DIV_46 /!< PLLSAI division factor for PLLSAIM output by 46 /
ganlikun	0:13413ea9a877	1356	#define LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLM_DIV_47 /!< PLLSAI division factor for PLLSAIM output by 47 /
ganlikun	0:13413ea9a877	1357	#define LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLM_DIV_48 /!< PLLSAI division factor for PLLSAIM output by 48 /
ganlikun	0:13413ea9a877	1358	#define LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLM_DIV_49 /!< PLLSAI division factor for PLLSAIM output by 49 /
ganlikun	0:13413ea9a877	1359	#define LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLM_DIV_50 /!< PLLSAI division factor for PLLSAIM output by 50 /
ganlikun	0:13413ea9a877	1360	#define LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLM_DIV_51 /!< PLLSAI division factor for PLLSAIM output by 51 /
ganlikun	0:13413ea9a877	1361	#define LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLM_DIV_52 /!< PLLSAI division factor for PLLSAIM output by 52 /
ganlikun	0:13413ea9a877	1362	#define LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLM_DIV_53 /!< PLLSAI division factor for PLLSAIM output by 53 /
ganlikun	0:13413ea9a877	1363	#define LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLM_DIV_54 /!< PLLSAI division factor for PLLSAIM output by 54 /
ganlikun	0:13413ea9a877	1364	#define LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLM_DIV_55 /!< PLLSAI division factor for PLLSAIM output by 55 /
ganlikun	0:13413ea9a877	1365	#define LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLM_DIV_56 /!< PLLSAI division factor for PLLSAIM output by 56 /
ganlikun	0:13413ea9a877	1366	#define LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLM_DIV_57 /!< PLLSAI division factor for PLLSAIM output by 57 /
ganlikun	0:13413ea9a877	1367	#define LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLM_DIV_58 /!< PLLSAI division factor for PLLSAIM output by 58 /
ganlikun	0:13413ea9a877	1368	#define LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLM_DIV_59 /!< PLLSAI division factor for PLLSAIM output by 59 /
ganlikun	0:13413ea9a877	1369	#define LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLM_DIV_60 /!< PLLSAI division factor for PLLSAIM output by 60 /
ganlikun	0:13413ea9a877	1370	#define LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLM_DIV_61 /!< PLLSAI division factor for PLLSAIM output by 61 /
ganlikun	0:13413ea9a877	1371	#define LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLM_DIV_62 /!< PLLSAI division factor for PLLSAIM output by 62 /
ganlikun	0:13413ea9a877	1372	#define LL_RCC_PLLSAIM_DIV_63 LL_RCC_PLLM_DIV_63 /!< PLLSAI division factor for PLLSAIM output by 63 /
ganlikun	0:13413ea9a877	1373	#endif /* RCC_PLLSAICFGR_PLLSAIM */
ganlikun	0:13413ea9a877	1374	/**
ganlikun	0:13413ea9a877	1375	* @}
ganlikun	0:13413ea9a877	1376	*/
ganlikun	0:13413ea9a877	1377
ganlikun	0:13413ea9a877	1378	/** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ)
ganlikun	0:13413ea9a877	1379	* @{
ganlikun	0:13413ea9a877	1380	*/
ganlikun	0:13413ea9a877	1381	#define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /!< PLLSAI division factor for PLLSAIQ output by 2 /
ganlikun	0:13413ea9a877	1382	#define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 3 /
ganlikun	0:13413ea9a877	1383	#define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /!< PLLSAI division factor for PLLSAIQ output by 4 /
ganlikun	0:13413ea9a877	1384	#define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 5 /
ganlikun	0:13413ea9a877	1385	#define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1) /!< PLLSAI division factor for PLLSAIQ output by 6 /
ganlikun	0:13413ea9a877	1386	#define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 7 /
ganlikun	0:13413ea9a877	1387	#define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /!< PLLSAI division factor for PLLSAIQ output by 8 /
ganlikun	0:13413ea9a877	1388	#define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 9 /
ganlikun	0:13413ea9a877	1389	#define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_1) /!< PLLSAI division factor for PLLSAIQ output by 10 /
ganlikun	0:13413ea9a877	1390	#define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 11 /
ganlikun	0:13413ea9a877	1391	#define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2) /!< PLLSAI division factor for PLLSAIQ output by 12 /
ganlikun	0:13413ea9a877	1392	#define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 13 /
ganlikun	0:13413ea9a877	1393	#define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1) /!< PLLSAI division factor for PLLSAIQ output by 14 /
ganlikun	0:13413ea9a877	1394	#define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 15 /
ganlikun	0:13413ea9a877	1395	/**
ganlikun	0:13413ea9a877	1396	* @}
ganlikun	0:13413ea9a877	1397	*/
ganlikun	0:13413ea9a877	1398
ganlikun	0:13413ea9a877	1399	#if defined(RCC_DCKCFGR_PLLSAIDIVQ)
ganlikun	0:13413ea9a877	1400	/** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ)
ganlikun	0:13413ea9a877	1401	* @{
ganlikun	0:13413ea9a877	1402	*/
ganlikun	0:13413ea9a877	1403	#define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /!< PLLSAI division factor for PLLSAIDIVQ output by 1 /
ganlikun	0:13413ea9a877	1404	#define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR_PLLSAIDIVQ_0 /!< PLLSAI division factor for PLLSAIDIVQ output by 2 /
ganlikun	0:13413ea9a877	1405	#define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR_PLLSAIDIVQ_1 /!< PLLSAI division factor for PLLSAIDIVQ output by 3 /
ganlikun	0:13413ea9a877	1406	#define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 4 /
ganlikun	0:13413ea9a877	1407	#define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR_PLLSAIDIVQ_2 /!< PLLSAI division factor for PLLSAIDIVQ output by 5 /
ganlikun	0:13413ea9a877	1408	#define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 6 /
ganlikun	0:13413ea9a877	1409	#define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 7 /
ganlikun	0:13413ea9a877	1410	#define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 8 /
ganlikun	0:13413ea9a877	1411	#define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR_PLLSAIDIVQ_3 /!< PLLSAI division factor for PLLSAIDIVQ output by 9 /
ganlikun	0:13413ea9a877	1412	#define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 10 /
ganlikun	0:13413ea9a877	1413	#define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 11 /
ganlikun	0:13413ea9a877	1414	#define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 12 /
ganlikun	0:13413ea9a877	1415	#define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2) /!< PLLSAI division factor for PLLSAIDIVQ output by 13 /
ganlikun	0:13413ea9a877	1416	#define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 14 /
ganlikun	0:13413ea9a877	1417	#define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 15 /
ganlikun	0:13413ea9a877	1418	#define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 16 /
ganlikun	0:13413ea9a877	1419	#define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR_PLLSAIDIVQ_4 /!< PLLSAI division factor for PLLSAIDIVQ output by 17 /
ganlikun	0:13413ea9a877	1420	#define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 18 /
ganlikun	0:13413ea9a877	1421	#define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 19 /
ganlikun	0:13413ea9a877	1422	#define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 20 /
ganlikun	0:13413ea9a877	1423	#define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_2) /!< PLLSAI division factor for PLLSAIDIVQ output by 21 /
ganlikun	0:13413ea9a877	1424	#define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 22 /
ganlikun	0:13413ea9a877	1425	#define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 23 /
ganlikun	0:13413ea9a877	1426	#define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 24 /
ganlikun	0:13413ea9a877	1427	#define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3) /!< PLLSAI division factor for PLLSAIDIVQ output by 25 /
ganlikun	0:13413ea9a877	1428	#define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 26 /
ganlikun	0:13413ea9a877	1429	#define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 27 /
ganlikun	0:13413ea9a877	1430	#define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 28 /
ganlikun	0:13413ea9a877	1431	#define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2) /!< PLLSAI division factor for PLLSAIDIVQ output by 29 /
ganlikun	0:13413ea9a877	1432	#define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 30 /
ganlikun	0:13413ea9a877	1433	#define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 31 /
ganlikun	0:13413ea9a877	1434	#define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 32 /
ganlikun	0:13413ea9a877	1435	/**
ganlikun	0:13413ea9a877	1436	* @}
ganlikun	0:13413ea9a877	1437	*/
ganlikun	0:13413ea9a877	1438	#endif /* RCC_DCKCFGR_PLLSAIDIVQ */
ganlikun	0:13413ea9a877	1439
ganlikun	0:13413ea9a877	1440	#if defined(RCC_PLLSAICFGR_PLLSAIR)
ganlikun	0:13413ea9a877	1441	/** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR)
ganlikun	0:13413ea9a877	1442	* @{
ganlikun	0:13413ea9a877	1443	*/
ganlikun	0:13413ea9a877	1444	#define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /!< PLLSAI division factor for PLLSAIR output by 2 /
ganlikun	0:13413ea9a877	1445	#define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 \| RCC_PLLSAICFGR_PLLSAIR_0) /!< PLLSAI division factor for PLLSAIR output by 3 /
ganlikun	0:13413ea9a877	1446	#define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /!< PLLSAI division factor for PLLSAIR output by 4 /
ganlikun	0:13413ea9a877	1447	#define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 \| RCC_PLLSAICFGR_PLLSAIR_0) /!< PLLSAI division factor for PLLSAIR output by 5 /
ganlikun	0:13413ea9a877	1448	#define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 \| RCC_PLLSAICFGR_PLLSAIR_1) /!< PLLSAI division factor for PLLSAIR output by 6 /
ganlikun	0:13413ea9a877	1449	#define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 \| RCC_PLLSAICFGR_PLLSAIR_1 \| RCC_PLLSAICFGR_PLLSAIR_0) /!< PLLSAI division factor for PLLSAIR output by 7 /
ganlikun	0:13413ea9a877	1450	/**
ganlikun	0:13413ea9a877	1451	* @}
ganlikun	0:13413ea9a877	1452	*/
ganlikun	0:13413ea9a877	1453	#endif /* RCC_PLLSAICFGR_PLLSAIR */
ganlikun	0:13413ea9a877	1454
ganlikun	0:13413ea9a877	1455	#if defined(RCC_DCKCFGR_PLLSAIDIVR)
ganlikun	0:13413ea9a877	1456	/** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR)
ganlikun	0:13413ea9a877	1457	* @{
ganlikun	0:13413ea9a877	1458	*/
ganlikun	0:13413ea9a877	1459	#define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /!< PLLSAI division factor for PLLSAIDIVR output by 2 /
ganlikun	0:13413ea9a877	1460	#define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR_PLLSAIDIVR_0 /!< PLLSAI division factor for PLLSAIDIVR output by 4 /
ganlikun	0:13413ea9a877	1461	#define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR_PLLSAIDIVR_1 /!< PLLSAI division factor for PLLSAIDIVR output by 8 /
ganlikun	0:13413ea9a877	1462	#define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR_PLLSAIDIVR_1 \| RCC_DCKCFGR_PLLSAIDIVR_0) /!< PLLSAI division factor for PLLSAIDIVR output by 16 /
ganlikun	0:13413ea9a877	1463	/**
ganlikun	0:13413ea9a877	1464	* @}
ganlikun	0:13413ea9a877	1465	*/
ganlikun	0:13413ea9a877	1466	#endif /* RCC_DCKCFGR_PLLSAIDIVR */
ganlikun	0:13413ea9a877	1467
ganlikun	0:13413ea9a877	1468	#if defined(RCC_PLLSAICFGR_PLLSAIP)
ganlikun	0:13413ea9a877	1469	/** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP)
ganlikun	0:13413ea9a877	1470	* @{
ganlikun	0:13413ea9a877	1471	*/
ganlikun	0:13413ea9a877	1472	#define LL_RCC_PLLSAIP_DIV_2 0x00000000U /!< PLLSAI division factor for PLLSAIP output by 2 /
ganlikun	0:13413ea9a877	1473	#define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /!< PLLSAI division factor for PLLSAIP output by 4 /
ganlikun	0:13413ea9a877	1474	#define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /!< PLLSAI division factor for PLLSAIP output by 6 /
ganlikun	0:13413ea9a877	1475	#define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 \| RCC_PLLSAICFGR_PLLSAIP_0) /!< PLLSAI division factor for PLLSAIP output by 8 /
ganlikun	0:13413ea9a877	1476	/**
ganlikun	0:13413ea9a877	1477	* @}
ganlikun	0:13413ea9a877	1478	*/
ganlikun	0:13413ea9a877	1479	#endif /* RCC_PLLSAICFGR_PLLSAIP */
ganlikun	0:13413ea9a877	1480	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	1481	/**
ganlikun	0:13413ea9a877	1482	* @}
ganlikun	0:13413ea9a877	1483	*/
ganlikun	0:13413ea9a877	1484
ganlikun	0:13413ea9a877	1485	/* Exported macro ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	1486	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
ganlikun	0:13413ea9a877	1487	* @{
ganlikun	0:13413ea9a877	1488	*/
ganlikun	0:13413ea9a877	1489
ganlikun	0:13413ea9a877	1490	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
ganlikun	0:13413ea9a877	1491	* @{
ganlikun	0:13413ea9a877	1492	*/
ganlikun	0:13413ea9a877	1493
ganlikun	0:13413ea9a877	1494	/**
ganlikun	0:13413ea9a877	1495	* @brief Write a value in RCC register
ganlikun	0:13413ea9a877	1496	* @param __REG__ Register to be written
ganlikun	0:13413ea9a877	1497	* @param __VALUE__ Value to be written in the register
ganlikun	0:13413ea9a877	1498	* @retval None
ganlikun	0:13413ea9a877	1499	*/
ganlikun	0:13413ea9a877	1500	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
ganlikun	0:13413ea9a877	1501
ganlikun	0:13413ea9a877	1502	/**
ganlikun	0:13413ea9a877	1503	* @brief Read a value in RCC register
ganlikun	0:13413ea9a877	1504	* @param __REG__ Register to be read
ganlikun	0:13413ea9a877	1505	* @retval Register value
ganlikun	0:13413ea9a877	1506	*/
ganlikun	0:13413ea9a877	1507	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
ganlikun	0:13413ea9a877	1508	/**
ganlikun	0:13413ea9a877	1509	* @}
ganlikun	0:13413ea9a877	1510	*/
ganlikun	0:13413ea9a877	1511
ganlikun	0:13413ea9a877	1512	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
ganlikun	0:13413ea9a877	1513	* @{
ganlikun	0:13413ea9a877	1514	*/
ganlikun	0:13413ea9a877	1515
ganlikun	0:13413ea9a877	1516	/**
ganlikun	0:13413ea9a877	1517	* @brief Helper macro to calculate the PLLCLK frequency on system domain
ganlikun	0:13413ea9a877	1518	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
ganlikun	0:13413ea9a877	1519	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
ganlikun	0:13413ea9a877	1520	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
ganlikun	0:13413ea9a877	1521	* @param __PLLM__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1522	* @arg @ref LL_RCC_PLLM_DIV_2
ganlikun	0:13413ea9a877	1523	* @arg @ref LL_RCC_PLLM_DIV_3
ganlikun	0:13413ea9a877	1524	* @arg @ref LL_RCC_PLLM_DIV_4
ganlikun	0:13413ea9a877	1525	* @arg @ref LL_RCC_PLLM_DIV_5
ganlikun	0:13413ea9a877	1526	* @arg @ref LL_RCC_PLLM_DIV_6
ganlikun	0:13413ea9a877	1527	* @arg @ref LL_RCC_PLLM_DIV_7
ganlikun	0:13413ea9a877	1528	* @arg @ref LL_RCC_PLLM_DIV_8
ganlikun	0:13413ea9a877	1529	* @arg @ref LL_RCC_PLLM_DIV_9
ganlikun	0:13413ea9a877	1530	* @arg @ref LL_RCC_PLLM_DIV_10
ganlikun	0:13413ea9a877	1531	* @arg @ref LL_RCC_PLLM_DIV_11
ganlikun	0:13413ea9a877	1532	* @arg @ref LL_RCC_PLLM_DIV_12
ganlikun	0:13413ea9a877	1533	* @arg @ref LL_RCC_PLLM_DIV_13
ganlikun	0:13413ea9a877	1534	* @arg @ref LL_RCC_PLLM_DIV_14
ganlikun	0:13413ea9a877	1535	* @arg @ref LL_RCC_PLLM_DIV_15
ganlikun	0:13413ea9a877	1536	* @arg @ref LL_RCC_PLLM_DIV_16
ganlikun	0:13413ea9a877	1537	* @arg @ref LL_RCC_PLLM_DIV_17
ganlikun	0:13413ea9a877	1538	* @arg @ref LL_RCC_PLLM_DIV_18
ganlikun	0:13413ea9a877	1539	* @arg @ref LL_RCC_PLLM_DIV_19
ganlikun	0:13413ea9a877	1540	* @arg @ref LL_RCC_PLLM_DIV_20
ganlikun	0:13413ea9a877	1541	* @arg @ref LL_RCC_PLLM_DIV_21
ganlikun	0:13413ea9a877	1542	* @arg @ref LL_RCC_PLLM_DIV_22
ganlikun	0:13413ea9a877	1543	* @arg @ref LL_RCC_PLLM_DIV_23
ganlikun	0:13413ea9a877	1544	* @arg @ref LL_RCC_PLLM_DIV_24
ganlikun	0:13413ea9a877	1545	* @arg @ref LL_RCC_PLLM_DIV_25
ganlikun	0:13413ea9a877	1546	* @arg @ref LL_RCC_PLLM_DIV_26
ganlikun	0:13413ea9a877	1547	* @arg @ref LL_RCC_PLLM_DIV_27
ganlikun	0:13413ea9a877	1548	* @arg @ref LL_RCC_PLLM_DIV_28
ganlikun	0:13413ea9a877	1549	* @arg @ref LL_RCC_PLLM_DIV_29
ganlikun	0:13413ea9a877	1550	* @arg @ref LL_RCC_PLLM_DIV_30
ganlikun	0:13413ea9a877	1551	* @arg @ref LL_RCC_PLLM_DIV_31
ganlikun	0:13413ea9a877	1552	* @arg @ref LL_RCC_PLLM_DIV_32
ganlikun	0:13413ea9a877	1553	* @arg @ref LL_RCC_PLLM_DIV_33
ganlikun	0:13413ea9a877	1554	* @arg @ref LL_RCC_PLLM_DIV_34
ganlikun	0:13413ea9a877	1555	* @arg @ref LL_RCC_PLLM_DIV_35
ganlikun	0:13413ea9a877	1556	* @arg @ref LL_RCC_PLLM_DIV_36
ganlikun	0:13413ea9a877	1557	* @arg @ref LL_RCC_PLLM_DIV_37
ganlikun	0:13413ea9a877	1558	* @arg @ref LL_RCC_PLLM_DIV_38
ganlikun	0:13413ea9a877	1559	* @arg @ref LL_RCC_PLLM_DIV_39
ganlikun	0:13413ea9a877	1560	* @arg @ref LL_RCC_PLLM_DIV_40
ganlikun	0:13413ea9a877	1561	* @arg @ref LL_RCC_PLLM_DIV_41
ganlikun	0:13413ea9a877	1562	* @arg @ref LL_RCC_PLLM_DIV_42
ganlikun	0:13413ea9a877	1563	* @arg @ref LL_RCC_PLLM_DIV_43
ganlikun	0:13413ea9a877	1564	* @arg @ref LL_RCC_PLLM_DIV_44
ganlikun	0:13413ea9a877	1565	* @arg @ref LL_RCC_PLLM_DIV_45
ganlikun	0:13413ea9a877	1566	* @arg @ref LL_RCC_PLLM_DIV_46
ganlikun	0:13413ea9a877	1567	* @arg @ref LL_RCC_PLLM_DIV_47
ganlikun	0:13413ea9a877	1568	* @arg @ref LL_RCC_PLLM_DIV_48
ganlikun	0:13413ea9a877	1569	* @arg @ref LL_RCC_PLLM_DIV_49
ganlikun	0:13413ea9a877	1570	* @arg @ref LL_RCC_PLLM_DIV_50
ganlikun	0:13413ea9a877	1571	* @arg @ref LL_RCC_PLLM_DIV_51
ganlikun	0:13413ea9a877	1572	* @arg @ref LL_RCC_PLLM_DIV_52
ganlikun	0:13413ea9a877	1573	* @arg @ref LL_RCC_PLLM_DIV_53
ganlikun	0:13413ea9a877	1574	* @arg @ref LL_RCC_PLLM_DIV_54
ganlikun	0:13413ea9a877	1575	* @arg @ref LL_RCC_PLLM_DIV_55
ganlikun	0:13413ea9a877	1576	* @arg @ref LL_RCC_PLLM_DIV_56
ganlikun	0:13413ea9a877	1577	* @arg @ref LL_RCC_PLLM_DIV_57
ganlikun	0:13413ea9a877	1578	* @arg @ref LL_RCC_PLLM_DIV_58
ganlikun	0:13413ea9a877	1579	* @arg @ref LL_RCC_PLLM_DIV_59
ganlikun	0:13413ea9a877	1580	* @arg @ref LL_RCC_PLLM_DIV_60
ganlikun	0:13413ea9a877	1581	* @arg @ref LL_RCC_PLLM_DIV_61
ganlikun	0:13413ea9a877	1582	* @arg @ref LL_RCC_PLLM_DIV_62
ganlikun	0:13413ea9a877	1583	* @arg @ref LL_RCC_PLLM_DIV_63
ganlikun	0:13413ea9a877	1584	* @param __PLLN__ Between 50/192(*) and 432
ganlikun	0:13413ea9a877	1585	*
ganlikun	0:13413ea9a877	1586	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1587	* @param __PLLP__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1588	* @arg @ref LL_RCC_PLLP_DIV_2
ganlikun	0:13413ea9a877	1589	* @arg @ref LL_RCC_PLLP_DIV_4
ganlikun	0:13413ea9a877	1590	* @arg @ref LL_RCC_PLLP_DIV_6
ganlikun	0:13413ea9a877	1591	* @arg @ref LL_RCC_PLLP_DIV_8
ganlikun	0:13413ea9a877	1592	* @retval PLL clock frequency (in Hz)
ganlikun	0:13413ea9a877	1593	*/
ganlikun	0:13413ea9a877	1594	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
ganlikun	0:13413ea9a877	1595	((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
ganlikun	0:13413ea9a877	1596
ganlikun	0:13413ea9a877	1597	#if defined(RCC_PLLR_SYSCLK_SUPPORT)
ganlikun	0:13413ea9a877	1598	/**
ganlikun	0:13413ea9a877	1599	* @brief Helper macro to calculate the PLLRCLK frequency on system domain
ganlikun	0:13413ea9a877	1600	* @note ex: @ref __LL_RCC_CALC_PLLRCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
ganlikun	0:13413ea9a877	1601	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
ganlikun	0:13413ea9a877	1602	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
ganlikun	0:13413ea9a877	1603	* @param __PLLM__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1604	* @arg @ref LL_RCC_PLLM_DIV_2
ganlikun	0:13413ea9a877	1605	* @arg @ref LL_RCC_PLLM_DIV_3
ganlikun	0:13413ea9a877	1606	* @arg @ref LL_RCC_PLLM_DIV_4
ganlikun	0:13413ea9a877	1607	* @arg @ref LL_RCC_PLLM_DIV_5
ganlikun	0:13413ea9a877	1608	* @arg @ref LL_RCC_PLLM_DIV_6
ganlikun	0:13413ea9a877	1609	* @arg @ref LL_RCC_PLLM_DIV_7
ganlikun	0:13413ea9a877	1610	* @arg @ref LL_RCC_PLLM_DIV_8
ganlikun	0:13413ea9a877	1611	* @arg @ref LL_RCC_PLLM_DIV_9
ganlikun	0:13413ea9a877	1612	* @arg @ref LL_RCC_PLLM_DIV_10
ganlikun	0:13413ea9a877	1613	* @arg @ref LL_RCC_PLLM_DIV_11
ganlikun	0:13413ea9a877	1614	* @arg @ref LL_RCC_PLLM_DIV_12
ganlikun	0:13413ea9a877	1615	* @arg @ref LL_RCC_PLLM_DIV_13
ganlikun	0:13413ea9a877	1616	* @arg @ref LL_RCC_PLLM_DIV_14
ganlikun	0:13413ea9a877	1617	* @arg @ref LL_RCC_PLLM_DIV_15
ganlikun	0:13413ea9a877	1618	* @arg @ref LL_RCC_PLLM_DIV_16
ganlikun	0:13413ea9a877	1619	* @arg @ref LL_RCC_PLLM_DIV_17
ganlikun	0:13413ea9a877	1620	* @arg @ref LL_RCC_PLLM_DIV_18
ganlikun	0:13413ea9a877	1621	* @arg @ref LL_RCC_PLLM_DIV_19
ganlikun	0:13413ea9a877	1622	* @arg @ref LL_RCC_PLLM_DIV_20
ganlikun	0:13413ea9a877	1623	* @arg @ref LL_RCC_PLLM_DIV_21
ganlikun	0:13413ea9a877	1624	* @arg @ref LL_RCC_PLLM_DIV_22
ganlikun	0:13413ea9a877	1625	* @arg @ref LL_RCC_PLLM_DIV_23
ganlikun	0:13413ea9a877	1626	* @arg @ref LL_RCC_PLLM_DIV_24
ganlikun	0:13413ea9a877	1627	* @arg @ref LL_RCC_PLLM_DIV_25
ganlikun	0:13413ea9a877	1628	* @arg @ref LL_RCC_PLLM_DIV_26
ganlikun	0:13413ea9a877	1629	* @arg @ref LL_RCC_PLLM_DIV_27
ganlikun	0:13413ea9a877	1630	* @arg @ref LL_RCC_PLLM_DIV_28
ganlikun	0:13413ea9a877	1631	* @arg @ref LL_RCC_PLLM_DIV_29
ganlikun	0:13413ea9a877	1632	* @arg @ref LL_RCC_PLLM_DIV_30
ganlikun	0:13413ea9a877	1633	* @arg @ref LL_RCC_PLLM_DIV_31
ganlikun	0:13413ea9a877	1634	* @arg @ref LL_RCC_PLLM_DIV_32
ganlikun	0:13413ea9a877	1635	* @arg @ref LL_RCC_PLLM_DIV_33
ganlikun	0:13413ea9a877	1636	* @arg @ref LL_RCC_PLLM_DIV_34
ganlikun	0:13413ea9a877	1637	* @arg @ref LL_RCC_PLLM_DIV_35
ganlikun	0:13413ea9a877	1638	* @arg @ref LL_RCC_PLLM_DIV_36
ganlikun	0:13413ea9a877	1639	* @arg @ref LL_RCC_PLLM_DIV_37
ganlikun	0:13413ea9a877	1640	* @arg @ref LL_RCC_PLLM_DIV_38
ganlikun	0:13413ea9a877	1641	* @arg @ref LL_RCC_PLLM_DIV_39
ganlikun	0:13413ea9a877	1642	* @arg @ref LL_RCC_PLLM_DIV_40
ganlikun	0:13413ea9a877	1643	* @arg @ref LL_RCC_PLLM_DIV_41
ganlikun	0:13413ea9a877	1644	* @arg @ref LL_RCC_PLLM_DIV_42
ganlikun	0:13413ea9a877	1645	* @arg @ref LL_RCC_PLLM_DIV_43
ganlikun	0:13413ea9a877	1646	* @arg @ref LL_RCC_PLLM_DIV_44
ganlikun	0:13413ea9a877	1647	* @arg @ref LL_RCC_PLLM_DIV_45
ganlikun	0:13413ea9a877	1648	* @arg @ref LL_RCC_PLLM_DIV_46
ganlikun	0:13413ea9a877	1649	* @arg @ref LL_RCC_PLLM_DIV_47
ganlikun	0:13413ea9a877	1650	* @arg @ref LL_RCC_PLLM_DIV_48
ganlikun	0:13413ea9a877	1651	* @arg @ref LL_RCC_PLLM_DIV_49
ganlikun	0:13413ea9a877	1652	* @arg @ref LL_RCC_PLLM_DIV_50
ganlikun	0:13413ea9a877	1653	* @arg @ref LL_RCC_PLLM_DIV_51
ganlikun	0:13413ea9a877	1654	* @arg @ref LL_RCC_PLLM_DIV_52
ganlikun	0:13413ea9a877	1655	* @arg @ref LL_RCC_PLLM_DIV_53
ganlikun	0:13413ea9a877	1656	* @arg @ref LL_RCC_PLLM_DIV_54
ganlikun	0:13413ea9a877	1657	* @arg @ref LL_RCC_PLLM_DIV_55
ganlikun	0:13413ea9a877	1658	* @arg @ref LL_RCC_PLLM_DIV_56
ganlikun	0:13413ea9a877	1659	* @arg @ref LL_RCC_PLLM_DIV_57
ganlikun	0:13413ea9a877	1660	* @arg @ref LL_RCC_PLLM_DIV_58
ganlikun	0:13413ea9a877	1661	* @arg @ref LL_RCC_PLLM_DIV_59
ganlikun	0:13413ea9a877	1662	* @arg @ref LL_RCC_PLLM_DIV_60
ganlikun	0:13413ea9a877	1663	* @arg @ref LL_RCC_PLLM_DIV_61
ganlikun	0:13413ea9a877	1664	* @arg @ref LL_RCC_PLLM_DIV_62
ganlikun	0:13413ea9a877	1665	* @arg @ref LL_RCC_PLLM_DIV_63
ganlikun	0:13413ea9a877	1666	* @param __PLLN__ Between 50 and 432
ganlikun	0:13413ea9a877	1667	* @param __PLLR__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1668	* @arg @ref LL_RCC_PLLR_DIV_2
ganlikun	0:13413ea9a877	1669	* @arg @ref LL_RCC_PLLR_DIV_3
ganlikun	0:13413ea9a877	1670	* @arg @ref LL_RCC_PLLR_DIV_4
ganlikun	0:13413ea9a877	1671	* @arg @ref LL_RCC_PLLR_DIV_5
ganlikun	0:13413ea9a877	1672	* @arg @ref LL_RCC_PLLR_DIV_6
ganlikun	0:13413ea9a877	1673	* @arg @ref LL_RCC_PLLR_DIV_7
ganlikun	0:13413ea9a877	1674	* @retval PLL clock frequency (in Hz)
ganlikun	0:13413ea9a877	1675	*/
ganlikun	0:13413ea9a877	1676	#define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
ganlikun	0:13413ea9a877	1677	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
ganlikun	0:13413ea9a877	1678
ganlikun	0:13413ea9a877	1679	#endif /* RCC_PLLR_SYSCLK_SUPPORT */
ganlikun	0:13413ea9a877	1680
ganlikun	0:13413ea9a877	1681	/**
ganlikun	0:13413ea9a877	1682	* @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
ganlikun	0:13413ea9a877	1683	* @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
ganlikun	0:13413ea9a877	1684	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
ganlikun	0:13413ea9a877	1685	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
ganlikun	0:13413ea9a877	1686	* @param __PLLM__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1687	* @arg @ref LL_RCC_PLLM_DIV_2
ganlikun	0:13413ea9a877	1688	* @arg @ref LL_RCC_PLLM_DIV_3
ganlikun	0:13413ea9a877	1689	* @arg @ref LL_RCC_PLLM_DIV_4
ganlikun	0:13413ea9a877	1690	* @arg @ref LL_RCC_PLLM_DIV_5
ganlikun	0:13413ea9a877	1691	* @arg @ref LL_RCC_PLLM_DIV_6
ganlikun	0:13413ea9a877	1692	* @arg @ref LL_RCC_PLLM_DIV_7
ganlikun	0:13413ea9a877	1693	* @arg @ref LL_RCC_PLLM_DIV_8
ganlikun	0:13413ea9a877	1694	* @arg @ref LL_RCC_PLLM_DIV_9
ganlikun	0:13413ea9a877	1695	* @arg @ref LL_RCC_PLLM_DIV_10
ganlikun	0:13413ea9a877	1696	* @arg @ref LL_RCC_PLLM_DIV_11
ganlikun	0:13413ea9a877	1697	* @arg @ref LL_RCC_PLLM_DIV_12
ganlikun	0:13413ea9a877	1698	* @arg @ref LL_RCC_PLLM_DIV_13
ganlikun	0:13413ea9a877	1699	* @arg @ref LL_RCC_PLLM_DIV_14
ganlikun	0:13413ea9a877	1700	* @arg @ref LL_RCC_PLLM_DIV_15
ganlikun	0:13413ea9a877	1701	* @arg @ref LL_RCC_PLLM_DIV_16
ganlikun	0:13413ea9a877	1702	* @arg @ref LL_RCC_PLLM_DIV_17
ganlikun	0:13413ea9a877	1703	* @arg @ref LL_RCC_PLLM_DIV_18
ganlikun	0:13413ea9a877	1704	* @arg @ref LL_RCC_PLLM_DIV_19
ganlikun	0:13413ea9a877	1705	* @arg @ref LL_RCC_PLLM_DIV_20
ganlikun	0:13413ea9a877	1706	* @arg @ref LL_RCC_PLLM_DIV_21
ganlikun	0:13413ea9a877	1707	* @arg @ref LL_RCC_PLLM_DIV_22
ganlikun	0:13413ea9a877	1708	* @arg @ref LL_RCC_PLLM_DIV_23
ganlikun	0:13413ea9a877	1709	* @arg @ref LL_RCC_PLLM_DIV_24
ganlikun	0:13413ea9a877	1710	* @arg @ref LL_RCC_PLLM_DIV_25
ganlikun	0:13413ea9a877	1711	* @arg @ref LL_RCC_PLLM_DIV_26
ganlikun	0:13413ea9a877	1712	* @arg @ref LL_RCC_PLLM_DIV_27
ganlikun	0:13413ea9a877	1713	* @arg @ref LL_RCC_PLLM_DIV_28
ganlikun	0:13413ea9a877	1714	* @arg @ref LL_RCC_PLLM_DIV_29
ganlikun	0:13413ea9a877	1715	* @arg @ref LL_RCC_PLLM_DIV_30
ganlikun	0:13413ea9a877	1716	* @arg @ref LL_RCC_PLLM_DIV_31
ganlikun	0:13413ea9a877	1717	* @arg @ref LL_RCC_PLLM_DIV_32
ganlikun	0:13413ea9a877	1718	* @arg @ref LL_RCC_PLLM_DIV_33
ganlikun	0:13413ea9a877	1719	* @arg @ref LL_RCC_PLLM_DIV_34
ganlikun	0:13413ea9a877	1720	* @arg @ref LL_RCC_PLLM_DIV_35
ganlikun	0:13413ea9a877	1721	* @arg @ref LL_RCC_PLLM_DIV_36
ganlikun	0:13413ea9a877	1722	* @arg @ref LL_RCC_PLLM_DIV_37
ganlikun	0:13413ea9a877	1723	* @arg @ref LL_RCC_PLLM_DIV_38
ganlikun	0:13413ea9a877	1724	* @arg @ref LL_RCC_PLLM_DIV_39
ganlikun	0:13413ea9a877	1725	* @arg @ref LL_RCC_PLLM_DIV_40
ganlikun	0:13413ea9a877	1726	* @arg @ref LL_RCC_PLLM_DIV_41
ganlikun	0:13413ea9a877	1727	* @arg @ref LL_RCC_PLLM_DIV_42
ganlikun	0:13413ea9a877	1728	* @arg @ref LL_RCC_PLLM_DIV_43
ganlikun	0:13413ea9a877	1729	* @arg @ref LL_RCC_PLLM_DIV_44
ganlikun	0:13413ea9a877	1730	* @arg @ref LL_RCC_PLLM_DIV_45
ganlikun	0:13413ea9a877	1731	* @arg @ref LL_RCC_PLLM_DIV_46
ganlikun	0:13413ea9a877	1732	* @arg @ref LL_RCC_PLLM_DIV_47
ganlikun	0:13413ea9a877	1733	* @arg @ref LL_RCC_PLLM_DIV_48
ganlikun	0:13413ea9a877	1734	* @arg @ref LL_RCC_PLLM_DIV_49
ganlikun	0:13413ea9a877	1735	* @arg @ref LL_RCC_PLLM_DIV_50
ganlikun	0:13413ea9a877	1736	* @arg @ref LL_RCC_PLLM_DIV_51
ganlikun	0:13413ea9a877	1737	* @arg @ref LL_RCC_PLLM_DIV_52
ganlikun	0:13413ea9a877	1738	* @arg @ref LL_RCC_PLLM_DIV_53
ganlikun	0:13413ea9a877	1739	* @arg @ref LL_RCC_PLLM_DIV_54
ganlikun	0:13413ea9a877	1740	* @arg @ref LL_RCC_PLLM_DIV_55
ganlikun	0:13413ea9a877	1741	* @arg @ref LL_RCC_PLLM_DIV_56
ganlikun	0:13413ea9a877	1742	* @arg @ref LL_RCC_PLLM_DIV_57
ganlikun	0:13413ea9a877	1743	* @arg @ref LL_RCC_PLLM_DIV_58
ganlikun	0:13413ea9a877	1744	* @arg @ref LL_RCC_PLLM_DIV_59
ganlikun	0:13413ea9a877	1745	* @arg @ref LL_RCC_PLLM_DIV_60
ganlikun	0:13413ea9a877	1746	* @arg @ref LL_RCC_PLLM_DIV_61
ganlikun	0:13413ea9a877	1747	* @arg @ref LL_RCC_PLLM_DIV_62
ganlikun	0:13413ea9a877	1748	* @arg @ref LL_RCC_PLLM_DIV_63
ganlikun	0:13413ea9a877	1749	* @param __PLLN__ Between 50/192(*) and 432
ganlikun	0:13413ea9a877	1750	*
ganlikun	0:13413ea9a877	1751	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	1752	* @param __PLLQ__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1753	* @arg @ref LL_RCC_PLLQ_DIV_2
ganlikun	0:13413ea9a877	1754	* @arg @ref LL_RCC_PLLQ_DIV_3
ganlikun	0:13413ea9a877	1755	* @arg @ref LL_RCC_PLLQ_DIV_4
ganlikun	0:13413ea9a877	1756	* @arg @ref LL_RCC_PLLQ_DIV_5
ganlikun	0:13413ea9a877	1757	* @arg @ref LL_RCC_PLLQ_DIV_6
ganlikun	0:13413ea9a877	1758	* @arg @ref LL_RCC_PLLQ_DIV_7
ganlikun	0:13413ea9a877	1759	* @arg @ref LL_RCC_PLLQ_DIV_8
ganlikun	0:13413ea9a877	1760	* @arg @ref LL_RCC_PLLQ_DIV_9
ganlikun	0:13413ea9a877	1761	* @arg @ref LL_RCC_PLLQ_DIV_10
ganlikun	0:13413ea9a877	1762	* @arg @ref LL_RCC_PLLQ_DIV_11
ganlikun	0:13413ea9a877	1763	* @arg @ref LL_RCC_PLLQ_DIV_12
ganlikun	0:13413ea9a877	1764	* @arg @ref LL_RCC_PLLQ_DIV_13
ganlikun	0:13413ea9a877	1765	* @arg @ref LL_RCC_PLLQ_DIV_14
ganlikun	0:13413ea9a877	1766	* @arg @ref LL_RCC_PLLQ_DIV_15
ganlikun	0:13413ea9a877	1767	* @retval PLL clock frequency (in Hz)
ganlikun	0:13413ea9a877	1768	*/
ganlikun	0:13413ea9a877	1769	#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
ganlikun	0:13413ea9a877	1770	((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
ganlikun	0:13413ea9a877	1771
ganlikun	0:13413ea9a877	1772	#if defined(DSI)
ganlikun	0:13413ea9a877	1773	/**
ganlikun	0:13413ea9a877	1774	* @brief Helper macro to calculate the PLLCLK frequency used on DSI
ganlikun	0:13413ea9a877	1775	* @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
ganlikun	0:13413ea9a877	1776	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
ganlikun	0:13413ea9a877	1777	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
ganlikun	0:13413ea9a877	1778	* @param __PLLM__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1779	* @arg @ref LL_RCC_PLLM_DIV_2
ganlikun	0:13413ea9a877	1780	* @arg @ref LL_RCC_PLLM_DIV_3
ganlikun	0:13413ea9a877	1781	* @arg @ref LL_RCC_PLLM_DIV_4
ganlikun	0:13413ea9a877	1782	* @arg @ref LL_RCC_PLLM_DIV_5
ganlikun	0:13413ea9a877	1783	* @arg @ref LL_RCC_PLLM_DIV_6
ganlikun	0:13413ea9a877	1784	* @arg @ref LL_RCC_PLLM_DIV_7
ganlikun	0:13413ea9a877	1785	* @arg @ref LL_RCC_PLLM_DIV_8
ganlikun	0:13413ea9a877	1786	* @arg @ref LL_RCC_PLLM_DIV_9
ganlikun	0:13413ea9a877	1787	* @arg @ref LL_RCC_PLLM_DIV_10
ganlikun	0:13413ea9a877	1788	* @arg @ref LL_RCC_PLLM_DIV_11
ganlikun	0:13413ea9a877	1789	* @arg @ref LL_RCC_PLLM_DIV_12
ganlikun	0:13413ea9a877	1790	* @arg @ref LL_RCC_PLLM_DIV_13
ganlikun	0:13413ea9a877	1791	* @arg @ref LL_RCC_PLLM_DIV_14
ganlikun	0:13413ea9a877	1792	* @arg @ref LL_RCC_PLLM_DIV_15
ganlikun	0:13413ea9a877	1793	* @arg @ref LL_RCC_PLLM_DIV_16
ganlikun	0:13413ea9a877	1794	* @arg @ref LL_RCC_PLLM_DIV_17
ganlikun	0:13413ea9a877	1795	* @arg @ref LL_RCC_PLLM_DIV_18
ganlikun	0:13413ea9a877	1796	* @arg @ref LL_RCC_PLLM_DIV_19
ganlikun	0:13413ea9a877	1797	* @arg @ref LL_RCC_PLLM_DIV_20
ganlikun	0:13413ea9a877	1798	* @arg @ref LL_RCC_PLLM_DIV_21
ganlikun	0:13413ea9a877	1799	* @arg @ref LL_RCC_PLLM_DIV_22
ganlikun	0:13413ea9a877	1800	* @arg @ref LL_RCC_PLLM_DIV_23
ganlikun	0:13413ea9a877	1801	* @arg @ref LL_RCC_PLLM_DIV_24
ganlikun	0:13413ea9a877	1802	* @arg @ref LL_RCC_PLLM_DIV_25
ganlikun	0:13413ea9a877	1803	* @arg @ref LL_RCC_PLLM_DIV_26
ganlikun	0:13413ea9a877	1804	* @arg @ref LL_RCC_PLLM_DIV_27
ganlikun	0:13413ea9a877	1805	* @arg @ref LL_RCC_PLLM_DIV_28
ganlikun	0:13413ea9a877	1806	* @arg @ref LL_RCC_PLLM_DIV_29
ganlikun	0:13413ea9a877	1807	* @arg @ref LL_RCC_PLLM_DIV_30
ganlikun	0:13413ea9a877	1808	* @arg @ref LL_RCC_PLLM_DIV_31
ganlikun	0:13413ea9a877	1809	* @arg @ref LL_RCC_PLLM_DIV_32
ganlikun	0:13413ea9a877	1810	* @arg @ref LL_RCC_PLLM_DIV_33
ganlikun	0:13413ea9a877	1811	* @arg @ref LL_RCC_PLLM_DIV_34
ganlikun	0:13413ea9a877	1812	* @arg @ref LL_RCC_PLLM_DIV_35
ganlikun	0:13413ea9a877	1813	* @arg @ref LL_RCC_PLLM_DIV_36
ganlikun	0:13413ea9a877	1814	* @arg @ref LL_RCC_PLLM_DIV_37
ganlikun	0:13413ea9a877	1815	* @arg @ref LL_RCC_PLLM_DIV_38
ganlikun	0:13413ea9a877	1816	* @arg @ref LL_RCC_PLLM_DIV_39
ganlikun	0:13413ea9a877	1817	* @arg @ref LL_RCC_PLLM_DIV_40
ganlikun	0:13413ea9a877	1818	* @arg @ref LL_RCC_PLLM_DIV_41
ganlikun	0:13413ea9a877	1819	* @arg @ref LL_RCC_PLLM_DIV_42
ganlikun	0:13413ea9a877	1820	* @arg @ref LL_RCC_PLLM_DIV_43
ganlikun	0:13413ea9a877	1821	* @arg @ref LL_RCC_PLLM_DIV_44
ganlikun	0:13413ea9a877	1822	* @arg @ref LL_RCC_PLLM_DIV_45
ganlikun	0:13413ea9a877	1823	* @arg @ref LL_RCC_PLLM_DIV_46
ganlikun	0:13413ea9a877	1824	* @arg @ref LL_RCC_PLLM_DIV_47
ganlikun	0:13413ea9a877	1825	* @arg @ref LL_RCC_PLLM_DIV_48
ganlikun	0:13413ea9a877	1826	* @arg @ref LL_RCC_PLLM_DIV_49
ganlikun	0:13413ea9a877	1827	* @arg @ref LL_RCC_PLLM_DIV_50
ganlikun	0:13413ea9a877	1828	* @arg @ref LL_RCC_PLLM_DIV_51
ganlikun	0:13413ea9a877	1829	* @arg @ref LL_RCC_PLLM_DIV_52
ganlikun	0:13413ea9a877	1830	* @arg @ref LL_RCC_PLLM_DIV_53
ganlikun	0:13413ea9a877	1831	* @arg @ref LL_RCC_PLLM_DIV_54
ganlikun	0:13413ea9a877	1832	* @arg @ref LL_RCC_PLLM_DIV_55
ganlikun	0:13413ea9a877	1833	* @arg @ref LL_RCC_PLLM_DIV_56
ganlikun	0:13413ea9a877	1834	* @arg @ref LL_RCC_PLLM_DIV_57
ganlikun	0:13413ea9a877	1835	* @arg @ref LL_RCC_PLLM_DIV_58
ganlikun	0:13413ea9a877	1836	* @arg @ref LL_RCC_PLLM_DIV_59
ganlikun	0:13413ea9a877	1837	* @arg @ref LL_RCC_PLLM_DIV_60
ganlikun	0:13413ea9a877	1838	* @arg @ref LL_RCC_PLLM_DIV_61
ganlikun	0:13413ea9a877	1839	* @arg @ref LL_RCC_PLLM_DIV_62
ganlikun	0:13413ea9a877	1840	* @arg @ref LL_RCC_PLLM_DIV_63
ganlikun	0:13413ea9a877	1841	* @param __PLLN__ Between 50 and 432
ganlikun	0:13413ea9a877	1842	* @param __PLLR__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1843	* @arg @ref LL_RCC_PLLR_DIV_2
ganlikun	0:13413ea9a877	1844	* @arg @ref LL_RCC_PLLR_DIV_3
ganlikun	0:13413ea9a877	1845	* @arg @ref LL_RCC_PLLR_DIV_4
ganlikun	0:13413ea9a877	1846	* @arg @ref LL_RCC_PLLR_DIV_5
ganlikun	0:13413ea9a877	1847	* @arg @ref LL_RCC_PLLR_DIV_6
ganlikun	0:13413ea9a877	1848	* @arg @ref LL_RCC_PLLR_DIV_7
ganlikun	0:13413ea9a877	1849	* @retval PLL clock frequency (in Hz)
ganlikun	0:13413ea9a877	1850	*/
ganlikun	0:13413ea9a877	1851	#define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
ganlikun	0:13413ea9a877	1852	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
ganlikun	0:13413ea9a877	1853	#endif /* DSI */
ganlikun	0:13413ea9a877	1854
ganlikun	0:13413ea9a877	1855	#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
ganlikun	0:13413ea9a877	1856	/**
ganlikun	0:13413ea9a877	1857	* @brief Helper macro to calculate the PLLCLK frequency used on I2S
ganlikun	0:13413ea9a877	1858	* @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
ganlikun	0:13413ea9a877	1859	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
ganlikun	0:13413ea9a877	1860	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
ganlikun	0:13413ea9a877	1861	* @param __PLLM__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1862	* @arg @ref LL_RCC_PLLM_DIV_2
ganlikun	0:13413ea9a877	1863	* @arg @ref LL_RCC_PLLM_DIV_3
ganlikun	0:13413ea9a877	1864	* @arg @ref LL_RCC_PLLM_DIV_4
ganlikun	0:13413ea9a877	1865	* @arg @ref LL_RCC_PLLM_DIV_5
ganlikun	0:13413ea9a877	1866	* @arg @ref LL_RCC_PLLM_DIV_6
ganlikun	0:13413ea9a877	1867	* @arg @ref LL_RCC_PLLM_DIV_7
ganlikun	0:13413ea9a877	1868	* @arg @ref LL_RCC_PLLM_DIV_8
ganlikun	0:13413ea9a877	1869	* @arg @ref LL_RCC_PLLM_DIV_9
ganlikun	0:13413ea9a877	1870	* @arg @ref LL_RCC_PLLM_DIV_10
ganlikun	0:13413ea9a877	1871	* @arg @ref LL_RCC_PLLM_DIV_11
ganlikun	0:13413ea9a877	1872	* @arg @ref LL_RCC_PLLM_DIV_12
ganlikun	0:13413ea9a877	1873	* @arg @ref LL_RCC_PLLM_DIV_13
ganlikun	0:13413ea9a877	1874	* @arg @ref LL_RCC_PLLM_DIV_14
ganlikun	0:13413ea9a877	1875	* @arg @ref LL_RCC_PLLM_DIV_15
ganlikun	0:13413ea9a877	1876	* @arg @ref LL_RCC_PLLM_DIV_16
ganlikun	0:13413ea9a877	1877	* @arg @ref LL_RCC_PLLM_DIV_17
ganlikun	0:13413ea9a877	1878	* @arg @ref LL_RCC_PLLM_DIV_18
ganlikun	0:13413ea9a877	1879	* @arg @ref LL_RCC_PLLM_DIV_19
ganlikun	0:13413ea9a877	1880	* @arg @ref LL_RCC_PLLM_DIV_20
ganlikun	0:13413ea9a877	1881	* @arg @ref LL_RCC_PLLM_DIV_21
ganlikun	0:13413ea9a877	1882	* @arg @ref LL_RCC_PLLM_DIV_22
ganlikun	0:13413ea9a877	1883	* @arg @ref LL_RCC_PLLM_DIV_23
ganlikun	0:13413ea9a877	1884	* @arg @ref LL_RCC_PLLM_DIV_24
ganlikun	0:13413ea9a877	1885	* @arg @ref LL_RCC_PLLM_DIV_25
ganlikun	0:13413ea9a877	1886	* @arg @ref LL_RCC_PLLM_DIV_26
ganlikun	0:13413ea9a877	1887	* @arg @ref LL_RCC_PLLM_DIV_27
ganlikun	0:13413ea9a877	1888	* @arg @ref LL_RCC_PLLM_DIV_28
ganlikun	0:13413ea9a877	1889	* @arg @ref LL_RCC_PLLM_DIV_29
ganlikun	0:13413ea9a877	1890	* @arg @ref LL_RCC_PLLM_DIV_30
ganlikun	0:13413ea9a877	1891	* @arg @ref LL_RCC_PLLM_DIV_31
ganlikun	0:13413ea9a877	1892	* @arg @ref LL_RCC_PLLM_DIV_32
ganlikun	0:13413ea9a877	1893	* @arg @ref LL_RCC_PLLM_DIV_33
ganlikun	0:13413ea9a877	1894	* @arg @ref LL_RCC_PLLM_DIV_34
ganlikun	0:13413ea9a877	1895	* @arg @ref LL_RCC_PLLM_DIV_35
ganlikun	0:13413ea9a877	1896	* @arg @ref LL_RCC_PLLM_DIV_36
ganlikun	0:13413ea9a877	1897	* @arg @ref LL_RCC_PLLM_DIV_37
ganlikun	0:13413ea9a877	1898	* @arg @ref LL_RCC_PLLM_DIV_38
ganlikun	0:13413ea9a877	1899	* @arg @ref LL_RCC_PLLM_DIV_39
ganlikun	0:13413ea9a877	1900	* @arg @ref LL_RCC_PLLM_DIV_40
ganlikun	0:13413ea9a877	1901	* @arg @ref LL_RCC_PLLM_DIV_41
ganlikun	0:13413ea9a877	1902	* @arg @ref LL_RCC_PLLM_DIV_42
ganlikun	0:13413ea9a877	1903	* @arg @ref LL_RCC_PLLM_DIV_43
ganlikun	0:13413ea9a877	1904	* @arg @ref LL_RCC_PLLM_DIV_44
ganlikun	0:13413ea9a877	1905	* @arg @ref LL_RCC_PLLM_DIV_45
ganlikun	0:13413ea9a877	1906	* @arg @ref LL_RCC_PLLM_DIV_46
ganlikun	0:13413ea9a877	1907	* @arg @ref LL_RCC_PLLM_DIV_47
ganlikun	0:13413ea9a877	1908	* @arg @ref LL_RCC_PLLM_DIV_48
ganlikun	0:13413ea9a877	1909	* @arg @ref LL_RCC_PLLM_DIV_49
ganlikun	0:13413ea9a877	1910	* @arg @ref LL_RCC_PLLM_DIV_50
ganlikun	0:13413ea9a877	1911	* @arg @ref LL_RCC_PLLM_DIV_51
ganlikun	0:13413ea9a877	1912	* @arg @ref LL_RCC_PLLM_DIV_52
ganlikun	0:13413ea9a877	1913	* @arg @ref LL_RCC_PLLM_DIV_53
ganlikun	0:13413ea9a877	1914	* @arg @ref LL_RCC_PLLM_DIV_54
ganlikun	0:13413ea9a877	1915	* @arg @ref LL_RCC_PLLM_DIV_55
ganlikun	0:13413ea9a877	1916	* @arg @ref LL_RCC_PLLM_DIV_56
ganlikun	0:13413ea9a877	1917	* @arg @ref LL_RCC_PLLM_DIV_57
ganlikun	0:13413ea9a877	1918	* @arg @ref LL_RCC_PLLM_DIV_58
ganlikun	0:13413ea9a877	1919	* @arg @ref LL_RCC_PLLM_DIV_59
ganlikun	0:13413ea9a877	1920	* @arg @ref LL_RCC_PLLM_DIV_60
ganlikun	0:13413ea9a877	1921	* @arg @ref LL_RCC_PLLM_DIV_61
ganlikun	0:13413ea9a877	1922	* @arg @ref LL_RCC_PLLM_DIV_62
ganlikun	0:13413ea9a877	1923	* @arg @ref LL_RCC_PLLM_DIV_63
ganlikun	0:13413ea9a877	1924	* @param __PLLN__ Between 50 and 432
ganlikun	0:13413ea9a877	1925	* @param __PLLR__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1926	* @arg @ref LL_RCC_PLLR_DIV_2
ganlikun	0:13413ea9a877	1927	* @arg @ref LL_RCC_PLLR_DIV_3
ganlikun	0:13413ea9a877	1928	* @arg @ref LL_RCC_PLLR_DIV_4
ganlikun	0:13413ea9a877	1929	* @arg @ref LL_RCC_PLLR_DIV_5
ganlikun	0:13413ea9a877	1930	* @arg @ref LL_RCC_PLLR_DIV_6
ganlikun	0:13413ea9a877	1931	* @arg @ref LL_RCC_PLLR_DIV_7
ganlikun	0:13413ea9a877	1932	* @retval PLL clock frequency (in Hz)
ganlikun	0:13413ea9a877	1933	*/
ganlikun	0:13413ea9a877	1934	#define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
ganlikun	0:13413ea9a877	1935	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
ganlikun	0:13413ea9a877	1936	#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
ganlikun	0:13413ea9a877	1937
ganlikun	0:13413ea9a877	1938	#if defined(SPDIFRX)
ganlikun	0:13413ea9a877	1939	/**
ganlikun	0:13413ea9a877	1940	* @brief Helper macro to calculate the PLLCLK frequency used on SPDIFRX
ganlikun	0:13413ea9a877	1941	* @note ex: @ref __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
ganlikun	0:13413ea9a877	1942	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
ganlikun	0:13413ea9a877	1943	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
ganlikun	0:13413ea9a877	1944	* @param __PLLM__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1945	* @arg @ref LL_RCC_PLLM_DIV_2
ganlikun	0:13413ea9a877	1946	* @arg @ref LL_RCC_PLLM_DIV_3
ganlikun	0:13413ea9a877	1947	* @arg @ref LL_RCC_PLLM_DIV_4
ganlikun	0:13413ea9a877	1948	* @arg @ref LL_RCC_PLLM_DIV_5
ganlikun	0:13413ea9a877	1949	* @arg @ref LL_RCC_PLLM_DIV_6
ganlikun	0:13413ea9a877	1950	* @arg @ref LL_RCC_PLLM_DIV_7
ganlikun	0:13413ea9a877	1951	* @arg @ref LL_RCC_PLLM_DIV_8
ganlikun	0:13413ea9a877	1952	* @arg @ref LL_RCC_PLLM_DIV_9
ganlikun	0:13413ea9a877	1953	* @arg @ref LL_RCC_PLLM_DIV_10
ganlikun	0:13413ea9a877	1954	* @arg @ref LL_RCC_PLLM_DIV_11
ganlikun	0:13413ea9a877	1955	* @arg @ref LL_RCC_PLLM_DIV_12
ganlikun	0:13413ea9a877	1956	* @arg @ref LL_RCC_PLLM_DIV_13
ganlikun	0:13413ea9a877	1957	* @arg @ref LL_RCC_PLLM_DIV_14
ganlikun	0:13413ea9a877	1958	* @arg @ref LL_RCC_PLLM_DIV_15
ganlikun	0:13413ea9a877	1959	* @arg @ref LL_RCC_PLLM_DIV_16
ganlikun	0:13413ea9a877	1960	* @arg @ref LL_RCC_PLLM_DIV_17
ganlikun	0:13413ea9a877	1961	* @arg @ref LL_RCC_PLLM_DIV_18
ganlikun	0:13413ea9a877	1962	* @arg @ref LL_RCC_PLLM_DIV_19
ganlikun	0:13413ea9a877	1963	* @arg @ref LL_RCC_PLLM_DIV_20
ganlikun	0:13413ea9a877	1964	* @arg @ref LL_RCC_PLLM_DIV_21
ganlikun	0:13413ea9a877	1965	* @arg @ref LL_RCC_PLLM_DIV_22
ganlikun	0:13413ea9a877	1966	* @arg @ref LL_RCC_PLLM_DIV_23
ganlikun	0:13413ea9a877	1967	* @arg @ref LL_RCC_PLLM_DIV_24
ganlikun	0:13413ea9a877	1968	* @arg @ref LL_RCC_PLLM_DIV_25
ganlikun	0:13413ea9a877	1969	* @arg @ref LL_RCC_PLLM_DIV_26
ganlikun	0:13413ea9a877	1970	* @arg @ref LL_RCC_PLLM_DIV_27
ganlikun	0:13413ea9a877	1971	* @arg @ref LL_RCC_PLLM_DIV_28
ganlikun	0:13413ea9a877	1972	* @arg @ref LL_RCC_PLLM_DIV_29
ganlikun	0:13413ea9a877	1973	* @arg @ref LL_RCC_PLLM_DIV_30
ganlikun	0:13413ea9a877	1974	* @arg @ref LL_RCC_PLLM_DIV_31
ganlikun	0:13413ea9a877	1975	* @arg @ref LL_RCC_PLLM_DIV_32
ganlikun	0:13413ea9a877	1976	* @arg @ref LL_RCC_PLLM_DIV_33
ganlikun	0:13413ea9a877	1977	* @arg @ref LL_RCC_PLLM_DIV_34
ganlikun	0:13413ea9a877	1978	* @arg @ref LL_RCC_PLLM_DIV_35
ganlikun	0:13413ea9a877	1979	* @arg @ref LL_RCC_PLLM_DIV_36
ganlikun	0:13413ea9a877	1980	* @arg @ref LL_RCC_PLLM_DIV_37
ganlikun	0:13413ea9a877	1981	* @arg @ref LL_RCC_PLLM_DIV_38
ganlikun	0:13413ea9a877	1982	* @arg @ref LL_RCC_PLLM_DIV_39
ganlikun	0:13413ea9a877	1983	* @arg @ref LL_RCC_PLLM_DIV_40
ganlikun	0:13413ea9a877	1984	* @arg @ref LL_RCC_PLLM_DIV_41
ganlikun	0:13413ea9a877	1985	* @arg @ref LL_RCC_PLLM_DIV_42
ganlikun	0:13413ea9a877	1986	* @arg @ref LL_RCC_PLLM_DIV_43
ganlikun	0:13413ea9a877	1987	* @arg @ref LL_RCC_PLLM_DIV_44
ganlikun	0:13413ea9a877	1988	* @arg @ref LL_RCC_PLLM_DIV_45
ganlikun	0:13413ea9a877	1989	* @arg @ref LL_RCC_PLLM_DIV_46
ganlikun	0:13413ea9a877	1990	* @arg @ref LL_RCC_PLLM_DIV_47
ganlikun	0:13413ea9a877	1991	* @arg @ref LL_RCC_PLLM_DIV_48
ganlikun	0:13413ea9a877	1992	* @arg @ref LL_RCC_PLLM_DIV_49
ganlikun	0:13413ea9a877	1993	* @arg @ref LL_RCC_PLLM_DIV_50
ganlikun	0:13413ea9a877	1994	* @arg @ref LL_RCC_PLLM_DIV_51
ganlikun	0:13413ea9a877	1995	* @arg @ref LL_RCC_PLLM_DIV_52
ganlikun	0:13413ea9a877	1996	* @arg @ref LL_RCC_PLLM_DIV_53
ganlikun	0:13413ea9a877	1997	* @arg @ref LL_RCC_PLLM_DIV_54
ganlikun	0:13413ea9a877	1998	* @arg @ref LL_RCC_PLLM_DIV_55
ganlikun	0:13413ea9a877	1999	* @arg @ref LL_RCC_PLLM_DIV_56
ganlikun	0:13413ea9a877	2000	* @arg @ref LL_RCC_PLLM_DIV_57
ganlikun	0:13413ea9a877	2001	* @arg @ref LL_RCC_PLLM_DIV_58
ganlikun	0:13413ea9a877	2002	* @arg @ref LL_RCC_PLLM_DIV_59
ganlikun	0:13413ea9a877	2003	* @arg @ref LL_RCC_PLLM_DIV_60
ganlikun	0:13413ea9a877	2004	* @arg @ref LL_RCC_PLLM_DIV_61
ganlikun	0:13413ea9a877	2005	* @arg @ref LL_RCC_PLLM_DIV_62
ganlikun	0:13413ea9a877	2006	* @arg @ref LL_RCC_PLLM_DIV_63
ganlikun	0:13413ea9a877	2007	* @param __PLLN__ Between 50 and 432
ganlikun	0:13413ea9a877	2008	* @param __PLLR__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2009	* @arg @ref LL_RCC_PLLR_DIV_2
ganlikun	0:13413ea9a877	2010	* @arg @ref LL_RCC_PLLR_DIV_3
ganlikun	0:13413ea9a877	2011	* @arg @ref LL_RCC_PLLR_DIV_4
ganlikun	0:13413ea9a877	2012	* @arg @ref LL_RCC_PLLR_DIV_5
ganlikun	0:13413ea9a877	2013	* @arg @ref LL_RCC_PLLR_DIV_6
ganlikun	0:13413ea9a877	2014	* @arg @ref LL_RCC_PLLR_DIV_7
ganlikun	0:13413ea9a877	2015	* @retval PLL clock frequency (in Hz)
ganlikun	0:13413ea9a877	2016	*/
ganlikun	0:13413ea9a877	2017	#define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
ganlikun	0:13413ea9a877	2018	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
ganlikun	0:13413ea9a877	2019	#endif /* SPDIFRX */
ganlikun	0:13413ea9a877	2020
ganlikun	0:13413ea9a877	2021	#if defined(RCC_PLLCFGR_PLLR)
ganlikun	0:13413ea9a877	2022	#if defined(SAI1)
ganlikun	0:13413ea9a877	2023	/**
ganlikun	0:13413ea9a877	2024	* @brief Helper macro to calculate the PLLCLK frequency used on SAI
ganlikun	0:13413ea9a877	2025	* @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
ganlikun	0:13413ea9a877	2026	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR (), @ref LL_RCC_PLL_GetDIVR ());
ganlikun	0:13413ea9a877	2027	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
ganlikun	0:13413ea9a877	2028	* @param __PLLM__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2029	* @arg @ref LL_RCC_PLLM_DIV_2
ganlikun	0:13413ea9a877	2030	* @arg @ref LL_RCC_PLLM_DIV_3
ganlikun	0:13413ea9a877	2031	* @arg @ref LL_RCC_PLLM_DIV_4
ganlikun	0:13413ea9a877	2032	* @arg @ref LL_RCC_PLLM_DIV_5
ganlikun	0:13413ea9a877	2033	* @arg @ref LL_RCC_PLLM_DIV_6
ganlikun	0:13413ea9a877	2034	* @arg @ref LL_RCC_PLLM_DIV_7
ganlikun	0:13413ea9a877	2035	* @arg @ref LL_RCC_PLLM_DIV_8
ganlikun	0:13413ea9a877	2036	* @arg @ref LL_RCC_PLLM_DIV_9
ganlikun	0:13413ea9a877	2037	* @arg @ref LL_RCC_PLLM_DIV_10
ganlikun	0:13413ea9a877	2038	* @arg @ref LL_RCC_PLLM_DIV_11
ganlikun	0:13413ea9a877	2039	* @arg @ref LL_RCC_PLLM_DIV_12
ganlikun	0:13413ea9a877	2040	* @arg @ref LL_RCC_PLLM_DIV_13
ganlikun	0:13413ea9a877	2041	* @arg @ref LL_RCC_PLLM_DIV_14
ganlikun	0:13413ea9a877	2042	* @arg @ref LL_RCC_PLLM_DIV_15
ganlikun	0:13413ea9a877	2043	* @arg @ref LL_RCC_PLLM_DIV_16
ganlikun	0:13413ea9a877	2044	* @arg @ref LL_RCC_PLLM_DIV_17
ganlikun	0:13413ea9a877	2045	* @arg @ref LL_RCC_PLLM_DIV_18
ganlikun	0:13413ea9a877	2046	* @arg @ref LL_RCC_PLLM_DIV_19
ganlikun	0:13413ea9a877	2047	* @arg @ref LL_RCC_PLLM_DIV_20
ganlikun	0:13413ea9a877	2048	* @arg @ref LL_RCC_PLLM_DIV_21
ganlikun	0:13413ea9a877	2049	* @arg @ref LL_RCC_PLLM_DIV_22
ganlikun	0:13413ea9a877	2050	* @arg @ref LL_RCC_PLLM_DIV_23
ganlikun	0:13413ea9a877	2051	* @arg @ref LL_RCC_PLLM_DIV_24
ganlikun	0:13413ea9a877	2052	* @arg @ref LL_RCC_PLLM_DIV_25
ganlikun	0:13413ea9a877	2053	* @arg @ref LL_RCC_PLLM_DIV_26
ganlikun	0:13413ea9a877	2054	* @arg @ref LL_RCC_PLLM_DIV_27
ganlikun	0:13413ea9a877	2055	* @arg @ref LL_RCC_PLLM_DIV_28
ganlikun	0:13413ea9a877	2056	* @arg @ref LL_RCC_PLLM_DIV_29
ganlikun	0:13413ea9a877	2057	* @arg @ref LL_RCC_PLLM_DIV_30
ganlikun	0:13413ea9a877	2058	* @arg @ref LL_RCC_PLLM_DIV_31
ganlikun	0:13413ea9a877	2059	* @arg @ref LL_RCC_PLLM_DIV_32
ganlikun	0:13413ea9a877	2060	* @arg @ref LL_RCC_PLLM_DIV_33
ganlikun	0:13413ea9a877	2061	* @arg @ref LL_RCC_PLLM_DIV_34
ganlikun	0:13413ea9a877	2062	* @arg @ref LL_RCC_PLLM_DIV_35
ganlikun	0:13413ea9a877	2063	* @arg @ref LL_RCC_PLLM_DIV_36
ganlikun	0:13413ea9a877	2064	* @arg @ref LL_RCC_PLLM_DIV_37
ganlikun	0:13413ea9a877	2065	* @arg @ref LL_RCC_PLLM_DIV_38
ganlikun	0:13413ea9a877	2066	* @arg @ref LL_RCC_PLLM_DIV_39
ganlikun	0:13413ea9a877	2067	* @arg @ref LL_RCC_PLLM_DIV_40
ganlikun	0:13413ea9a877	2068	* @arg @ref LL_RCC_PLLM_DIV_41
ganlikun	0:13413ea9a877	2069	* @arg @ref LL_RCC_PLLM_DIV_42
ganlikun	0:13413ea9a877	2070	* @arg @ref LL_RCC_PLLM_DIV_43
ganlikun	0:13413ea9a877	2071	* @arg @ref LL_RCC_PLLM_DIV_44
ganlikun	0:13413ea9a877	2072	* @arg @ref LL_RCC_PLLM_DIV_45
ganlikun	0:13413ea9a877	2073	* @arg @ref LL_RCC_PLLM_DIV_46
ganlikun	0:13413ea9a877	2074	* @arg @ref LL_RCC_PLLM_DIV_47
ganlikun	0:13413ea9a877	2075	* @arg @ref LL_RCC_PLLM_DIV_48
ganlikun	0:13413ea9a877	2076	* @arg @ref LL_RCC_PLLM_DIV_49
ganlikun	0:13413ea9a877	2077	* @arg @ref LL_RCC_PLLM_DIV_50
ganlikun	0:13413ea9a877	2078	* @arg @ref LL_RCC_PLLM_DIV_51
ganlikun	0:13413ea9a877	2079	* @arg @ref LL_RCC_PLLM_DIV_52
ganlikun	0:13413ea9a877	2080	* @arg @ref LL_RCC_PLLM_DIV_53
ganlikun	0:13413ea9a877	2081	* @arg @ref LL_RCC_PLLM_DIV_54
ganlikun	0:13413ea9a877	2082	* @arg @ref LL_RCC_PLLM_DIV_55
ganlikun	0:13413ea9a877	2083	* @arg @ref LL_RCC_PLLM_DIV_56
ganlikun	0:13413ea9a877	2084	* @arg @ref LL_RCC_PLLM_DIV_57
ganlikun	0:13413ea9a877	2085	* @arg @ref LL_RCC_PLLM_DIV_58
ganlikun	0:13413ea9a877	2086	* @arg @ref LL_RCC_PLLM_DIV_59
ganlikun	0:13413ea9a877	2087	* @arg @ref LL_RCC_PLLM_DIV_60
ganlikun	0:13413ea9a877	2088	* @arg @ref LL_RCC_PLLM_DIV_61
ganlikun	0:13413ea9a877	2089	* @arg @ref LL_RCC_PLLM_DIV_62
ganlikun	0:13413ea9a877	2090	* @arg @ref LL_RCC_PLLM_DIV_63
ganlikun	0:13413ea9a877	2091	* @param __PLLN__ Between 50 and 432
ganlikun	0:13413ea9a877	2092	* @param __PLLR__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2093	* @arg @ref LL_RCC_PLLR_DIV_2
ganlikun	0:13413ea9a877	2094	* @arg @ref LL_RCC_PLLR_DIV_3
ganlikun	0:13413ea9a877	2095	* @arg @ref LL_RCC_PLLR_DIV_4
ganlikun	0:13413ea9a877	2096	* @arg @ref LL_RCC_PLLR_DIV_5
ganlikun	0:13413ea9a877	2097	* @arg @ref LL_RCC_PLLR_DIV_6
ganlikun	0:13413ea9a877	2098	* @arg @ref LL_RCC_PLLR_DIV_7
ganlikun	0:13413ea9a877	2099	* @param __PLLDIVR__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2100	* @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
ganlikun	0:13413ea9a877	2101	* @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
ganlikun	0:13413ea9a877	2102	* @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
ganlikun	0:13413ea9a877	2103	* @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
ganlikun	0:13413ea9a877	2104	* @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
ganlikun	0:13413ea9a877	2105	* @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
ganlikun	0:13413ea9a877	2106	* @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
ganlikun	0:13413ea9a877	2107	* @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
ganlikun	0:13413ea9a877	2108	* @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
ganlikun	0:13413ea9a877	2109	* @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
ganlikun	0:13413ea9a877	2110	* @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
ganlikun	0:13413ea9a877	2111	* @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
ganlikun	0:13413ea9a877	2112	* @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
ganlikun	0:13413ea9a877	2113	* @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
ganlikun	0:13413ea9a877	2114	* @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
ganlikun	0:13413ea9a877	2115	* @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
ganlikun	0:13413ea9a877	2116	* @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
ganlikun	0:13413ea9a877	2117	* @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
ganlikun	0:13413ea9a877	2118	* @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
ganlikun	0:13413ea9a877	2119	* @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
ganlikun	0:13413ea9a877	2120	* @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
ganlikun	0:13413ea9a877	2121	* @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
ganlikun	0:13413ea9a877	2122	* @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
ganlikun	0:13413ea9a877	2123	* @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
ganlikun	0:13413ea9a877	2124	* @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
ganlikun	0:13413ea9a877	2125	* @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
ganlikun	0:13413ea9a877	2126	* @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
ganlikun	0:13413ea9a877	2127	* @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
ganlikun	0:13413ea9a877	2128	* @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
ganlikun	0:13413ea9a877	2129	* @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
ganlikun	0:13413ea9a877	2130	* @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
ganlikun	0:13413ea9a877	2131	*
ganlikun	0:13413ea9a877	2132	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	2133	* @retval PLL clock frequency (in Hz)
ganlikun	0:13413ea9a877	2134	*/
ganlikun	0:13413ea9a877	2135	#if defined(RCC_DCKCFGR_PLLDIVR)
ganlikun	0:13413ea9a877	2136	#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
ganlikun	0:13413ea9a877	2137	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos ))
ganlikun	0:13413ea9a877	2138	#else
ganlikun	0:13413ea9a877	2139	#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
ganlikun	0:13413ea9a877	2140	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
ganlikun	0:13413ea9a877	2141	#endif /* RCC_DCKCFGR_PLLDIVR */
ganlikun	0:13413ea9a877	2142	#endif /* SAI1 */
ganlikun	0:13413ea9a877	2143	#endif /* RCC_PLLCFGR_PLLR */
ganlikun	0:13413ea9a877	2144
ganlikun	0:13413ea9a877	2145	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	2146	/**
ganlikun	0:13413ea9a877	2147	* @brief Helper macro to calculate the PLLSAI frequency used for SAI domain
ganlikun	0:13413ea9a877	2148	* @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
ganlikun	0:13413ea9a877	2149	* @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ());
ganlikun	0:13413ea9a877	2150	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
ganlikun	0:13413ea9a877	2151	* @param __PLLM__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2152	* @arg @ref LL_RCC_PLLSAIM_DIV_2
ganlikun	0:13413ea9a877	2153	* @arg @ref LL_RCC_PLLSAIM_DIV_3
ganlikun	0:13413ea9a877	2154	* @arg @ref LL_RCC_PLLSAIM_DIV_4
ganlikun	0:13413ea9a877	2155	* @arg @ref LL_RCC_PLLSAIM_DIV_5
ganlikun	0:13413ea9a877	2156	* @arg @ref LL_RCC_PLLSAIM_DIV_6
ganlikun	0:13413ea9a877	2157	* @arg @ref LL_RCC_PLLSAIM_DIV_7
ganlikun	0:13413ea9a877	2158	* @arg @ref LL_RCC_PLLSAIM_DIV_8
ganlikun	0:13413ea9a877	2159	* @arg @ref LL_RCC_PLLSAIM_DIV_9
ganlikun	0:13413ea9a877	2160	* @arg @ref LL_RCC_PLLSAIM_DIV_10
ganlikun	0:13413ea9a877	2161	* @arg @ref LL_RCC_PLLSAIM_DIV_11
ganlikun	0:13413ea9a877	2162	* @arg @ref LL_RCC_PLLSAIM_DIV_12
ganlikun	0:13413ea9a877	2163	* @arg @ref LL_RCC_PLLSAIM_DIV_13
ganlikun	0:13413ea9a877	2164	* @arg @ref LL_RCC_PLLSAIM_DIV_14
ganlikun	0:13413ea9a877	2165	* @arg @ref LL_RCC_PLLSAIM_DIV_15
ganlikun	0:13413ea9a877	2166	* @arg @ref LL_RCC_PLLSAIM_DIV_16
ganlikun	0:13413ea9a877	2167	* @arg @ref LL_RCC_PLLSAIM_DIV_17
ganlikun	0:13413ea9a877	2168	* @arg @ref LL_RCC_PLLSAIM_DIV_18
ganlikun	0:13413ea9a877	2169	* @arg @ref LL_RCC_PLLSAIM_DIV_19
ganlikun	0:13413ea9a877	2170	* @arg @ref LL_RCC_PLLSAIM_DIV_20
ganlikun	0:13413ea9a877	2171	* @arg @ref LL_RCC_PLLSAIM_DIV_21
ganlikun	0:13413ea9a877	2172	* @arg @ref LL_RCC_PLLSAIM_DIV_22
ganlikun	0:13413ea9a877	2173	* @arg @ref LL_RCC_PLLSAIM_DIV_23
ganlikun	0:13413ea9a877	2174	* @arg @ref LL_RCC_PLLSAIM_DIV_24
ganlikun	0:13413ea9a877	2175	* @arg @ref LL_RCC_PLLSAIM_DIV_25
ganlikun	0:13413ea9a877	2176	* @arg @ref LL_RCC_PLLSAIM_DIV_26
ganlikun	0:13413ea9a877	2177	* @arg @ref LL_RCC_PLLSAIM_DIV_27
ganlikun	0:13413ea9a877	2178	* @arg @ref LL_RCC_PLLSAIM_DIV_28
ganlikun	0:13413ea9a877	2179	* @arg @ref LL_RCC_PLLSAIM_DIV_29
ganlikun	0:13413ea9a877	2180	* @arg @ref LL_RCC_PLLSAIM_DIV_30
ganlikun	0:13413ea9a877	2181	* @arg @ref LL_RCC_PLLSAIM_DIV_31
ganlikun	0:13413ea9a877	2182	* @arg @ref LL_RCC_PLLSAIM_DIV_32
ganlikun	0:13413ea9a877	2183	* @arg @ref LL_RCC_PLLSAIM_DIV_33
ganlikun	0:13413ea9a877	2184	* @arg @ref LL_RCC_PLLSAIM_DIV_34
ganlikun	0:13413ea9a877	2185	* @arg @ref LL_RCC_PLLSAIM_DIV_35
ganlikun	0:13413ea9a877	2186	* @arg @ref LL_RCC_PLLSAIM_DIV_36
ganlikun	0:13413ea9a877	2187	* @arg @ref LL_RCC_PLLSAIM_DIV_37
ganlikun	0:13413ea9a877	2188	* @arg @ref LL_RCC_PLLSAIM_DIV_38
ganlikun	0:13413ea9a877	2189	* @arg @ref LL_RCC_PLLSAIM_DIV_39
ganlikun	0:13413ea9a877	2190	* @arg @ref LL_RCC_PLLSAIM_DIV_40
ganlikun	0:13413ea9a877	2191	* @arg @ref LL_RCC_PLLSAIM_DIV_41
ganlikun	0:13413ea9a877	2192	* @arg @ref LL_RCC_PLLSAIM_DIV_42
ganlikun	0:13413ea9a877	2193	* @arg @ref LL_RCC_PLLSAIM_DIV_43
ganlikun	0:13413ea9a877	2194	* @arg @ref LL_RCC_PLLSAIM_DIV_44
ganlikun	0:13413ea9a877	2195	* @arg @ref LL_RCC_PLLSAIM_DIV_45
ganlikun	0:13413ea9a877	2196	* @arg @ref LL_RCC_PLLSAIM_DIV_46
ganlikun	0:13413ea9a877	2197	* @arg @ref LL_RCC_PLLSAIM_DIV_47
ganlikun	0:13413ea9a877	2198	* @arg @ref LL_RCC_PLLSAIM_DIV_48
ganlikun	0:13413ea9a877	2199	* @arg @ref LL_RCC_PLLSAIM_DIV_49
ganlikun	0:13413ea9a877	2200	* @arg @ref LL_RCC_PLLSAIM_DIV_50
ganlikun	0:13413ea9a877	2201	* @arg @ref LL_RCC_PLLSAIM_DIV_51
ganlikun	0:13413ea9a877	2202	* @arg @ref LL_RCC_PLLSAIM_DIV_52
ganlikun	0:13413ea9a877	2203	* @arg @ref LL_RCC_PLLSAIM_DIV_53
ganlikun	0:13413ea9a877	2204	* @arg @ref LL_RCC_PLLSAIM_DIV_54
ganlikun	0:13413ea9a877	2205	* @arg @ref LL_RCC_PLLSAIM_DIV_55
ganlikun	0:13413ea9a877	2206	* @arg @ref LL_RCC_PLLSAIM_DIV_56
ganlikun	0:13413ea9a877	2207	* @arg @ref LL_RCC_PLLSAIM_DIV_57
ganlikun	0:13413ea9a877	2208	* @arg @ref LL_RCC_PLLSAIM_DIV_58
ganlikun	0:13413ea9a877	2209	* @arg @ref LL_RCC_PLLSAIM_DIV_59
ganlikun	0:13413ea9a877	2210	* @arg @ref LL_RCC_PLLSAIM_DIV_60
ganlikun	0:13413ea9a877	2211	* @arg @ref LL_RCC_PLLSAIM_DIV_61
ganlikun	0:13413ea9a877	2212	* @arg @ref LL_RCC_PLLSAIM_DIV_62
ganlikun	0:13413ea9a877	2213	* @arg @ref LL_RCC_PLLSAIM_DIV_63
ganlikun	0:13413ea9a877	2214	* @param __PLLSAIN__ Between 49/50(*) and 432
ganlikun	0:13413ea9a877	2215	*
ganlikun	0:13413ea9a877	2216	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	2217	* @param __PLLSAIQ__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2218	* @arg @ref LL_RCC_PLLSAIQ_DIV_2
ganlikun	0:13413ea9a877	2219	* @arg @ref LL_RCC_PLLSAIQ_DIV_3
ganlikun	0:13413ea9a877	2220	* @arg @ref LL_RCC_PLLSAIQ_DIV_4
ganlikun	0:13413ea9a877	2221	* @arg @ref LL_RCC_PLLSAIQ_DIV_5
ganlikun	0:13413ea9a877	2222	* @arg @ref LL_RCC_PLLSAIQ_DIV_6
ganlikun	0:13413ea9a877	2223	* @arg @ref LL_RCC_PLLSAIQ_DIV_7
ganlikun	0:13413ea9a877	2224	* @arg @ref LL_RCC_PLLSAIQ_DIV_8
ganlikun	0:13413ea9a877	2225	* @arg @ref LL_RCC_PLLSAIQ_DIV_9
ganlikun	0:13413ea9a877	2226	* @arg @ref LL_RCC_PLLSAIQ_DIV_10
ganlikun	0:13413ea9a877	2227	* @arg @ref LL_RCC_PLLSAIQ_DIV_11
ganlikun	0:13413ea9a877	2228	* @arg @ref LL_RCC_PLLSAIQ_DIV_12
ganlikun	0:13413ea9a877	2229	* @arg @ref LL_RCC_PLLSAIQ_DIV_13
ganlikun	0:13413ea9a877	2230	* @arg @ref LL_RCC_PLLSAIQ_DIV_14
ganlikun	0:13413ea9a877	2231	* @arg @ref LL_RCC_PLLSAIQ_DIV_15
ganlikun	0:13413ea9a877	2232	* @param __PLLSAIDIVQ__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2233	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
ganlikun	0:13413ea9a877	2234	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
ganlikun	0:13413ea9a877	2235	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
ganlikun	0:13413ea9a877	2236	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
ganlikun	0:13413ea9a877	2237	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
ganlikun	0:13413ea9a877	2238	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
ganlikun	0:13413ea9a877	2239	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
ganlikun	0:13413ea9a877	2240	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
ganlikun	0:13413ea9a877	2241	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
ganlikun	0:13413ea9a877	2242	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
ganlikun	0:13413ea9a877	2243	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
ganlikun	0:13413ea9a877	2244	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
ganlikun	0:13413ea9a877	2245	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
ganlikun	0:13413ea9a877	2246	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
ganlikun	0:13413ea9a877	2247	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
ganlikun	0:13413ea9a877	2248	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
ganlikun	0:13413ea9a877	2249	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
ganlikun	0:13413ea9a877	2250	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
ganlikun	0:13413ea9a877	2251	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
ganlikun	0:13413ea9a877	2252	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
ganlikun	0:13413ea9a877	2253	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
ganlikun	0:13413ea9a877	2254	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
ganlikun	0:13413ea9a877	2255	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
ganlikun	0:13413ea9a877	2256	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
ganlikun	0:13413ea9a877	2257	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
ganlikun	0:13413ea9a877	2258	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
ganlikun	0:13413ea9a877	2259	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
ganlikun	0:13413ea9a877	2260	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
ganlikun	0:13413ea9a877	2261	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
ganlikun	0:13413ea9a877	2262	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
ganlikun	0:13413ea9a877	2263	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
ganlikun	0:13413ea9a877	2264	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
ganlikun	0:13413ea9a877	2265	* @retval PLLSAI clock frequency (in Hz)
ganlikun	0:13413ea9a877	2266	*/
ganlikun	0:13413ea9a877	2267	#define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
ganlikun	0:13413ea9a877	2268	(((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U)))
ganlikun	0:13413ea9a877	2269
ganlikun	0:13413ea9a877	2270	#if defined(RCC_PLLSAICFGR_PLLSAIP)
ganlikun	0:13413ea9a877	2271	/**
ganlikun	0:13413ea9a877	2272	* @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain
ganlikun	0:13413ea9a877	2273	* @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
ganlikun	0:13413ea9a877	2274	* @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());
ganlikun	0:13413ea9a877	2275	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
ganlikun	0:13413ea9a877	2276	* @param __PLLM__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2277	* @arg @ref LL_RCC_PLLSAIM_DIV_2
ganlikun	0:13413ea9a877	2278	* @arg @ref LL_RCC_PLLSAIM_DIV_3
ganlikun	0:13413ea9a877	2279	* @arg @ref LL_RCC_PLLSAIM_DIV_4
ganlikun	0:13413ea9a877	2280	* @arg @ref LL_RCC_PLLSAIM_DIV_5
ganlikun	0:13413ea9a877	2281	* @arg @ref LL_RCC_PLLSAIM_DIV_6
ganlikun	0:13413ea9a877	2282	* @arg @ref LL_RCC_PLLSAIM_DIV_7
ganlikun	0:13413ea9a877	2283	* @arg @ref LL_RCC_PLLSAIM_DIV_8
ganlikun	0:13413ea9a877	2284	* @arg @ref LL_RCC_PLLSAIM_DIV_9
ganlikun	0:13413ea9a877	2285	* @arg @ref LL_RCC_PLLSAIM_DIV_10
ganlikun	0:13413ea9a877	2286	* @arg @ref LL_RCC_PLLSAIM_DIV_11
ganlikun	0:13413ea9a877	2287	* @arg @ref LL_RCC_PLLSAIM_DIV_12
ganlikun	0:13413ea9a877	2288	* @arg @ref LL_RCC_PLLSAIM_DIV_13
ganlikun	0:13413ea9a877	2289	* @arg @ref LL_RCC_PLLSAIM_DIV_14
ganlikun	0:13413ea9a877	2290	* @arg @ref LL_RCC_PLLSAIM_DIV_15
ganlikun	0:13413ea9a877	2291	* @arg @ref LL_RCC_PLLSAIM_DIV_16
ganlikun	0:13413ea9a877	2292	* @arg @ref LL_RCC_PLLSAIM_DIV_17
ganlikun	0:13413ea9a877	2293	* @arg @ref LL_RCC_PLLSAIM_DIV_18
ganlikun	0:13413ea9a877	2294	* @arg @ref LL_RCC_PLLSAIM_DIV_19
ganlikun	0:13413ea9a877	2295	* @arg @ref LL_RCC_PLLSAIM_DIV_20
ganlikun	0:13413ea9a877	2296	* @arg @ref LL_RCC_PLLSAIM_DIV_21
ganlikun	0:13413ea9a877	2297	* @arg @ref LL_RCC_PLLSAIM_DIV_22
ganlikun	0:13413ea9a877	2298	* @arg @ref LL_RCC_PLLSAIM_DIV_23
ganlikun	0:13413ea9a877	2299	* @arg @ref LL_RCC_PLLSAIM_DIV_24
ganlikun	0:13413ea9a877	2300	* @arg @ref LL_RCC_PLLSAIM_DIV_25
ganlikun	0:13413ea9a877	2301	* @arg @ref LL_RCC_PLLSAIM_DIV_26
ganlikun	0:13413ea9a877	2302	* @arg @ref LL_RCC_PLLSAIM_DIV_27
ganlikun	0:13413ea9a877	2303	* @arg @ref LL_RCC_PLLSAIM_DIV_28
ganlikun	0:13413ea9a877	2304	* @arg @ref LL_RCC_PLLSAIM_DIV_29
ganlikun	0:13413ea9a877	2305	* @arg @ref LL_RCC_PLLSAIM_DIV_30
ganlikun	0:13413ea9a877	2306	* @arg @ref LL_RCC_PLLSAIM_DIV_31
ganlikun	0:13413ea9a877	2307	* @arg @ref LL_RCC_PLLSAIM_DIV_32
ganlikun	0:13413ea9a877	2308	* @arg @ref LL_RCC_PLLSAIM_DIV_33
ganlikun	0:13413ea9a877	2309	* @arg @ref LL_RCC_PLLSAIM_DIV_34
ganlikun	0:13413ea9a877	2310	* @arg @ref LL_RCC_PLLSAIM_DIV_35
ganlikun	0:13413ea9a877	2311	* @arg @ref LL_RCC_PLLSAIM_DIV_36
ganlikun	0:13413ea9a877	2312	* @arg @ref LL_RCC_PLLSAIM_DIV_37
ganlikun	0:13413ea9a877	2313	* @arg @ref LL_RCC_PLLSAIM_DIV_38
ganlikun	0:13413ea9a877	2314	* @arg @ref LL_RCC_PLLSAIM_DIV_39
ganlikun	0:13413ea9a877	2315	* @arg @ref LL_RCC_PLLSAIM_DIV_40
ganlikun	0:13413ea9a877	2316	* @arg @ref LL_RCC_PLLSAIM_DIV_41
ganlikun	0:13413ea9a877	2317	* @arg @ref LL_RCC_PLLSAIM_DIV_42
ganlikun	0:13413ea9a877	2318	* @arg @ref LL_RCC_PLLSAIM_DIV_43
ganlikun	0:13413ea9a877	2319	* @arg @ref LL_RCC_PLLSAIM_DIV_44
ganlikun	0:13413ea9a877	2320	* @arg @ref LL_RCC_PLLSAIM_DIV_45
ganlikun	0:13413ea9a877	2321	* @arg @ref LL_RCC_PLLSAIM_DIV_46
ganlikun	0:13413ea9a877	2322	* @arg @ref LL_RCC_PLLSAIM_DIV_47
ganlikun	0:13413ea9a877	2323	* @arg @ref LL_RCC_PLLSAIM_DIV_48
ganlikun	0:13413ea9a877	2324	* @arg @ref LL_RCC_PLLSAIM_DIV_49
ganlikun	0:13413ea9a877	2325	* @arg @ref LL_RCC_PLLSAIM_DIV_50
ganlikun	0:13413ea9a877	2326	* @arg @ref LL_RCC_PLLSAIM_DIV_51
ganlikun	0:13413ea9a877	2327	* @arg @ref LL_RCC_PLLSAIM_DIV_52
ganlikun	0:13413ea9a877	2328	* @arg @ref LL_RCC_PLLSAIM_DIV_53
ganlikun	0:13413ea9a877	2329	* @arg @ref LL_RCC_PLLSAIM_DIV_54
ganlikun	0:13413ea9a877	2330	* @arg @ref LL_RCC_PLLSAIM_DIV_55
ganlikun	0:13413ea9a877	2331	* @arg @ref LL_RCC_PLLSAIM_DIV_56
ganlikun	0:13413ea9a877	2332	* @arg @ref LL_RCC_PLLSAIM_DIV_57
ganlikun	0:13413ea9a877	2333	* @arg @ref LL_RCC_PLLSAIM_DIV_58
ganlikun	0:13413ea9a877	2334	* @arg @ref LL_RCC_PLLSAIM_DIV_59
ganlikun	0:13413ea9a877	2335	* @arg @ref LL_RCC_PLLSAIM_DIV_60
ganlikun	0:13413ea9a877	2336	* @arg @ref LL_RCC_PLLSAIM_DIV_61
ganlikun	0:13413ea9a877	2337	* @arg @ref LL_RCC_PLLSAIM_DIV_62
ganlikun	0:13413ea9a877	2338	* @arg @ref LL_RCC_PLLSAIM_DIV_63
ganlikun	0:13413ea9a877	2339	* @param __PLLSAIN__ Between 50 and 432
ganlikun	0:13413ea9a877	2340	* @param __PLLSAIP__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2341	* @arg @ref LL_RCC_PLLSAIP_DIV_2
ganlikun	0:13413ea9a877	2342	* @arg @ref LL_RCC_PLLSAIP_DIV_4
ganlikun	0:13413ea9a877	2343	* @arg @ref LL_RCC_PLLSAIP_DIV_6
ganlikun	0:13413ea9a877	2344	* @arg @ref LL_RCC_PLLSAIP_DIV_8
ganlikun	0:13413ea9a877	2345	* @retval PLLSAI clock frequency (in Hz)
ganlikun	0:13413ea9a877	2346	*/
ganlikun	0:13413ea9a877	2347	#define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
ganlikun	0:13413ea9a877	2348	((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U))
ganlikun	0:13413ea9a877	2349	#endif /* RCC_PLLSAICFGR_PLLSAIP */
ganlikun	0:13413ea9a877	2350
ganlikun	0:13413ea9a877	2351	#if defined(LTDC)
ganlikun	0:13413ea9a877	2352	/**
ganlikun	0:13413ea9a877	2353	* @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain
ganlikun	0:13413ea9a877	2354	* @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
ganlikun	0:13413ea9a877	2355	* @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ());
ganlikun	0:13413ea9a877	2356	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
ganlikun	0:13413ea9a877	2357	* @param __PLLM__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2358	* @arg @ref LL_RCC_PLLSAIM_DIV_2
ganlikun	0:13413ea9a877	2359	* @arg @ref LL_RCC_PLLSAIM_DIV_3
ganlikun	0:13413ea9a877	2360	* @arg @ref LL_RCC_PLLSAIM_DIV_4
ganlikun	0:13413ea9a877	2361	* @arg @ref LL_RCC_PLLSAIM_DIV_5
ganlikun	0:13413ea9a877	2362	* @arg @ref LL_RCC_PLLSAIM_DIV_6
ganlikun	0:13413ea9a877	2363	* @arg @ref LL_RCC_PLLSAIM_DIV_7
ganlikun	0:13413ea9a877	2364	* @arg @ref LL_RCC_PLLSAIM_DIV_8
ganlikun	0:13413ea9a877	2365	* @arg @ref LL_RCC_PLLSAIM_DIV_9
ganlikun	0:13413ea9a877	2366	* @arg @ref LL_RCC_PLLSAIM_DIV_10
ganlikun	0:13413ea9a877	2367	* @arg @ref LL_RCC_PLLSAIM_DIV_11
ganlikun	0:13413ea9a877	2368	* @arg @ref LL_RCC_PLLSAIM_DIV_12
ganlikun	0:13413ea9a877	2369	* @arg @ref LL_RCC_PLLSAIM_DIV_13
ganlikun	0:13413ea9a877	2370	* @arg @ref LL_RCC_PLLSAIM_DIV_14
ganlikun	0:13413ea9a877	2371	* @arg @ref LL_RCC_PLLSAIM_DIV_15
ganlikun	0:13413ea9a877	2372	* @arg @ref LL_RCC_PLLSAIM_DIV_16
ganlikun	0:13413ea9a877	2373	* @arg @ref LL_RCC_PLLSAIM_DIV_17
ganlikun	0:13413ea9a877	2374	* @arg @ref LL_RCC_PLLSAIM_DIV_18
ganlikun	0:13413ea9a877	2375	* @arg @ref LL_RCC_PLLSAIM_DIV_19
ganlikun	0:13413ea9a877	2376	* @arg @ref LL_RCC_PLLSAIM_DIV_20
ganlikun	0:13413ea9a877	2377	* @arg @ref LL_RCC_PLLSAIM_DIV_21
ganlikun	0:13413ea9a877	2378	* @arg @ref LL_RCC_PLLSAIM_DIV_22
ganlikun	0:13413ea9a877	2379	* @arg @ref LL_RCC_PLLSAIM_DIV_23
ganlikun	0:13413ea9a877	2380	* @arg @ref LL_RCC_PLLSAIM_DIV_24
ganlikun	0:13413ea9a877	2381	* @arg @ref LL_RCC_PLLSAIM_DIV_25
ganlikun	0:13413ea9a877	2382	* @arg @ref LL_RCC_PLLSAIM_DIV_26
ganlikun	0:13413ea9a877	2383	* @arg @ref LL_RCC_PLLSAIM_DIV_27
ganlikun	0:13413ea9a877	2384	* @arg @ref LL_RCC_PLLSAIM_DIV_28
ganlikun	0:13413ea9a877	2385	* @arg @ref LL_RCC_PLLSAIM_DIV_29
ganlikun	0:13413ea9a877	2386	* @arg @ref LL_RCC_PLLSAIM_DIV_30
ganlikun	0:13413ea9a877	2387	* @arg @ref LL_RCC_PLLSAIM_DIV_31
ganlikun	0:13413ea9a877	2388	* @arg @ref LL_RCC_PLLSAIM_DIV_32
ganlikun	0:13413ea9a877	2389	* @arg @ref LL_RCC_PLLSAIM_DIV_33
ganlikun	0:13413ea9a877	2390	* @arg @ref LL_RCC_PLLSAIM_DIV_34
ganlikun	0:13413ea9a877	2391	* @arg @ref LL_RCC_PLLSAIM_DIV_35
ganlikun	0:13413ea9a877	2392	* @arg @ref LL_RCC_PLLSAIM_DIV_36
ganlikun	0:13413ea9a877	2393	* @arg @ref LL_RCC_PLLSAIM_DIV_37
ganlikun	0:13413ea9a877	2394	* @arg @ref LL_RCC_PLLSAIM_DIV_38
ganlikun	0:13413ea9a877	2395	* @arg @ref LL_RCC_PLLSAIM_DIV_39
ganlikun	0:13413ea9a877	2396	* @arg @ref LL_RCC_PLLSAIM_DIV_40
ganlikun	0:13413ea9a877	2397	* @arg @ref LL_RCC_PLLSAIM_DIV_41
ganlikun	0:13413ea9a877	2398	* @arg @ref LL_RCC_PLLSAIM_DIV_42
ganlikun	0:13413ea9a877	2399	* @arg @ref LL_RCC_PLLSAIM_DIV_43
ganlikun	0:13413ea9a877	2400	* @arg @ref LL_RCC_PLLSAIM_DIV_44
ganlikun	0:13413ea9a877	2401	* @arg @ref LL_RCC_PLLSAIM_DIV_45
ganlikun	0:13413ea9a877	2402	* @arg @ref LL_RCC_PLLSAIM_DIV_46
ganlikun	0:13413ea9a877	2403	* @arg @ref LL_RCC_PLLSAIM_DIV_47
ganlikun	0:13413ea9a877	2404	* @arg @ref LL_RCC_PLLSAIM_DIV_48
ganlikun	0:13413ea9a877	2405	* @arg @ref LL_RCC_PLLSAIM_DIV_49
ganlikun	0:13413ea9a877	2406	* @arg @ref LL_RCC_PLLSAIM_DIV_50
ganlikun	0:13413ea9a877	2407	* @arg @ref LL_RCC_PLLSAIM_DIV_51
ganlikun	0:13413ea9a877	2408	* @arg @ref LL_RCC_PLLSAIM_DIV_52
ganlikun	0:13413ea9a877	2409	* @arg @ref LL_RCC_PLLSAIM_DIV_53
ganlikun	0:13413ea9a877	2410	* @arg @ref LL_RCC_PLLSAIM_DIV_54
ganlikun	0:13413ea9a877	2411	* @arg @ref LL_RCC_PLLSAIM_DIV_55
ganlikun	0:13413ea9a877	2412	* @arg @ref LL_RCC_PLLSAIM_DIV_56
ganlikun	0:13413ea9a877	2413	* @arg @ref LL_RCC_PLLSAIM_DIV_57
ganlikun	0:13413ea9a877	2414	* @arg @ref LL_RCC_PLLSAIM_DIV_58
ganlikun	0:13413ea9a877	2415	* @arg @ref LL_RCC_PLLSAIM_DIV_59
ganlikun	0:13413ea9a877	2416	* @arg @ref LL_RCC_PLLSAIM_DIV_60
ganlikun	0:13413ea9a877	2417	* @arg @ref LL_RCC_PLLSAIM_DIV_61
ganlikun	0:13413ea9a877	2418	* @arg @ref LL_RCC_PLLSAIM_DIV_62
ganlikun	0:13413ea9a877	2419	* @arg @ref LL_RCC_PLLSAIM_DIV_63
ganlikun	0:13413ea9a877	2420	* @param __PLLSAIN__ Between 49/50(*) and 432
ganlikun	0:13413ea9a877	2421	*
ganlikun	0:13413ea9a877	2422	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	2423	* @param __PLLSAIR__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2424	* @arg @ref LL_RCC_PLLSAIR_DIV_2
ganlikun	0:13413ea9a877	2425	* @arg @ref LL_RCC_PLLSAIR_DIV_3
ganlikun	0:13413ea9a877	2426	* @arg @ref LL_RCC_PLLSAIR_DIV_4
ganlikun	0:13413ea9a877	2427	* @arg @ref LL_RCC_PLLSAIR_DIV_5
ganlikun	0:13413ea9a877	2428	* @arg @ref LL_RCC_PLLSAIR_DIV_6
ganlikun	0:13413ea9a877	2429	* @arg @ref LL_RCC_PLLSAIR_DIV_7
ganlikun	0:13413ea9a877	2430	* @param __PLLSAIDIVR__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2431	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
ganlikun	0:13413ea9a877	2432	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
ganlikun	0:13413ea9a877	2433	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
ganlikun	0:13413ea9a877	2434	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
ganlikun	0:13413ea9a877	2435	* @retval PLLSAI clock frequency (in Hz)
ganlikun	0:13413ea9a877	2436	*/
ganlikun	0:13413ea9a877	2437	#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
ganlikun	0:13413ea9a877	2438	(((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos])))
ganlikun	0:13413ea9a877	2439	#endif /* LTDC */
ganlikun	0:13413ea9a877	2440	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	2441
ganlikun	0:13413ea9a877	2442	#if defined(RCC_PLLI2S_SUPPORT)
ganlikun	0:13413ea9a877	2443	#if defined(RCC_DCKCFGR_PLLI2SDIVQ) \|\| defined(RCC_DCKCFGR_PLLI2SDIVR)
ganlikun	0:13413ea9a877	2444	/**
ganlikun	0:13413ea9a877	2445	* @brief Helper macro to calculate the PLLI2S frequency used for SAI domain
ganlikun	0:13413ea9a877	2446	* @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
ganlikun	0:13413ea9a877	2447	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ());
ganlikun	0:13413ea9a877	2448	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
ganlikun	0:13413ea9a877	2449	* @param __PLLM__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2450	* @arg @ref LL_RCC_PLLI2SM_DIV_2
ganlikun	0:13413ea9a877	2451	* @arg @ref LL_RCC_PLLI2SM_DIV_3
ganlikun	0:13413ea9a877	2452	* @arg @ref LL_RCC_PLLI2SM_DIV_4
ganlikun	0:13413ea9a877	2453	* @arg @ref LL_RCC_PLLI2SM_DIV_5
ganlikun	0:13413ea9a877	2454	* @arg @ref LL_RCC_PLLI2SM_DIV_6
ganlikun	0:13413ea9a877	2455	* @arg @ref LL_RCC_PLLI2SM_DIV_7
ganlikun	0:13413ea9a877	2456	* @arg @ref LL_RCC_PLLI2SM_DIV_8
ganlikun	0:13413ea9a877	2457	* @arg @ref LL_RCC_PLLI2SM_DIV_9
ganlikun	0:13413ea9a877	2458	* @arg @ref LL_RCC_PLLI2SM_DIV_10
ganlikun	0:13413ea9a877	2459	* @arg @ref LL_RCC_PLLI2SM_DIV_11
ganlikun	0:13413ea9a877	2460	* @arg @ref LL_RCC_PLLI2SM_DIV_12
ganlikun	0:13413ea9a877	2461	* @arg @ref LL_RCC_PLLI2SM_DIV_13
ganlikun	0:13413ea9a877	2462	* @arg @ref LL_RCC_PLLI2SM_DIV_14
ganlikun	0:13413ea9a877	2463	* @arg @ref LL_RCC_PLLI2SM_DIV_15
ganlikun	0:13413ea9a877	2464	* @arg @ref LL_RCC_PLLI2SM_DIV_16
ganlikun	0:13413ea9a877	2465	* @arg @ref LL_RCC_PLLI2SM_DIV_17
ganlikun	0:13413ea9a877	2466	* @arg @ref LL_RCC_PLLI2SM_DIV_18
ganlikun	0:13413ea9a877	2467	* @arg @ref LL_RCC_PLLI2SM_DIV_19
ganlikun	0:13413ea9a877	2468	* @arg @ref LL_RCC_PLLI2SM_DIV_20
ganlikun	0:13413ea9a877	2469	* @arg @ref LL_RCC_PLLI2SM_DIV_21
ganlikun	0:13413ea9a877	2470	* @arg @ref LL_RCC_PLLI2SM_DIV_22
ganlikun	0:13413ea9a877	2471	* @arg @ref LL_RCC_PLLI2SM_DIV_23
ganlikun	0:13413ea9a877	2472	* @arg @ref LL_RCC_PLLI2SM_DIV_24
ganlikun	0:13413ea9a877	2473	* @arg @ref LL_RCC_PLLI2SM_DIV_25
ganlikun	0:13413ea9a877	2474	* @arg @ref LL_RCC_PLLI2SM_DIV_26
ganlikun	0:13413ea9a877	2475	* @arg @ref LL_RCC_PLLI2SM_DIV_27
ganlikun	0:13413ea9a877	2476	* @arg @ref LL_RCC_PLLI2SM_DIV_28
ganlikun	0:13413ea9a877	2477	* @arg @ref LL_RCC_PLLI2SM_DIV_29
ganlikun	0:13413ea9a877	2478	* @arg @ref LL_RCC_PLLI2SM_DIV_30
ganlikun	0:13413ea9a877	2479	* @arg @ref LL_RCC_PLLI2SM_DIV_31
ganlikun	0:13413ea9a877	2480	* @arg @ref LL_RCC_PLLI2SM_DIV_32
ganlikun	0:13413ea9a877	2481	* @arg @ref LL_RCC_PLLI2SM_DIV_33
ganlikun	0:13413ea9a877	2482	* @arg @ref LL_RCC_PLLI2SM_DIV_34
ganlikun	0:13413ea9a877	2483	* @arg @ref LL_RCC_PLLI2SM_DIV_35
ganlikun	0:13413ea9a877	2484	* @arg @ref LL_RCC_PLLI2SM_DIV_36
ganlikun	0:13413ea9a877	2485	* @arg @ref LL_RCC_PLLI2SM_DIV_37
ganlikun	0:13413ea9a877	2486	* @arg @ref LL_RCC_PLLI2SM_DIV_38
ganlikun	0:13413ea9a877	2487	* @arg @ref LL_RCC_PLLI2SM_DIV_39
ganlikun	0:13413ea9a877	2488	* @arg @ref LL_RCC_PLLI2SM_DIV_40
ganlikun	0:13413ea9a877	2489	* @arg @ref LL_RCC_PLLI2SM_DIV_41
ganlikun	0:13413ea9a877	2490	* @arg @ref LL_RCC_PLLI2SM_DIV_42
ganlikun	0:13413ea9a877	2491	* @arg @ref LL_RCC_PLLI2SM_DIV_43
ganlikun	0:13413ea9a877	2492	* @arg @ref LL_RCC_PLLI2SM_DIV_44
ganlikun	0:13413ea9a877	2493	* @arg @ref LL_RCC_PLLI2SM_DIV_45
ganlikun	0:13413ea9a877	2494	* @arg @ref LL_RCC_PLLI2SM_DIV_46
ganlikun	0:13413ea9a877	2495	* @arg @ref LL_RCC_PLLI2SM_DIV_47
ganlikun	0:13413ea9a877	2496	* @arg @ref LL_RCC_PLLI2SM_DIV_48
ganlikun	0:13413ea9a877	2497	* @arg @ref LL_RCC_PLLI2SM_DIV_49
ganlikun	0:13413ea9a877	2498	* @arg @ref LL_RCC_PLLI2SM_DIV_50
ganlikun	0:13413ea9a877	2499	* @arg @ref LL_RCC_PLLI2SM_DIV_51
ganlikun	0:13413ea9a877	2500	* @arg @ref LL_RCC_PLLI2SM_DIV_52
ganlikun	0:13413ea9a877	2501	* @arg @ref LL_RCC_PLLI2SM_DIV_53
ganlikun	0:13413ea9a877	2502	* @arg @ref LL_RCC_PLLI2SM_DIV_54
ganlikun	0:13413ea9a877	2503	* @arg @ref LL_RCC_PLLI2SM_DIV_55
ganlikun	0:13413ea9a877	2504	* @arg @ref LL_RCC_PLLI2SM_DIV_56
ganlikun	0:13413ea9a877	2505	* @arg @ref LL_RCC_PLLI2SM_DIV_57
ganlikun	0:13413ea9a877	2506	* @arg @ref LL_RCC_PLLI2SM_DIV_58
ganlikun	0:13413ea9a877	2507	* @arg @ref LL_RCC_PLLI2SM_DIV_59
ganlikun	0:13413ea9a877	2508	* @arg @ref LL_RCC_PLLI2SM_DIV_60
ganlikun	0:13413ea9a877	2509	* @arg @ref LL_RCC_PLLI2SM_DIV_61
ganlikun	0:13413ea9a877	2510	* @arg @ref LL_RCC_PLLI2SM_DIV_62
ganlikun	0:13413ea9a877	2511	* @arg @ref LL_RCC_PLLI2SM_DIV_63
ganlikun	0:13413ea9a877	2512	* @param __PLLI2SN__ Between 50/192(*) and 432
ganlikun	0:13413ea9a877	2513	*
ganlikun	0:13413ea9a877	2514	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	2515	* @param __PLLI2SQ_R__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2516	* @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
ganlikun	0:13413ea9a877	2517	* @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
ganlikun	0:13413ea9a877	2518	* @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
ganlikun	0:13413ea9a877	2519	* @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
ganlikun	0:13413ea9a877	2520	* @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
ganlikun	0:13413ea9a877	2521	* @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
ganlikun	0:13413ea9a877	2522	* @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
ganlikun	0:13413ea9a877	2523	* @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
ganlikun	0:13413ea9a877	2524	* @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
ganlikun	0:13413ea9a877	2525	* @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
ganlikun	0:13413ea9a877	2526	* @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
ganlikun	0:13413ea9a877	2527	* @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
ganlikun	0:13413ea9a877	2528	* @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
ganlikun	0:13413ea9a877	2529	* @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
ganlikun	0:13413ea9a877	2530	* @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
ganlikun	0:13413ea9a877	2531	* @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
ganlikun	0:13413ea9a877	2532	* @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
ganlikun	0:13413ea9a877	2533	* @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
ganlikun	0:13413ea9a877	2534	* @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
ganlikun	0:13413ea9a877	2535	* @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
ganlikun	0:13413ea9a877	2536	*
ganlikun	0:13413ea9a877	2537	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	2538	* @param __PLLI2SDIVQ_R__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2539	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
ganlikun	0:13413ea9a877	2540	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
ganlikun	0:13413ea9a877	2541	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
ganlikun	0:13413ea9a877	2542	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
ganlikun	0:13413ea9a877	2543	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
ganlikun	0:13413ea9a877	2544	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
ganlikun	0:13413ea9a877	2545	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
ganlikun	0:13413ea9a877	2546	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
ganlikun	0:13413ea9a877	2547	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
ganlikun	0:13413ea9a877	2548	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
ganlikun	0:13413ea9a877	2549	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
ganlikun	0:13413ea9a877	2550	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
ganlikun	0:13413ea9a877	2551	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
ganlikun	0:13413ea9a877	2552	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
ganlikun	0:13413ea9a877	2553	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
ganlikun	0:13413ea9a877	2554	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
ganlikun	0:13413ea9a877	2555	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
ganlikun	0:13413ea9a877	2556	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
ganlikun	0:13413ea9a877	2557	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
ganlikun	0:13413ea9a877	2558	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
ganlikun	0:13413ea9a877	2559	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
ganlikun	0:13413ea9a877	2560	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
ganlikun	0:13413ea9a877	2561	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
ganlikun	0:13413ea9a877	2562	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
ganlikun	0:13413ea9a877	2563	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
ganlikun	0:13413ea9a877	2564	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
ganlikun	0:13413ea9a877	2565	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
ganlikun	0:13413ea9a877	2566	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
ganlikun	0:13413ea9a877	2567	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
ganlikun	0:13413ea9a877	2568	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
ganlikun	0:13413ea9a877	2569	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
ganlikun	0:13413ea9a877	2570	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
ganlikun	0:13413ea9a877	2571	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
ganlikun	0:13413ea9a877	2572	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
ganlikun	0:13413ea9a877	2573	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
ganlikun	0:13413ea9a877	2574	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
ganlikun	0:13413ea9a877	2575	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
ganlikun	0:13413ea9a877	2576	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
ganlikun	0:13413ea9a877	2577	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
ganlikun	0:13413ea9a877	2578	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
ganlikun	0:13413ea9a877	2579	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
ganlikun	0:13413ea9a877	2580	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
ganlikun	0:13413ea9a877	2581	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
ganlikun	0:13413ea9a877	2582	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
ganlikun	0:13413ea9a877	2583	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
ganlikun	0:13413ea9a877	2584	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
ganlikun	0:13413ea9a877	2585	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
ganlikun	0:13413ea9a877	2586	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
ganlikun	0:13413ea9a877	2587	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
ganlikun	0:13413ea9a877	2588	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
ganlikun	0:13413ea9a877	2589	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
ganlikun	0:13413ea9a877	2590	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
ganlikun	0:13413ea9a877	2591	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
ganlikun	0:13413ea9a877	2592	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
ganlikun	0:13413ea9a877	2593	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
ganlikun	0:13413ea9a877	2594	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
ganlikun	0:13413ea9a877	2595	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
ganlikun	0:13413ea9a877	2596	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
ganlikun	0:13413ea9a877	2597	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
ganlikun	0:13413ea9a877	2598	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
ganlikun	0:13413ea9a877	2599	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
ganlikun	0:13413ea9a877	2600	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
ganlikun	0:13413ea9a877	2601	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
ganlikun	0:13413ea9a877	2602	*
ganlikun	0:13413ea9a877	2603	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	2604	* @retval PLLI2S clock frequency (in Hz)
ganlikun	0:13413ea9a877	2605	*/
ganlikun	0:13413ea9a877	2606	#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
ganlikun	0:13413ea9a877	2607	#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
ganlikun	0:13413ea9a877	2608	(((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U)))
ganlikun	0:13413ea9a877	2609	#else
ganlikun	0:13413ea9a877	2610	#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
ganlikun	0:13413ea9a877	2611	(((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos)))
ganlikun	0:13413ea9a877	2612
ganlikun	0:13413ea9a877	2613	#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
ganlikun	0:13413ea9a877	2614	#endif /* RCC_DCKCFGR_PLLI2SDIVQ \|\| RCC_DCKCFGR_PLLI2SDIVR */
ganlikun	0:13413ea9a877	2615
ganlikun	0:13413ea9a877	2616	#if defined(SPDIFRX)
ganlikun	0:13413ea9a877	2617	/**
ganlikun	0:13413ea9a877	2618	* @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain
ganlikun	0:13413ea9a877	2619	* @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
ganlikun	0:13413ea9a877	2620	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());
ganlikun	0:13413ea9a877	2621	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
ganlikun	0:13413ea9a877	2622	* @param __PLLM__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2623	* @arg @ref LL_RCC_PLLI2SM_DIV_2
ganlikun	0:13413ea9a877	2624	* @arg @ref LL_RCC_PLLI2SM_DIV_3
ganlikun	0:13413ea9a877	2625	* @arg @ref LL_RCC_PLLI2SM_DIV_4
ganlikun	0:13413ea9a877	2626	* @arg @ref LL_RCC_PLLI2SM_DIV_5
ganlikun	0:13413ea9a877	2627	* @arg @ref LL_RCC_PLLI2SM_DIV_6
ganlikun	0:13413ea9a877	2628	* @arg @ref LL_RCC_PLLI2SM_DIV_7
ganlikun	0:13413ea9a877	2629	* @arg @ref LL_RCC_PLLI2SM_DIV_8
ganlikun	0:13413ea9a877	2630	* @arg @ref LL_RCC_PLLI2SM_DIV_9
ganlikun	0:13413ea9a877	2631	* @arg @ref LL_RCC_PLLI2SM_DIV_10
ganlikun	0:13413ea9a877	2632	* @arg @ref LL_RCC_PLLI2SM_DIV_11
ganlikun	0:13413ea9a877	2633	* @arg @ref LL_RCC_PLLI2SM_DIV_12
ganlikun	0:13413ea9a877	2634	* @arg @ref LL_RCC_PLLI2SM_DIV_13
ganlikun	0:13413ea9a877	2635	* @arg @ref LL_RCC_PLLI2SM_DIV_14
ganlikun	0:13413ea9a877	2636	* @arg @ref LL_RCC_PLLI2SM_DIV_15
ganlikun	0:13413ea9a877	2637	* @arg @ref LL_RCC_PLLI2SM_DIV_16
ganlikun	0:13413ea9a877	2638	* @arg @ref LL_RCC_PLLI2SM_DIV_17
ganlikun	0:13413ea9a877	2639	* @arg @ref LL_RCC_PLLI2SM_DIV_18
ganlikun	0:13413ea9a877	2640	* @arg @ref LL_RCC_PLLI2SM_DIV_19
ganlikun	0:13413ea9a877	2641	* @arg @ref LL_RCC_PLLI2SM_DIV_20
ganlikun	0:13413ea9a877	2642	* @arg @ref LL_RCC_PLLI2SM_DIV_21
ganlikun	0:13413ea9a877	2643	* @arg @ref LL_RCC_PLLI2SM_DIV_22
ganlikun	0:13413ea9a877	2644	* @arg @ref LL_RCC_PLLI2SM_DIV_23
ganlikun	0:13413ea9a877	2645	* @arg @ref LL_RCC_PLLI2SM_DIV_24
ganlikun	0:13413ea9a877	2646	* @arg @ref LL_RCC_PLLI2SM_DIV_25
ganlikun	0:13413ea9a877	2647	* @arg @ref LL_RCC_PLLI2SM_DIV_26
ganlikun	0:13413ea9a877	2648	* @arg @ref LL_RCC_PLLI2SM_DIV_27
ganlikun	0:13413ea9a877	2649	* @arg @ref LL_RCC_PLLI2SM_DIV_28
ganlikun	0:13413ea9a877	2650	* @arg @ref LL_RCC_PLLI2SM_DIV_29
ganlikun	0:13413ea9a877	2651	* @arg @ref LL_RCC_PLLI2SM_DIV_30
ganlikun	0:13413ea9a877	2652	* @arg @ref LL_RCC_PLLI2SM_DIV_31
ganlikun	0:13413ea9a877	2653	* @arg @ref LL_RCC_PLLI2SM_DIV_32
ganlikun	0:13413ea9a877	2654	* @arg @ref LL_RCC_PLLI2SM_DIV_33
ganlikun	0:13413ea9a877	2655	* @arg @ref LL_RCC_PLLI2SM_DIV_34
ganlikun	0:13413ea9a877	2656	* @arg @ref LL_RCC_PLLI2SM_DIV_35
ganlikun	0:13413ea9a877	2657	* @arg @ref LL_RCC_PLLI2SM_DIV_36
ganlikun	0:13413ea9a877	2658	* @arg @ref LL_RCC_PLLI2SM_DIV_37
ganlikun	0:13413ea9a877	2659	* @arg @ref LL_RCC_PLLI2SM_DIV_38
ganlikun	0:13413ea9a877	2660	* @arg @ref LL_RCC_PLLI2SM_DIV_39
ganlikun	0:13413ea9a877	2661	* @arg @ref LL_RCC_PLLI2SM_DIV_40
ganlikun	0:13413ea9a877	2662	* @arg @ref LL_RCC_PLLI2SM_DIV_41
ganlikun	0:13413ea9a877	2663	* @arg @ref LL_RCC_PLLI2SM_DIV_42
ganlikun	0:13413ea9a877	2664	* @arg @ref LL_RCC_PLLI2SM_DIV_43
ganlikun	0:13413ea9a877	2665	* @arg @ref LL_RCC_PLLI2SM_DIV_44
ganlikun	0:13413ea9a877	2666	* @arg @ref LL_RCC_PLLI2SM_DIV_45
ganlikun	0:13413ea9a877	2667	* @arg @ref LL_RCC_PLLI2SM_DIV_46
ganlikun	0:13413ea9a877	2668	* @arg @ref LL_RCC_PLLI2SM_DIV_47
ganlikun	0:13413ea9a877	2669	* @arg @ref LL_RCC_PLLI2SM_DIV_48
ganlikun	0:13413ea9a877	2670	* @arg @ref LL_RCC_PLLI2SM_DIV_49
ganlikun	0:13413ea9a877	2671	* @arg @ref LL_RCC_PLLI2SM_DIV_50
ganlikun	0:13413ea9a877	2672	* @arg @ref LL_RCC_PLLI2SM_DIV_51
ganlikun	0:13413ea9a877	2673	* @arg @ref LL_RCC_PLLI2SM_DIV_52
ganlikun	0:13413ea9a877	2674	* @arg @ref LL_RCC_PLLI2SM_DIV_53
ganlikun	0:13413ea9a877	2675	* @arg @ref LL_RCC_PLLI2SM_DIV_54
ganlikun	0:13413ea9a877	2676	* @arg @ref LL_RCC_PLLI2SM_DIV_55
ganlikun	0:13413ea9a877	2677	* @arg @ref LL_RCC_PLLI2SM_DIV_56
ganlikun	0:13413ea9a877	2678	* @arg @ref LL_RCC_PLLI2SM_DIV_57
ganlikun	0:13413ea9a877	2679	* @arg @ref LL_RCC_PLLI2SM_DIV_58
ganlikun	0:13413ea9a877	2680	* @arg @ref LL_RCC_PLLI2SM_DIV_59
ganlikun	0:13413ea9a877	2681	* @arg @ref LL_RCC_PLLI2SM_DIV_60
ganlikun	0:13413ea9a877	2682	* @arg @ref LL_RCC_PLLI2SM_DIV_61
ganlikun	0:13413ea9a877	2683	* @arg @ref LL_RCC_PLLI2SM_DIV_62
ganlikun	0:13413ea9a877	2684	* @arg @ref LL_RCC_PLLI2SM_DIV_63
ganlikun	0:13413ea9a877	2685	* @param __PLLI2SN__ Between 50 and 432
ganlikun	0:13413ea9a877	2686	* @param __PLLI2SP__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2687	* @arg @ref LL_RCC_PLLI2SP_DIV_2
ganlikun	0:13413ea9a877	2688	* @arg @ref LL_RCC_PLLI2SP_DIV_4
ganlikun	0:13413ea9a877	2689	* @arg @ref LL_RCC_PLLI2SP_DIV_6
ganlikun	0:13413ea9a877	2690	* @arg @ref LL_RCC_PLLI2SP_DIV_8
ganlikun	0:13413ea9a877	2691	* @retval PLLI2S clock frequency (in Hz)
ganlikun	0:13413ea9a877	2692	*/
ganlikun	0:13413ea9a877	2693	#define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
ganlikun	0:13413ea9a877	2694	((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
ganlikun	0:13413ea9a877	2695
ganlikun	0:13413ea9a877	2696	#endif /* SPDIFRX */
ganlikun	0:13413ea9a877	2697
ganlikun	0:13413ea9a877	2698	/**
ganlikun	0:13413ea9a877	2699	* @brief Helper macro to calculate the PLLI2S frequency used for I2S domain
ganlikun	0:13413ea9a877	2700	* @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
ganlikun	0:13413ea9a877	2701	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
ganlikun	0:13413ea9a877	2702	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
ganlikun	0:13413ea9a877	2703	* @param __PLLM__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2704	* @arg @ref LL_RCC_PLLI2SM_DIV_2
ganlikun	0:13413ea9a877	2705	* @arg @ref LL_RCC_PLLI2SM_DIV_3
ganlikun	0:13413ea9a877	2706	* @arg @ref LL_RCC_PLLI2SM_DIV_4
ganlikun	0:13413ea9a877	2707	* @arg @ref LL_RCC_PLLI2SM_DIV_5
ganlikun	0:13413ea9a877	2708	* @arg @ref LL_RCC_PLLI2SM_DIV_6
ganlikun	0:13413ea9a877	2709	* @arg @ref LL_RCC_PLLI2SM_DIV_7
ganlikun	0:13413ea9a877	2710	* @arg @ref LL_RCC_PLLI2SM_DIV_8
ganlikun	0:13413ea9a877	2711	* @arg @ref LL_RCC_PLLI2SM_DIV_9
ganlikun	0:13413ea9a877	2712	* @arg @ref LL_RCC_PLLI2SM_DIV_10
ganlikun	0:13413ea9a877	2713	* @arg @ref LL_RCC_PLLI2SM_DIV_11
ganlikun	0:13413ea9a877	2714	* @arg @ref LL_RCC_PLLI2SM_DIV_12
ganlikun	0:13413ea9a877	2715	* @arg @ref LL_RCC_PLLI2SM_DIV_13
ganlikun	0:13413ea9a877	2716	* @arg @ref LL_RCC_PLLI2SM_DIV_14
ganlikun	0:13413ea9a877	2717	* @arg @ref LL_RCC_PLLI2SM_DIV_15
ganlikun	0:13413ea9a877	2718	* @arg @ref LL_RCC_PLLI2SM_DIV_16
ganlikun	0:13413ea9a877	2719	* @arg @ref LL_RCC_PLLI2SM_DIV_17
ganlikun	0:13413ea9a877	2720	* @arg @ref LL_RCC_PLLI2SM_DIV_18
ganlikun	0:13413ea9a877	2721	* @arg @ref LL_RCC_PLLI2SM_DIV_19
ganlikun	0:13413ea9a877	2722	* @arg @ref LL_RCC_PLLI2SM_DIV_20
ganlikun	0:13413ea9a877	2723	* @arg @ref LL_RCC_PLLI2SM_DIV_21
ganlikun	0:13413ea9a877	2724	* @arg @ref LL_RCC_PLLI2SM_DIV_22
ganlikun	0:13413ea9a877	2725	* @arg @ref LL_RCC_PLLI2SM_DIV_23
ganlikun	0:13413ea9a877	2726	* @arg @ref LL_RCC_PLLI2SM_DIV_24
ganlikun	0:13413ea9a877	2727	* @arg @ref LL_RCC_PLLI2SM_DIV_25
ganlikun	0:13413ea9a877	2728	* @arg @ref LL_RCC_PLLI2SM_DIV_26
ganlikun	0:13413ea9a877	2729	* @arg @ref LL_RCC_PLLI2SM_DIV_27
ganlikun	0:13413ea9a877	2730	* @arg @ref LL_RCC_PLLI2SM_DIV_28
ganlikun	0:13413ea9a877	2731	* @arg @ref LL_RCC_PLLI2SM_DIV_29
ganlikun	0:13413ea9a877	2732	* @arg @ref LL_RCC_PLLI2SM_DIV_30
ganlikun	0:13413ea9a877	2733	* @arg @ref LL_RCC_PLLI2SM_DIV_31
ganlikun	0:13413ea9a877	2734	* @arg @ref LL_RCC_PLLI2SM_DIV_32
ganlikun	0:13413ea9a877	2735	* @arg @ref LL_RCC_PLLI2SM_DIV_33
ganlikun	0:13413ea9a877	2736	* @arg @ref LL_RCC_PLLI2SM_DIV_34
ganlikun	0:13413ea9a877	2737	* @arg @ref LL_RCC_PLLI2SM_DIV_35
ganlikun	0:13413ea9a877	2738	* @arg @ref LL_RCC_PLLI2SM_DIV_36
ganlikun	0:13413ea9a877	2739	* @arg @ref LL_RCC_PLLI2SM_DIV_37
ganlikun	0:13413ea9a877	2740	* @arg @ref LL_RCC_PLLI2SM_DIV_38
ganlikun	0:13413ea9a877	2741	* @arg @ref LL_RCC_PLLI2SM_DIV_39
ganlikun	0:13413ea9a877	2742	* @arg @ref LL_RCC_PLLI2SM_DIV_40
ganlikun	0:13413ea9a877	2743	* @arg @ref LL_RCC_PLLI2SM_DIV_41
ganlikun	0:13413ea9a877	2744	* @arg @ref LL_RCC_PLLI2SM_DIV_42
ganlikun	0:13413ea9a877	2745	* @arg @ref LL_RCC_PLLI2SM_DIV_43
ganlikun	0:13413ea9a877	2746	* @arg @ref LL_RCC_PLLI2SM_DIV_44
ganlikun	0:13413ea9a877	2747	* @arg @ref LL_RCC_PLLI2SM_DIV_45
ganlikun	0:13413ea9a877	2748	* @arg @ref LL_RCC_PLLI2SM_DIV_46
ganlikun	0:13413ea9a877	2749	* @arg @ref LL_RCC_PLLI2SM_DIV_47
ganlikun	0:13413ea9a877	2750	* @arg @ref LL_RCC_PLLI2SM_DIV_48
ganlikun	0:13413ea9a877	2751	* @arg @ref LL_RCC_PLLI2SM_DIV_49
ganlikun	0:13413ea9a877	2752	* @arg @ref LL_RCC_PLLI2SM_DIV_50
ganlikun	0:13413ea9a877	2753	* @arg @ref LL_RCC_PLLI2SM_DIV_51
ganlikun	0:13413ea9a877	2754	* @arg @ref LL_RCC_PLLI2SM_DIV_52
ganlikun	0:13413ea9a877	2755	* @arg @ref LL_RCC_PLLI2SM_DIV_53
ganlikun	0:13413ea9a877	2756	* @arg @ref LL_RCC_PLLI2SM_DIV_54
ganlikun	0:13413ea9a877	2757	* @arg @ref LL_RCC_PLLI2SM_DIV_55
ganlikun	0:13413ea9a877	2758	* @arg @ref LL_RCC_PLLI2SM_DIV_56
ganlikun	0:13413ea9a877	2759	* @arg @ref LL_RCC_PLLI2SM_DIV_57
ganlikun	0:13413ea9a877	2760	* @arg @ref LL_RCC_PLLI2SM_DIV_58
ganlikun	0:13413ea9a877	2761	* @arg @ref LL_RCC_PLLI2SM_DIV_59
ganlikun	0:13413ea9a877	2762	* @arg @ref LL_RCC_PLLI2SM_DIV_60
ganlikun	0:13413ea9a877	2763	* @arg @ref LL_RCC_PLLI2SM_DIV_61
ganlikun	0:13413ea9a877	2764	* @arg @ref LL_RCC_PLLI2SM_DIV_62
ganlikun	0:13413ea9a877	2765	* @arg @ref LL_RCC_PLLI2SM_DIV_63
ganlikun	0:13413ea9a877	2766	* @param __PLLI2SN__ Between 50/192(*) and 432
ganlikun	0:13413ea9a877	2767	*
ganlikun	0:13413ea9a877	2768	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	2769	* @param __PLLI2SR__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2770	* @arg @ref LL_RCC_PLLI2SR_DIV_2
ganlikun	0:13413ea9a877	2771	* @arg @ref LL_RCC_PLLI2SR_DIV_3
ganlikun	0:13413ea9a877	2772	* @arg @ref LL_RCC_PLLI2SR_DIV_4
ganlikun	0:13413ea9a877	2773	* @arg @ref LL_RCC_PLLI2SR_DIV_5
ganlikun	0:13413ea9a877	2774	* @arg @ref LL_RCC_PLLI2SR_DIV_6
ganlikun	0:13413ea9a877	2775	* @arg @ref LL_RCC_PLLI2SR_DIV_7
ganlikun	0:13413ea9a877	2776	* @retval PLLI2S clock frequency (in Hz)
ganlikun	0:13413ea9a877	2777	*/
ganlikun	0:13413ea9a877	2778	#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
ganlikun	0:13413ea9a877	2779	((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
ganlikun	0:13413ea9a877	2780
ganlikun	0:13413ea9a877	2781	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
ganlikun	0:13413ea9a877	2782	/**
ganlikun	0:13413ea9a877	2783	* @brief Helper macro to calculate the PLLI2S frequency used for 48Mhz domain
ganlikun	0:13413ea9a877	2784	* @note ex: @ref __LL_RCC_CALC_PLLI2S_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
ganlikun	0:13413ea9a877	2785	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ ());
ganlikun	0:13413ea9a877	2786	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
ganlikun	0:13413ea9a877	2787	* @param __PLLM__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2788	* @arg @ref LL_RCC_PLLI2SM_DIV_2
ganlikun	0:13413ea9a877	2789	* @arg @ref LL_RCC_PLLI2SM_DIV_3
ganlikun	0:13413ea9a877	2790	* @arg @ref LL_RCC_PLLI2SM_DIV_4
ganlikun	0:13413ea9a877	2791	* @arg @ref LL_RCC_PLLI2SM_DIV_5
ganlikun	0:13413ea9a877	2792	* @arg @ref LL_RCC_PLLI2SM_DIV_6
ganlikun	0:13413ea9a877	2793	* @arg @ref LL_RCC_PLLI2SM_DIV_7
ganlikun	0:13413ea9a877	2794	* @arg @ref LL_RCC_PLLI2SM_DIV_8
ganlikun	0:13413ea9a877	2795	* @arg @ref LL_RCC_PLLI2SM_DIV_9
ganlikun	0:13413ea9a877	2796	* @arg @ref LL_RCC_PLLI2SM_DIV_10
ganlikun	0:13413ea9a877	2797	* @arg @ref LL_RCC_PLLI2SM_DIV_11
ganlikun	0:13413ea9a877	2798	* @arg @ref LL_RCC_PLLI2SM_DIV_12
ganlikun	0:13413ea9a877	2799	* @arg @ref LL_RCC_PLLI2SM_DIV_13
ganlikun	0:13413ea9a877	2800	* @arg @ref LL_RCC_PLLI2SM_DIV_14
ganlikun	0:13413ea9a877	2801	* @arg @ref LL_RCC_PLLI2SM_DIV_15
ganlikun	0:13413ea9a877	2802	* @arg @ref LL_RCC_PLLI2SM_DIV_16
ganlikun	0:13413ea9a877	2803	* @arg @ref LL_RCC_PLLI2SM_DIV_17
ganlikun	0:13413ea9a877	2804	* @arg @ref LL_RCC_PLLI2SM_DIV_18
ganlikun	0:13413ea9a877	2805	* @arg @ref LL_RCC_PLLI2SM_DIV_19
ganlikun	0:13413ea9a877	2806	* @arg @ref LL_RCC_PLLI2SM_DIV_20
ganlikun	0:13413ea9a877	2807	* @arg @ref LL_RCC_PLLI2SM_DIV_21
ganlikun	0:13413ea9a877	2808	* @arg @ref LL_RCC_PLLI2SM_DIV_22
ganlikun	0:13413ea9a877	2809	* @arg @ref LL_RCC_PLLI2SM_DIV_23
ganlikun	0:13413ea9a877	2810	* @arg @ref LL_RCC_PLLI2SM_DIV_24
ganlikun	0:13413ea9a877	2811	* @arg @ref LL_RCC_PLLI2SM_DIV_25
ganlikun	0:13413ea9a877	2812	* @arg @ref LL_RCC_PLLI2SM_DIV_26
ganlikun	0:13413ea9a877	2813	* @arg @ref LL_RCC_PLLI2SM_DIV_27
ganlikun	0:13413ea9a877	2814	* @arg @ref LL_RCC_PLLI2SM_DIV_28
ganlikun	0:13413ea9a877	2815	* @arg @ref LL_RCC_PLLI2SM_DIV_29
ganlikun	0:13413ea9a877	2816	* @arg @ref LL_RCC_PLLI2SM_DIV_30
ganlikun	0:13413ea9a877	2817	* @arg @ref LL_RCC_PLLI2SM_DIV_31
ganlikun	0:13413ea9a877	2818	* @arg @ref LL_RCC_PLLI2SM_DIV_32
ganlikun	0:13413ea9a877	2819	* @arg @ref LL_RCC_PLLI2SM_DIV_33
ganlikun	0:13413ea9a877	2820	* @arg @ref LL_RCC_PLLI2SM_DIV_34
ganlikun	0:13413ea9a877	2821	* @arg @ref LL_RCC_PLLI2SM_DIV_35
ganlikun	0:13413ea9a877	2822	* @arg @ref LL_RCC_PLLI2SM_DIV_36
ganlikun	0:13413ea9a877	2823	* @arg @ref LL_RCC_PLLI2SM_DIV_37
ganlikun	0:13413ea9a877	2824	* @arg @ref LL_RCC_PLLI2SM_DIV_38
ganlikun	0:13413ea9a877	2825	* @arg @ref LL_RCC_PLLI2SM_DIV_39
ganlikun	0:13413ea9a877	2826	* @arg @ref LL_RCC_PLLI2SM_DIV_40
ganlikun	0:13413ea9a877	2827	* @arg @ref LL_RCC_PLLI2SM_DIV_41
ganlikun	0:13413ea9a877	2828	* @arg @ref LL_RCC_PLLI2SM_DIV_42
ganlikun	0:13413ea9a877	2829	* @arg @ref LL_RCC_PLLI2SM_DIV_43
ganlikun	0:13413ea9a877	2830	* @arg @ref LL_RCC_PLLI2SM_DIV_44
ganlikun	0:13413ea9a877	2831	* @arg @ref LL_RCC_PLLI2SM_DIV_45
ganlikun	0:13413ea9a877	2832	* @arg @ref LL_RCC_PLLI2SM_DIV_46
ganlikun	0:13413ea9a877	2833	* @arg @ref LL_RCC_PLLI2SM_DIV_47
ganlikun	0:13413ea9a877	2834	* @arg @ref LL_RCC_PLLI2SM_DIV_48
ganlikun	0:13413ea9a877	2835	* @arg @ref LL_RCC_PLLI2SM_DIV_49
ganlikun	0:13413ea9a877	2836	* @arg @ref LL_RCC_PLLI2SM_DIV_50
ganlikun	0:13413ea9a877	2837	* @arg @ref LL_RCC_PLLI2SM_DIV_51
ganlikun	0:13413ea9a877	2838	* @arg @ref LL_RCC_PLLI2SM_DIV_52
ganlikun	0:13413ea9a877	2839	* @arg @ref LL_RCC_PLLI2SM_DIV_53
ganlikun	0:13413ea9a877	2840	* @arg @ref LL_RCC_PLLI2SM_DIV_54
ganlikun	0:13413ea9a877	2841	* @arg @ref LL_RCC_PLLI2SM_DIV_55
ganlikun	0:13413ea9a877	2842	* @arg @ref LL_RCC_PLLI2SM_DIV_56
ganlikun	0:13413ea9a877	2843	* @arg @ref LL_RCC_PLLI2SM_DIV_57
ganlikun	0:13413ea9a877	2844	* @arg @ref LL_RCC_PLLI2SM_DIV_58
ganlikun	0:13413ea9a877	2845	* @arg @ref LL_RCC_PLLI2SM_DIV_59
ganlikun	0:13413ea9a877	2846	* @arg @ref LL_RCC_PLLI2SM_DIV_60
ganlikun	0:13413ea9a877	2847	* @arg @ref LL_RCC_PLLI2SM_DIV_61
ganlikun	0:13413ea9a877	2848	* @arg @ref LL_RCC_PLLI2SM_DIV_62
ganlikun	0:13413ea9a877	2849	* @arg @ref LL_RCC_PLLI2SM_DIV_63
ganlikun	0:13413ea9a877	2850	* @param __PLLI2SN__ Between 50 and 432
ganlikun	0:13413ea9a877	2851	* @param __PLLI2SQ__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2852	* @arg @ref LL_RCC_PLLI2SQ_DIV_2
ganlikun	0:13413ea9a877	2853	* @arg @ref LL_RCC_PLLI2SQ_DIV_3
ganlikun	0:13413ea9a877	2854	* @arg @ref LL_RCC_PLLI2SQ_DIV_4
ganlikun	0:13413ea9a877	2855	* @arg @ref LL_RCC_PLLI2SQ_DIV_5
ganlikun	0:13413ea9a877	2856	* @arg @ref LL_RCC_PLLI2SQ_DIV_6
ganlikun	0:13413ea9a877	2857	* @arg @ref LL_RCC_PLLI2SQ_DIV_7
ganlikun	0:13413ea9a877	2858	* @arg @ref LL_RCC_PLLI2SQ_DIV_8
ganlikun	0:13413ea9a877	2859	* @arg @ref LL_RCC_PLLI2SQ_DIV_9
ganlikun	0:13413ea9a877	2860	* @arg @ref LL_RCC_PLLI2SQ_DIV_10
ganlikun	0:13413ea9a877	2861	* @arg @ref LL_RCC_PLLI2SQ_DIV_11
ganlikun	0:13413ea9a877	2862	* @arg @ref LL_RCC_PLLI2SQ_DIV_12
ganlikun	0:13413ea9a877	2863	* @arg @ref LL_RCC_PLLI2SQ_DIV_13
ganlikun	0:13413ea9a877	2864	* @arg @ref LL_RCC_PLLI2SQ_DIV_14
ganlikun	0:13413ea9a877	2865	* @arg @ref LL_RCC_PLLI2SQ_DIV_15
ganlikun	0:13413ea9a877	2866	* @retval PLLI2S clock frequency (in Hz)
ganlikun	0:13413ea9a877	2867	*/
ganlikun	0:13413ea9a877	2868	#define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
ganlikun	0:13413ea9a877	2869	((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos))
ganlikun	0:13413ea9a877	2870
ganlikun	0:13413ea9a877	2871	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
ganlikun	0:13413ea9a877	2872	#endif /* RCC_PLLI2S_SUPPORT */
ganlikun	0:13413ea9a877	2873
ganlikun	0:13413ea9a877	2874	/**
ganlikun	0:13413ea9a877	2875	* @brief Helper macro to calculate the HCLK frequency
ganlikun	0:13413ea9a877	2876	* @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
ganlikun	0:13413ea9a877	2877	* @param __AHBPRESCALER__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2878	* @arg @ref LL_RCC_SYSCLK_DIV_1
ganlikun	0:13413ea9a877	2879	* @arg @ref LL_RCC_SYSCLK_DIV_2
ganlikun	0:13413ea9a877	2880	* @arg @ref LL_RCC_SYSCLK_DIV_4
ganlikun	0:13413ea9a877	2881	* @arg @ref LL_RCC_SYSCLK_DIV_8
ganlikun	0:13413ea9a877	2882	* @arg @ref LL_RCC_SYSCLK_DIV_16
ganlikun	0:13413ea9a877	2883	* @arg @ref LL_RCC_SYSCLK_DIV_64
ganlikun	0:13413ea9a877	2884	* @arg @ref LL_RCC_SYSCLK_DIV_128
ganlikun	0:13413ea9a877	2885	* @arg @ref LL_RCC_SYSCLK_DIV_256
ganlikun	0:13413ea9a877	2886	* @arg @ref LL_RCC_SYSCLK_DIV_512
ganlikun	0:13413ea9a877	2887	* @retval HCLK clock frequency (in Hz)
ganlikun	0:13413ea9a877	2888	*/
ganlikun	0:13413ea9a877	2889	#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
ganlikun	0:13413ea9a877	2890
ganlikun	0:13413ea9a877	2891	/**
ganlikun	0:13413ea9a877	2892	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
ganlikun	0:13413ea9a877	2893	* @param __HCLKFREQ__ HCLK frequency
ganlikun	0:13413ea9a877	2894	* @param __APB1PRESCALER__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2895	* @arg @ref LL_RCC_APB1_DIV_1
ganlikun	0:13413ea9a877	2896	* @arg @ref LL_RCC_APB1_DIV_2
ganlikun	0:13413ea9a877	2897	* @arg @ref LL_RCC_APB1_DIV_4
ganlikun	0:13413ea9a877	2898	* @arg @ref LL_RCC_APB1_DIV_8
ganlikun	0:13413ea9a877	2899	* @arg @ref LL_RCC_APB1_DIV_16
ganlikun	0:13413ea9a877	2900	* @retval PCLK1 clock frequency (in Hz)
ganlikun	0:13413ea9a877	2901	*/
ganlikun	0:13413ea9a877	2902	#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
ganlikun	0:13413ea9a877	2903
ganlikun	0:13413ea9a877	2904	/**
ganlikun	0:13413ea9a877	2905	* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
ganlikun	0:13413ea9a877	2906	* @param __HCLKFREQ__ HCLK frequency
ganlikun	0:13413ea9a877	2907	* @param __APB2PRESCALER__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	2908	* @arg @ref LL_RCC_APB2_DIV_1
ganlikun	0:13413ea9a877	2909	* @arg @ref LL_RCC_APB2_DIV_2
ganlikun	0:13413ea9a877	2910	* @arg @ref LL_RCC_APB2_DIV_4
ganlikun	0:13413ea9a877	2911	* @arg @ref LL_RCC_APB2_DIV_8
ganlikun	0:13413ea9a877	2912	* @arg @ref LL_RCC_APB2_DIV_16
ganlikun	0:13413ea9a877	2913	* @retval PCLK2 clock frequency (in Hz)
ganlikun	0:13413ea9a877	2914	*/
ganlikun	0:13413ea9a877	2915	#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
ganlikun	0:13413ea9a877	2916
ganlikun	0:13413ea9a877	2917	/**
ganlikun	0:13413ea9a877	2918	* @}
ganlikun	0:13413ea9a877	2919	*/
ganlikun	0:13413ea9a877	2920
ganlikun	0:13413ea9a877	2921	/**
ganlikun	0:13413ea9a877	2922	* @}
ganlikun	0:13413ea9a877	2923	*/
ganlikun	0:13413ea9a877	2924
ganlikun	0:13413ea9a877	2925	/* Exported functions --------------------------------------------------------*/
ganlikun	0:13413ea9a877	2926	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
ganlikun	0:13413ea9a877	2927	* @{
ganlikun	0:13413ea9a877	2928	*/
ganlikun	0:13413ea9a877	2929
ganlikun	0:13413ea9a877	2930	/** @defgroup RCC_LL_EF_HSE HSE
ganlikun	0:13413ea9a877	2931	* @{
ganlikun	0:13413ea9a877	2932	*/
ganlikun	0:13413ea9a877	2933
ganlikun	0:13413ea9a877	2934	/**
ganlikun	0:13413ea9a877	2935	* @brief Enable the Clock Security System.
ganlikun	0:13413ea9a877	2936	* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
ganlikun	0:13413ea9a877	2937	* @retval None
ganlikun	0:13413ea9a877	2938	*/
ganlikun	0:13413ea9a877	2939	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
ganlikun	0:13413ea9a877	2940	{
ganlikun	0:13413ea9a877	2941	SET_BIT(RCC->CR, RCC_CR_CSSON);
ganlikun	0:13413ea9a877	2942	}
ganlikun	0:13413ea9a877	2943
ganlikun	0:13413ea9a877	2944	/**
ganlikun	0:13413ea9a877	2945	* @brief Enable HSE external oscillator (HSE Bypass)
ganlikun	0:13413ea9a877	2946	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
ganlikun	0:13413ea9a877	2947	* @retval None
ganlikun	0:13413ea9a877	2948	*/
ganlikun	0:13413ea9a877	2949	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
ganlikun	0:13413ea9a877	2950	{
ganlikun	0:13413ea9a877	2951	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
ganlikun	0:13413ea9a877	2952	}
ganlikun	0:13413ea9a877	2953
ganlikun	0:13413ea9a877	2954	/**
ganlikun	0:13413ea9a877	2955	* @brief Disable HSE external oscillator (HSE Bypass)
ganlikun	0:13413ea9a877	2956	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
ganlikun	0:13413ea9a877	2957	* @retval None
ganlikun	0:13413ea9a877	2958	*/
ganlikun	0:13413ea9a877	2959	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
ganlikun	0:13413ea9a877	2960	{
ganlikun	0:13413ea9a877	2961	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
ganlikun	0:13413ea9a877	2962	}
ganlikun	0:13413ea9a877	2963
ganlikun	0:13413ea9a877	2964	/**
ganlikun	0:13413ea9a877	2965	* @brief Enable HSE crystal oscillator (HSE ON)
ganlikun	0:13413ea9a877	2966	* @rmtoll CR HSEON LL_RCC_HSE_Enable
ganlikun	0:13413ea9a877	2967	* @retval None
ganlikun	0:13413ea9a877	2968	*/
ganlikun	0:13413ea9a877	2969	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
ganlikun	0:13413ea9a877	2970	{
ganlikun	0:13413ea9a877	2971	SET_BIT(RCC->CR, RCC_CR_HSEON);
ganlikun	0:13413ea9a877	2972	}
ganlikun	0:13413ea9a877	2973
ganlikun	0:13413ea9a877	2974	/**
ganlikun	0:13413ea9a877	2975	* @brief Disable HSE crystal oscillator (HSE ON)
ganlikun	0:13413ea9a877	2976	* @rmtoll CR HSEON LL_RCC_HSE_Disable
ganlikun	0:13413ea9a877	2977	* @retval None
ganlikun	0:13413ea9a877	2978	*/
ganlikun	0:13413ea9a877	2979	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
ganlikun	0:13413ea9a877	2980	{
ganlikun	0:13413ea9a877	2981	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
ganlikun	0:13413ea9a877	2982	}
ganlikun	0:13413ea9a877	2983
ganlikun	0:13413ea9a877	2984	/**
ganlikun	0:13413ea9a877	2985	* @brief Check if HSE oscillator Ready
ganlikun	0:13413ea9a877	2986	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
ganlikun	0:13413ea9a877	2987	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	2988	*/
ganlikun	0:13413ea9a877	2989	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
ganlikun	0:13413ea9a877	2990	{
ganlikun	0:13413ea9a877	2991	return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
ganlikun	0:13413ea9a877	2992	}
ganlikun	0:13413ea9a877	2993
ganlikun	0:13413ea9a877	2994	/**
ganlikun	0:13413ea9a877	2995	* @}
ganlikun	0:13413ea9a877	2996	*/
ganlikun	0:13413ea9a877	2997
ganlikun	0:13413ea9a877	2998	/** @defgroup RCC_LL_EF_HSI HSI
ganlikun	0:13413ea9a877	2999	* @{
ganlikun	0:13413ea9a877	3000	*/
ganlikun	0:13413ea9a877	3001
ganlikun	0:13413ea9a877	3002	/**
ganlikun	0:13413ea9a877	3003	* @brief Enable HSI oscillator
ganlikun	0:13413ea9a877	3004	* @rmtoll CR HSION LL_RCC_HSI_Enable
ganlikun	0:13413ea9a877	3005	* @retval None
ganlikun	0:13413ea9a877	3006	*/
ganlikun	0:13413ea9a877	3007	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
ganlikun	0:13413ea9a877	3008	{
ganlikun	0:13413ea9a877	3009	SET_BIT(RCC->CR, RCC_CR_HSION);
ganlikun	0:13413ea9a877	3010	}
ganlikun	0:13413ea9a877	3011
ganlikun	0:13413ea9a877	3012	/**
ganlikun	0:13413ea9a877	3013	* @brief Disable HSI oscillator
ganlikun	0:13413ea9a877	3014	* @rmtoll CR HSION LL_RCC_HSI_Disable
ganlikun	0:13413ea9a877	3015	* @retval None
ganlikun	0:13413ea9a877	3016	*/
ganlikun	0:13413ea9a877	3017	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
ganlikun	0:13413ea9a877	3018	{
ganlikun	0:13413ea9a877	3019	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
ganlikun	0:13413ea9a877	3020	}
ganlikun	0:13413ea9a877	3021
ganlikun	0:13413ea9a877	3022	/**
ganlikun	0:13413ea9a877	3023	* @brief Check if HSI clock is ready
ganlikun	0:13413ea9a877	3024	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
ganlikun	0:13413ea9a877	3025	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	3026	*/
ganlikun	0:13413ea9a877	3027	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
ganlikun	0:13413ea9a877	3028	{
ganlikun	0:13413ea9a877	3029	return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
ganlikun	0:13413ea9a877	3030	}
ganlikun	0:13413ea9a877	3031
ganlikun	0:13413ea9a877	3032	/**
ganlikun	0:13413ea9a877	3033	* @brief Get HSI Calibration value
ganlikun	0:13413ea9a877	3034	* @note When HSITRIM is written, HSICAL is updated with the sum of
ganlikun	0:13413ea9a877	3035	* HSITRIM and the factory trim value
ganlikun	0:13413ea9a877	3036	* @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
ganlikun	0:13413ea9a877	3037	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
ganlikun	0:13413ea9a877	3038	*/
ganlikun	0:13413ea9a877	3039	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
ganlikun	0:13413ea9a877	3040	{
ganlikun	0:13413ea9a877	3041	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
ganlikun	0:13413ea9a877	3042	}
ganlikun	0:13413ea9a877	3043
ganlikun	0:13413ea9a877	3044	/**
ganlikun	0:13413ea9a877	3045	* @brief Set HSI Calibration trimming
ganlikun	0:13413ea9a877	3046	* @note user-programmable trimming value that is added to the HSICAL
ganlikun	0:13413ea9a877	3047	* @note Default value is 16, which, when added to the HSICAL value,
ganlikun	0:13413ea9a877	3048	* should trim the HSI to 16 MHz +/- 1 %
ganlikun	0:13413ea9a877	3049	* @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
ganlikun	0:13413ea9a877	3050	* @param Value Between Min_Data = 0 and Max_Data = 31
ganlikun	0:13413ea9a877	3051	* @retval None
ganlikun	0:13413ea9a877	3052	*/
ganlikun	0:13413ea9a877	3053	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
ganlikun	0:13413ea9a877	3054	{
ganlikun	0:13413ea9a877	3055	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
ganlikun	0:13413ea9a877	3056	}
ganlikun	0:13413ea9a877	3057
ganlikun	0:13413ea9a877	3058	/**
ganlikun	0:13413ea9a877	3059	* @brief Get HSI Calibration trimming
ganlikun	0:13413ea9a877	3060	* @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
ganlikun	0:13413ea9a877	3061	* @retval Between Min_Data = 0 and Max_Data = 31
ganlikun	0:13413ea9a877	3062	*/
ganlikun	0:13413ea9a877	3063	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
ganlikun	0:13413ea9a877	3064	{
ganlikun	0:13413ea9a877	3065	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
ganlikun	0:13413ea9a877	3066	}
ganlikun	0:13413ea9a877	3067
ganlikun	0:13413ea9a877	3068	/**
ganlikun	0:13413ea9a877	3069	* @}
ganlikun	0:13413ea9a877	3070	*/
ganlikun	0:13413ea9a877	3071
ganlikun	0:13413ea9a877	3072	/** @defgroup RCC_LL_EF_LSE LSE
ganlikun	0:13413ea9a877	3073	* @{
ganlikun	0:13413ea9a877	3074	*/
ganlikun	0:13413ea9a877	3075
ganlikun	0:13413ea9a877	3076	/**
ganlikun	0:13413ea9a877	3077	* @brief Enable Low Speed External (LSE) crystal.
ganlikun	0:13413ea9a877	3078	* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
ganlikun	0:13413ea9a877	3079	* @retval None
ganlikun	0:13413ea9a877	3080	*/
ganlikun	0:13413ea9a877	3081	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
ganlikun	0:13413ea9a877	3082	{
ganlikun	0:13413ea9a877	3083	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
ganlikun	0:13413ea9a877	3084	}
ganlikun	0:13413ea9a877	3085
ganlikun	0:13413ea9a877	3086	/**
ganlikun	0:13413ea9a877	3087	* @brief Disable Low Speed External (LSE) crystal.
ganlikun	0:13413ea9a877	3088	* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
ganlikun	0:13413ea9a877	3089	* @retval None
ganlikun	0:13413ea9a877	3090	*/
ganlikun	0:13413ea9a877	3091	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
ganlikun	0:13413ea9a877	3092	{
ganlikun	0:13413ea9a877	3093	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
ganlikun	0:13413ea9a877	3094	}
ganlikun	0:13413ea9a877	3095
ganlikun	0:13413ea9a877	3096	/**
ganlikun	0:13413ea9a877	3097	* @brief Enable external clock source (LSE bypass).
ganlikun	0:13413ea9a877	3098	* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
ganlikun	0:13413ea9a877	3099	* @retval None
ganlikun	0:13413ea9a877	3100	*/
ganlikun	0:13413ea9a877	3101	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
ganlikun	0:13413ea9a877	3102	{
ganlikun	0:13413ea9a877	3103	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
ganlikun	0:13413ea9a877	3104	}
ganlikun	0:13413ea9a877	3105
ganlikun	0:13413ea9a877	3106	/**
ganlikun	0:13413ea9a877	3107	* @brief Disable external clock source (LSE bypass).
ganlikun	0:13413ea9a877	3108	* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
ganlikun	0:13413ea9a877	3109	* @retval None
ganlikun	0:13413ea9a877	3110	*/
ganlikun	0:13413ea9a877	3111	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
ganlikun	0:13413ea9a877	3112	{
ganlikun	0:13413ea9a877	3113	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
ganlikun	0:13413ea9a877	3114	}
ganlikun	0:13413ea9a877	3115
ganlikun	0:13413ea9a877	3116	/**
ganlikun	0:13413ea9a877	3117	* @brief Check if LSE oscillator Ready
ganlikun	0:13413ea9a877	3118	* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
ganlikun	0:13413ea9a877	3119	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	3120	*/
ganlikun	0:13413ea9a877	3121	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
ganlikun	0:13413ea9a877	3122	{
ganlikun	0:13413ea9a877	3123	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
ganlikun	0:13413ea9a877	3124	}
ganlikun	0:13413ea9a877	3125
ganlikun	0:13413ea9a877	3126	#if defined(RCC_BDCR_LSEMOD)
ganlikun	0:13413ea9a877	3127	/**
ganlikun	0:13413ea9a877	3128	* @brief Enable LSE high drive mode.
ganlikun	0:13413ea9a877	3129	* @note LSE high drive mode can be enabled only when the LSE clock is disabled
ganlikun	0:13413ea9a877	3130	* @rmtoll BDCR LSEMOD LL_RCC_LSE_EnableHighDriveMode
ganlikun	0:13413ea9a877	3131	* @retval None
ganlikun	0:13413ea9a877	3132	*/
ganlikun	0:13413ea9a877	3133	__STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void)
ganlikun	0:13413ea9a877	3134	{
ganlikun	0:13413ea9a877	3135	SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
ganlikun	0:13413ea9a877	3136	}
ganlikun	0:13413ea9a877	3137
ganlikun	0:13413ea9a877	3138	/**
ganlikun	0:13413ea9a877	3139	* @brief Disable LSE high drive mode.
ganlikun	0:13413ea9a877	3140	* @note LSE high drive mode can be disabled only when the LSE clock is disabled
ganlikun	0:13413ea9a877	3141	* @rmtoll BDCR LSEMOD LL_RCC_LSE_DisableHighDriveMode
ganlikun	0:13413ea9a877	3142	* @retval None
ganlikun	0:13413ea9a877	3143	*/
ganlikun	0:13413ea9a877	3144	__STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void)
ganlikun	0:13413ea9a877	3145	{
ganlikun	0:13413ea9a877	3146	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
ganlikun	0:13413ea9a877	3147	}
ganlikun	0:13413ea9a877	3148	#endif /* RCC_BDCR_LSEMOD */
ganlikun	0:13413ea9a877	3149
ganlikun	0:13413ea9a877	3150	/**
ganlikun	0:13413ea9a877	3151	* @}
ganlikun	0:13413ea9a877	3152	*/
ganlikun	0:13413ea9a877	3153
ganlikun	0:13413ea9a877	3154	/** @defgroup RCC_LL_EF_LSI LSI
ganlikun	0:13413ea9a877	3155	* @{
ganlikun	0:13413ea9a877	3156	*/
ganlikun	0:13413ea9a877	3157
ganlikun	0:13413ea9a877	3158	/**
ganlikun	0:13413ea9a877	3159	* @brief Enable LSI Oscillator
ganlikun	0:13413ea9a877	3160	* @rmtoll CSR LSION LL_RCC_LSI_Enable
ganlikun	0:13413ea9a877	3161	* @retval None
ganlikun	0:13413ea9a877	3162	*/
ganlikun	0:13413ea9a877	3163	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
ganlikun	0:13413ea9a877	3164	{
ganlikun	0:13413ea9a877	3165	SET_BIT(RCC->CSR, RCC_CSR_LSION);
ganlikun	0:13413ea9a877	3166	}
ganlikun	0:13413ea9a877	3167
ganlikun	0:13413ea9a877	3168	/**
ganlikun	0:13413ea9a877	3169	* @brief Disable LSI Oscillator
ganlikun	0:13413ea9a877	3170	* @rmtoll CSR LSION LL_RCC_LSI_Disable
ganlikun	0:13413ea9a877	3171	* @retval None
ganlikun	0:13413ea9a877	3172	*/
ganlikun	0:13413ea9a877	3173	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
ganlikun	0:13413ea9a877	3174	{
ganlikun	0:13413ea9a877	3175	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
ganlikun	0:13413ea9a877	3176	}
ganlikun	0:13413ea9a877	3177
ganlikun	0:13413ea9a877	3178	/**
ganlikun	0:13413ea9a877	3179	* @brief Check if LSI is Ready
ganlikun	0:13413ea9a877	3180	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
ganlikun	0:13413ea9a877	3181	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	3182	*/
ganlikun	0:13413ea9a877	3183	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
ganlikun	0:13413ea9a877	3184	{
ganlikun	0:13413ea9a877	3185	return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
ganlikun	0:13413ea9a877	3186	}
ganlikun	0:13413ea9a877	3187
ganlikun	0:13413ea9a877	3188	/**
ganlikun	0:13413ea9a877	3189	* @}
ganlikun	0:13413ea9a877	3190	*/
ganlikun	0:13413ea9a877	3191
ganlikun	0:13413ea9a877	3192	/** @defgroup RCC_LL_EF_System System
ganlikun	0:13413ea9a877	3193	* @{
ganlikun	0:13413ea9a877	3194	*/
ganlikun	0:13413ea9a877	3195
ganlikun	0:13413ea9a877	3196	/**
ganlikun	0:13413ea9a877	3197	* @brief Configure the system clock source
ganlikun	0:13413ea9a877	3198	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
ganlikun	0:13413ea9a877	3199	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3200	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
ganlikun	0:13413ea9a877	3201	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
ganlikun	0:13413ea9a877	3202	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
ganlikun	0:13413ea9a877	3203	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLLR (*)
ganlikun	0:13413ea9a877	3204	*
ganlikun	0:13413ea9a877	3205	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	3206	* @retval None
ganlikun	0:13413ea9a877	3207	*/
ganlikun	0:13413ea9a877	3208	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
ganlikun	0:13413ea9a877	3209	{
ganlikun	0:13413ea9a877	3210	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
ganlikun	0:13413ea9a877	3211	}
ganlikun	0:13413ea9a877	3212
ganlikun	0:13413ea9a877	3213	/**
ganlikun	0:13413ea9a877	3214	* @brief Get the system clock source
ganlikun	0:13413ea9a877	3215	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
ganlikun	0:13413ea9a877	3216	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	3217	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
ganlikun	0:13413ea9a877	3218	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
ganlikun	0:13413ea9a877	3219	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
ganlikun	0:13413ea9a877	3220	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLLR (*)
ganlikun	0:13413ea9a877	3221	*
ganlikun	0:13413ea9a877	3222	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	3223	*/
ganlikun	0:13413ea9a877	3224	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
ganlikun	0:13413ea9a877	3225	{
ganlikun	0:13413ea9a877	3226	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
ganlikun	0:13413ea9a877	3227	}
ganlikun	0:13413ea9a877	3228
ganlikun	0:13413ea9a877	3229	/**
ganlikun	0:13413ea9a877	3230	* @brief Set AHB prescaler
ganlikun	0:13413ea9a877	3231	* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
ganlikun	0:13413ea9a877	3232	* @param Prescaler This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3233	* @arg @ref LL_RCC_SYSCLK_DIV_1
ganlikun	0:13413ea9a877	3234	* @arg @ref LL_RCC_SYSCLK_DIV_2
ganlikun	0:13413ea9a877	3235	* @arg @ref LL_RCC_SYSCLK_DIV_4
ganlikun	0:13413ea9a877	3236	* @arg @ref LL_RCC_SYSCLK_DIV_8
ganlikun	0:13413ea9a877	3237	* @arg @ref LL_RCC_SYSCLK_DIV_16
ganlikun	0:13413ea9a877	3238	* @arg @ref LL_RCC_SYSCLK_DIV_64
ganlikun	0:13413ea9a877	3239	* @arg @ref LL_RCC_SYSCLK_DIV_128
ganlikun	0:13413ea9a877	3240	* @arg @ref LL_RCC_SYSCLK_DIV_256
ganlikun	0:13413ea9a877	3241	* @arg @ref LL_RCC_SYSCLK_DIV_512
ganlikun	0:13413ea9a877	3242	* @retval None
ganlikun	0:13413ea9a877	3243	*/
ganlikun	0:13413ea9a877	3244	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
ganlikun	0:13413ea9a877	3245	{
ganlikun	0:13413ea9a877	3246	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
ganlikun	0:13413ea9a877	3247	}
ganlikun	0:13413ea9a877	3248
ganlikun	0:13413ea9a877	3249	/**
ganlikun	0:13413ea9a877	3250	* @brief Set APB1 prescaler
ganlikun	0:13413ea9a877	3251	* @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
ganlikun	0:13413ea9a877	3252	* @param Prescaler This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3253	* @arg @ref LL_RCC_APB1_DIV_1
ganlikun	0:13413ea9a877	3254	* @arg @ref LL_RCC_APB1_DIV_2
ganlikun	0:13413ea9a877	3255	* @arg @ref LL_RCC_APB1_DIV_4
ganlikun	0:13413ea9a877	3256	* @arg @ref LL_RCC_APB1_DIV_8
ganlikun	0:13413ea9a877	3257	* @arg @ref LL_RCC_APB1_DIV_16
ganlikun	0:13413ea9a877	3258	* @retval None
ganlikun	0:13413ea9a877	3259	*/
ganlikun	0:13413ea9a877	3260	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
ganlikun	0:13413ea9a877	3261	{
ganlikun	0:13413ea9a877	3262	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
ganlikun	0:13413ea9a877	3263	}
ganlikun	0:13413ea9a877	3264
ganlikun	0:13413ea9a877	3265	/**
ganlikun	0:13413ea9a877	3266	* @brief Set APB2 prescaler
ganlikun	0:13413ea9a877	3267	* @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
ganlikun	0:13413ea9a877	3268	* @param Prescaler This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3269	* @arg @ref LL_RCC_APB2_DIV_1
ganlikun	0:13413ea9a877	3270	* @arg @ref LL_RCC_APB2_DIV_2
ganlikun	0:13413ea9a877	3271	* @arg @ref LL_RCC_APB2_DIV_4
ganlikun	0:13413ea9a877	3272	* @arg @ref LL_RCC_APB2_DIV_8
ganlikun	0:13413ea9a877	3273	* @arg @ref LL_RCC_APB2_DIV_16
ganlikun	0:13413ea9a877	3274	* @retval None
ganlikun	0:13413ea9a877	3275	*/
ganlikun	0:13413ea9a877	3276	__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
ganlikun	0:13413ea9a877	3277	{
ganlikun	0:13413ea9a877	3278	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
ganlikun	0:13413ea9a877	3279	}
ganlikun	0:13413ea9a877	3280
ganlikun	0:13413ea9a877	3281	/**
ganlikun	0:13413ea9a877	3282	* @brief Get AHB prescaler
ganlikun	0:13413ea9a877	3283	* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
ganlikun	0:13413ea9a877	3284	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	3285	* @arg @ref LL_RCC_SYSCLK_DIV_1
ganlikun	0:13413ea9a877	3286	* @arg @ref LL_RCC_SYSCLK_DIV_2
ganlikun	0:13413ea9a877	3287	* @arg @ref LL_RCC_SYSCLK_DIV_4
ganlikun	0:13413ea9a877	3288	* @arg @ref LL_RCC_SYSCLK_DIV_8
ganlikun	0:13413ea9a877	3289	* @arg @ref LL_RCC_SYSCLK_DIV_16
ganlikun	0:13413ea9a877	3290	* @arg @ref LL_RCC_SYSCLK_DIV_64
ganlikun	0:13413ea9a877	3291	* @arg @ref LL_RCC_SYSCLK_DIV_128
ganlikun	0:13413ea9a877	3292	* @arg @ref LL_RCC_SYSCLK_DIV_256
ganlikun	0:13413ea9a877	3293	* @arg @ref LL_RCC_SYSCLK_DIV_512
ganlikun	0:13413ea9a877	3294	*/
ganlikun	0:13413ea9a877	3295	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
ganlikun	0:13413ea9a877	3296	{
ganlikun	0:13413ea9a877	3297	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
ganlikun	0:13413ea9a877	3298	}
ganlikun	0:13413ea9a877	3299
ganlikun	0:13413ea9a877	3300	/**
ganlikun	0:13413ea9a877	3301	* @brief Get APB1 prescaler
ganlikun	0:13413ea9a877	3302	* @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
ganlikun	0:13413ea9a877	3303	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	3304	* @arg @ref LL_RCC_APB1_DIV_1
ganlikun	0:13413ea9a877	3305	* @arg @ref LL_RCC_APB1_DIV_2
ganlikun	0:13413ea9a877	3306	* @arg @ref LL_RCC_APB1_DIV_4
ganlikun	0:13413ea9a877	3307	* @arg @ref LL_RCC_APB1_DIV_8
ganlikun	0:13413ea9a877	3308	* @arg @ref LL_RCC_APB1_DIV_16
ganlikun	0:13413ea9a877	3309	*/
ganlikun	0:13413ea9a877	3310	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
ganlikun	0:13413ea9a877	3311	{
ganlikun	0:13413ea9a877	3312	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
ganlikun	0:13413ea9a877	3313	}
ganlikun	0:13413ea9a877	3314
ganlikun	0:13413ea9a877	3315	/**
ganlikun	0:13413ea9a877	3316	* @brief Get APB2 prescaler
ganlikun	0:13413ea9a877	3317	* @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
ganlikun	0:13413ea9a877	3318	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	3319	* @arg @ref LL_RCC_APB2_DIV_1
ganlikun	0:13413ea9a877	3320	* @arg @ref LL_RCC_APB2_DIV_2
ganlikun	0:13413ea9a877	3321	* @arg @ref LL_RCC_APB2_DIV_4
ganlikun	0:13413ea9a877	3322	* @arg @ref LL_RCC_APB2_DIV_8
ganlikun	0:13413ea9a877	3323	* @arg @ref LL_RCC_APB2_DIV_16
ganlikun	0:13413ea9a877	3324	*/
ganlikun	0:13413ea9a877	3325	__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
ganlikun	0:13413ea9a877	3326	{
ganlikun	0:13413ea9a877	3327	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
ganlikun	0:13413ea9a877	3328	}
ganlikun	0:13413ea9a877	3329
ganlikun	0:13413ea9a877	3330	/**
ganlikun	0:13413ea9a877	3331	* @}
ganlikun	0:13413ea9a877	3332	*/
ganlikun	0:13413ea9a877	3333
ganlikun	0:13413ea9a877	3334	/** @defgroup RCC_LL_EF_MCO MCO
ganlikun	0:13413ea9a877	3335	* @{
ganlikun	0:13413ea9a877	3336	*/
ganlikun	0:13413ea9a877	3337
ganlikun	0:13413ea9a877	3338	#if defined(RCC_CFGR_MCO1EN)
ganlikun	0:13413ea9a877	3339	/**
ganlikun	0:13413ea9a877	3340	* @brief Enable MCO1 output
ganlikun	0:13413ea9a877	3341	* @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Enable
ganlikun	0:13413ea9a877	3342	* @retval None
ganlikun	0:13413ea9a877	3343	*/
ganlikun	0:13413ea9a877	3344	__STATIC_INLINE void LL_RCC_MCO1_Enable(void)
ganlikun	0:13413ea9a877	3345	{
ganlikun	0:13413ea9a877	3346	SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
ganlikun	0:13413ea9a877	3347	}
ganlikun	0:13413ea9a877	3348
ganlikun	0:13413ea9a877	3349	/**
ganlikun	0:13413ea9a877	3350	* @brief Disable MCO1 output
ganlikun	0:13413ea9a877	3351	* @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Disable
ganlikun	0:13413ea9a877	3352	* @retval None
ganlikun	0:13413ea9a877	3353	*/
ganlikun	0:13413ea9a877	3354	__STATIC_INLINE void LL_RCC_MCO1_Disable(void)
ganlikun	0:13413ea9a877	3355	{
ganlikun	0:13413ea9a877	3356	CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
ganlikun	0:13413ea9a877	3357	}
ganlikun	0:13413ea9a877	3358	#endif /* RCC_CFGR_MCO1EN */
ganlikun	0:13413ea9a877	3359
ganlikun	0:13413ea9a877	3360	#if defined(RCC_CFGR_MCO2EN)
ganlikun	0:13413ea9a877	3361	/**
ganlikun	0:13413ea9a877	3362	* @brief Enable MCO2 output
ganlikun	0:13413ea9a877	3363	* @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Enable
ganlikun	0:13413ea9a877	3364	* @retval None
ganlikun	0:13413ea9a877	3365	*/
ganlikun	0:13413ea9a877	3366	__STATIC_INLINE void LL_RCC_MCO2_Enable(void)
ganlikun	0:13413ea9a877	3367	{
ganlikun	0:13413ea9a877	3368	SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
ganlikun	0:13413ea9a877	3369	}
ganlikun	0:13413ea9a877	3370
ganlikun	0:13413ea9a877	3371	/**
ganlikun	0:13413ea9a877	3372	* @brief Disable MCO2 output
ganlikun	0:13413ea9a877	3373	* @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Disable
ganlikun	0:13413ea9a877	3374	* @retval None
ganlikun	0:13413ea9a877	3375	*/
ganlikun	0:13413ea9a877	3376	__STATIC_INLINE void LL_RCC_MCO2_Disable(void)
ganlikun	0:13413ea9a877	3377	{
ganlikun	0:13413ea9a877	3378	CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
ganlikun	0:13413ea9a877	3379	}
ganlikun	0:13413ea9a877	3380	#endif /* RCC_CFGR_MCO2EN */
ganlikun	0:13413ea9a877	3381
ganlikun	0:13413ea9a877	3382	/**
ganlikun	0:13413ea9a877	3383	* @brief Configure MCOx
ganlikun	0:13413ea9a877	3384	* @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
ganlikun	0:13413ea9a877	3385	* CFGR MCO1PRE LL_RCC_ConfigMCO\n
ganlikun	0:13413ea9a877	3386	* CFGR MCO2 LL_RCC_ConfigMCO\n
ganlikun	0:13413ea9a877	3387	* CFGR MCO2PRE LL_RCC_ConfigMCO
ganlikun	0:13413ea9a877	3388	* @param MCOxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3389	* @arg @ref LL_RCC_MCO1SOURCE_HSI
ganlikun	0:13413ea9a877	3390	* @arg @ref LL_RCC_MCO1SOURCE_LSE
ganlikun	0:13413ea9a877	3391	* @arg @ref LL_RCC_MCO1SOURCE_HSE
ganlikun	0:13413ea9a877	3392	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
ganlikun	0:13413ea9a877	3393	* @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
ganlikun	0:13413ea9a877	3394	* @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
ganlikun	0:13413ea9a877	3395	* @arg @ref LL_RCC_MCO2SOURCE_HSE
ganlikun	0:13413ea9a877	3396	* @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
ganlikun	0:13413ea9a877	3397	* @param MCOxPrescaler This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3398	* @arg @ref LL_RCC_MCO1_DIV_1
ganlikun	0:13413ea9a877	3399	* @arg @ref LL_RCC_MCO1_DIV_2
ganlikun	0:13413ea9a877	3400	* @arg @ref LL_RCC_MCO1_DIV_3
ganlikun	0:13413ea9a877	3401	* @arg @ref LL_RCC_MCO1_DIV_4
ganlikun	0:13413ea9a877	3402	* @arg @ref LL_RCC_MCO1_DIV_5
ganlikun	0:13413ea9a877	3403	* @arg @ref LL_RCC_MCO2_DIV_1
ganlikun	0:13413ea9a877	3404	* @arg @ref LL_RCC_MCO2_DIV_2
ganlikun	0:13413ea9a877	3405	* @arg @ref LL_RCC_MCO2_DIV_3
ganlikun	0:13413ea9a877	3406	* @arg @ref LL_RCC_MCO2_DIV_4
ganlikun	0:13413ea9a877	3407	* @arg @ref LL_RCC_MCO2_DIV_5
ganlikun	0:13413ea9a877	3408	* @retval None
ganlikun	0:13413ea9a877	3409	*/
ganlikun	0:13413ea9a877	3410	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
ganlikun	0:13413ea9a877	3411	{
ganlikun	0:13413ea9a877	3412	MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) \| (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) \| (MCOxPrescaler << 16U));
ganlikun	0:13413ea9a877	3413	}
ganlikun	0:13413ea9a877	3414
ganlikun	0:13413ea9a877	3415	/**
ganlikun	0:13413ea9a877	3416	* @}
ganlikun	0:13413ea9a877	3417	*/
ganlikun	0:13413ea9a877	3418
ganlikun	0:13413ea9a877	3419	/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
ganlikun	0:13413ea9a877	3420	* @{
ganlikun	0:13413ea9a877	3421	*/
ganlikun	0:13413ea9a877	3422	#if defined(FMPI2C1)
ganlikun	0:13413ea9a877	3423	/**
ganlikun	0:13413ea9a877	3424	* @brief Configure FMPI2C clock source
ganlikun	0:13413ea9a877	3425	* @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_SetFMPI2CClockSource
ganlikun	0:13413ea9a877	3426	* @param FMPI2CxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3427	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
ganlikun	0:13413ea9a877	3428	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
ganlikun	0:13413ea9a877	3429	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
ganlikun	0:13413ea9a877	3430	* @retval None
ganlikun	0:13413ea9a877	3431	*/
ganlikun	0:13413ea9a877	3432	__STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource)
ganlikun	0:13413ea9a877	3433	{
ganlikun	0:13413ea9a877	3434	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource);
ganlikun	0:13413ea9a877	3435	}
ganlikun	0:13413ea9a877	3436	#endif /* FMPI2C1 */
ganlikun	0:13413ea9a877	3437
ganlikun	0:13413ea9a877	3438	#if defined(LPTIM1)
ganlikun	0:13413ea9a877	3439	/**
ganlikun	0:13413ea9a877	3440	* @brief Configure LPTIMx clock source
ganlikun	0:13413ea9a877	3441	* @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource
ganlikun	0:13413ea9a877	3442	* @param LPTIMxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3443	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
ganlikun	0:13413ea9a877	3444	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
ganlikun	0:13413ea9a877	3445	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
ganlikun	0:13413ea9a877	3446	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
ganlikun	0:13413ea9a877	3447	* @retval None
ganlikun	0:13413ea9a877	3448	*/
ganlikun	0:13413ea9a877	3449	__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
ganlikun	0:13413ea9a877	3450	{
ganlikun	0:13413ea9a877	3451	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
ganlikun	0:13413ea9a877	3452	}
ganlikun	0:13413ea9a877	3453	#endif /* LPTIM1 */
ganlikun	0:13413ea9a877	3454
ganlikun	0:13413ea9a877	3455	#if defined(SAI1)
ganlikun	0:13413ea9a877	3456	/**
ganlikun	0:13413ea9a877	3457	* @brief Configure SAIx clock source
ganlikun	0:13413ea9a877	3458	* @rmtoll DCKCFGR SAI1SRC LL_RCC_SetSAIClockSource\n
ganlikun	0:13413ea9a877	3459	* DCKCFGR SAI2SRC LL_RCC_SetSAIClockSource\n
ganlikun	0:13413ea9a877	3460	* DCKCFGR SAI1ASRC LL_RCC_SetSAIClockSource\n
ganlikun	0:13413ea9a877	3461	* DCKCFGR SAI1BSRC LL_RCC_SetSAIClockSource
ganlikun	0:13413ea9a877	3462	* @param SAIxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3463	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
ganlikun	0:13413ea9a877	3464	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
ganlikun	0:13413ea9a877	3465	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
ganlikun	0:13413ea9a877	3466	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
ganlikun	0:13413ea9a877	3467	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
ganlikun	0:13413ea9a877	3468	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
ganlikun	0:13413ea9a877	3469	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
ganlikun	0:13413ea9a877	3470	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
ganlikun	0:13413ea9a877	3471	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
ganlikun	0:13413ea9a877	3472	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
ganlikun	0:13413ea9a877	3473	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
ganlikun	0:13413ea9a877	3474	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
ganlikun	0:13413ea9a877	3475	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
ganlikun	0:13413ea9a877	3476	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
ganlikun	0:13413ea9a877	3477	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
ganlikun	0:13413ea9a877	3478	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
ganlikun	0:13413ea9a877	3479	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*)
ganlikun	0:13413ea9a877	3480	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
ganlikun	0:13413ea9a877	3481	*
ganlikun	0:13413ea9a877	3482	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	3483	* @retval None
ganlikun	0:13413ea9a877	3484	*/
ganlikun	0:13413ea9a877	3485	__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
ganlikun	0:13413ea9a877	3486	{
ganlikun	0:13413ea9a877	3487	MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
ganlikun	0:13413ea9a877	3488	}
ganlikun	0:13413ea9a877	3489	#endif /* SAI1 */
ganlikun	0:13413ea9a877	3490
ganlikun	0:13413ea9a877	3491	#if defined(RCC_DCKCFGR_SDIOSEL) \|\| defined(RCC_DCKCFGR2_SDIOSEL)
ganlikun	0:13413ea9a877	3492	/**
ganlikun	0:13413ea9a877	3493	* @brief Configure SDIO clock source
ganlikun	0:13413ea9a877	3494	* @rmtoll DCKCFGR SDIOSEL LL_RCC_SetSDIOClockSource\n
ganlikun	0:13413ea9a877	3495	* DCKCFGR2 SDIOSEL LL_RCC_SetSDIOClockSource
ganlikun	0:13413ea9a877	3496	* @param SDIOxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3497	* @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
ganlikun	0:13413ea9a877	3498	* @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
ganlikun	0:13413ea9a877	3499	* @retval None
ganlikun	0:13413ea9a877	3500	*/
ganlikun	0:13413ea9a877	3501	__STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource)
ganlikun	0:13413ea9a877	3502	{
ganlikun	0:13413ea9a877	3503	#if defined(RCC_DCKCFGR_SDIOSEL)
ganlikun	0:13413ea9a877	3504	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource);
ganlikun	0:13413ea9a877	3505	#else
ganlikun	0:13413ea9a877	3506	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource);
ganlikun	0:13413ea9a877	3507	#endif /* RCC_DCKCFGR_SDIOSEL */
ganlikun	0:13413ea9a877	3508	}
ganlikun	0:13413ea9a877	3509	#endif /* RCC_DCKCFGR_SDIOSEL \|\| RCC_DCKCFGR2_SDIOSEL */
ganlikun	0:13413ea9a877	3510
ganlikun	0:13413ea9a877	3511	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
ganlikun	0:13413ea9a877	3512	/**
ganlikun	0:13413ea9a877	3513	* @brief Configure 48Mhz domain clock source
ganlikun	0:13413ea9a877	3514	* @rmtoll DCKCFGR CK48MSEL LL_RCC_SetCK48MClockSource\n
ganlikun	0:13413ea9a877	3515	* DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource
ganlikun	0:13413ea9a877	3516	* @param CK48MxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3517	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
ganlikun	0:13413ea9a877	3518	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
ganlikun	0:13413ea9a877	3519	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
ganlikun	0:13413ea9a877	3520	*
ganlikun	0:13413ea9a877	3521	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	3522	* @retval None
ganlikun	0:13413ea9a877	3523	*/
ganlikun	0:13413ea9a877	3524	__STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
ganlikun	0:13413ea9a877	3525	{
ganlikun	0:13413ea9a877	3526	#if defined(RCC_DCKCFGR_CK48MSEL)
ganlikun	0:13413ea9a877	3527	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource);
ganlikun	0:13413ea9a877	3528	#else
ganlikun	0:13413ea9a877	3529	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
ganlikun	0:13413ea9a877	3530	#endif /* RCC_DCKCFGR_CK48MSEL */
ganlikun	0:13413ea9a877	3531	}
ganlikun	0:13413ea9a877	3532
ganlikun	0:13413ea9a877	3533	#if defined(RNG)
ganlikun	0:13413ea9a877	3534	/**
ganlikun	0:13413ea9a877	3535	* @brief Configure RNG clock source
ganlikun	0:13413ea9a877	3536	* @rmtoll DCKCFGR CK48MSEL LL_RCC_SetRNGClockSource\n
ganlikun	0:13413ea9a877	3537	* DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource
ganlikun	0:13413ea9a877	3538	* @param RNGxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3539	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
ganlikun	0:13413ea9a877	3540	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
ganlikun	0:13413ea9a877	3541	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
ganlikun	0:13413ea9a877	3542	*
ganlikun	0:13413ea9a877	3543	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	3544	* @retval None
ganlikun	0:13413ea9a877	3545	*/
ganlikun	0:13413ea9a877	3546	__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
ganlikun	0:13413ea9a877	3547	{
ganlikun	0:13413ea9a877	3548	#if defined(RCC_DCKCFGR_CK48MSEL)
ganlikun	0:13413ea9a877	3549	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource);
ganlikun	0:13413ea9a877	3550	#else
ganlikun	0:13413ea9a877	3551	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
ganlikun	0:13413ea9a877	3552	#endif /* RCC_DCKCFGR_CK48MSEL */
ganlikun	0:13413ea9a877	3553	}
ganlikun	0:13413ea9a877	3554	#endif /* RNG */
ganlikun	0:13413ea9a877	3555
ganlikun	0:13413ea9a877	3556	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
ganlikun	0:13413ea9a877	3557	/**
ganlikun	0:13413ea9a877	3558	* @brief Configure USB clock source
ganlikun	0:13413ea9a877	3559	* @rmtoll DCKCFGR CK48MSEL LL_RCC_SetUSBClockSource\n
ganlikun	0:13413ea9a877	3560	* DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource
ganlikun	0:13413ea9a877	3561	* @param USBxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3562	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
ganlikun	0:13413ea9a877	3563	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
ganlikun	0:13413ea9a877	3564	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
ganlikun	0:13413ea9a877	3565	*
ganlikun	0:13413ea9a877	3566	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	3567	* @retval None
ganlikun	0:13413ea9a877	3568	*/
ganlikun	0:13413ea9a877	3569	__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
ganlikun	0:13413ea9a877	3570	{
ganlikun	0:13413ea9a877	3571	#if defined(RCC_DCKCFGR_CK48MSEL)
ganlikun	0:13413ea9a877	3572	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource);
ganlikun	0:13413ea9a877	3573	#else
ganlikun	0:13413ea9a877	3574	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
ganlikun	0:13413ea9a877	3575	#endif /* RCC_DCKCFGR_CK48MSEL */
ganlikun	0:13413ea9a877	3576	}
ganlikun	0:13413ea9a877	3577	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
ganlikun	0:13413ea9a877	3578	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
ganlikun	0:13413ea9a877	3579
ganlikun	0:13413ea9a877	3580	#if defined(CEC)
ganlikun	0:13413ea9a877	3581	/**
ganlikun	0:13413ea9a877	3582	* @brief Configure CEC clock source
ganlikun	0:13413ea9a877	3583	* @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource
ganlikun	0:13413ea9a877	3584	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3585	* @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
ganlikun	0:13413ea9a877	3586	* @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
ganlikun	0:13413ea9a877	3587	* @retval None
ganlikun	0:13413ea9a877	3588	*/
ganlikun	0:13413ea9a877	3589	__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
ganlikun	0:13413ea9a877	3590	{
ganlikun	0:13413ea9a877	3591	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
ganlikun	0:13413ea9a877	3592	}
ganlikun	0:13413ea9a877	3593	#endif /* CEC */
ganlikun	0:13413ea9a877	3594
ganlikun	0:13413ea9a877	3595	/**
ganlikun	0:13413ea9a877	3596	* @brief Configure I2S clock source
ganlikun	0:13413ea9a877	3597	* @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource\n
ganlikun	0:13413ea9a877	3598	* DCKCFGR I2SSRC LL_RCC_SetI2SClockSource\n
ganlikun	0:13413ea9a877	3599	* DCKCFGR I2S1SRC LL_RCC_SetI2SClockSource\n
ganlikun	0:13413ea9a877	3600	* DCKCFGR I2S2SRC LL_RCC_SetI2SClockSource
ganlikun	0:13413ea9a877	3601	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3602	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
ganlikun	0:13413ea9a877	3603	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
ganlikun	0:13413ea9a877	3604	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
ganlikun	0:13413ea9a877	3605	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
ganlikun	0:13413ea9a877	3606	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
ganlikun	0:13413ea9a877	3607	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
ganlikun	0:13413ea9a877	3608	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
ganlikun	0:13413ea9a877	3609	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
ganlikun	0:13413ea9a877	3610	*
ganlikun	0:13413ea9a877	3611	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	3612	* @retval None
ganlikun	0:13413ea9a877	3613	*/
ganlikun	0:13413ea9a877	3614	__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
ganlikun	0:13413ea9a877	3615	{
ganlikun	0:13413ea9a877	3616	#if defined(RCC_CFGR_I2SSRC)
ganlikun	0:13413ea9a877	3617	MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
ganlikun	0:13413ea9a877	3618	#else
ganlikun	0:13413ea9a877	3619	MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U));
ganlikun	0:13413ea9a877	3620	#endif /* RCC_CFGR_I2SSRC */
ganlikun	0:13413ea9a877	3621	}
ganlikun	0:13413ea9a877	3622
ganlikun	0:13413ea9a877	3623	#if defined(DSI)
ganlikun	0:13413ea9a877	3624	/**
ganlikun	0:13413ea9a877	3625	* @brief Configure DSI clock source
ganlikun	0:13413ea9a877	3626	* @rmtoll DCKCFGR DSISEL LL_RCC_SetDSIClockSource
ganlikun	0:13413ea9a877	3627	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3628	* @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
ganlikun	0:13413ea9a877	3629	* @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
ganlikun	0:13413ea9a877	3630	* @retval None
ganlikun	0:13413ea9a877	3631	*/
ganlikun	0:13413ea9a877	3632	__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
ganlikun	0:13413ea9a877	3633	{
ganlikun	0:13413ea9a877	3634	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source);
ganlikun	0:13413ea9a877	3635	}
ganlikun	0:13413ea9a877	3636	#endif /* DSI */
ganlikun	0:13413ea9a877	3637
ganlikun	0:13413ea9a877	3638	#if defined(DFSDM1_Channel0)
ganlikun	0:13413ea9a877	3639	/**
ganlikun	0:13413ea9a877	3640	* @brief Configure DFSDM Audio clock source
ganlikun	0:13413ea9a877	3641	* @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_SetDFSDMAudioClockSource\n
ganlikun	0:13413ea9a877	3642	* DCKCFGR CKDFSDM2ASEL LL_RCC_SetDFSDMAudioClockSource
ganlikun	0:13413ea9a877	3643	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3644	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
ganlikun	0:13413ea9a877	3645	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
ganlikun	0:13413ea9a877	3646	* @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
ganlikun	0:13413ea9a877	3647	* @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
ganlikun	0:13413ea9a877	3648	*
ganlikun	0:13413ea9a877	3649	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	3650	* @retval None
ganlikun	0:13413ea9a877	3651	*/
ganlikun	0:13413ea9a877	3652	__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
ganlikun	0:13413ea9a877	3653	{
ganlikun	0:13413ea9a877	3654	MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U));
ganlikun	0:13413ea9a877	3655	}
ganlikun	0:13413ea9a877	3656
ganlikun	0:13413ea9a877	3657	/**
ganlikun	0:13413ea9a877	3658	* @brief Configure DFSDM Kernel clock source
ganlikun	0:13413ea9a877	3659	* @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_SetDFSDMClockSource
ganlikun	0:13413ea9a877	3660	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3661	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
ganlikun	0:13413ea9a877	3662	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
ganlikun	0:13413ea9a877	3663	* @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
ganlikun	0:13413ea9a877	3664	* @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
ganlikun	0:13413ea9a877	3665	*
ganlikun	0:13413ea9a877	3666	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	3667	* @retval None
ganlikun	0:13413ea9a877	3668	*/
ganlikun	0:13413ea9a877	3669	__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
ganlikun	0:13413ea9a877	3670	{
ganlikun	0:13413ea9a877	3671	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source);
ganlikun	0:13413ea9a877	3672	}
ganlikun	0:13413ea9a877	3673	#endif /* DFSDM1_Channel0 */
ganlikun	0:13413ea9a877	3674
ganlikun	0:13413ea9a877	3675	#if defined(SPDIFRX)
ganlikun	0:13413ea9a877	3676	/**
ganlikun	0:13413ea9a877	3677	* @brief Configure SPDIFRX clock source
ganlikun	0:13413ea9a877	3678	* @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_SetSPDIFRXClockSource
ganlikun	0:13413ea9a877	3679	* @param SPDIFRXxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3680	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
ganlikun	0:13413ea9a877	3681	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
ganlikun	0:13413ea9a877	3682	*
ganlikun	0:13413ea9a877	3683	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	3684	* @retval None
ganlikun	0:13413ea9a877	3685	*/
ganlikun	0:13413ea9a877	3686	__STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource)
ganlikun	0:13413ea9a877	3687	{
ganlikun	0:13413ea9a877	3688	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource);
ganlikun	0:13413ea9a877	3689	}
ganlikun	0:13413ea9a877	3690	#endif /* SPDIFRX */
ganlikun	0:13413ea9a877	3691
ganlikun	0:13413ea9a877	3692	#if defined(FMPI2C1)
ganlikun	0:13413ea9a877	3693	/**
ganlikun	0:13413ea9a877	3694	* @brief Get FMPI2C clock source
ganlikun	0:13413ea9a877	3695	* @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_GetFMPI2CClockSource
ganlikun	0:13413ea9a877	3696	* @param FMPI2Cx This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3697	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
ganlikun	0:13413ea9a877	3698	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	3699	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
ganlikun	0:13413ea9a877	3700	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
ganlikun	0:13413ea9a877	3701	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
ganlikun	0:13413ea9a877	3702	*/
ganlikun	0:13413ea9a877	3703	__STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx)
ganlikun	0:13413ea9a877	3704	{
ganlikun	0:13413ea9a877	3705	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx));
ganlikun	0:13413ea9a877	3706	}
ganlikun	0:13413ea9a877	3707	#endif /* FMPI2C1 */
ganlikun	0:13413ea9a877	3708
ganlikun	0:13413ea9a877	3709	#if defined(LPTIM1)
ganlikun	0:13413ea9a877	3710	/**
ganlikun	0:13413ea9a877	3711	* @brief Get LPTIMx clock source
ganlikun	0:13413ea9a877	3712	* @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource
ganlikun	0:13413ea9a877	3713	* @param LPTIMx This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3714	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
ganlikun	0:13413ea9a877	3715	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	3716	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
ganlikun	0:13413ea9a877	3717	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
ganlikun	0:13413ea9a877	3718	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
ganlikun	0:13413ea9a877	3719	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
ganlikun	0:13413ea9a877	3720	*/
ganlikun	0:13413ea9a877	3721	__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
ganlikun	0:13413ea9a877	3722	{
ganlikun	0:13413ea9a877	3723	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
ganlikun	0:13413ea9a877	3724	}
ganlikun	0:13413ea9a877	3725	#endif /* LPTIM1 */
ganlikun	0:13413ea9a877	3726
ganlikun	0:13413ea9a877	3727	#if defined(SAI1)
ganlikun	0:13413ea9a877	3728	/**
ganlikun	0:13413ea9a877	3729	* @brief Get SAIx clock source
ganlikun	0:13413ea9a877	3730	* @rmtoll DCKCFGR SAI1SEL LL_RCC_GetSAIClockSource\n
ganlikun	0:13413ea9a877	3731	* DCKCFGR SAI2SEL LL_RCC_GetSAIClockSource\n
ganlikun	0:13413ea9a877	3732	* DCKCFGR SAI1ASRC LL_RCC_GetSAIClockSource\n
ganlikun	0:13413ea9a877	3733	* DCKCFGR SAI1BSRC LL_RCC_GetSAIClockSource
ganlikun	0:13413ea9a877	3734	* @param SAIx This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3735	* @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
ganlikun	0:13413ea9a877	3736	* @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
ganlikun	0:13413ea9a877	3737	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
ganlikun	0:13413ea9a877	3738	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
ganlikun	0:13413ea9a877	3739	*
ganlikun	0:13413ea9a877	3740	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	3741	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	3742	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
ganlikun	0:13413ea9a877	3743	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
ganlikun	0:13413ea9a877	3744	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
ganlikun	0:13413ea9a877	3745	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
ganlikun	0:13413ea9a877	3746	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
ganlikun	0:13413ea9a877	3747	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
ganlikun	0:13413ea9a877	3748	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
ganlikun	0:13413ea9a877	3749	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
ganlikun	0:13413ea9a877	3750	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
ganlikun	0:13413ea9a877	3751	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
ganlikun	0:13413ea9a877	3752	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
ganlikun	0:13413ea9a877	3753	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
ganlikun	0:13413ea9a877	3754	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
ganlikun	0:13413ea9a877	3755	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
ganlikun	0:13413ea9a877	3756	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
ganlikun	0:13413ea9a877	3757	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
ganlikun	0:13413ea9a877	3758	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*)
ganlikun	0:13413ea9a877	3759	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
ganlikun	0:13413ea9a877	3760	*
ganlikun	0:13413ea9a877	3761	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	3762	*/
ganlikun	0:13413ea9a877	3763	__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
ganlikun	0:13413ea9a877	3764	{
ganlikun	0:13413ea9a877	3765	return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U \| SAIx);
ganlikun	0:13413ea9a877	3766	}
ganlikun	0:13413ea9a877	3767	#endif /* SAI1 */
ganlikun	0:13413ea9a877	3768
ganlikun	0:13413ea9a877	3769	#if defined(RCC_DCKCFGR_SDIOSEL) \|\| defined(RCC_DCKCFGR2_SDIOSEL)
ganlikun	0:13413ea9a877	3770	/**
ganlikun	0:13413ea9a877	3771	* @brief Get SDIOx clock source
ganlikun	0:13413ea9a877	3772	* @rmtoll DCKCFGR SDIOSEL LL_RCC_GetSDIOClockSource\n
ganlikun	0:13413ea9a877	3773	* DCKCFGR2 SDIOSEL LL_RCC_GetSDIOClockSource
ganlikun	0:13413ea9a877	3774	* @param SDIOx This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3775	* @arg @ref LL_RCC_SDIO_CLKSOURCE
ganlikun	0:13413ea9a877	3776	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	3777	* @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
ganlikun	0:13413ea9a877	3778	* @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
ganlikun	0:13413ea9a877	3779	*/
ganlikun	0:13413ea9a877	3780	__STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx)
ganlikun	0:13413ea9a877	3781	{
ganlikun	0:13413ea9a877	3782	#if defined(RCC_DCKCFGR_SDIOSEL)
ganlikun	0:13413ea9a877	3783	return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx));
ganlikun	0:13413ea9a877	3784	#else
ganlikun	0:13413ea9a877	3785	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx));
ganlikun	0:13413ea9a877	3786	#endif /* RCC_DCKCFGR_SDIOSEL */
ganlikun	0:13413ea9a877	3787	}
ganlikun	0:13413ea9a877	3788	#endif /* RCC_DCKCFGR_SDIOSEL \|\| RCC_DCKCFGR2_SDIOSEL */
ganlikun	0:13413ea9a877	3789
ganlikun	0:13413ea9a877	3790	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
ganlikun	0:13413ea9a877	3791	/**
ganlikun	0:13413ea9a877	3792	* @brief Get 48Mhz domain clock source
ganlikun	0:13413ea9a877	3793	* @rmtoll DCKCFGR CK48MSEL LL_RCC_GetCK48MClockSource\n
ganlikun	0:13413ea9a877	3794	* DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource
ganlikun	0:13413ea9a877	3795	* @param CK48Mx This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3796	* @arg @ref LL_RCC_CK48M_CLKSOURCE
ganlikun	0:13413ea9a877	3797	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	3798	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
ganlikun	0:13413ea9a877	3799	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
ganlikun	0:13413ea9a877	3800	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
ganlikun	0:13413ea9a877	3801	*
ganlikun	0:13413ea9a877	3802	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	3803	*/
ganlikun	0:13413ea9a877	3804	__STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
ganlikun	0:13413ea9a877	3805	{
ganlikun	0:13413ea9a877	3806	#if defined(RCC_DCKCFGR_CK48MSEL)
ganlikun	0:13413ea9a877	3807	return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx));
ganlikun	0:13413ea9a877	3808	#else
ganlikun	0:13413ea9a877	3809	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
ganlikun	0:13413ea9a877	3810	#endif /* RCC_DCKCFGR_CK48MSEL */
ganlikun	0:13413ea9a877	3811	}
ganlikun	0:13413ea9a877	3812
ganlikun	0:13413ea9a877	3813	#if defined(RNG)
ganlikun	0:13413ea9a877	3814	/**
ganlikun	0:13413ea9a877	3815	* @brief Get RNGx clock source
ganlikun	0:13413ea9a877	3816	* @rmtoll DCKCFGR CK48MSEL LL_RCC_GetRNGClockSource\n
ganlikun	0:13413ea9a877	3817	* DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource
ganlikun	0:13413ea9a877	3818	* @param RNGx This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3819	* @arg @ref LL_RCC_RNG_CLKSOURCE
ganlikun	0:13413ea9a877	3820	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	3821	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
ganlikun	0:13413ea9a877	3822	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
ganlikun	0:13413ea9a877	3823	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
ganlikun	0:13413ea9a877	3824	*
ganlikun	0:13413ea9a877	3825	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	3826	*/
ganlikun	0:13413ea9a877	3827	__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
ganlikun	0:13413ea9a877	3828	{
ganlikun	0:13413ea9a877	3829	#if defined(RCC_DCKCFGR_CK48MSEL)
ganlikun	0:13413ea9a877	3830	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx));
ganlikun	0:13413ea9a877	3831	#else
ganlikun	0:13413ea9a877	3832	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
ganlikun	0:13413ea9a877	3833	#endif /* RCC_DCKCFGR_CK48MSEL */
ganlikun	0:13413ea9a877	3834	}
ganlikun	0:13413ea9a877	3835	#endif /* RNG */
ganlikun	0:13413ea9a877	3836
ganlikun	0:13413ea9a877	3837	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
ganlikun	0:13413ea9a877	3838	/**
ganlikun	0:13413ea9a877	3839	* @brief Get USBx clock source
ganlikun	0:13413ea9a877	3840	* @rmtoll DCKCFGR CK48MSEL LL_RCC_GetUSBClockSource\n
ganlikun	0:13413ea9a877	3841	* DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource
ganlikun	0:13413ea9a877	3842	* @param USBx This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3843	* @arg @ref LL_RCC_USB_CLKSOURCE
ganlikun	0:13413ea9a877	3844	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	3845	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
ganlikun	0:13413ea9a877	3846	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
ganlikun	0:13413ea9a877	3847	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
ganlikun	0:13413ea9a877	3848	*
ganlikun	0:13413ea9a877	3849	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	3850	*/
ganlikun	0:13413ea9a877	3851	__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
ganlikun	0:13413ea9a877	3852	{
ganlikun	0:13413ea9a877	3853	#if defined(RCC_DCKCFGR_CK48MSEL)
ganlikun	0:13413ea9a877	3854	return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx));
ganlikun	0:13413ea9a877	3855	#else
ganlikun	0:13413ea9a877	3856	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
ganlikun	0:13413ea9a877	3857	#endif /* RCC_DCKCFGR_CK48MSEL */
ganlikun	0:13413ea9a877	3858	}
ganlikun	0:13413ea9a877	3859	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
ganlikun	0:13413ea9a877	3860	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
ganlikun	0:13413ea9a877	3861
ganlikun	0:13413ea9a877	3862	#if defined(CEC)
ganlikun	0:13413ea9a877	3863	/**
ganlikun	0:13413ea9a877	3864	* @brief Get CEC Clock Source
ganlikun	0:13413ea9a877	3865	* @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource
ganlikun	0:13413ea9a877	3866	* @param CECx This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3867	* @arg @ref LL_RCC_CEC_CLKSOURCE
ganlikun	0:13413ea9a877	3868	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	3869	* @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
ganlikun	0:13413ea9a877	3870	* @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
ganlikun	0:13413ea9a877	3871	*/
ganlikun	0:13413ea9a877	3872	__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
ganlikun	0:13413ea9a877	3873	{
ganlikun	0:13413ea9a877	3874	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
ganlikun	0:13413ea9a877	3875	}
ganlikun	0:13413ea9a877	3876	#endif /* CEC */
ganlikun	0:13413ea9a877	3877
ganlikun	0:13413ea9a877	3878	/**
ganlikun	0:13413ea9a877	3879	* @brief Get I2S Clock Source
ganlikun	0:13413ea9a877	3880	* @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource\n
ganlikun	0:13413ea9a877	3881	* DCKCFGR I2SSRC LL_RCC_GetI2SClockSource\n
ganlikun	0:13413ea9a877	3882	* DCKCFGR I2S1SRC LL_RCC_GetI2SClockSource\n
ganlikun	0:13413ea9a877	3883	* DCKCFGR I2S2SRC LL_RCC_GetI2SClockSource
ganlikun	0:13413ea9a877	3884	* @param I2Sx This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3885	* @arg @ref LL_RCC_I2S1_CLKSOURCE
ganlikun	0:13413ea9a877	3886	* @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
ganlikun	0:13413ea9a877	3887	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	3888	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
ganlikun	0:13413ea9a877	3889	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
ganlikun	0:13413ea9a877	3890	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
ganlikun	0:13413ea9a877	3891	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
ganlikun	0:13413ea9a877	3892	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
ganlikun	0:13413ea9a877	3893	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
ganlikun	0:13413ea9a877	3894	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
ganlikun	0:13413ea9a877	3895	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
ganlikun	0:13413ea9a877	3896	*
ganlikun	0:13413ea9a877	3897	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	3898	*/
ganlikun	0:13413ea9a877	3899	__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
ganlikun	0:13413ea9a877	3900	{
ganlikun	0:13413ea9a877	3901	#if defined(RCC_CFGR_I2SSRC)
ganlikun	0:13413ea9a877	3902	return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
ganlikun	0:13413ea9a877	3903	#else
ganlikun	0:13413ea9a877	3904	return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U \| I2Sx);
ganlikun	0:13413ea9a877	3905	#endif /* RCC_CFGR_I2SSRC */
ganlikun	0:13413ea9a877	3906	}
ganlikun	0:13413ea9a877	3907
ganlikun	0:13413ea9a877	3908	#if defined(DFSDM1_Channel0)
ganlikun	0:13413ea9a877	3909	/**
ganlikun	0:13413ea9a877	3910	* @brief Get DFSDM Audio Clock Source
ganlikun	0:13413ea9a877	3911	* @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_GetDFSDMAudioClockSource\n
ganlikun	0:13413ea9a877	3912	* DCKCFGR CKDFSDM2ASEL LL_RCC_GetDFSDMAudioClockSource
ganlikun	0:13413ea9a877	3913	* @param DFSDMx This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3914	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
ganlikun	0:13413ea9a877	3915	* @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
ganlikun	0:13413ea9a877	3916	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	3917	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
ganlikun	0:13413ea9a877	3918	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
ganlikun	0:13413ea9a877	3919	* @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
ganlikun	0:13413ea9a877	3920	* @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
ganlikun	0:13413ea9a877	3921	*
ganlikun	0:13413ea9a877	3922	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	3923	*/
ganlikun	0:13413ea9a877	3924	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
ganlikun	0:13413ea9a877	3925	{
ganlikun	0:13413ea9a877	3926	return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U \| DFSDMx);
ganlikun	0:13413ea9a877	3927	}
ganlikun	0:13413ea9a877	3928
ganlikun	0:13413ea9a877	3929	/**
ganlikun	0:13413ea9a877	3930	* @brief Get DFSDM Audio Clock Source
ganlikun	0:13413ea9a877	3931	* @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_GetDFSDMClockSource
ganlikun	0:13413ea9a877	3932	* @param DFSDMx This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3933	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE
ganlikun	0:13413ea9a877	3934	* @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
ganlikun	0:13413ea9a877	3935	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	3936	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
ganlikun	0:13413ea9a877	3937	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
ganlikun	0:13413ea9a877	3938	* @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
ganlikun	0:13413ea9a877	3939	* @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
ganlikun	0:13413ea9a877	3940	*
ganlikun	0:13413ea9a877	3941	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	3942	*/
ganlikun	0:13413ea9a877	3943	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
ganlikun	0:13413ea9a877	3944	{
ganlikun	0:13413ea9a877	3945	return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx));
ganlikun	0:13413ea9a877	3946	}
ganlikun	0:13413ea9a877	3947	#endif /* DFSDM1_Channel0 */
ganlikun	0:13413ea9a877	3948
ganlikun	0:13413ea9a877	3949	#if defined(SPDIFRX)
ganlikun	0:13413ea9a877	3950	/**
ganlikun	0:13413ea9a877	3951	* @brief Get SPDIFRX clock source
ganlikun	0:13413ea9a877	3952	* @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_GetSPDIFRXClockSource
ganlikun	0:13413ea9a877	3953	* @param SPDIFRXx This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3954	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
ganlikun	0:13413ea9a877	3955	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	3956	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
ganlikun	0:13413ea9a877	3957	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
ganlikun	0:13413ea9a877	3958	*
ganlikun	0:13413ea9a877	3959	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	3960	*/
ganlikun	0:13413ea9a877	3961	__STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx)
ganlikun	0:13413ea9a877	3962	{
ganlikun	0:13413ea9a877	3963	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx));
ganlikun	0:13413ea9a877	3964	}
ganlikun	0:13413ea9a877	3965	#endif /* SPDIFRX */
ganlikun	0:13413ea9a877	3966
ganlikun	0:13413ea9a877	3967	#if defined(DSI)
ganlikun	0:13413ea9a877	3968	/**
ganlikun	0:13413ea9a877	3969	* @brief Get DSI Clock Source
ganlikun	0:13413ea9a877	3970	* @rmtoll DCKCFGR DSISEL LL_RCC_GetDSIClockSource
ganlikun	0:13413ea9a877	3971	* @param DSIx This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3972	* @arg @ref LL_RCC_DSI_CLKSOURCE
ganlikun	0:13413ea9a877	3973	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	3974	* @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
ganlikun	0:13413ea9a877	3975	* @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
ganlikun	0:13413ea9a877	3976	*/
ganlikun	0:13413ea9a877	3977	__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
ganlikun	0:13413ea9a877	3978	{
ganlikun	0:13413ea9a877	3979	return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx));
ganlikun	0:13413ea9a877	3980	}
ganlikun	0:13413ea9a877	3981	#endif /* DSI */
ganlikun	0:13413ea9a877	3982
ganlikun	0:13413ea9a877	3983	/**
ganlikun	0:13413ea9a877	3984	* @}
ganlikun	0:13413ea9a877	3985	*/
ganlikun	0:13413ea9a877	3986
ganlikun	0:13413ea9a877	3987	/** @defgroup RCC_LL_EF_RTC RTC
ganlikun	0:13413ea9a877	3988	* @{
ganlikun	0:13413ea9a877	3989	*/
ganlikun	0:13413ea9a877	3990
ganlikun	0:13413ea9a877	3991	/**
ganlikun	0:13413ea9a877	3992	* @brief Set RTC Clock Source
ganlikun	0:13413ea9a877	3993	* @note Once the RTC clock source has been selected, it cannot be changed anymore unless
ganlikun	0:13413ea9a877	3994	* the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
ganlikun	0:13413ea9a877	3995	* set). The BDRST bit can be used to reset them.
ganlikun	0:13413ea9a877	3996	* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
ganlikun	0:13413ea9a877	3997	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	3998	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
ganlikun	0:13413ea9a877	3999	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
ganlikun	0:13413ea9a877	4000	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
ganlikun	0:13413ea9a877	4001	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
ganlikun	0:13413ea9a877	4002	* @retval None
ganlikun	0:13413ea9a877	4003	*/
ganlikun	0:13413ea9a877	4004	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
ganlikun	0:13413ea9a877	4005	{
ganlikun	0:13413ea9a877	4006	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
ganlikun	0:13413ea9a877	4007	}
ganlikun	0:13413ea9a877	4008
ganlikun	0:13413ea9a877	4009	/**
ganlikun	0:13413ea9a877	4010	* @brief Get RTC Clock Source
ganlikun	0:13413ea9a877	4011	* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
ganlikun	0:13413ea9a877	4012	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	4013	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
ganlikun	0:13413ea9a877	4014	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
ganlikun	0:13413ea9a877	4015	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
ganlikun	0:13413ea9a877	4016	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
ganlikun	0:13413ea9a877	4017	*/
ganlikun	0:13413ea9a877	4018	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
ganlikun	0:13413ea9a877	4019	{
ganlikun	0:13413ea9a877	4020	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
ganlikun	0:13413ea9a877	4021	}
ganlikun	0:13413ea9a877	4022
ganlikun	0:13413ea9a877	4023	/**
ganlikun	0:13413ea9a877	4024	* @brief Enable RTC
ganlikun	0:13413ea9a877	4025	* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
ganlikun	0:13413ea9a877	4026	* @retval None
ganlikun	0:13413ea9a877	4027	*/
ganlikun	0:13413ea9a877	4028	__STATIC_INLINE void LL_RCC_EnableRTC(void)
ganlikun	0:13413ea9a877	4029	{
ganlikun	0:13413ea9a877	4030	SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
ganlikun	0:13413ea9a877	4031	}
ganlikun	0:13413ea9a877	4032
ganlikun	0:13413ea9a877	4033	/**
ganlikun	0:13413ea9a877	4034	* @brief Disable RTC
ganlikun	0:13413ea9a877	4035	* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
ganlikun	0:13413ea9a877	4036	* @retval None
ganlikun	0:13413ea9a877	4037	*/
ganlikun	0:13413ea9a877	4038	__STATIC_INLINE void LL_RCC_DisableRTC(void)
ganlikun	0:13413ea9a877	4039	{
ganlikun	0:13413ea9a877	4040	CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
ganlikun	0:13413ea9a877	4041	}
ganlikun	0:13413ea9a877	4042
ganlikun	0:13413ea9a877	4043	/**
ganlikun	0:13413ea9a877	4044	* @brief Check if RTC has been enabled or not
ganlikun	0:13413ea9a877	4045	* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
ganlikun	0:13413ea9a877	4046	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	4047	*/
ganlikun	0:13413ea9a877	4048	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
ganlikun	0:13413ea9a877	4049	{
ganlikun	0:13413ea9a877	4050	return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
ganlikun	0:13413ea9a877	4051	}
ganlikun	0:13413ea9a877	4052
ganlikun	0:13413ea9a877	4053	/**
ganlikun	0:13413ea9a877	4054	* @brief Force the Backup domain reset
ganlikun	0:13413ea9a877	4055	* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
ganlikun	0:13413ea9a877	4056	* @retval None
ganlikun	0:13413ea9a877	4057	*/
ganlikun	0:13413ea9a877	4058	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
ganlikun	0:13413ea9a877	4059	{
ganlikun	0:13413ea9a877	4060	SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
ganlikun	0:13413ea9a877	4061	}
ganlikun	0:13413ea9a877	4062
ganlikun	0:13413ea9a877	4063	/**
ganlikun	0:13413ea9a877	4064	* @brief Release the Backup domain reset
ganlikun	0:13413ea9a877	4065	* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
ganlikun	0:13413ea9a877	4066	* @retval None
ganlikun	0:13413ea9a877	4067	*/
ganlikun	0:13413ea9a877	4068	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
ganlikun	0:13413ea9a877	4069	{
ganlikun	0:13413ea9a877	4070	CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
ganlikun	0:13413ea9a877	4071	}
ganlikun	0:13413ea9a877	4072
ganlikun	0:13413ea9a877	4073	/**
ganlikun	0:13413ea9a877	4074	* @brief Set HSE Prescalers for RTC Clock
ganlikun	0:13413ea9a877	4075	* @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
ganlikun	0:13413ea9a877	4076	* @param Prescaler This parameter can be one of the following values:
ganlikun	0:13413ea9a877	4077	* @arg @ref LL_RCC_RTC_NOCLOCK
ganlikun	0:13413ea9a877	4078	* @arg @ref LL_RCC_RTC_HSE_DIV_2
ganlikun	0:13413ea9a877	4079	* @arg @ref LL_RCC_RTC_HSE_DIV_3
ganlikun	0:13413ea9a877	4080	* @arg @ref LL_RCC_RTC_HSE_DIV_4
ganlikun	0:13413ea9a877	4081	* @arg @ref LL_RCC_RTC_HSE_DIV_5
ganlikun	0:13413ea9a877	4082	* @arg @ref LL_RCC_RTC_HSE_DIV_6
ganlikun	0:13413ea9a877	4083	* @arg @ref LL_RCC_RTC_HSE_DIV_7
ganlikun	0:13413ea9a877	4084	* @arg @ref LL_RCC_RTC_HSE_DIV_8
ganlikun	0:13413ea9a877	4085	* @arg @ref LL_RCC_RTC_HSE_DIV_9
ganlikun	0:13413ea9a877	4086	* @arg @ref LL_RCC_RTC_HSE_DIV_10
ganlikun	0:13413ea9a877	4087	* @arg @ref LL_RCC_RTC_HSE_DIV_11
ganlikun	0:13413ea9a877	4088	* @arg @ref LL_RCC_RTC_HSE_DIV_12
ganlikun	0:13413ea9a877	4089	* @arg @ref LL_RCC_RTC_HSE_DIV_13
ganlikun	0:13413ea9a877	4090	* @arg @ref LL_RCC_RTC_HSE_DIV_14
ganlikun	0:13413ea9a877	4091	* @arg @ref LL_RCC_RTC_HSE_DIV_15
ganlikun	0:13413ea9a877	4092	* @arg @ref LL_RCC_RTC_HSE_DIV_16
ganlikun	0:13413ea9a877	4093	* @arg @ref LL_RCC_RTC_HSE_DIV_17
ganlikun	0:13413ea9a877	4094	* @arg @ref LL_RCC_RTC_HSE_DIV_18
ganlikun	0:13413ea9a877	4095	* @arg @ref LL_RCC_RTC_HSE_DIV_19
ganlikun	0:13413ea9a877	4096	* @arg @ref LL_RCC_RTC_HSE_DIV_20
ganlikun	0:13413ea9a877	4097	* @arg @ref LL_RCC_RTC_HSE_DIV_21
ganlikun	0:13413ea9a877	4098	* @arg @ref LL_RCC_RTC_HSE_DIV_22
ganlikun	0:13413ea9a877	4099	* @arg @ref LL_RCC_RTC_HSE_DIV_23
ganlikun	0:13413ea9a877	4100	* @arg @ref LL_RCC_RTC_HSE_DIV_24
ganlikun	0:13413ea9a877	4101	* @arg @ref LL_RCC_RTC_HSE_DIV_25
ganlikun	0:13413ea9a877	4102	* @arg @ref LL_RCC_RTC_HSE_DIV_26
ganlikun	0:13413ea9a877	4103	* @arg @ref LL_RCC_RTC_HSE_DIV_27
ganlikun	0:13413ea9a877	4104	* @arg @ref LL_RCC_RTC_HSE_DIV_28
ganlikun	0:13413ea9a877	4105	* @arg @ref LL_RCC_RTC_HSE_DIV_29
ganlikun	0:13413ea9a877	4106	* @arg @ref LL_RCC_RTC_HSE_DIV_30
ganlikun	0:13413ea9a877	4107	* @arg @ref LL_RCC_RTC_HSE_DIV_31
ganlikun	0:13413ea9a877	4108	* @retval None
ganlikun	0:13413ea9a877	4109	*/
ganlikun	0:13413ea9a877	4110	__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
ganlikun	0:13413ea9a877	4111	{
ganlikun	0:13413ea9a877	4112	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
ganlikun	0:13413ea9a877	4113	}
ganlikun	0:13413ea9a877	4114
ganlikun	0:13413ea9a877	4115	/**
ganlikun	0:13413ea9a877	4116	* @brief Get HSE Prescalers for RTC Clock
ganlikun	0:13413ea9a877	4117	* @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
ganlikun	0:13413ea9a877	4118	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	4119	* @arg @ref LL_RCC_RTC_NOCLOCK
ganlikun	0:13413ea9a877	4120	* @arg @ref LL_RCC_RTC_HSE_DIV_2
ganlikun	0:13413ea9a877	4121	* @arg @ref LL_RCC_RTC_HSE_DIV_3
ganlikun	0:13413ea9a877	4122	* @arg @ref LL_RCC_RTC_HSE_DIV_4
ganlikun	0:13413ea9a877	4123	* @arg @ref LL_RCC_RTC_HSE_DIV_5
ganlikun	0:13413ea9a877	4124	* @arg @ref LL_RCC_RTC_HSE_DIV_6
ganlikun	0:13413ea9a877	4125	* @arg @ref LL_RCC_RTC_HSE_DIV_7
ganlikun	0:13413ea9a877	4126	* @arg @ref LL_RCC_RTC_HSE_DIV_8
ganlikun	0:13413ea9a877	4127	* @arg @ref LL_RCC_RTC_HSE_DIV_9
ganlikun	0:13413ea9a877	4128	* @arg @ref LL_RCC_RTC_HSE_DIV_10
ganlikun	0:13413ea9a877	4129	* @arg @ref LL_RCC_RTC_HSE_DIV_11
ganlikun	0:13413ea9a877	4130	* @arg @ref LL_RCC_RTC_HSE_DIV_12
ganlikun	0:13413ea9a877	4131	* @arg @ref LL_RCC_RTC_HSE_DIV_13
ganlikun	0:13413ea9a877	4132	* @arg @ref LL_RCC_RTC_HSE_DIV_14
ganlikun	0:13413ea9a877	4133	* @arg @ref LL_RCC_RTC_HSE_DIV_15
ganlikun	0:13413ea9a877	4134	* @arg @ref LL_RCC_RTC_HSE_DIV_16
ganlikun	0:13413ea9a877	4135	* @arg @ref LL_RCC_RTC_HSE_DIV_17
ganlikun	0:13413ea9a877	4136	* @arg @ref LL_RCC_RTC_HSE_DIV_18
ganlikun	0:13413ea9a877	4137	* @arg @ref LL_RCC_RTC_HSE_DIV_19
ganlikun	0:13413ea9a877	4138	* @arg @ref LL_RCC_RTC_HSE_DIV_20
ganlikun	0:13413ea9a877	4139	* @arg @ref LL_RCC_RTC_HSE_DIV_21
ganlikun	0:13413ea9a877	4140	* @arg @ref LL_RCC_RTC_HSE_DIV_22
ganlikun	0:13413ea9a877	4141	* @arg @ref LL_RCC_RTC_HSE_DIV_23
ganlikun	0:13413ea9a877	4142	* @arg @ref LL_RCC_RTC_HSE_DIV_24
ganlikun	0:13413ea9a877	4143	* @arg @ref LL_RCC_RTC_HSE_DIV_25
ganlikun	0:13413ea9a877	4144	* @arg @ref LL_RCC_RTC_HSE_DIV_26
ganlikun	0:13413ea9a877	4145	* @arg @ref LL_RCC_RTC_HSE_DIV_27
ganlikun	0:13413ea9a877	4146	* @arg @ref LL_RCC_RTC_HSE_DIV_28
ganlikun	0:13413ea9a877	4147	* @arg @ref LL_RCC_RTC_HSE_DIV_29
ganlikun	0:13413ea9a877	4148	* @arg @ref LL_RCC_RTC_HSE_DIV_30
ganlikun	0:13413ea9a877	4149	* @arg @ref LL_RCC_RTC_HSE_DIV_31
ganlikun	0:13413ea9a877	4150	*/
ganlikun	0:13413ea9a877	4151	__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
ganlikun	0:13413ea9a877	4152	{
ganlikun	0:13413ea9a877	4153	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
ganlikun	0:13413ea9a877	4154	}
ganlikun	0:13413ea9a877	4155
ganlikun	0:13413ea9a877	4156	/**
ganlikun	0:13413ea9a877	4157	* @}
ganlikun	0:13413ea9a877	4158	*/
ganlikun	0:13413ea9a877	4159
ganlikun	0:13413ea9a877	4160	#if defined(RCC_DCKCFGR_TIMPRE)
ganlikun	0:13413ea9a877	4161	/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
ganlikun	0:13413ea9a877	4162	* @{
ganlikun	0:13413ea9a877	4163	*/
ganlikun	0:13413ea9a877	4164
ganlikun	0:13413ea9a877	4165	/**
ganlikun	0:13413ea9a877	4166	* @brief Set Timers Clock Prescalers
ganlikun	0:13413ea9a877	4167	* @rmtoll DCKCFGR TIMPRE LL_RCC_SetTIMPrescaler
ganlikun	0:13413ea9a877	4168	* @param Prescaler This parameter can be one of the following values:
ganlikun	0:13413ea9a877	4169	* @arg @ref LL_RCC_TIM_PRESCALER_TWICE
ganlikun	0:13413ea9a877	4170	* @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
ganlikun	0:13413ea9a877	4171	* @retval None
ganlikun	0:13413ea9a877	4172	*/
ganlikun	0:13413ea9a877	4173	__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
ganlikun	0:13413ea9a877	4174	{
ganlikun	0:13413ea9a877	4175	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler);
ganlikun	0:13413ea9a877	4176	}
ganlikun	0:13413ea9a877	4177
ganlikun	0:13413ea9a877	4178	/**
ganlikun	0:13413ea9a877	4179	* @brief Get Timers Clock Prescalers
ganlikun	0:13413ea9a877	4180	* @rmtoll DCKCFGR TIMPRE LL_RCC_GetTIMPrescaler
ganlikun	0:13413ea9a877	4181	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	4182	* @arg @ref LL_RCC_TIM_PRESCALER_TWICE
ganlikun	0:13413ea9a877	4183	* @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
ganlikun	0:13413ea9a877	4184	*/
ganlikun	0:13413ea9a877	4185	__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
ganlikun	0:13413ea9a877	4186	{
ganlikun	0:13413ea9a877	4187	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE));
ganlikun	0:13413ea9a877	4188	}
ganlikun	0:13413ea9a877	4189
ganlikun	0:13413ea9a877	4190	/**
ganlikun	0:13413ea9a877	4191	* @}
ganlikun	0:13413ea9a877	4192	*/
ganlikun	0:13413ea9a877	4193	#endif /* RCC_DCKCFGR_TIMPRE */
ganlikun	0:13413ea9a877	4194
ganlikun	0:13413ea9a877	4195	/** @defgroup RCC_LL_EF_PLL PLL
ganlikun	0:13413ea9a877	4196	* @{
ganlikun	0:13413ea9a877	4197	*/
ganlikun	0:13413ea9a877	4198
ganlikun	0:13413ea9a877	4199	/**
ganlikun	0:13413ea9a877	4200	* @brief Enable PLL
ganlikun	0:13413ea9a877	4201	* @rmtoll CR PLLON LL_RCC_PLL_Enable
ganlikun	0:13413ea9a877	4202	* @retval None
ganlikun	0:13413ea9a877	4203	*/
ganlikun	0:13413ea9a877	4204	__STATIC_INLINE void LL_RCC_PLL_Enable(void)
ganlikun	0:13413ea9a877	4205	{
ganlikun	0:13413ea9a877	4206	SET_BIT(RCC->CR, RCC_CR_PLLON);
ganlikun	0:13413ea9a877	4207	}
ganlikun	0:13413ea9a877	4208
ganlikun	0:13413ea9a877	4209	/**
ganlikun	0:13413ea9a877	4210	* @brief Disable PLL
ganlikun	0:13413ea9a877	4211	* @note Cannot be disabled if the PLL clock is used as the system clock
ganlikun	0:13413ea9a877	4212	* @rmtoll CR PLLON LL_RCC_PLL_Disable
ganlikun	0:13413ea9a877	4213	* @retval None
ganlikun	0:13413ea9a877	4214	*/
ganlikun	0:13413ea9a877	4215	__STATIC_INLINE void LL_RCC_PLL_Disable(void)
ganlikun	0:13413ea9a877	4216	{
ganlikun	0:13413ea9a877	4217	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
ganlikun	0:13413ea9a877	4218	}
ganlikun	0:13413ea9a877	4219
ganlikun	0:13413ea9a877	4220	/**
ganlikun	0:13413ea9a877	4221	* @brief Check if PLL Ready
ganlikun	0:13413ea9a877	4222	* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
ganlikun	0:13413ea9a877	4223	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	4224	*/
ganlikun	0:13413ea9a877	4225	__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
ganlikun	0:13413ea9a877	4226	{
ganlikun	0:13413ea9a877	4227	return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
ganlikun	0:13413ea9a877	4228	}
ganlikun	0:13413ea9a877	4229
ganlikun	0:13413ea9a877	4230	/**
ganlikun	0:13413ea9a877	4231	* @brief Configure PLL used for SYSCLK Domain
ganlikun	0:13413ea9a877	4232	* @note PLL Source and PLLM Divider can be written only when PLL,
ganlikun	0:13413ea9a877	4233	* PLLI2S and PLLSAI(*) are disabled
ganlikun	0:13413ea9a877	4234	* @note PLLN/PLLP can be written only when PLL is disabled
ganlikun	0:13413ea9a877	4235	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
ganlikun	0:13413ea9a877	4236	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
ganlikun	0:13413ea9a877	4237	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
ganlikun	0:13413ea9a877	4238	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS\n
ganlikun	0:13413ea9a877	4239	* PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS
ganlikun	0:13413ea9a877	4240	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	4241	* @arg @ref LL_RCC_PLLSOURCE_HSI
ganlikun	0:13413ea9a877	4242	* @arg @ref LL_RCC_PLLSOURCE_HSE
ganlikun	0:13413ea9a877	4243	* @param PLLM This parameter can be one of the following values:
ganlikun	0:13413ea9a877	4244	* @arg @ref LL_RCC_PLLM_DIV_2
ganlikun	0:13413ea9a877	4245	* @arg @ref LL_RCC_PLLM_DIV_3
ganlikun	0:13413ea9a877	4246	* @arg @ref LL_RCC_PLLM_DIV_4
ganlikun	0:13413ea9a877	4247	* @arg @ref LL_RCC_PLLM_DIV_5
ganlikun	0:13413ea9a877	4248	* @arg @ref LL_RCC_PLLM_DIV_6
ganlikun	0:13413ea9a877	4249	* @arg @ref LL_RCC_PLLM_DIV_7
ganlikun	0:13413ea9a877	4250	* @arg @ref LL_RCC_PLLM_DIV_8
ganlikun	0:13413ea9a877	4251	* @arg @ref LL_RCC_PLLM_DIV_9
ganlikun	0:13413ea9a877	4252	* @arg @ref LL_RCC_PLLM_DIV_10
ganlikun	0:13413ea9a877	4253	* @arg @ref LL_RCC_PLLM_DIV_11
ganlikun	0:13413ea9a877	4254	* @arg @ref LL_RCC_PLLM_DIV_12
ganlikun	0:13413ea9a877	4255	* @arg @ref LL_RCC_PLLM_DIV_13
ganlikun	0:13413ea9a877	4256	* @arg @ref LL_RCC_PLLM_DIV_14
ganlikun	0:13413ea9a877	4257	* @arg @ref LL_RCC_PLLM_DIV_15
ganlikun	0:13413ea9a877	4258	* @arg @ref LL_RCC_PLLM_DIV_16
ganlikun	0:13413ea9a877	4259	* @arg @ref LL_RCC_PLLM_DIV_17
ganlikun	0:13413ea9a877	4260	* @arg @ref LL_RCC_PLLM_DIV_18
ganlikun	0:13413ea9a877	4261	* @arg @ref LL_RCC_PLLM_DIV_19
ganlikun	0:13413ea9a877	4262	* @arg @ref LL_RCC_PLLM_DIV_20
ganlikun	0:13413ea9a877	4263	* @arg @ref LL_RCC_PLLM_DIV_21
ganlikun	0:13413ea9a877	4264	* @arg @ref LL_RCC_PLLM_DIV_22
ganlikun	0:13413ea9a877	4265	* @arg @ref LL_RCC_PLLM_DIV_23
ganlikun	0:13413ea9a877	4266	* @arg @ref LL_RCC_PLLM_DIV_24
ganlikun	0:13413ea9a877	4267	* @arg @ref LL_RCC_PLLM_DIV_25
ganlikun	0:13413ea9a877	4268	* @arg @ref LL_RCC_PLLM_DIV_26
ganlikun	0:13413ea9a877	4269	* @arg @ref LL_RCC_PLLM_DIV_27
ganlikun	0:13413ea9a877	4270	* @arg @ref LL_RCC_PLLM_DIV_28
ganlikun	0:13413ea9a877	4271	* @arg @ref LL_RCC_PLLM_DIV_29
ganlikun	0:13413ea9a877	4272	* @arg @ref LL_RCC_PLLM_DIV_30
ganlikun	0:13413ea9a877	4273	* @arg @ref LL_RCC_PLLM_DIV_31
ganlikun	0:13413ea9a877	4274	* @arg @ref LL_RCC_PLLM_DIV_32
ganlikun	0:13413ea9a877	4275	* @arg @ref LL_RCC_PLLM_DIV_33
ganlikun	0:13413ea9a877	4276	* @arg @ref LL_RCC_PLLM_DIV_34
ganlikun	0:13413ea9a877	4277	* @arg @ref LL_RCC_PLLM_DIV_35
ganlikun	0:13413ea9a877	4278	* @arg @ref LL_RCC_PLLM_DIV_36
ganlikun	0:13413ea9a877	4279	* @arg @ref LL_RCC_PLLM_DIV_37
ganlikun	0:13413ea9a877	4280	* @arg @ref LL_RCC_PLLM_DIV_38
ganlikun	0:13413ea9a877	4281	* @arg @ref LL_RCC_PLLM_DIV_39
ganlikun	0:13413ea9a877	4282	* @arg @ref LL_RCC_PLLM_DIV_40
ganlikun	0:13413ea9a877	4283	* @arg @ref LL_RCC_PLLM_DIV_41
ganlikun	0:13413ea9a877	4284	* @arg @ref LL_RCC_PLLM_DIV_42
ganlikun	0:13413ea9a877	4285	* @arg @ref LL_RCC_PLLM_DIV_43
ganlikun	0:13413ea9a877	4286	* @arg @ref LL_RCC_PLLM_DIV_44
ganlikun	0:13413ea9a877	4287	* @arg @ref LL_RCC_PLLM_DIV_45
ganlikun	0:13413ea9a877	4288	* @arg @ref LL_RCC_PLLM_DIV_46
ganlikun	0:13413ea9a877	4289	* @arg @ref LL_RCC_PLLM_DIV_47
ganlikun	0:13413ea9a877	4290	* @arg @ref LL_RCC_PLLM_DIV_48
ganlikun	0:13413ea9a877	4291	* @arg @ref LL_RCC_PLLM_DIV_49
ganlikun	0:13413ea9a877	4292	* @arg @ref LL_RCC_PLLM_DIV_50
ganlikun	0:13413ea9a877	4293	* @arg @ref LL_RCC_PLLM_DIV_51
ganlikun	0:13413ea9a877	4294	* @arg @ref LL_RCC_PLLM_DIV_52
ganlikun	0:13413ea9a877	4295	* @arg @ref LL_RCC_PLLM_DIV_53
ganlikun	0:13413ea9a877	4296	* @arg @ref LL_RCC_PLLM_DIV_54
ganlikun	0:13413ea9a877	4297	* @arg @ref LL_RCC_PLLM_DIV_55
ganlikun	0:13413ea9a877	4298	* @arg @ref LL_RCC_PLLM_DIV_56
ganlikun	0:13413ea9a877	4299	* @arg @ref LL_RCC_PLLM_DIV_57
ganlikun	0:13413ea9a877	4300	* @arg @ref LL_RCC_PLLM_DIV_58
ganlikun	0:13413ea9a877	4301	* @arg @ref LL_RCC_PLLM_DIV_59
ganlikun	0:13413ea9a877	4302	* @arg @ref LL_RCC_PLLM_DIV_60
ganlikun	0:13413ea9a877	4303	* @arg @ref LL_RCC_PLLM_DIV_61
ganlikun	0:13413ea9a877	4304	* @arg @ref LL_RCC_PLLM_DIV_62
ganlikun	0:13413ea9a877	4305	* @arg @ref LL_RCC_PLLM_DIV_63
ganlikun	0:13413ea9a877	4306	* @param PLLN Between 50/192(*) and 432
ganlikun	0:13413ea9a877	4307	*
ganlikun	0:13413ea9a877	4308	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	4309	* @param PLLP_R This parameter can be one of the following values:
ganlikun	0:13413ea9a877	4310	* @arg @ref LL_RCC_PLLP_DIV_2
ganlikun	0:13413ea9a877	4311	* @arg @ref LL_RCC_PLLP_DIV_4
ganlikun	0:13413ea9a877	4312	* @arg @ref LL_RCC_PLLP_DIV_6
ganlikun	0:13413ea9a877	4313	* @arg @ref LL_RCC_PLLP_DIV_8
ganlikun	0:13413ea9a877	4314	* @arg @ref LL_RCC_PLLR_DIV_2 (*)
ganlikun	0:13413ea9a877	4315	* @arg @ref LL_RCC_PLLR_DIV_3 (*)
ganlikun	0:13413ea9a877	4316	* @arg @ref LL_RCC_PLLR_DIV_4 (*)
ganlikun	0:13413ea9a877	4317	* @arg @ref LL_RCC_PLLR_DIV_5 (*)
ganlikun	0:13413ea9a877	4318	* @arg @ref LL_RCC_PLLR_DIV_6 (*)
ganlikun	0:13413ea9a877	4319	* @arg @ref LL_RCC_PLLR_DIV_7 (*)
ganlikun	0:13413ea9a877	4320	*
ganlikun	0:13413ea9a877	4321	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	4322	* @retval None
ganlikun	0:13413ea9a877	4323	*/
ganlikun	0:13413ea9a877	4324	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R)
ganlikun	0:13413ea9a877	4325	{
ganlikun	0:13413ea9a877	4326	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN,
ganlikun	0:13413ea9a877	4327	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos);
ganlikun	0:13413ea9a877	4328	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R);
ganlikun	0:13413ea9a877	4329	#if defined(RCC_PLLR_SYSCLK_SUPPORT)
ganlikun	0:13413ea9a877	4330	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R);
ganlikun	0:13413ea9a877	4331	#endif /* RCC_PLLR_SYSCLK_SUPPORT */
ganlikun	0:13413ea9a877	4332	}
ganlikun	0:13413ea9a877	4333
ganlikun	0:13413ea9a877	4334	/**
ganlikun	0:13413ea9a877	4335	* @brief Configure PLL used for 48Mhz domain clock
ganlikun	0:13413ea9a877	4336	* @note PLL Source and PLLM Divider can be written only when PLL,
ganlikun	0:13413ea9a877	4337	* PLLI2S and PLLSAI(*) are disabled
ganlikun	0:13413ea9a877	4338	* @note PLLN/PLLQ can be written only when PLL is disabled
ganlikun	0:13413ea9a877	4339	* @note This can be selected for USB, RNG, SDIO
ganlikun	0:13413ea9a877	4340	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
ganlikun	0:13413ea9a877	4341	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
ganlikun	0:13413ea9a877	4342	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
ganlikun	0:13413ea9a877	4343	* PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
ganlikun	0:13413ea9a877	4344	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	4345	* @arg @ref LL_RCC_PLLSOURCE_HSI
ganlikun	0:13413ea9a877	4346	* @arg @ref LL_RCC_PLLSOURCE_HSE
ganlikun	0:13413ea9a877	4347	* @param PLLM This parameter can be one of the following values:
ganlikun	0:13413ea9a877	4348	* @arg @ref LL_RCC_PLLM_DIV_2
ganlikun	0:13413ea9a877	4349	* @arg @ref LL_RCC_PLLM_DIV_3
ganlikun	0:13413ea9a877	4350	* @arg @ref LL_RCC_PLLM_DIV_4
ganlikun	0:13413ea9a877	4351	* @arg @ref LL_RCC_PLLM_DIV_5
ganlikun	0:13413ea9a877	4352	* @arg @ref LL_RCC_PLLM_DIV_6
ganlikun	0:13413ea9a877	4353	* @arg @ref LL_RCC_PLLM_DIV_7
ganlikun	0:13413ea9a877	4354	* @arg @ref LL_RCC_PLLM_DIV_8
ganlikun	0:13413ea9a877	4355	* @arg @ref LL_RCC_PLLM_DIV_9
ganlikun	0:13413ea9a877	4356	* @arg @ref LL_RCC_PLLM_DIV_10
ganlikun	0:13413ea9a877	4357	* @arg @ref LL_RCC_PLLM_DIV_11
ganlikun	0:13413ea9a877	4358	* @arg @ref LL_RCC_PLLM_DIV_12
ganlikun	0:13413ea9a877	4359	* @arg @ref LL_RCC_PLLM_DIV_13
ganlikun	0:13413ea9a877	4360	* @arg @ref LL_RCC_PLLM_DIV_14
ganlikun	0:13413ea9a877	4361	* @arg @ref LL_RCC_PLLM_DIV_15
ganlikun	0:13413ea9a877	4362	* @arg @ref LL_RCC_PLLM_DIV_16
ganlikun	0:13413ea9a877	4363	* @arg @ref LL_RCC_PLLM_DIV_17
ganlikun	0:13413ea9a877	4364	* @arg @ref LL_RCC_PLLM_DIV_18
ganlikun	0:13413ea9a877	4365	* @arg @ref LL_RCC_PLLM_DIV_19
ganlikun	0:13413ea9a877	4366	* @arg @ref LL_RCC_PLLM_DIV_20
ganlikun	0:13413ea9a877	4367	* @arg @ref LL_RCC_PLLM_DIV_21
ganlikun	0:13413ea9a877	4368	* @arg @ref LL_RCC_PLLM_DIV_22
ganlikun	0:13413ea9a877	4369	* @arg @ref LL_RCC_PLLM_DIV_23
ganlikun	0:13413ea9a877	4370	* @arg @ref LL_RCC_PLLM_DIV_24
ganlikun	0:13413ea9a877	4371	* @arg @ref LL_RCC_PLLM_DIV_25
ganlikun	0:13413ea9a877	4372	* @arg @ref LL_RCC_PLLM_DIV_26
ganlikun	0:13413ea9a877	4373	* @arg @ref LL_RCC_PLLM_DIV_27
ganlikun	0:13413ea9a877	4374	* @arg @ref LL_RCC_PLLM_DIV_28
ganlikun	0:13413ea9a877	4375	* @arg @ref LL_RCC_PLLM_DIV_29
ganlikun	0:13413ea9a877	4376	* @arg @ref LL_RCC_PLLM_DIV_30
ganlikun	0:13413ea9a877	4377	* @arg @ref LL_RCC_PLLM_DIV_31
ganlikun	0:13413ea9a877	4378	* @arg @ref LL_RCC_PLLM_DIV_32
ganlikun	0:13413ea9a877	4379	* @arg @ref LL_RCC_PLLM_DIV_33
ganlikun	0:13413ea9a877	4380	* @arg @ref LL_RCC_PLLM_DIV_34
ganlikun	0:13413ea9a877	4381	* @arg @ref LL_RCC_PLLM_DIV_35
ganlikun	0:13413ea9a877	4382	* @arg @ref LL_RCC_PLLM_DIV_36
ganlikun	0:13413ea9a877	4383	* @arg @ref LL_RCC_PLLM_DIV_37
ganlikun	0:13413ea9a877	4384	* @arg @ref LL_RCC_PLLM_DIV_38
ganlikun	0:13413ea9a877	4385	* @arg @ref LL_RCC_PLLM_DIV_39
ganlikun	0:13413ea9a877	4386	* @arg @ref LL_RCC_PLLM_DIV_40
ganlikun	0:13413ea9a877	4387	* @arg @ref LL_RCC_PLLM_DIV_41
ganlikun	0:13413ea9a877	4388	* @arg @ref LL_RCC_PLLM_DIV_42
ganlikun	0:13413ea9a877	4389	* @arg @ref LL_RCC_PLLM_DIV_43
ganlikun	0:13413ea9a877	4390	* @arg @ref LL_RCC_PLLM_DIV_44
ganlikun	0:13413ea9a877	4391	* @arg @ref LL_RCC_PLLM_DIV_45
ganlikun	0:13413ea9a877	4392	* @arg @ref LL_RCC_PLLM_DIV_46
ganlikun	0:13413ea9a877	4393	* @arg @ref LL_RCC_PLLM_DIV_47
ganlikun	0:13413ea9a877	4394	* @arg @ref LL_RCC_PLLM_DIV_48
ganlikun	0:13413ea9a877	4395	* @arg @ref LL_RCC_PLLM_DIV_49
ganlikun	0:13413ea9a877	4396	* @arg @ref LL_RCC_PLLM_DIV_50
ganlikun	0:13413ea9a877	4397	* @arg @ref LL_RCC_PLLM_DIV_51
ganlikun	0:13413ea9a877	4398	* @arg @ref LL_RCC_PLLM_DIV_52
ganlikun	0:13413ea9a877	4399	* @arg @ref LL_RCC_PLLM_DIV_53
ganlikun	0:13413ea9a877	4400	* @arg @ref LL_RCC_PLLM_DIV_54
ganlikun	0:13413ea9a877	4401	* @arg @ref LL_RCC_PLLM_DIV_55
ganlikun	0:13413ea9a877	4402	* @arg @ref LL_RCC_PLLM_DIV_56
ganlikun	0:13413ea9a877	4403	* @arg @ref LL_RCC_PLLM_DIV_57
ganlikun	0:13413ea9a877	4404	* @arg @ref LL_RCC_PLLM_DIV_58
ganlikun	0:13413ea9a877	4405	* @arg @ref LL_RCC_PLLM_DIV_59
ganlikun	0:13413ea9a877	4406	* @arg @ref LL_RCC_PLLM_DIV_60
ganlikun	0:13413ea9a877	4407	* @arg @ref LL_RCC_PLLM_DIV_61
ganlikun	0:13413ea9a877	4408	* @arg @ref LL_RCC_PLLM_DIV_62
ganlikun	0:13413ea9a877	4409	* @arg @ref LL_RCC_PLLM_DIV_63
ganlikun	0:13413ea9a877	4410	* @param PLLN Between 50/192(*) and 432
ganlikun	0:13413ea9a877	4411	*
ganlikun	0:13413ea9a877	4412	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	4413	* @param PLLQ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	4414	* @arg @ref LL_RCC_PLLQ_DIV_2
ganlikun	0:13413ea9a877	4415	* @arg @ref LL_RCC_PLLQ_DIV_3
ganlikun	0:13413ea9a877	4416	* @arg @ref LL_RCC_PLLQ_DIV_4
ganlikun	0:13413ea9a877	4417	* @arg @ref LL_RCC_PLLQ_DIV_5
ganlikun	0:13413ea9a877	4418	* @arg @ref LL_RCC_PLLQ_DIV_6
ganlikun	0:13413ea9a877	4419	* @arg @ref LL_RCC_PLLQ_DIV_7
ganlikun	0:13413ea9a877	4420	* @arg @ref LL_RCC_PLLQ_DIV_8
ganlikun	0:13413ea9a877	4421	* @arg @ref LL_RCC_PLLQ_DIV_9
ganlikun	0:13413ea9a877	4422	* @arg @ref LL_RCC_PLLQ_DIV_10
ganlikun	0:13413ea9a877	4423	* @arg @ref LL_RCC_PLLQ_DIV_11
ganlikun	0:13413ea9a877	4424	* @arg @ref LL_RCC_PLLQ_DIV_12
ganlikun	0:13413ea9a877	4425	* @arg @ref LL_RCC_PLLQ_DIV_13
ganlikun	0:13413ea9a877	4426	* @arg @ref LL_RCC_PLLQ_DIV_14
ganlikun	0:13413ea9a877	4427	* @arg @ref LL_RCC_PLLQ_DIV_15
ganlikun	0:13413ea9a877	4428	* @retval None
ganlikun	0:13413ea9a877	4429	*/
ganlikun	0:13413ea9a877	4430	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
ganlikun	0:13413ea9a877	4431	{
ganlikun	0:13413ea9a877	4432	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLQ,
ganlikun	0:13413ea9a877	4433	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLQ);
ganlikun	0:13413ea9a877	4434	}
ganlikun	0:13413ea9a877	4435
ganlikun	0:13413ea9a877	4436	#if defined(DSI)
ganlikun	0:13413ea9a877	4437	/**
ganlikun	0:13413ea9a877	4438	* @brief Configure PLL used for DSI clock
ganlikun	0:13413ea9a877	4439	* @note PLL Source and PLLM Divider can be written only when PLL,
ganlikun	0:13413ea9a877	4440	* PLLI2S and PLLSAI are disabled
ganlikun	0:13413ea9a877	4441	* @note PLLN/PLLR can be written only when PLL is disabled
ganlikun	0:13413ea9a877	4442	* @note This can be selected for DSI
ganlikun	0:13413ea9a877	4443	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n
ganlikun	0:13413ea9a877	4444	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n
ganlikun	0:13413ea9a877	4445	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n
ganlikun	0:13413ea9a877	4446	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI
ganlikun	0:13413ea9a877	4447	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	4448	* @arg @ref LL_RCC_PLLSOURCE_HSI
ganlikun	0:13413ea9a877	4449	* @arg @ref LL_RCC_PLLSOURCE_HSE
ganlikun	0:13413ea9a877	4450	* @param PLLM This parameter can be one of the following values:
ganlikun	0:13413ea9a877	4451	* @arg @ref LL_RCC_PLLM_DIV_2
ganlikun	0:13413ea9a877	4452	* @arg @ref LL_RCC_PLLM_DIV_3
ganlikun	0:13413ea9a877	4453	* @arg @ref LL_RCC_PLLM_DIV_4
ganlikun	0:13413ea9a877	4454	* @arg @ref LL_RCC_PLLM_DIV_5
ganlikun	0:13413ea9a877	4455	* @arg @ref LL_RCC_PLLM_DIV_6
ganlikun	0:13413ea9a877	4456	* @arg @ref LL_RCC_PLLM_DIV_7
ganlikun	0:13413ea9a877	4457	* @arg @ref LL_RCC_PLLM_DIV_8
ganlikun	0:13413ea9a877	4458	* @arg @ref LL_RCC_PLLM_DIV_9
ganlikun	0:13413ea9a877	4459	* @arg @ref LL_RCC_PLLM_DIV_10
ganlikun	0:13413ea9a877	4460	* @arg @ref LL_RCC_PLLM_DIV_11
ganlikun	0:13413ea9a877	4461	* @arg @ref LL_RCC_PLLM_DIV_12
ganlikun	0:13413ea9a877	4462	* @arg @ref LL_RCC_PLLM_DIV_13
ganlikun	0:13413ea9a877	4463	* @arg @ref LL_RCC_PLLM_DIV_14
ganlikun	0:13413ea9a877	4464	* @arg @ref LL_RCC_PLLM_DIV_15
ganlikun	0:13413ea9a877	4465	* @arg @ref LL_RCC_PLLM_DIV_16
ganlikun	0:13413ea9a877	4466	* @arg @ref LL_RCC_PLLM_DIV_17
ganlikun	0:13413ea9a877	4467	* @arg @ref LL_RCC_PLLM_DIV_18
ganlikun	0:13413ea9a877	4468	* @arg @ref LL_RCC_PLLM_DIV_19
ganlikun	0:13413ea9a877	4469	* @arg @ref LL_RCC_PLLM_DIV_20
ganlikun	0:13413ea9a877	4470	* @arg @ref LL_RCC_PLLM_DIV_21
ganlikun	0:13413ea9a877	4471	* @arg @ref LL_RCC_PLLM_DIV_22
ganlikun	0:13413ea9a877	4472	* @arg @ref LL_RCC_PLLM_DIV_23
ganlikun	0:13413ea9a877	4473	* @arg @ref LL_RCC_PLLM_DIV_24
ganlikun	0:13413ea9a877	4474	* @arg @ref LL_RCC_PLLM_DIV_25
ganlikun	0:13413ea9a877	4475	* @arg @ref LL_RCC_PLLM_DIV_26
ganlikun	0:13413ea9a877	4476	* @arg @ref LL_RCC_PLLM_DIV_27
ganlikun	0:13413ea9a877	4477	* @arg @ref LL_RCC_PLLM_DIV_28
ganlikun	0:13413ea9a877	4478	* @arg @ref LL_RCC_PLLM_DIV_29
ganlikun	0:13413ea9a877	4479	* @arg @ref LL_RCC_PLLM_DIV_30
ganlikun	0:13413ea9a877	4480	* @arg @ref LL_RCC_PLLM_DIV_31
ganlikun	0:13413ea9a877	4481	* @arg @ref LL_RCC_PLLM_DIV_32
ganlikun	0:13413ea9a877	4482	* @arg @ref LL_RCC_PLLM_DIV_33
ganlikun	0:13413ea9a877	4483	* @arg @ref LL_RCC_PLLM_DIV_34
ganlikun	0:13413ea9a877	4484	* @arg @ref LL_RCC_PLLM_DIV_35
ganlikun	0:13413ea9a877	4485	* @arg @ref LL_RCC_PLLM_DIV_36
ganlikun	0:13413ea9a877	4486	* @arg @ref LL_RCC_PLLM_DIV_37
ganlikun	0:13413ea9a877	4487	* @arg @ref LL_RCC_PLLM_DIV_38
ganlikun	0:13413ea9a877	4488	* @arg @ref LL_RCC_PLLM_DIV_39
ganlikun	0:13413ea9a877	4489	* @arg @ref LL_RCC_PLLM_DIV_40
ganlikun	0:13413ea9a877	4490	* @arg @ref LL_RCC_PLLM_DIV_41
ganlikun	0:13413ea9a877	4491	* @arg @ref LL_RCC_PLLM_DIV_42
ganlikun	0:13413ea9a877	4492	* @arg @ref LL_RCC_PLLM_DIV_43
ganlikun	0:13413ea9a877	4493	* @arg @ref LL_RCC_PLLM_DIV_44
ganlikun	0:13413ea9a877	4494	* @arg @ref LL_RCC_PLLM_DIV_45
ganlikun	0:13413ea9a877	4495	* @arg @ref LL_RCC_PLLM_DIV_46
ganlikun	0:13413ea9a877	4496	* @arg @ref LL_RCC_PLLM_DIV_47
ganlikun	0:13413ea9a877	4497	* @arg @ref LL_RCC_PLLM_DIV_48
ganlikun	0:13413ea9a877	4498	* @arg @ref LL_RCC_PLLM_DIV_49
ganlikun	0:13413ea9a877	4499	* @arg @ref LL_RCC_PLLM_DIV_50
ganlikun	0:13413ea9a877	4500	* @arg @ref LL_RCC_PLLM_DIV_51
ganlikun	0:13413ea9a877	4501	* @arg @ref LL_RCC_PLLM_DIV_52
ganlikun	0:13413ea9a877	4502	* @arg @ref LL_RCC_PLLM_DIV_53
ganlikun	0:13413ea9a877	4503	* @arg @ref LL_RCC_PLLM_DIV_54
ganlikun	0:13413ea9a877	4504	* @arg @ref LL_RCC_PLLM_DIV_55
ganlikun	0:13413ea9a877	4505	* @arg @ref LL_RCC_PLLM_DIV_56
ganlikun	0:13413ea9a877	4506	* @arg @ref LL_RCC_PLLM_DIV_57
ganlikun	0:13413ea9a877	4507	* @arg @ref LL_RCC_PLLM_DIV_58
ganlikun	0:13413ea9a877	4508	* @arg @ref LL_RCC_PLLM_DIV_59
ganlikun	0:13413ea9a877	4509	* @arg @ref LL_RCC_PLLM_DIV_60
ganlikun	0:13413ea9a877	4510	* @arg @ref LL_RCC_PLLM_DIV_61
ganlikun	0:13413ea9a877	4511	* @arg @ref LL_RCC_PLLM_DIV_62
ganlikun	0:13413ea9a877	4512	* @arg @ref LL_RCC_PLLM_DIV_63
ganlikun	0:13413ea9a877	4513	* @param PLLN Between 50 and 432
ganlikun	0:13413ea9a877	4514	* @param PLLR This parameter can be one of the following values:
ganlikun	0:13413ea9a877	4515	* @arg @ref LL_RCC_PLLR_DIV_2
ganlikun	0:13413ea9a877	4516	* @arg @ref LL_RCC_PLLR_DIV_3
ganlikun	0:13413ea9a877	4517	* @arg @ref LL_RCC_PLLR_DIV_4
ganlikun	0:13413ea9a877	4518	* @arg @ref LL_RCC_PLLR_DIV_5
ganlikun	0:13413ea9a877	4519	* @arg @ref LL_RCC_PLLR_DIV_6
ganlikun	0:13413ea9a877	4520	* @arg @ref LL_RCC_PLLR_DIV_7
ganlikun	0:13413ea9a877	4521	* @retval None
ganlikun	0:13413ea9a877	4522	*/
ganlikun	0:13413ea9a877	4523	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
ganlikun	0:13413ea9a877	4524	{
ganlikun	0:13413ea9a877	4525	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
ganlikun	0:13413ea9a877	4526	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
ganlikun	0:13413ea9a877	4527	}
ganlikun	0:13413ea9a877	4528	#endif /* DSI */
ganlikun	0:13413ea9a877	4529
ganlikun	0:13413ea9a877	4530	#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
ganlikun	0:13413ea9a877	4531	/**
ganlikun	0:13413ea9a877	4532	* @brief Configure PLL used for I2S clock
ganlikun	0:13413ea9a877	4533	* @note PLL Source and PLLM Divider can be written only when PLL,
ganlikun	0:13413ea9a877	4534	* PLLI2S and PLLSAI are disabled
ganlikun	0:13413ea9a877	4535	* @note PLLN/PLLR can be written only when PLL is disabled
ganlikun	0:13413ea9a877	4536	* @note This can be selected for I2S
ganlikun	0:13413ea9a877	4537	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S\n
ganlikun	0:13413ea9a877	4538	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S\n
ganlikun	0:13413ea9a877	4539	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S\n
ganlikun	0:13413ea9a877	4540	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_I2S
ganlikun	0:13413ea9a877	4541	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	4542	* @arg @ref LL_RCC_PLLSOURCE_HSI
ganlikun	0:13413ea9a877	4543	* @arg @ref LL_RCC_PLLSOURCE_HSE
ganlikun	0:13413ea9a877	4544	* @param PLLM This parameter can be one of the following values:
ganlikun	0:13413ea9a877	4545	* @arg @ref LL_RCC_PLLM_DIV_2
ganlikun	0:13413ea9a877	4546	* @arg @ref LL_RCC_PLLM_DIV_3
ganlikun	0:13413ea9a877	4547	* @arg @ref LL_RCC_PLLM_DIV_4
ganlikun	0:13413ea9a877	4548	* @arg @ref LL_RCC_PLLM_DIV_5
ganlikun	0:13413ea9a877	4549	* @arg @ref LL_RCC_PLLM_DIV_6
ganlikun	0:13413ea9a877	4550	* @arg @ref LL_RCC_PLLM_DIV_7
ganlikun	0:13413ea9a877	4551	* @arg @ref LL_RCC_PLLM_DIV_8
ganlikun	0:13413ea9a877	4552	* @arg @ref LL_RCC_PLLM_DIV_9
ganlikun	0:13413ea9a877	4553	* @arg @ref LL_RCC_PLLM_DIV_10
ganlikun	0:13413ea9a877	4554	* @arg @ref LL_RCC_PLLM_DIV_11
ganlikun	0:13413ea9a877	4555	* @arg @ref LL_RCC_PLLM_DIV_12
ganlikun	0:13413ea9a877	4556	* @arg @ref LL_RCC_PLLM_DIV_13
ganlikun	0:13413ea9a877	4557	* @arg @ref LL_RCC_PLLM_DIV_14
ganlikun	0:13413ea9a877	4558	* @arg @ref LL_RCC_PLLM_DIV_15
ganlikun	0:13413ea9a877	4559	* @arg @ref LL_RCC_PLLM_DIV_16
ganlikun	0:13413ea9a877	4560	* @arg @ref LL_RCC_PLLM_DIV_17
ganlikun	0:13413ea9a877	4561	* @arg @ref LL_RCC_PLLM_DIV_18
ganlikun	0:13413ea9a877	4562	* @arg @ref LL_RCC_PLLM_DIV_19
ganlikun	0:13413ea9a877	4563	* @arg @ref LL_RCC_PLLM_DIV_20
ganlikun	0:13413ea9a877	4564	* @arg @ref LL_RCC_PLLM_DIV_21
ganlikun	0:13413ea9a877	4565	* @arg @ref LL_RCC_PLLM_DIV_22
ganlikun	0:13413ea9a877	4566	* @arg @ref LL_RCC_PLLM_DIV_23
ganlikun	0:13413ea9a877	4567	* @arg @ref LL_RCC_PLLM_DIV_24
ganlikun	0:13413ea9a877	4568	* @arg @ref LL_RCC_PLLM_DIV_25
ganlikun	0:13413ea9a877	4569	* @arg @ref LL_RCC_PLLM_DIV_26
ganlikun	0:13413ea9a877	4570	* @arg @ref LL_RCC_PLLM_DIV_27
ganlikun	0:13413ea9a877	4571	* @arg @ref LL_RCC_PLLM_DIV_28
ganlikun	0:13413ea9a877	4572	* @arg @ref LL_RCC_PLLM_DIV_29
ganlikun	0:13413ea9a877	4573	* @arg @ref LL_RCC_PLLM_DIV_30
ganlikun	0:13413ea9a877	4574	* @arg @ref LL_RCC_PLLM_DIV_31
ganlikun	0:13413ea9a877	4575	* @arg @ref LL_RCC_PLLM_DIV_32
ganlikun	0:13413ea9a877	4576	* @arg @ref LL_RCC_PLLM_DIV_33
ganlikun	0:13413ea9a877	4577	* @arg @ref LL_RCC_PLLM_DIV_34
ganlikun	0:13413ea9a877	4578	* @arg @ref LL_RCC_PLLM_DIV_35
ganlikun	0:13413ea9a877	4579	* @arg @ref LL_RCC_PLLM_DIV_36
ganlikun	0:13413ea9a877	4580	* @arg @ref LL_RCC_PLLM_DIV_37
ganlikun	0:13413ea9a877	4581	* @arg @ref LL_RCC_PLLM_DIV_38
ganlikun	0:13413ea9a877	4582	* @arg @ref LL_RCC_PLLM_DIV_39
ganlikun	0:13413ea9a877	4583	* @arg @ref LL_RCC_PLLM_DIV_40
ganlikun	0:13413ea9a877	4584	* @arg @ref LL_RCC_PLLM_DIV_41
ganlikun	0:13413ea9a877	4585	* @arg @ref LL_RCC_PLLM_DIV_42
ganlikun	0:13413ea9a877	4586	* @arg @ref LL_RCC_PLLM_DIV_43
ganlikun	0:13413ea9a877	4587	* @arg @ref LL_RCC_PLLM_DIV_44
ganlikun	0:13413ea9a877	4588	* @arg @ref LL_RCC_PLLM_DIV_45
ganlikun	0:13413ea9a877	4589	* @arg @ref LL_RCC_PLLM_DIV_46
ganlikun	0:13413ea9a877	4590	* @arg @ref LL_RCC_PLLM_DIV_47
ganlikun	0:13413ea9a877	4591	* @arg @ref LL_RCC_PLLM_DIV_48
ganlikun	0:13413ea9a877	4592	* @arg @ref LL_RCC_PLLM_DIV_49
ganlikun	0:13413ea9a877	4593	* @arg @ref LL_RCC_PLLM_DIV_50
ganlikun	0:13413ea9a877	4594	* @arg @ref LL_RCC_PLLM_DIV_51
ganlikun	0:13413ea9a877	4595	* @arg @ref LL_RCC_PLLM_DIV_52
ganlikun	0:13413ea9a877	4596	* @arg @ref LL_RCC_PLLM_DIV_53
ganlikun	0:13413ea9a877	4597	* @arg @ref LL_RCC_PLLM_DIV_54
ganlikun	0:13413ea9a877	4598	* @arg @ref LL_RCC_PLLM_DIV_55
ganlikun	0:13413ea9a877	4599	* @arg @ref LL_RCC_PLLM_DIV_56
ganlikun	0:13413ea9a877	4600	* @arg @ref LL_RCC_PLLM_DIV_57
ganlikun	0:13413ea9a877	4601	* @arg @ref LL_RCC_PLLM_DIV_58
ganlikun	0:13413ea9a877	4602	* @arg @ref LL_RCC_PLLM_DIV_59
ganlikun	0:13413ea9a877	4603	* @arg @ref LL_RCC_PLLM_DIV_60
ganlikun	0:13413ea9a877	4604	* @arg @ref LL_RCC_PLLM_DIV_61
ganlikun	0:13413ea9a877	4605	* @arg @ref LL_RCC_PLLM_DIV_62
ganlikun	0:13413ea9a877	4606	* @arg @ref LL_RCC_PLLM_DIV_63
ganlikun	0:13413ea9a877	4607	* @param PLLN Between 50 and 432
ganlikun	0:13413ea9a877	4608	* @param PLLR This parameter can be one of the following values:
ganlikun	0:13413ea9a877	4609	* @arg @ref LL_RCC_PLLR_DIV_2
ganlikun	0:13413ea9a877	4610	* @arg @ref LL_RCC_PLLR_DIV_3
ganlikun	0:13413ea9a877	4611	* @arg @ref LL_RCC_PLLR_DIV_4
ganlikun	0:13413ea9a877	4612	* @arg @ref LL_RCC_PLLR_DIV_5
ganlikun	0:13413ea9a877	4613	* @arg @ref LL_RCC_PLLR_DIV_6
ganlikun	0:13413ea9a877	4614	* @arg @ref LL_RCC_PLLR_DIV_7
ganlikun	0:13413ea9a877	4615	* @retval None
ganlikun	0:13413ea9a877	4616	*/
ganlikun	0:13413ea9a877	4617	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
ganlikun	0:13413ea9a877	4618	{
ganlikun	0:13413ea9a877	4619	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
ganlikun	0:13413ea9a877	4620	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
ganlikun	0:13413ea9a877	4621	}
ganlikun	0:13413ea9a877	4622	#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
ganlikun	0:13413ea9a877	4623
ganlikun	0:13413ea9a877	4624	#if defined(SPDIFRX)
ganlikun	0:13413ea9a877	4625	/**
ganlikun	0:13413ea9a877	4626	* @brief Configure PLL used for SPDIFRX clock
ganlikun	0:13413ea9a877	4627	* @note PLL Source and PLLM Divider can be written only when PLL,
ganlikun	0:13413ea9a877	4628	* PLLI2S and PLLSAI are disabled
ganlikun	0:13413ea9a877	4629	* @note PLLN/PLLR can be written only when PLL is disabled
ganlikun	0:13413ea9a877	4630	* @note This can be selected for SPDIFRX
ganlikun	0:13413ea9a877	4631	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SPDIFRX\n
ganlikun	0:13413ea9a877	4632	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SPDIFRX\n
ganlikun	0:13413ea9a877	4633	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SPDIFRX\n
ganlikun	0:13413ea9a877	4634	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SPDIFRX
ganlikun	0:13413ea9a877	4635	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	4636	* @arg @ref LL_RCC_PLLSOURCE_HSI
ganlikun	0:13413ea9a877	4637	* @arg @ref LL_RCC_PLLSOURCE_HSE
ganlikun	0:13413ea9a877	4638	* @param PLLM This parameter can be one of the following values:
ganlikun	0:13413ea9a877	4639	* @arg @ref LL_RCC_PLLM_DIV_2
ganlikun	0:13413ea9a877	4640	* @arg @ref LL_RCC_PLLM_DIV_3
ganlikun	0:13413ea9a877	4641	* @arg @ref LL_RCC_PLLM_DIV_4
ganlikun	0:13413ea9a877	4642	* @arg @ref LL_RCC_PLLM_DIV_5
ganlikun	0:13413ea9a877	4643	* @arg @ref LL_RCC_PLLM_DIV_6
ganlikun	0:13413ea9a877	4644	* @arg @ref LL_RCC_PLLM_DIV_7
ganlikun	0:13413ea9a877	4645	* @arg @ref LL_RCC_PLLM_DIV_8
ganlikun	0:13413ea9a877	4646	* @arg @ref LL_RCC_PLLM_DIV_9
ganlikun	0:13413ea9a877	4647	* @arg @ref LL_RCC_PLLM_DIV_10
ganlikun	0:13413ea9a877	4648	* @arg @ref LL_RCC_PLLM_DIV_11
ganlikun	0:13413ea9a877	4649	* @arg @ref LL_RCC_PLLM_DIV_12
ganlikun	0:13413ea9a877	4650	* @arg @ref LL_RCC_PLLM_DIV_13
ganlikun	0:13413ea9a877	4651	* @arg @ref LL_RCC_PLLM_DIV_14
ganlikun	0:13413ea9a877	4652	* @arg @ref LL_RCC_PLLM_DIV_15
ganlikun	0:13413ea9a877	4653	* @arg @ref LL_RCC_PLLM_DIV_16
ganlikun	0:13413ea9a877	4654	* @arg @ref LL_RCC_PLLM_DIV_17
ganlikun	0:13413ea9a877	4655	* @arg @ref LL_RCC_PLLM_DIV_18
ganlikun	0:13413ea9a877	4656	* @arg @ref LL_RCC_PLLM_DIV_19
ganlikun	0:13413ea9a877	4657	* @arg @ref LL_RCC_PLLM_DIV_20
ganlikun	0:13413ea9a877	4658	* @arg @ref LL_RCC_PLLM_DIV_21
ganlikun	0:13413ea9a877	4659	* @arg @ref LL_RCC_PLLM_DIV_22
ganlikun	0:13413ea9a877	4660	* @arg @ref LL_RCC_PLLM_DIV_23
ganlikun	0:13413ea9a877	4661	* @arg @ref LL_RCC_PLLM_DIV_24
ganlikun	0:13413ea9a877	4662	* @arg @ref LL_RCC_PLLM_DIV_25
ganlikun	0:13413ea9a877	4663	* @arg @ref LL_RCC_PLLM_DIV_26
ganlikun	0:13413ea9a877	4664	* @arg @ref LL_RCC_PLLM_DIV_27
ganlikun	0:13413ea9a877	4665	* @arg @ref LL_RCC_PLLM_DIV_28
ganlikun	0:13413ea9a877	4666	* @arg @ref LL_RCC_PLLM_DIV_29
ganlikun	0:13413ea9a877	4667	* @arg @ref LL_RCC_PLLM_DIV_30
ganlikun	0:13413ea9a877	4668	* @arg @ref LL_RCC_PLLM_DIV_31
ganlikun	0:13413ea9a877	4669	* @arg @ref LL_RCC_PLLM_DIV_32
ganlikun	0:13413ea9a877	4670	* @arg @ref LL_RCC_PLLM_DIV_33
ganlikun	0:13413ea9a877	4671	* @arg @ref LL_RCC_PLLM_DIV_34
ganlikun	0:13413ea9a877	4672	* @arg @ref LL_RCC_PLLM_DIV_35
ganlikun	0:13413ea9a877	4673	* @arg @ref LL_RCC_PLLM_DIV_36
ganlikun	0:13413ea9a877	4674	* @arg @ref LL_RCC_PLLM_DIV_37
ganlikun	0:13413ea9a877	4675	* @arg @ref LL_RCC_PLLM_DIV_38
ganlikun	0:13413ea9a877	4676	* @arg @ref LL_RCC_PLLM_DIV_39
ganlikun	0:13413ea9a877	4677	* @arg @ref LL_RCC_PLLM_DIV_40
ganlikun	0:13413ea9a877	4678	* @arg @ref LL_RCC_PLLM_DIV_41
ganlikun	0:13413ea9a877	4679	* @arg @ref LL_RCC_PLLM_DIV_42
ganlikun	0:13413ea9a877	4680	* @arg @ref LL_RCC_PLLM_DIV_43
ganlikun	0:13413ea9a877	4681	* @arg @ref LL_RCC_PLLM_DIV_44
ganlikun	0:13413ea9a877	4682	* @arg @ref LL_RCC_PLLM_DIV_45
ganlikun	0:13413ea9a877	4683	* @arg @ref LL_RCC_PLLM_DIV_46
ganlikun	0:13413ea9a877	4684	* @arg @ref LL_RCC_PLLM_DIV_47
ganlikun	0:13413ea9a877	4685	* @arg @ref LL_RCC_PLLM_DIV_48
ganlikun	0:13413ea9a877	4686	* @arg @ref LL_RCC_PLLM_DIV_49
ganlikun	0:13413ea9a877	4687	* @arg @ref LL_RCC_PLLM_DIV_50
ganlikun	0:13413ea9a877	4688	* @arg @ref LL_RCC_PLLM_DIV_51
ganlikun	0:13413ea9a877	4689	* @arg @ref LL_RCC_PLLM_DIV_52
ganlikun	0:13413ea9a877	4690	* @arg @ref LL_RCC_PLLM_DIV_53
ganlikun	0:13413ea9a877	4691	* @arg @ref LL_RCC_PLLM_DIV_54
ganlikun	0:13413ea9a877	4692	* @arg @ref LL_RCC_PLLM_DIV_55
ganlikun	0:13413ea9a877	4693	* @arg @ref LL_RCC_PLLM_DIV_56
ganlikun	0:13413ea9a877	4694	* @arg @ref LL_RCC_PLLM_DIV_57
ganlikun	0:13413ea9a877	4695	* @arg @ref LL_RCC_PLLM_DIV_58
ganlikun	0:13413ea9a877	4696	* @arg @ref LL_RCC_PLLM_DIV_59
ganlikun	0:13413ea9a877	4697	* @arg @ref LL_RCC_PLLM_DIV_60
ganlikun	0:13413ea9a877	4698	* @arg @ref LL_RCC_PLLM_DIV_61
ganlikun	0:13413ea9a877	4699	* @arg @ref LL_RCC_PLLM_DIV_62
ganlikun	0:13413ea9a877	4700	* @arg @ref LL_RCC_PLLM_DIV_63
ganlikun	0:13413ea9a877	4701	* @param PLLN Between 50 and 432
ganlikun	0:13413ea9a877	4702	* @param PLLR This parameter can be one of the following values:
ganlikun	0:13413ea9a877	4703	* @arg @ref LL_RCC_PLLR_DIV_2
ganlikun	0:13413ea9a877	4704	* @arg @ref LL_RCC_PLLR_DIV_3
ganlikun	0:13413ea9a877	4705	* @arg @ref LL_RCC_PLLR_DIV_4
ganlikun	0:13413ea9a877	4706	* @arg @ref LL_RCC_PLLR_DIV_5
ganlikun	0:13413ea9a877	4707	* @arg @ref LL_RCC_PLLR_DIV_6
ganlikun	0:13413ea9a877	4708	* @arg @ref LL_RCC_PLLR_DIV_7
ganlikun	0:13413ea9a877	4709	* @retval None
ganlikun	0:13413ea9a877	4710	*/
ganlikun	0:13413ea9a877	4711	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
ganlikun	0:13413ea9a877	4712	{
ganlikun	0:13413ea9a877	4713	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
ganlikun	0:13413ea9a877	4714	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
ganlikun	0:13413ea9a877	4715	}
ganlikun	0:13413ea9a877	4716	#endif /* SPDIFRX */
ganlikun	0:13413ea9a877	4717
ganlikun	0:13413ea9a877	4718	#if defined(RCC_PLLCFGR_PLLR)
ganlikun	0:13413ea9a877	4719	#if defined(SAI1)
ganlikun	0:13413ea9a877	4720	/**
ganlikun	0:13413ea9a877	4721	* @brief Configure PLL used for SAI clock
ganlikun	0:13413ea9a877	4722	* @note PLL Source and PLLM Divider can be written only when PLL,
ganlikun	0:13413ea9a877	4723	* PLLI2S and PLLSAI are disabled
ganlikun	0:13413ea9a877	4724	* @note PLLN/PLLR can be written only when PLL is disabled
ganlikun	0:13413ea9a877	4725	* @note This can be selected for SAI
ganlikun	0:13413ea9a877	4726	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
ganlikun	0:13413ea9a877	4727	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
ganlikun	0:13413ea9a877	4728	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
ganlikun	0:13413ea9a877	4729	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SAI\n
ganlikun	0:13413ea9a877	4730	* DCKCFGR PLLDIVR LL_RCC_PLL_ConfigDomain_SAI
ganlikun	0:13413ea9a877	4731	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	4732	* @arg @ref LL_RCC_PLLSOURCE_HSI
ganlikun	0:13413ea9a877	4733	* @arg @ref LL_RCC_PLLSOURCE_HSE
ganlikun	0:13413ea9a877	4734	* @param PLLM This parameter can be one of the following values:
ganlikun	0:13413ea9a877	4735	* @arg @ref LL_RCC_PLLM_DIV_2
ganlikun	0:13413ea9a877	4736	* @arg @ref LL_RCC_PLLM_DIV_3
ganlikun	0:13413ea9a877	4737	* @arg @ref LL_RCC_PLLM_DIV_4
ganlikun	0:13413ea9a877	4738	* @arg @ref LL_RCC_PLLM_DIV_5
ganlikun	0:13413ea9a877	4739	* @arg @ref LL_RCC_PLLM_DIV_6
ganlikun	0:13413ea9a877	4740	* @arg @ref LL_RCC_PLLM_DIV_7
ganlikun	0:13413ea9a877	4741	* @arg @ref LL_RCC_PLLM_DIV_8
ganlikun	0:13413ea9a877	4742	* @arg @ref LL_RCC_PLLM_DIV_9
ganlikun	0:13413ea9a877	4743	* @arg @ref LL_RCC_PLLM_DIV_10
ganlikun	0:13413ea9a877	4744	* @arg @ref LL_RCC_PLLM_DIV_11
ganlikun	0:13413ea9a877	4745	* @arg @ref LL_RCC_PLLM_DIV_12
ganlikun	0:13413ea9a877	4746	* @arg @ref LL_RCC_PLLM_DIV_13
ganlikun	0:13413ea9a877	4747	* @arg @ref LL_RCC_PLLM_DIV_14
ganlikun	0:13413ea9a877	4748	* @arg @ref LL_RCC_PLLM_DIV_15
ganlikun	0:13413ea9a877	4749	* @arg @ref LL_RCC_PLLM_DIV_16
ganlikun	0:13413ea9a877	4750	* @arg @ref LL_RCC_PLLM_DIV_17
ganlikun	0:13413ea9a877	4751	* @arg @ref LL_RCC_PLLM_DIV_18
ganlikun	0:13413ea9a877	4752	* @arg @ref LL_RCC_PLLM_DIV_19
ganlikun	0:13413ea9a877	4753	* @arg @ref LL_RCC_PLLM_DIV_20
ganlikun	0:13413ea9a877	4754	* @arg @ref LL_RCC_PLLM_DIV_21
ganlikun	0:13413ea9a877	4755	* @arg @ref LL_RCC_PLLM_DIV_22
ganlikun	0:13413ea9a877	4756	* @arg @ref LL_RCC_PLLM_DIV_23
ganlikun	0:13413ea9a877	4757	* @arg @ref LL_RCC_PLLM_DIV_24
ganlikun	0:13413ea9a877	4758	* @arg @ref LL_RCC_PLLM_DIV_25
ganlikun	0:13413ea9a877	4759	* @arg @ref LL_RCC_PLLM_DIV_26
ganlikun	0:13413ea9a877	4760	* @arg @ref LL_RCC_PLLM_DIV_27
ganlikun	0:13413ea9a877	4761	* @arg @ref LL_RCC_PLLM_DIV_28
ganlikun	0:13413ea9a877	4762	* @arg @ref LL_RCC_PLLM_DIV_29
ganlikun	0:13413ea9a877	4763	* @arg @ref LL_RCC_PLLM_DIV_30
ganlikun	0:13413ea9a877	4764	* @arg @ref LL_RCC_PLLM_DIV_31
ganlikun	0:13413ea9a877	4765	* @arg @ref LL_RCC_PLLM_DIV_32
ganlikun	0:13413ea9a877	4766	* @arg @ref LL_RCC_PLLM_DIV_33
ganlikun	0:13413ea9a877	4767	* @arg @ref LL_RCC_PLLM_DIV_34
ganlikun	0:13413ea9a877	4768	* @arg @ref LL_RCC_PLLM_DIV_35
ganlikun	0:13413ea9a877	4769	* @arg @ref LL_RCC_PLLM_DIV_36
ganlikun	0:13413ea9a877	4770	* @arg @ref LL_RCC_PLLM_DIV_37
ganlikun	0:13413ea9a877	4771	* @arg @ref LL_RCC_PLLM_DIV_38
ganlikun	0:13413ea9a877	4772	* @arg @ref LL_RCC_PLLM_DIV_39
ganlikun	0:13413ea9a877	4773	* @arg @ref LL_RCC_PLLM_DIV_40
ganlikun	0:13413ea9a877	4774	* @arg @ref LL_RCC_PLLM_DIV_41
ganlikun	0:13413ea9a877	4775	* @arg @ref LL_RCC_PLLM_DIV_42
ganlikun	0:13413ea9a877	4776	* @arg @ref LL_RCC_PLLM_DIV_43
ganlikun	0:13413ea9a877	4777	* @arg @ref LL_RCC_PLLM_DIV_44
ganlikun	0:13413ea9a877	4778	* @arg @ref LL_RCC_PLLM_DIV_45
ganlikun	0:13413ea9a877	4779	* @arg @ref LL_RCC_PLLM_DIV_46
ganlikun	0:13413ea9a877	4780	* @arg @ref LL_RCC_PLLM_DIV_47
ganlikun	0:13413ea9a877	4781	* @arg @ref LL_RCC_PLLM_DIV_48
ganlikun	0:13413ea9a877	4782	* @arg @ref LL_RCC_PLLM_DIV_49
ganlikun	0:13413ea9a877	4783	* @arg @ref LL_RCC_PLLM_DIV_50
ganlikun	0:13413ea9a877	4784	* @arg @ref LL_RCC_PLLM_DIV_51
ganlikun	0:13413ea9a877	4785	* @arg @ref LL_RCC_PLLM_DIV_52
ganlikun	0:13413ea9a877	4786	* @arg @ref LL_RCC_PLLM_DIV_53
ganlikun	0:13413ea9a877	4787	* @arg @ref LL_RCC_PLLM_DIV_54
ganlikun	0:13413ea9a877	4788	* @arg @ref LL_RCC_PLLM_DIV_55
ganlikun	0:13413ea9a877	4789	* @arg @ref LL_RCC_PLLM_DIV_56
ganlikun	0:13413ea9a877	4790	* @arg @ref LL_RCC_PLLM_DIV_57
ganlikun	0:13413ea9a877	4791	* @arg @ref LL_RCC_PLLM_DIV_58
ganlikun	0:13413ea9a877	4792	* @arg @ref LL_RCC_PLLM_DIV_59
ganlikun	0:13413ea9a877	4793	* @arg @ref LL_RCC_PLLM_DIV_60
ganlikun	0:13413ea9a877	4794	* @arg @ref LL_RCC_PLLM_DIV_61
ganlikun	0:13413ea9a877	4795	* @arg @ref LL_RCC_PLLM_DIV_62
ganlikun	0:13413ea9a877	4796	* @arg @ref LL_RCC_PLLM_DIV_63
ganlikun	0:13413ea9a877	4797	* @param PLLN Between 50 and 432
ganlikun	0:13413ea9a877	4798	* @param PLLR This parameter can be one of the following values:
ganlikun	0:13413ea9a877	4799	* @arg @ref LL_RCC_PLLR_DIV_2
ganlikun	0:13413ea9a877	4800	* @arg @ref LL_RCC_PLLR_DIV_3
ganlikun	0:13413ea9a877	4801	* @arg @ref LL_RCC_PLLR_DIV_4
ganlikun	0:13413ea9a877	4802	* @arg @ref LL_RCC_PLLR_DIV_5
ganlikun	0:13413ea9a877	4803	* @arg @ref LL_RCC_PLLR_DIV_6
ganlikun	0:13413ea9a877	4804	* @arg @ref LL_RCC_PLLR_DIV_7
ganlikun	0:13413ea9a877	4805	* @param PLLDIVR This parameter can be one of the following values:
ganlikun	0:13413ea9a877	4806	* @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
ganlikun	0:13413ea9a877	4807	* @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
ganlikun	0:13413ea9a877	4808	* @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
ganlikun	0:13413ea9a877	4809	* @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
ganlikun	0:13413ea9a877	4810	* @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
ganlikun	0:13413ea9a877	4811	* @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
ganlikun	0:13413ea9a877	4812	* @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
ganlikun	0:13413ea9a877	4813	* @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
ganlikun	0:13413ea9a877	4814	* @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
ganlikun	0:13413ea9a877	4815	* @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
ganlikun	0:13413ea9a877	4816	* @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
ganlikun	0:13413ea9a877	4817	* @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
ganlikun	0:13413ea9a877	4818	* @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
ganlikun	0:13413ea9a877	4819	* @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
ganlikun	0:13413ea9a877	4820	* @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
ganlikun	0:13413ea9a877	4821	* @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
ganlikun	0:13413ea9a877	4822	* @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
ganlikun	0:13413ea9a877	4823	* @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
ganlikun	0:13413ea9a877	4824	* @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
ganlikun	0:13413ea9a877	4825	* @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
ganlikun	0:13413ea9a877	4826	* @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
ganlikun	0:13413ea9a877	4827	* @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
ganlikun	0:13413ea9a877	4828	* @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
ganlikun	0:13413ea9a877	4829	* @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
ganlikun	0:13413ea9a877	4830	* @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
ganlikun	0:13413ea9a877	4831	* @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
ganlikun	0:13413ea9a877	4832	* @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
ganlikun	0:13413ea9a877	4833	* @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
ganlikun	0:13413ea9a877	4834	* @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
ganlikun	0:13413ea9a877	4835	* @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
ganlikun	0:13413ea9a877	4836	* @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
ganlikun	0:13413ea9a877	4837	*
ganlikun	0:13413ea9a877	4838	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	4839	* @retval None
ganlikun	0:13413ea9a877	4840	*/
ganlikun	0:13413ea9a877	4841	#if defined(RCC_DCKCFGR_PLLDIVR)
ganlikun	0:13413ea9a877	4842	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
ganlikun	0:13413ea9a877	4843	#else
ganlikun	0:13413ea9a877	4844	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
ganlikun	0:13413ea9a877	4845	#endif /* RCC_DCKCFGR_PLLDIVR */
ganlikun	0:13413ea9a877	4846	{
ganlikun	0:13413ea9a877	4847	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
ganlikun	0:13413ea9a877	4848	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
ganlikun	0:13413ea9a877	4849	#if defined(RCC_DCKCFGR_PLLDIVR)
ganlikun	0:13413ea9a877	4850	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR);
ganlikun	0:13413ea9a877	4851	#endif /* RCC_DCKCFGR_PLLDIVR */
ganlikun	0:13413ea9a877	4852	}
ganlikun	0:13413ea9a877	4853	#endif /* SAI1 */
ganlikun	0:13413ea9a877	4854	#endif /* RCC_PLLCFGR_PLLR */
ganlikun	0:13413ea9a877	4855
ganlikun	0:13413ea9a877	4856	/**
ganlikun	0:13413ea9a877	4857	* @brief Get Main PLL multiplication factor for VCO
ganlikun	0:13413ea9a877	4858	* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
ganlikun	0:13413ea9a877	4859	* @retval Between 50/192(*) and 432
ganlikun	0:13413ea9a877	4860	*
ganlikun	0:13413ea9a877	4861	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	4862	*/
ganlikun	0:13413ea9a877	4863	__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
ganlikun	0:13413ea9a877	4864	{
ganlikun	0:13413ea9a877	4865	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
ganlikun	0:13413ea9a877	4866	}
ganlikun	0:13413ea9a877	4867
ganlikun	0:13413ea9a877	4868	/**
ganlikun	0:13413ea9a877	4869	* @brief Get Main PLL division factor for PLLP
ganlikun	0:13413ea9a877	4870	* @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
ganlikun	0:13413ea9a877	4871	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	4872	* @arg @ref LL_RCC_PLLP_DIV_2
ganlikun	0:13413ea9a877	4873	* @arg @ref LL_RCC_PLLP_DIV_4
ganlikun	0:13413ea9a877	4874	* @arg @ref LL_RCC_PLLP_DIV_6
ganlikun	0:13413ea9a877	4875	* @arg @ref LL_RCC_PLLP_DIV_8
ganlikun	0:13413ea9a877	4876	*/
ganlikun	0:13413ea9a877	4877	__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
ganlikun	0:13413ea9a877	4878	{
ganlikun	0:13413ea9a877	4879	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
ganlikun	0:13413ea9a877	4880	}
ganlikun	0:13413ea9a877	4881
ganlikun	0:13413ea9a877	4882	/**
ganlikun	0:13413ea9a877	4883	* @brief Get Main PLL division factor for PLLQ
ganlikun	0:13413ea9a877	4884	* @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock)
ganlikun	0:13413ea9a877	4885	* @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
ganlikun	0:13413ea9a877	4886	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	4887	* @arg @ref LL_RCC_PLLQ_DIV_2
ganlikun	0:13413ea9a877	4888	* @arg @ref LL_RCC_PLLQ_DIV_3
ganlikun	0:13413ea9a877	4889	* @arg @ref LL_RCC_PLLQ_DIV_4
ganlikun	0:13413ea9a877	4890	* @arg @ref LL_RCC_PLLQ_DIV_5
ganlikun	0:13413ea9a877	4891	* @arg @ref LL_RCC_PLLQ_DIV_6
ganlikun	0:13413ea9a877	4892	* @arg @ref LL_RCC_PLLQ_DIV_7
ganlikun	0:13413ea9a877	4893	* @arg @ref LL_RCC_PLLQ_DIV_8
ganlikun	0:13413ea9a877	4894	* @arg @ref LL_RCC_PLLQ_DIV_9
ganlikun	0:13413ea9a877	4895	* @arg @ref LL_RCC_PLLQ_DIV_10
ganlikun	0:13413ea9a877	4896	* @arg @ref LL_RCC_PLLQ_DIV_11
ganlikun	0:13413ea9a877	4897	* @arg @ref LL_RCC_PLLQ_DIV_12
ganlikun	0:13413ea9a877	4898	* @arg @ref LL_RCC_PLLQ_DIV_13
ganlikun	0:13413ea9a877	4899	* @arg @ref LL_RCC_PLLQ_DIV_14
ganlikun	0:13413ea9a877	4900	* @arg @ref LL_RCC_PLLQ_DIV_15
ganlikun	0:13413ea9a877	4901	*/
ganlikun	0:13413ea9a877	4902	__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
ganlikun	0:13413ea9a877	4903	{
ganlikun	0:13413ea9a877	4904	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
ganlikun	0:13413ea9a877	4905	}
ganlikun	0:13413ea9a877	4906
ganlikun	0:13413ea9a877	4907	#if defined(RCC_PLLCFGR_PLLR)
ganlikun	0:13413ea9a877	4908	/**
ganlikun	0:13413ea9a877	4909	* @brief Get Main PLL division factor for PLLR
ganlikun	0:13413ea9a877	4910	* @note used for PLLCLK (system clock)
ganlikun	0:13413ea9a877	4911	* @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
ganlikun	0:13413ea9a877	4912	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	4913	* @arg @ref LL_RCC_PLLR_DIV_2
ganlikun	0:13413ea9a877	4914	* @arg @ref LL_RCC_PLLR_DIV_3
ganlikun	0:13413ea9a877	4915	* @arg @ref LL_RCC_PLLR_DIV_4
ganlikun	0:13413ea9a877	4916	* @arg @ref LL_RCC_PLLR_DIV_5
ganlikun	0:13413ea9a877	4917	* @arg @ref LL_RCC_PLLR_DIV_6
ganlikun	0:13413ea9a877	4918	* @arg @ref LL_RCC_PLLR_DIV_7
ganlikun	0:13413ea9a877	4919	*/
ganlikun	0:13413ea9a877	4920	__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
ganlikun	0:13413ea9a877	4921	{
ganlikun	0:13413ea9a877	4922	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
ganlikun	0:13413ea9a877	4923	}
ganlikun	0:13413ea9a877	4924	#endif /* RCC_PLLCFGR_PLLR */
ganlikun	0:13413ea9a877	4925
ganlikun	0:13413ea9a877	4926	#if defined(RCC_DCKCFGR_PLLDIVR)
ganlikun	0:13413ea9a877	4927	/**
ganlikun	0:13413ea9a877	4928	* @brief Get Main PLL division factor for PLLDIVR
ganlikun	0:13413ea9a877	4929	* @note used for PLLSAICLK (SAI1 and SAI2 clock)
ganlikun	0:13413ea9a877	4930	* @rmtoll DCKCFGR PLLDIVR LL_RCC_PLL_GetDIVR
ganlikun	0:13413ea9a877	4931	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	4932	* @arg @ref LL_RCC_PLLDIVR_DIV_1
ganlikun	0:13413ea9a877	4933	* @arg @ref LL_RCC_PLLDIVR_DIV_2
ganlikun	0:13413ea9a877	4934	* @arg @ref LL_RCC_PLLDIVR_DIV_3
ganlikun	0:13413ea9a877	4935	* @arg @ref LL_RCC_PLLDIVR_DIV_4
ganlikun	0:13413ea9a877	4936	* @arg @ref LL_RCC_PLLDIVR_DIV_5
ganlikun	0:13413ea9a877	4937	* @arg @ref LL_RCC_PLLDIVR_DIV_6
ganlikun	0:13413ea9a877	4938	* @arg @ref LL_RCC_PLLDIVR_DIV_7
ganlikun	0:13413ea9a877	4939	* @arg @ref LL_RCC_PLLDIVR_DIV_8
ganlikun	0:13413ea9a877	4940	* @arg @ref LL_RCC_PLLDIVR_DIV_9
ganlikun	0:13413ea9a877	4941	* @arg @ref LL_RCC_PLLDIVR_DIV_10
ganlikun	0:13413ea9a877	4942	* @arg @ref LL_RCC_PLLDIVR_DIV_11
ganlikun	0:13413ea9a877	4943	* @arg @ref LL_RCC_PLLDIVR_DIV_12
ganlikun	0:13413ea9a877	4944	* @arg @ref LL_RCC_PLLDIVR_DIV_13
ganlikun	0:13413ea9a877	4945	* @arg @ref LL_RCC_PLLDIVR_DIV_14
ganlikun	0:13413ea9a877	4946	* @arg @ref LL_RCC_PLLDIVR_DIV_15
ganlikun	0:13413ea9a877	4947	* @arg @ref LL_RCC_PLLDIVR_DIV_16
ganlikun	0:13413ea9a877	4948	* @arg @ref LL_RCC_PLLDIVR_DIV_17
ganlikun	0:13413ea9a877	4949	* @arg @ref LL_RCC_PLLDIVR_DIV_18
ganlikun	0:13413ea9a877	4950	* @arg @ref LL_RCC_PLLDIVR_DIV_19
ganlikun	0:13413ea9a877	4951	* @arg @ref LL_RCC_PLLDIVR_DIV_20
ganlikun	0:13413ea9a877	4952	* @arg @ref LL_RCC_PLLDIVR_DIV_21
ganlikun	0:13413ea9a877	4953	* @arg @ref LL_RCC_PLLDIVR_DIV_22
ganlikun	0:13413ea9a877	4954	* @arg @ref LL_RCC_PLLDIVR_DIV_23
ganlikun	0:13413ea9a877	4955	* @arg @ref LL_RCC_PLLDIVR_DIV_24
ganlikun	0:13413ea9a877	4956	* @arg @ref LL_RCC_PLLDIVR_DIV_25
ganlikun	0:13413ea9a877	4957	* @arg @ref LL_RCC_PLLDIVR_DIV_26
ganlikun	0:13413ea9a877	4958	* @arg @ref LL_RCC_PLLDIVR_DIV_27
ganlikun	0:13413ea9a877	4959	* @arg @ref LL_RCC_PLLDIVR_DIV_28
ganlikun	0:13413ea9a877	4960	* @arg @ref LL_RCC_PLLDIVR_DIV_29
ganlikun	0:13413ea9a877	4961	* @arg @ref LL_RCC_PLLDIVR_DIV_30
ganlikun	0:13413ea9a877	4962	* @arg @ref LL_RCC_PLLDIVR_DIV_31
ganlikun	0:13413ea9a877	4963	*/
ganlikun	0:13413ea9a877	4964	__STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void)
ganlikun	0:13413ea9a877	4965	{
ganlikun	0:13413ea9a877	4966	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR));
ganlikun	0:13413ea9a877	4967	}
ganlikun	0:13413ea9a877	4968	#endif /* RCC_DCKCFGR_PLLDIVR */
ganlikun	0:13413ea9a877	4969
ganlikun	0:13413ea9a877	4970	/**
ganlikun	0:13413ea9a877	4971	* @brief Get the oscillator used as PLL clock source.
ganlikun	0:13413ea9a877	4972	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
ganlikun	0:13413ea9a877	4973	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	4974	* @arg @ref LL_RCC_PLLSOURCE_HSI
ganlikun	0:13413ea9a877	4975	* @arg @ref LL_RCC_PLLSOURCE_HSE
ganlikun	0:13413ea9a877	4976	*/
ganlikun	0:13413ea9a877	4977	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
ganlikun	0:13413ea9a877	4978	{
ganlikun	0:13413ea9a877	4979	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
ganlikun	0:13413ea9a877	4980	}
ganlikun	0:13413ea9a877	4981
ganlikun	0:13413ea9a877	4982	/**
ganlikun	0:13413ea9a877	4983	* @brief Get Division factor for the main PLL and other PLL
ganlikun	0:13413ea9a877	4984	* @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
ganlikun	0:13413ea9a877	4985	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	4986	* @arg @ref LL_RCC_PLLM_DIV_2
ganlikun	0:13413ea9a877	4987	* @arg @ref LL_RCC_PLLM_DIV_3
ganlikun	0:13413ea9a877	4988	* @arg @ref LL_RCC_PLLM_DIV_4
ganlikun	0:13413ea9a877	4989	* @arg @ref LL_RCC_PLLM_DIV_5
ganlikun	0:13413ea9a877	4990	* @arg @ref LL_RCC_PLLM_DIV_6
ganlikun	0:13413ea9a877	4991	* @arg @ref LL_RCC_PLLM_DIV_7
ganlikun	0:13413ea9a877	4992	* @arg @ref LL_RCC_PLLM_DIV_8
ganlikun	0:13413ea9a877	4993	* @arg @ref LL_RCC_PLLM_DIV_9
ganlikun	0:13413ea9a877	4994	* @arg @ref LL_RCC_PLLM_DIV_10
ganlikun	0:13413ea9a877	4995	* @arg @ref LL_RCC_PLLM_DIV_11
ganlikun	0:13413ea9a877	4996	* @arg @ref LL_RCC_PLLM_DIV_12
ganlikun	0:13413ea9a877	4997	* @arg @ref LL_RCC_PLLM_DIV_13
ganlikun	0:13413ea9a877	4998	* @arg @ref LL_RCC_PLLM_DIV_14
ganlikun	0:13413ea9a877	4999	* @arg @ref LL_RCC_PLLM_DIV_15
ganlikun	0:13413ea9a877	5000	* @arg @ref LL_RCC_PLLM_DIV_16
ganlikun	0:13413ea9a877	5001	* @arg @ref LL_RCC_PLLM_DIV_17
ganlikun	0:13413ea9a877	5002	* @arg @ref LL_RCC_PLLM_DIV_18
ganlikun	0:13413ea9a877	5003	* @arg @ref LL_RCC_PLLM_DIV_19
ganlikun	0:13413ea9a877	5004	* @arg @ref LL_RCC_PLLM_DIV_20
ganlikun	0:13413ea9a877	5005	* @arg @ref LL_RCC_PLLM_DIV_21
ganlikun	0:13413ea9a877	5006	* @arg @ref LL_RCC_PLLM_DIV_22
ganlikun	0:13413ea9a877	5007	* @arg @ref LL_RCC_PLLM_DIV_23
ganlikun	0:13413ea9a877	5008	* @arg @ref LL_RCC_PLLM_DIV_24
ganlikun	0:13413ea9a877	5009	* @arg @ref LL_RCC_PLLM_DIV_25
ganlikun	0:13413ea9a877	5010	* @arg @ref LL_RCC_PLLM_DIV_26
ganlikun	0:13413ea9a877	5011	* @arg @ref LL_RCC_PLLM_DIV_27
ganlikun	0:13413ea9a877	5012	* @arg @ref LL_RCC_PLLM_DIV_28
ganlikun	0:13413ea9a877	5013	* @arg @ref LL_RCC_PLLM_DIV_29
ganlikun	0:13413ea9a877	5014	* @arg @ref LL_RCC_PLLM_DIV_30
ganlikun	0:13413ea9a877	5015	* @arg @ref LL_RCC_PLLM_DIV_31
ganlikun	0:13413ea9a877	5016	* @arg @ref LL_RCC_PLLM_DIV_32
ganlikun	0:13413ea9a877	5017	* @arg @ref LL_RCC_PLLM_DIV_33
ganlikun	0:13413ea9a877	5018	* @arg @ref LL_RCC_PLLM_DIV_34
ganlikun	0:13413ea9a877	5019	* @arg @ref LL_RCC_PLLM_DIV_35
ganlikun	0:13413ea9a877	5020	* @arg @ref LL_RCC_PLLM_DIV_36
ganlikun	0:13413ea9a877	5021	* @arg @ref LL_RCC_PLLM_DIV_37
ganlikun	0:13413ea9a877	5022	* @arg @ref LL_RCC_PLLM_DIV_38
ganlikun	0:13413ea9a877	5023	* @arg @ref LL_RCC_PLLM_DIV_39
ganlikun	0:13413ea9a877	5024	* @arg @ref LL_RCC_PLLM_DIV_40
ganlikun	0:13413ea9a877	5025	* @arg @ref LL_RCC_PLLM_DIV_41
ganlikun	0:13413ea9a877	5026	* @arg @ref LL_RCC_PLLM_DIV_42
ganlikun	0:13413ea9a877	5027	* @arg @ref LL_RCC_PLLM_DIV_43
ganlikun	0:13413ea9a877	5028	* @arg @ref LL_RCC_PLLM_DIV_44
ganlikun	0:13413ea9a877	5029	* @arg @ref LL_RCC_PLLM_DIV_45
ganlikun	0:13413ea9a877	5030	* @arg @ref LL_RCC_PLLM_DIV_46
ganlikun	0:13413ea9a877	5031	* @arg @ref LL_RCC_PLLM_DIV_47
ganlikun	0:13413ea9a877	5032	* @arg @ref LL_RCC_PLLM_DIV_48
ganlikun	0:13413ea9a877	5033	* @arg @ref LL_RCC_PLLM_DIV_49
ganlikun	0:13413ea9a877	5034	* @arg @ref LL_RCC_PLLM_DIV_50
ganlikun	0:13413ea9a877	5035	* @arg @ref LL_RCC_PLLM_DIV_51
ganlikun	0:13413ea9a877	5036	* @arg @ref LL_RCC_PLLM_DIV_52
ganlikun	0:13413ea9a877	5037	* @arg @ref LL_RCC_PLLM_DIV_53
ganlikun	0:13413ea9a877	5038	* @arg @ref LL_RCC_PLLM_DIV_54
ganlikun	0:13413ea9a877	5039	* @arg @ref LL_RCC_PLLM_DIV_55
ganlikun	0:13413ea9a877	5040	* @arg @ref LL_RCC_PLLM_DIV_56
ganlikun	0:13413ea9a877	5041	* @arg @ref LL_RCC_PLLM_DIV_57
ganlikun	0:13413ea9a877	5042	* @arg @ref LL_RCC_PLLM_DIV_58
ganlikun	0:13413ea9a877	5043	* @arg @ref LL_RCC_PLLM_DIV_59
ganlikun	0:13413ea9a877	5044	* @arg @ref LL_RCC_PLLM_DIV_60
ganlikun	0:13413ea9a877	5045	* @arg @ref LL_RCC_PLLM_DIV_61
ganlikun	0:13413ea9a877	5046	* @arg @ref LL_RCC_PLLM_DIV_62
ganlikun	0:13413ea9a877	5047	* @arg @ref LL_RCC_PLLM_DIV_63
ganlikun	0:13413ea9a877	5048	*/
ganlikun	0:13413ea9a877	5049	__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
ganlikun	0:13413ea9a877	5050	{
ganlikun	0:13413ea9a877	5051	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
ganlikun	0:13413ea9a877	5052	}
ganlikun	0:13413ea9a877	5053
ganlikun	0:13413ea9a877	5054	/**
ganlikun	0:13413ea9a877	5055	* @brief Configure Spread Spectrum used for PLL
ganlikun	0:13413ea9a877	5056	* @note These bits must be written before enabling PLL
ganlikun	0:13413ea9a877	5057	* @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n
ganlikun	0:13413ea9a877	5058	* SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n
ganlikun	0:13413ea9a877	5059	* SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum
ganlikun	0:13413ea9a877	5060	* @param Mod Between Min_Data=0 and Max_Data=8191
ganlikun	0:13413ea9a877	5061	* @param Inc Between Min_Data=0 and Max_Data=32767
ganlikun	0:13413ea9a877	5062	* @param Sel This parameter can be one of the following values:
ganlikun	0:13413ea9a877	5063	* @arg @ref LL_RCC_SPREAD_SELECT_CENTER
ganlikun	0:13413ea9a877	5064	* @arg @ref LL_RCC_SPREAD_SELECT_DOWN
ganlikun	0:13413ea9a877	5065	* @retval None
ganlikun	0:13413ea9a877	5066	*/
ganlikun	0:13413ea9a877	5067	__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
ganlikun	0:13413ea9a877	5068	{
ganlikun	0:13413ea9a877	5069	MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER \| RCC_SSCGR_INCSTEP \| RCC_SSCGR_SPREADSEL, Mod \| (Inc << RCC_SSCGR_INCSTEP_Pos) \| Sel);
ganlikun	0:13413ea9a877	5070	}
ganlikun	0:13413ea9a877	5071
ganlikun	0:13413ea9a877	5072	/**
ganlikun	0:13413ea9a877	5073	* @brief Get Spread Spectrum Modulation Period for PLL
ganlikun	0:13413ea9a877	5074	* @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation
ganlikun	0:13413ea9a877	5075	* @retval Between Min_Data=0 and Max_Data=8191
ganlikun	0:13413ea9a877	5076	*/
ganlikun	0:13413ea9a877	5077	__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
ganlikun	0:13413ea9a877	5078	{
ganlikun	0:13413ea9a877	5079	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
ganlikun	0:13413ea9a877	5080	}
ganlikun	0:13413ea9a877	5081
ganlikun	0:13413ea9a877	5082	/**
ganlikun	0:13413ea9a877	5083	* @brief Get Spread Spectrum Incrementation Step for PLL
ganlikun	0:13413ea9a877	5084	* @note Must be written before enabling PLL
ganlikun	0:13413ea9a877	5085	* @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation
ganlikun	0:13413ea9a877	5086	* @retval Between Min_Data=0 and Max_Data=32767
ganlikun	0:13413ea9a877	5087	*/
ganlikun	0:13413ea9a877	5088	__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
ganlikun	0:13413ea9a877	5089	{
ganlikun	0:13413ea9a877	5090	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
ganlikun	0:13413ea9a877	5091	}
ganlikun	0:13413ea9a877	5092
ganlikun	0:13413ea9a877	5093	/**
ganlikun	0:13413ea9a877	5094	* @brief Get Spread Spectrum Selection for PLL
ganlikun	0:13413ea9a877	5095	* @note Must be written before enabling PLL
ganlikun	0:13413ea9a877	5096	* @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection
ganlikun	0:13413ea9a877	5097	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	5098	* @arg @ref LL_RCC_SPREAD_SELECT_CENTER
ganlikun	0:13413ea9a877	5099	* @arg @ref LL_RCC_SPREAD_SELECT_DOWN
ganlikun	0:13413ea9a877	5100	*/
ganlikun	0:13413ea9a877	5101	__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
ganlikun	0:13413ea9a877	5102	{
ganlikun	0:13413ea9a877	5103	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
ganlikun	0:13413ea9a877	5104	}
ganlikun	0:13413ea9a877	5105
ganlikun	0:13413ea9a877	5106	/**
ganlikun	0:13413ea9a877	5107	* @brief Enable Spread Spectrum for PLL.
ganlikun	0:13413ea9a877	5108	* @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable
ganlikun	0:13413ea9a877	5109	* @retval None
ganlikun	0:13413ea9a877	5110	*/
ganlikun	0:13413ea9a877	5111	__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
ganlikun	0:13413ea9a877	5112	{
ganlikun	0:13413ea9a877	5113	SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
ganlikun	0:13413ea9a877	5114	}
ganlikun	0:13413ea9a877	5115
ganlikun	0:13413ea9a877	5116	/**
ganlikun	0:13413ea9a877	5117	* @brief Disable Spread Spectrum for PLL.
ganlikun	0:13413ea9a877	5118	* @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable
ganlikun	0:13413ea9a877	5119	* @retval None
ganlikun	0:13413ea9a877	5120	*/
ganlikun	0:13413ea9a877	5121	__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
ganlikun	0:13413ea9a877	5122	{
ganlikun	0:13413ea9a877	5123	CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
ganlikun	0:13413ea9a877	5124	}
ganlikun	0:13413ea9a877	5125
ganlikun	0:13413ea9a877	5126	/**
ganlikun	0:13413ea9a877	5127	* @}
ganlikun	0:13413ea9a877	5128	*/
ganlikun	0:13413ea9a877	5129
ganlikun	0:13413ea9a877	5130	#if defined(RCC_PLLI2S_SUPPORT)
ganlikun	0:13413ea9a877	5131	/** @defgroup RCC_LL_EF_PLLI2S PLLI2S
ganlikun	0:13413ea9a877	5132	* @{
ganlikun	0:13413ea9a877	5133	*/
ganlikun	0:13413ea9a877	5134
ganlikun	0:13413ea9a877	5135	/**
ganlikun	0:13413ea9a877	5136	* @brief Enable PLLI2S
ganlikun	0:13413ea9a877	5137	* @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable
ganlikun	0:13413ea9a877	5138	* @retval None
ganlikun	0:13413ea9a877	5139	*/
ganlikun	0:13413ea9a877	5140	__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
ganlikun	0:13413ea9a877	5141	{
ganlikun	0:13413ea9a877	5142	SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
ganlikun	0:13413ea9a877	5143	}
ganlikun	0:13413ea9a877	5144
ganlikun	0:13413ea9a877	5145	/**
ganlikun	0:13413ea9a877	5146	* @brief Disable PLLI2S
ganlikun	0:13413ea9a877	5147	* @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable
ganlikun	0:13413ea9a877	5148	* @retval None
ganlikun	0:13413ea9a877	5149	*/
ganlikun	0:13413ea9a877	5150	__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
ganlikun	0:13413ea9a877	5151	{
ganlikun	0:13413ea9a877	5152	CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
ganlikun	0:13413ea9a877	5153	}
ganlikun	0:13413ea9a877	5154
ganlikun	0:13413ea9a877	5155	/**
ganlikun	0:13413ea9a877	5156	* @brief Check if PLLI2S Ready
ganlikun	0:13413ea9a877	5157	* @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady
ganlikun	0:13413ea9a877	5158	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	5159	*/
ganlikun	0:13413ea9a877	5160	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
ganlikun	0:13413ea9a877	5161	{
ganlikun	0:13413ea9a877	5162	return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
ganlikun	0:13413ea9a877	5163	}
ganlikun	0:13413ea9a877	5164
ganlikun	0:13413ea9a877	5165	#if (defined(RCC_DCKCFGR_PLLI2SDIVQ) \|\| defined(RCC_DCKCFGR_PLLI2SDIVR))
ganlikun	0:13413ea9a877	5166	/**
ganlikun	0:13413ea9a877	5167	* @brief Configure PLLI2S used for SAI domain clock
ganlikun	0:13413ea9a877	5168	* @note PLL Source and PLLM Divider can be written only when PLL,
ganlikun	0:13413ea9a877	5169	* PLLI2S and PLLSAI(*) are disabled
ganlikun	0:13413ea9a877	5170	* @note PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled
ganlikun	0:13413ea9a877	5171	* @note This can be selected for SAI
ganlikun	0:13413ea9a877	5172	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
ganlikun	0:13413ea9a877	5173	* PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
ganlikun	0:13413ea9a877	5174	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n
ganlikun	0:13413ea9a877	5175	* PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SAI\n
ganlikun	0:13413ea9a877	5176	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n
ganlikun	0:13413ea9a877	5177	* PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
ganlikun	0:13413ea9a877	5178	* PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_SAI\n
ganlikun	0:13413ea9a877	5179	* DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
ganlikun	0:13413ea9a877	5180	* DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_ConfigDomain_SAI
ganlikun	0:13413ea9a877	5181	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	5182	* @arg @ref LL_RCC_PLLSOURCE_HSI
ganlikun	0:13413ea9a877	5183	* @arg @ref LL_RCC_PLLSOURCE_HSE
ganlikun	0:13413ea9a877	5184	* @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
ganlikun	0:13413ea9a877	5185	*
ganlikun	0:13413ea9a877	5186	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	5187	* @param PLLM This parameter can be one of the following values:
ganlikun	0:13413ea9a877	5188	* @arg @ref LL_RCC_PLLI2SM_DIV_2
ganlikun	0:13413ea9a877	5189	* @arg @ref LL_RCC_PLLI2SM_DIV_3
ganlikun	0:13413ea9a877	5190	* @arg @ref LL_RCC_PLLI2SM_DIV_4
ganlikun	0:13413ea9a877	5191	* @arg @ref LL_RCC_PLLI2SM_DIV_5
ganlikun	0:13413ea9a877	5192	* @arg @ref LL_RCC_PLLI2SM_DIV_6
ganlikun	0:13413ea9a877	5193	* @arg @ref LL_RCC_PLLI2SM_DIV_7
ganlikun	0:13413ea9a877	5194	* @arg @ref LL_RCC_PLLI2SM_DIV_8
ganlikun	0:13413ea9a877	5195	* @arg @ref LL_RCC_PLLI2SM_DIV_9
ganlikun	0:13413ea9a877	5196	* @arg @ref LL_RCC_PLLI2SM_DIV_10
ganlikun	0:13413ea9a877	5197	* @arg @ref LL_RCC_PLLI2SM_DIV_11
ganlikun	0:13413ea9a877	5198	* @arg @ref LL_RCC_PLLI2SM_DIV_12
ganlikun	0:13413ea9a877	5199	* @arg @ref LL_RCC_PLLI2SM_DIV_13
ganlikun	0:13413ea9a877	5200	* @arg @ref LL_RCC_PLLI2SM_DIV_14
ganlikun	0:13413ea9a877	5201	* @arg @ref LL_RCC_PLLI2SM_DIV_15
ganlikun	0:13413ea9a877	5202	* @arg @ref LL_RCC_PLLI2SM_DIV_16
ganlikun	0:13413ea9a877	5203	* @arg @ref LL_RCC_PLLI2SM_DIV_17
ganlikun	0:13413ea9a877	5204	* @arg @ref LL_RCC_PLLI2SM_DIV_18
ganlikun	0:13413ea9a877	5205	* @arg @ref LL_RCC_PLLI2SM_DIV_19
ganlikun	0:13413ea9a877	5206	* @arg @ref LL_RCC_PLLI2SM_DIV_20
ganlikun	0:13413ea9a877	5207	* @arg @ref LL_RCC_PLLI2SM_DIV_21
ganlikun	0:13413ea9a877	5208	* @arg @ref LL_RCC_PLLI2SM_DIV_22
ganlikun	0:13413ea9a877	5209	* @arg @ref LL_RCC_PLLI2SM_DIV_23
ganlikun	0:13413ea9a877	5210	* @arg @ref LL_RCC_PLLI2SM_DIV_24
ganlikun	0:13413ea9a877	5211	* @arg @ref LL_RCC_PLLI2SM_DIV_25
ganlikun	0:13413ea9a877	5212	* @arg @ref LL_RCC_PLLI2SM_DIV_26
ganlikun	0:13413ea9a877	5213	* @arg @ref LL_RCC_PLLI2SM_DIV_27
ganlikun	0:13413ea9a877	5214	* @arg @ref LL_RCC_PLLI2SM_DIV_28
ganlikun	0:13413ea9a877	5215	* @arg @ref LL_RCC_PLLI2SM_DIV_29
ganlikun	0:13413ea9a877	5216	* @arg @ref LL_RCC_PLLI2SM_DIV_30
ganlikun	0:13413ea9a877	5217	* @arg @ref LL_RCC_PLLI2SM_DIV_31
ganlikun	0:13413ea9a877	5218	* @arg @ref LL_RCC_PLLI2SM_DIV_32
ganlikun	0:13413ea9a877	5219	* @arg @ref LL_RCC_PLLI2SM_DIV_33
ganlikun	0:13413ea9a877	5220	* @arg @ref LL_RCC_PLLI2SM_DIV_34
ganlikun	0:13413ea9a877	5221	* @arg @ref LL_RCC_PLLI2SM_DIV_35
ganlikun	0:13413ea9a877	5222	* @arg @ref LL_RCC_PLLI2SM_DIV_36
ganlikun	0:13413ea9a877	5223	* @arg @ref LL_RCC_PLLI2SM_DIV_37
ganlikun	0:13413ea9a877	5224	* @arg @ref LL_RCC_PLLI2SM_DIV_38
ganlikun	0:13413ea9a877	5225	* @arg @ref LL_RCC_PLLI2SM_DIV_39
ganlikun	0:13413ea9a877	5226	* @arg @ref LL_RCC_PLLI2SM_DIV_40
ganlikun	0:13413ea9a877	5227	* @arg @ref LL_RCC_PLLI2SM_DIV_41
ganlikun	0:13413ea9a877	5228	* @arg @ref LL_RCC_PLLI2SM_DIV_42
ganlikun	0:13413ea9a877	5229	* @arg @ref LL_RCC_PLLI2SM_DIV_43
ganlikun	0:13413ea9a877	5230	* @arg @ref LL_RCC_PLLI2SM_DIV_44
ganlikun	0:13413ea9a877	5231	* @arg @ref LL_RCC_PLLI2SM_DIV_45
ganlikun	0:13413ea9a877	5232	* @arg @ref LL_RCC_PLLI2SM_DIV_46
ganlikun	0:13413ea9a877	5233	* @arg @ref LL_RCC_PLLI2SM_DIV_47
ganlikun	0:13413ea9a877	5234	* @arg @ref LL_RCC_PLLI2SM_DIV_48
ganlikun	0:13413ea9a877	5235	* @arg @ref LL_RCC_PLLI2SM_DIV_49
ganlikun	0:13413ea9a877	5236	* @arg @ref LL_RCC_PLLI2SM_DIV_50
ganlikun	0:13413ea9a877	5237	* @arg @ref LL_RCC_PLLI2SM_DIV_51
ganlikun	0:13413ea9a877	5238	* @arg @ref LL_RCC_PLLI2SM_DIV_52
ganlikun	0:13413ea9a877	5239	* @arg @ref LL_RCC_PLLI2SM_DIV_53
ganlikun	0:13413ea9a877	5240	* @arg @ref LL_RCC_PLLI2SM_DIV_54
ganlikun	0:13413ea9a877	5241	* @arg @ref LL_RCC_PLLI2SM_DIV_55
ganlikun	0:13413ea9a877	5242	* @arg @ref LL_RCC_PLLI2SM_DIV_56
ganlikun	0:13413ea9a877	5243	* @arg @ref LL_RCC_PLLI2SM_DIV_57
ganlikun	0:13413ea9a877	5244	* @arg @ref LL_RCC_PLLI2SM_DIV_58
ganlikun	0:13413ea9a877	5245	* @arg @ref LL_RCC_PLLI2SM_DIV_59
ganlikun	0:13413ea9a877	5246	* @arg @ref LL_RCC_PLLI2SM_DIV_60
ganlikun	0:13413ea9a877	5247	* @arg @ref LL_RCC_PLLI2SM_DIV_61
ganlikun	0:13413ea9a877	5248	* @arg @ref LL_RCC_PLLI2SM_DIV_62
ganlikun	0:13413ea9a877	5249	* @arg @ref LL_RCC_PLLI2SM_DIV_63
ganlikun	0:13413ea9a877	5250	* @param PLLN Between 50/192(*) and 432
ganlikun	0:13413ea9a877	5251	*
ganlikun	0:13413ea9a877	5252	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	5253	* @param PLLQ_R This parameter can be one of the following values:
ganlikun	0:13413ea9a877	5254	* @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
ganlikun	0:13413ea9a877	5255	* @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
ganlikun	0:13413ea9a877	5256	* @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
ganlikun	0:13413ea9a877	5257	* @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
ganlikun	0:13413ea9a877	5258	* @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
ganlikun	0:13413ea9a877	5259	* @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
ganlikun	0:13413ea9a877	5260	* @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
ganlikun	0:13413ea9a877	5261	* @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
ganlikun	0:13413ea9a877	5262	* @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
ganlikun	0:13413ea9a877	5263	* @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
ganlikun	0:13413ea9a877	5264	* @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
ganlikun	0:13413ea9a877	5265	* @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
ganlikun	0:13413ea9a877	5266	* @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
ganlikun	0:13413ea9a877	5267	* @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
ganlikun	0:13413ea9a877	5268	* @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
ganlikun	0:13413ea9a877	5269	* @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
ganlikun	0:13413ea9a877	5270	* @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
ganlikun	0:13413ea9a877	5271	* @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
ganlikun	0:13413ea9a877	5272	* @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
ganlikun	0:13413ea9a877	5273	* @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
ganlikun	0:13413ea9a877	5274	*
ganlikun	0:13413ea9a877	5275	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	5276	* @param PLLDIVQ_R This parameter can be one of the following values:
ganlikun	0:13413ea9a877	5277	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
ganlikun	0:13413ea9a877	5278	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
ganlikun	0:13413ea9a877	5279	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
ganlikun	0:13413ea9a877	5280	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
ganlikun	0:13413ea9a877	5281	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
ganlikun	0:13413ea9a877	5282	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
ganlikun	0:13413ea9a877	5283	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
ganlikun	0:13413ea9a877	5284	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
ganlikun	0:13413ea9a877	5285	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
ganlikun	0:13413ea9a877	5286	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
ganlikun	0:13413ea9a877	5287	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
ganlikun	0:13413ea9a877	5288	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
ganlikun	0:13413ea9a877	5289	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
ganlikun	0:13413ea9a877	5290	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
ganlikun	0:13413ea9a877	5291	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
ganlikun	0:13413ea9a877	5292	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
ganlikun	0:13413ea9a877	5293	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
ganlikun	0:13413ea9a877	5294	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
ganlikun	0:13413ea9a877	5295	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
ganlikun	0:13413ea9a877	5296	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
ganlikun	0:13413ea9a877	5297	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
ganlikun	0:13413ea9a877	5298	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
ganlikun	0:13413ea9a877	5299	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
ganlikun	0:13413ea9a877	5300	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
ganlikun	0:13413ea9a877	5301	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
ganlikun	0:13413ea9a877	5302	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
ganlikun	0:13413ea9a877	5303	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
ganlikun	0:13413ea9a877	5304	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
ganlikun	0:13413ea9a877	5305	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
ganlikun	0:13413ea9a877	5306	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
ganlikun	0:13413ea9a877	5307	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
ganlikun	0:13413ea9a877	5308	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
ganlikun	0:13413ea9a877	5309	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
ganlikun	0:13413ea9a877	5310	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
ganlikun	0:13413ea9a877	5311	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
ganlikun	0:13413ea9a877	5312	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
ganlikun	0:13413ea9a877	5313	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
ganlikun	0:13413ea9a877	5314	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
ganlikun	0:13413ea9a877	5315	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
ganlikun	0:13413ea9a877	5316	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
ganlikun	0:13413ea9a877	5317	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
ganlikun	0:13413ea9a877	5318	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
ganlikun	0:13413ea9a877	5319	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
ganlikun	0:13413ea9a877	5320	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
ganlikun	0:13413ea9a877	5321	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
ganlikun	0:13413ea9a877	5322	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
ganlikun	0:13413ea9a877	5323	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
ganlikun	0:13413ea9a877	5324	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
ganlikun	0:13413ea9a877	5325	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
ganlikun	0:13413ea9a877	5326	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
ganlikun	0:13413ea9a877	5327	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
ganlikun	0:13413ea9a877	5328	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
ganlikun	0:13413ea9a877	5329	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
ganlikun	0:13413ea9a877	5330	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
ganlikun	0:13413ea9a877	5331	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
ganlikun	0:13413ea9a877	5332	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
ganlikun	0:13413ea9a877	5333	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
ganlikun	0:13413ea9a877	5334	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
ganlikun	0:13413ea9a877	5335	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
ganlikun	0:13413ea9a877	5336	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
ganlikun	0:13413ea9a877	5337	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
ganlikun	0:13413ea9a877	5338	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
ganlikun	0:13413ea9a877	5339	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
ganlikun	0:13413ea9a877	5340	*
ganlikun	0:13413ea9a877	5341	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	5342	* @retval None
ganlikun	0:13413ea9a877	5343	*/
ganlikun	0:13413ea9a877	5344	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R)
ganlikun	0:13413ea9a877	5345	{
ganlikun	0:13413ea9a877	5346	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
ganlikun	0:13413ea9a877	5347	MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
ganlikun	0:13413ea9a877	5348	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
ganlikun	0:13413ea9a877	5349	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
ganlikun	0:13413ea9a877	5350	#else
ganlikun	0:13413ea9a877	5351	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
ganlikun	0:13413ea9a877	5352	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
ganlikun	0:13413ea9a877	5353	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos);
ganlikun	0:13413ea9a877	5354	#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
ganlikun	0:13413ea9a877	5355	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R);
ganlikun	0:13413ea9a877	5356	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R);
ganlikun	0:13413ea9a877	5357	#else
ganlikun	0:13413ea9a877	5358	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R);
ganlikun	0:13413ea9a877	5359	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R);
ganlikun	0:13413ea9a877	5360	#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
ganlikun	0:13413ea9a877	5361	}
ganlikun	0:13413ea9a877	5362	#endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */
ganlikun	0:13413ea9a877	5363
ganlikun	0:13413ea9a877	5364	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
ganlikun	0:13413ea9a877	5365	/**
ganlikun	0:13413ea9a877	5366	* @brief Configure PLLI2S used for 48Mhz domain clock
ganlikun	0:13413ea9a877	5367	* @note PLL Source and PLLM Divider can be written only when PLL,
ganlikun	0:13413ea9a877	5368	* PLLI2S and PLLSAI(*) are disabled
ganlikun	0:13413ea9a877	5369	* @note PLLN/PLLQ can be written only when PLLI2S is disabled
ganlikun	0:13413ea9a877	5370	* @note This can be selected for RNG, USB, SDIO
ganlikun	0:13413ea9a877	5371	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_48M\n
ganlikun	0:13413ea9a877	5372	* PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_48M\n
ganlikun	0:13413ea9a877	5373	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_48M\n
ganlikun	0:13413ea9a877	5374	* PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_48M\n
ganlikun	0:13413ea9a877	5375	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_48M\n
ganlikun	0:13413ea9a877	5376	* PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_48M
ganlikun	0:13413ea9a877	5377	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	5378	* @arg @ref LL_RCC_PLLSOURCE_HSI
ganlikun	0:13413ea9a877	5379	* @arg @ref LL_RCC_PLLSOURCE_HSE
ganlikun	0:13413ea9a877	5380	* @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
ganlikun	0:13413ea9a877	5381	*
ganlikun	0:13413ea9a877	5382	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	5383	* @param PLLM This parameter can be one of the following values:
ganlikun	0:13413ea9a877	5384	* @arg @ref LL_RCC_PLLI2SM_DIV_2
ganlikun	0:13413ea9a877	5385	* @arg @ref LL_RCC_PLLI2SM_DIV_3
ganlikun	0:13413ea9a877	5386	* @arg @ref LL_RCC_PLLI2SM_DIV_4
ganlikun	0:13413ea9a877	5387	* @arg @ref LL_RCC_PLLI2SM_DIV_5
ganlikun	0:13413ea9a877	5388	* @arg @ref LL_RCC_PLLI2SM_DIV_6
ganlikun	0:13413ea9a877	5389	* @arg @ref LL_RCC_PLLI2SM_DIV_7
ganlikun	0:13413ea9a877	5390	* @arg @ref LL_RCC_PLLI2SM_DIV_8
ganlikun	0:13413ea9a877	5391	* @arg @ref LL_RCC_PLLI2SM_DIV_9
ganlikun	0:13413ea9a877	5392	* @arg @ref LL_RCC_PLLI2SM_DIV_10
ganlikun	0:13413ea9a877	5393	* @arg @ref LL_RCC_PLLI2SM_DIV_11
ganlikun	0:13413ea9a877	5394	* @arg @ref LL_RCC_PLLI2SM_DIV_12
ganlikun	0:13413ea9a877	5395	* @arg @ref LL_RCC_PLLI2SM_DIV_13
ganlikun	0:13413ea9a877	5396	* @arg @ref LL_RCC_PLLI2SM_DIV_14
ganlikun	0:13413ea9a877	5397	* @arg @ref LL_RCC_PLLI2SM_DIV_15
ganlikun	0:13413ea9a877	5398	* @arg @ref LL_RCC_PLLI2SM_DIV_16
ganlikun	0:13413ea9a877	5399	* @arg @ref LL_RCC_PLLI2SM_DIV_17
ganlikun	0:13413ea9a877	5400	* @arg @ref LL_RCC_PLLI2SM_DIV_18
ganlikun	0:13413ea9a877	5401	* @arg @ref LL_RCC_PLLI2SM_DIV_19
ganlikun	0:13413ea9a877	5402	* @arg @ref LL_RCC_PLLI2SM_DIV_20
ganlikun	0:13413ea9a877	5403	* @arg @ref LL_RCC_PLLI2SM_DIV_21
ganlikun	0:13413ea9a877	5404	* @arg @ref LL_RCC_PLLI2SM_DIV_22
ganlikun	0:13413ea9a877	5405	* @arg @ref LL_RCC_PLLI2SM_DIV_23
ganlikun	0:13413ea9a877	5406	* @arg @ref LL_RCC_PLLI2SM_DIV_24
ganlikun	0:13413ea9a877	5407	* @arg @ref LL_RCC_PLLI2SM_DIV_25
ganlikun	0:13413ea9a877	5408	* @arg @ref LL_RCC_PLLI2SM_DIV_26
ganlikun	0:13413ea9a877	5409	* @arg @ref LL_RCC_PLLI2SM_DIV_27
ganlikun	0:13413ea9a877	5410	* @arg @ref LL_RCC_PLLI2SM_DIV_28
ganlikun	0:13413ea9a877	5411	* @arg @ref LL_RCC_PLLI2SM_DIV_29
ganlikun	0:13413ea9a877	5412	* @arg @ref LL_RCC_PLLI2SM_DIV_30
ganlikun	0:13413ea9a877	5413	* @arg @ref LL_RCC_PLLI2SM_DIV_31
ganlikun	0:13413ea9a877	5414	* @arg @ref LL_RCC_PLLI2SM_DIV_32
ganlikun	0:13413ea9a877	5415	* @arg @ref LL_RCC_PLLI2SM_DIV_33
ganlikun	0:13413ea9a877	5416	* @arg @ref LL_RCC_PLLI2SM_DIV_34
ganlikun	0:13413ea9a877	5417	* @arg @ref LL_RCC_PLLI2SM_DIV_35
ganlikun	0:13413ea9a877	5418	* @arg @ref LL_RCC_PLLI2SM_DIV_36
ganlikun	0:13413ea9a877	5419	* @arg @ref LL_RCC_PLLI2SM_DIV_37
ganlikun	0:13413ea9a877	5420	* @arg @ref LL_RCC_PLLI2SM_DIV_38
ganlikun	0:13413ea9a877	5421	* @arg @ref LL_RCC_PLLI2SM_DIV_39
ganlikun	0:13413ea9a877	5422	* @arg @ref LL_RCC_PLLI2SM_DIV_40
ganlikun	0:13413ea9a877	5423	* @arg @ref LL_RCC_PLLI2SM_DIV_41
ganlikun	0:13413ea9a877	5424	* @arg @ref LL_RCC_PLLI2SM_DIV_42
ganlikun	0:13413ea9a877	5425	* @arg @ref LL_RCC_PLLI2SM_DIV_43
ganlikun	0:13413ea9a877	5426	* @arg @ref LL_RCC_PLLI2SM_DIV_44
ganlikun	0:13413ea9a877	5427	* @arg @ref LL_RCC_PLLI2SM_DIV_45
ganlikun	0:13413ea9a877	5428	* @arg @ref LL_RCC_PLLI2SM_DIV_46
ganlikun	0:13413ea9a877	5429	* @arg @ref LL_RCC_PLLI2SM_DIV_47
ganlikun	0:13413ea9a877	5430	* @arg @ref LL_RCC_PLLI2SM_DIV_48
ganlikun	0:13413ea9a877	5431	* @arg @ref LL_RCC_PLLI2SM_DIV_49
ganlikun	0:13413ea9a877	5432	* @arg @ref LL_RCC_PLLI2SM_DIV_50
ganlikun	0:13413ea9a877	5433	* @arg @ref LL_RCC_PLLI2SM_DIV_51
ganlikun	0:13413ea9a877	5434	* @arg @ref LL_RCC_PLLI2SM_DIV_52
ganlikun	0:13413ea9a877	5435	* @arg @ref LL_RCC_PLLI2SM_DIV_53
ganlikun	0:13413ea9a877	5436	* @arg @ref LL_RCC_PLLI2SM_DIV_54
ganlikun	0:13413ea9a877	5437	* @arg @ref LL_RCC_PLLI2SM_DIV_55
ganlikun	0:13413ea9a877	5438	* @arg @ref LL_RCC_PLLI2SM_DIV_56
ganlikun	0:13413ea9a877	5439	* @arg @ref LL_RCC_PLLI2SM_DIV_57
ganlikun	0:13413ea9a877	5440	* @arg @ref LL_RCC_PLLI2SM_DIV_58
ganlikun	0:13413ea9a877	5441	* @arg @ref LL_RCC_PLLI2SM_DIV_59
ganlikun	0:13413ea9a877	5442	* @arg @ref LL_RCC_PLLI2SM_DIV_60
ganlikun	0:13413ea9a877	5443	* @arg @ref LL_RCC_PLLI2SM_DIV_61
ganlikun	0:13413ea9a877	5444	* @arg @ref LL_RCC_PLLI2SM_DIV_62
ganlikun	0:13413ea9a877	5445	* @arg @ref LL_RCC_PLLI2SM_DIV_63
ganlikun	0:13413ea9a877	5446	* @param PLLN Between 50 and 432
ganlikun	0:13413ea9a877	5447	* @param PLLQ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	5448	* @arg @ref LL_RCC_PLLI2SQ_DIV_2
ganlikun	0:13413ea9a877	5449	* @arg @ref LL_RCC_PLLI2SQ_DIV_3
ganlikun	0:13413ea9a877	5450	* @arg @ref LL_RCC_PLLI2SQ_DIV_4
ganlikun	0:13413ea9a877	5451	* @arg @ref LL_RCC_PLLI2SQ_DIV_5
ganlikun	0:13413ea9a877	5452	* @arg @ref LL_RCC_PLLI2SQ_DIV_6
ganlikun	0:13413ea9a877	5453	* @arg @ref LL_RCC_PLLI2SQ_DIV_7
ganlikun	0:13413ea9a877	5454	* @arg @ref LL_RCC_PLLI2SQ_DIV_8
ganlikun	0:13413ea9a877	5455	* @arg @ref LL_RCC_PLLI2SQ_DIV_9
ganlikun	0:13413ea9a877	5456	* @arg @ref LL_RCC_PLLI2SQ_DIV_10
ganlikun	0:13413ea9a877	5457	* @arg @ref LL_RCC_PLLI2SQ_DIV_11
ganlikun	0:13413ea9a877	5458	* @arg @ref LL_RCC_PLLI2SQ_DIV_12
ganlikun	0:13413ea9a877	5459	* @arg @ref LL_RCC_PLLI2SQ_DIV_13
ganlikun	0:13413ea9a877	5460	* @arg @ref LL_RCC_PLLI2SQ_DIV_14
ganlikun	0:13413ea9a877	5461	* @arg @ref LL_RCC_PLLI2SQ_DIV_15
ganlikun	0:13413ea9a877	5462	* @retval None
ganlikun	0:13413ea9a877	5463	*/
ganlikun	0:13413ea9a877	5464	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
ganlikun	0:13413ea9a877	5465	{
ganlikun	0:13413ea9a877	5466	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
ganlikun	0:13413ea9a877	5467	MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
ganlikun	0:13413ea9a877	5468	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
ganlikun	0:13413ea9a877	5469	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
ganlikun	0:13413ea9a877	5470	#else
ganlikun	0:13413ea9a877	5471	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
ganlikun	0:13413ea9a877	5472	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
ganlikun	0:13413ea9a877	5473	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN \| RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos \| PLLQ);
ganlikun	0:13413ea9a877	5474	}
ganlikun	0:13413ea9a877	5475	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
ganlikun	0:13413ea9a877	5476
ganlikun	0:13413ea9a877	5477	#if defined(SPDIFRX)
ganlikun	0:13413ea9a877	5478	/**
ganlikun	0:13413ea9a877	5479	* @brief Configure PLLI2S used for SPDIFRX domain clock
ganlikun	0:13413ea9a877	5480	* @note PLL Source and PLLM Divider can be written only when PLL,
ganlikun	0:13413ea9a877	5481	* PLLI2S and PLLSAI(*) are disabled
ganlikun	0:13413ea9a877	5482	* @note PLLN/PLLP can be written only when PLLI2S is disabled
ganlikun	0:13413ea9a877	5483	* @note This can be selected for SPDIFRX
ganlikun	0:13413ea9a877	5484	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
ganlikun	0:13413ea9a877	5485	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
ganlikun	0:13413ea9a877	5486	* PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
ganlikun	0:13413ea9a877	5487	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
ganlikun	0:13413ea9a877	5488	* PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
ganlikun	0:13413ea9a877	5489	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	5490	* @arg @ref LL_RCC_PLLSOURCE_HSI
ganlikun	0:13413ea9a877	5491	* @arg @ref LL_RCC_PLLSOURCE_HSE
ganlikun	0:13413ea9a877	5492	* @param PLLM This parameter can be one of the following values:
ganlikun	0:13413ea9a877	5493	* @arg @ref LL_RCC_PLLI2SM_DIV_2
ganlikun	0:13413ea9a877	5494	* @arg @ref LL_RCC_PLLI2SM_DIV_3
ganlikun	0:13413ea9a877	5495	* @arg @ref LL_RCC_PLLI2SM_DIV_4
ganlikun	0:13413ea9a877	5496	* @arg @ref LL_RCC_PLLI2SM_DIV_5
ganlikun	0:13413ea9a877	5497	* @arg @ref LL_RCC_PLLI2SM_DIV_6
ganlikun	0:13413ea9a877	5498	* @arg @ref LL_RCC_PLLI2SM_DIV_7
ganlikun	0:13413ea9a877	5499	* @arg @ref LL_RCC_PLLI2SM_DIV_8
ganlikun	0:13413ea9a877	5500	* @arg @ref LL_RCC_PLLI2SM_DIV_9
ganlikun	0:13413ea9a877	5501	* @arg @ref LL_RCC_PLLI2SM_DIV_10
ganlikun	0:13413ea9a877	5502	* @arg @ref LL_RCC_PLLI2SM_DIV_11
ganlikun	0:13413ea9a877	5503	* @arg @ref LL_RCC_PLLI2SM_DIV_12
ganlikun	0:13413ea9a877	5504	* @arg @ref LL_RCC_PLLI2SM_DIV_13
ganlikun	0:13413ea9a877	5505	* @arg @ref LL_RCC_PLLI2SM_DIV_14
ganlikun	0:13413ea9a877	5506	* @arg @ref LL_RCC_PLLI2SM_DIV_15
ganlikun	0:13413ea9a877	5507	* @arg @ref LL_RCC_PLLI2SM_DIV_16
ganlikun	0:13413ea9a877	5508	* @arg @ref LL_RCC_PLLI2SM_DIV_17
ganlikun	0:13413ea9a877	5509	* @arg @ref LL_RCC_PLLI2SM_DIV_18
ganlikun	0:13413ea9a877	5510	* @arg @ref LL_RCC_PLLI2SM_DIV_19
ganlikun	0:13413ea9a877	5511	* @arg @ref LL_RCC_PLLI2SM_DIV_20
ganlikun	0:13413ea9a877	5512	* @arg @ref LL_RCC_PLLI2SM_DIV_21
ganlikun	0:13413ea9a877	5513	* @arg @ref LL_RCC_PLLI2SM_DIV_22
ganlikun	0:13413ea9a877	5514	* @arg @ref LL_RCC_PLLI2SM_DIV_23
ganlikun	0:13413ea9a877	5515	* @arg @ref LL_RCC_PLLI2SM_DIV_24
ganlikun	0:13413ea9a877	5516	* @arg @ref LL_RCC_PLLI2SM_DIV_25
ganlikun	0:13413ea9a877	5517	* @arg @ref LL_RCC_PLLI2SM_DIV_26
ganlikun	0:13413ea9a877	5518	* @arg @ref LL_RCC_PLLI2SM_DIV_27
ganlikun	0:13413ea9a877	5519	* @arg @ref LL_RCC_PLLI2SM_DIV_28
ganlikun	0:13413ea9a877	5520	* @arg @ref LL_RCC_PLLI2SM_DIV_29
ganlikun	0:13413ea9a877	5521	* @arg @ref LL_RCC_PLLI2SM_DIV_30
ganlikun	0:13413ea9a877	5522	* @arg @ref LL_RCC_PLLI2SM_DIV_31
ganlikun	0:13413ea9a877	5523	* @arg @ref LL_RCC_PLLI2SM_DIV_32
ganlikun	0:13413ea9a877	5524	* @arg @ref LL_RCC_PLLI2SM_DIV_33
ganlikun	0:13413ea9a877	5525	* @arg @ref LL_RCC_PLLI2SM_DIV_34
ganlikun	0:13413ea9a877	5526	* @arg @ref LL_RCC_PLLI2SM_DIV_35
ganlikun	0:13413ea9a877	5527	* @arg @ref LL_RCC_PLLI2SM_DIV_36
ganlikun	0:13413ea9a877	5528	* @arg @ref LL_RCC_PLLI2SM_DIV_37
ganlikun	0:13413ea9a877	5529	* @arg @ref LL_RCC_PLLI2SM_DIV_38
ganlikun	0:13413ea9a877	5530	* @arg @ref LL_RCC_PLLI2SM_DIV_39
ganlikun	0:13413ea9a877	5531	* @arg @ref LL_RCC_PLLI2SM_DIV_40
ganlikun	0:13413ea9a877	5532	* @arg @ref LL_RCC_PLLI2SM_DIV_41
ganlikun	0:13413ea9a877	5533	* @arg @ref LL_RCC_PLLI2SM_DIV_42
ganlikun	0:13413ea9a877	5534	* @arg @ref LL_RCC_PLLI2SM_DIV_43
ganlikun	0:13413ea9a877	5535	* @arg @ref LL_RCC_PLLI2SM_DIV_44
ganlikun	0:13413ea9a877	5536	* @arg @ref LL_RCC_PLLI2SM_DIV_45
ganlikun	0:13413ea9a877	5537	* @arg @ref LL_RCC_PLLI2SM_DIV_46
ganlikun	0:13413ea9a877	5538	* @arg @ref LL_RCC_PLLI2SM_DIV_47
ganlikun	0:13413ea9a877	5539	* @arg @ref LL_RCC_PLLI2SM_DIV_48
ganlikun	0:13413ea9a877	5540	* @arg @ref LL_RCC_PLLI2SM_DIV_49
ganlikun	0:13413ea9a877	5541	* @arg @ref LL_RCC_PLLI2SM_DIV_50
ganlikun	0:13413ea9a877	5542	* @arg @ref LL_RCC_PLLI2SM_DIV_51
ganlikun	0:13413ea9a877	5543	* @arg @ref LL_RCC_PLLI2SM_DIV_52
ganlikun	0:13413ea9a877	5544	* @arg @ref LL_RCC_PLLI2SM_DIV_53
ganlikun	0:13413ea9a877	5545	* @arg @ref LL_RCC_PLLI2SM_DIV_54
ganlikun	0:13413ea9a877	5546	* @arg @ref LL_RCC_PLLI2SM_DIV_55
ganlikun	0:13413ea9a877	5547	* @arg @ref LL_RCC_PLLI2SM_DIV_56
ganlikun	0:13413ea9a877	5548	* @arg @ref LL_RCC_PLLI2SM_DIV_57
ganlikun	0:13413ea9a877	5549	* @arg @ref LL_RCC_PLLI2SM_DIV_58
ganlikun	0:13413ea9a877	5550	* @arg @ref LL_RCC_PLLI2SM_DIV_59
ganlikun	0:13413ea9a877	5551	* @arg @ref LL_RCC_PLLI2SM_DIV_60
ganlikun	0:13413ea9a877	5552	* @arg @ref LL_RCC_PLLI2SM_DIV_61
ganlikun	0:13413ea9a877	5553	* @arg @ref LL_RCC_PLLI2SM_DIV_62
ganlikun	0:13413ea9a877	5554	* @arg @ref LL_RCC_PLLI2SM_DIV_63
ganlikun	0:13413ea9a877	5555	* @param PLLN Between 50 and 432
ganlikun	0:13413ea9a877	5556	* @param PLLP This parameter can be one of the following values:
ganlikun	0:13413ea9a877	5557	* @arg @ref LL_RCC_PLLI2SP_DIV_2
ganlikun	0:13413ea9a877	5558	* @arg @ref LL_RCC_PLLI2SP_DIV_4
ganlikun	0:13413ea9a877	5559	* @arg @ref LL_RCC_PLLI2SP_DIV_6
ganlikun	0:13413ea9a877	5560	* @arg @ref LL_RCC_PLLI2SP_DIV_8
ganlikun	0:13413ea9a877	5561	* @retval None
ganlikun	0:13413ea9a877	5562	*/
ganlikun	0:13413ea9a877	5563	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
ganlikun	0:13413ea9a877	5564	{
ganlikun	0:13413ea9a877	5565	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
ganlikun	0:13413ea9a877	5566	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
ganlikun	0:13413ea9a877	5567	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
ganlikun	0:13413ea9a877	5568	#else
ganlikun	0:13413ea9a877	5569	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
ganlikun	0:13413ea9a877	5570	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
ganlikun	0:13413ea9a877	5571	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN \| RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos \| PLLP);
ganlikun	0:13413ea9a877	5572	}
ganlikun	0:13413ea9a877	5573	#endif /* SPDIFRX */
ganlikun	0:13413ea9a877	5574
ganlikun	0:13413ea9a877	5575	/**
ganlikun	0:13413ea9a877	5576	* @brief Configure PLLI2S used for I2S1 domain clock
ganlikun	0:13413ea9a877	5577	* @note PLL Source and PLLM Divider can be written only when PLL,
ganlikun	0:13413ea9a877	5578	* PLLI2S and PLLSAI(*) are disabled
ganlikun	0:13413ea9a877	5579	* @note PLLN/PLLR can be written only when PLLI2S is disabled
ganlikun	0:13413ea9a877	5580	* @note This can be selected for I2S
ganlikun	0:13413ea9a877	5581	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
ganlikun	0:13413ea9a877	5582	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n
ganlikun	0:13413ea9a877	5583	* PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
ganlikun	0:13413ea9a877	5584	* PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_I2S\n
ganlikun	0:13413ea9a877	5585	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n
ganlikun	0:13413ea9a877	5586	* PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S
ganlikun	0:13413ea9a877	5587	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	5588	* @arg @ref LL_RCC_PLLSOURCE_HSI
ganlikun	0:13413ea9a877	5589	* @arg @ref LL_RCC_PLLSOURCE_HSE
ganlikun	0:13413ea9a877	5590	* @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
ganlikun	0:13413ea9a877	5591	*
ganlikun	0:13413ea9a877	5592	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	5593	* @param PLLM This parameter can be one of the following values:
ganlikun	0:13413ea9a877	5594	* @arg @ref LL_RCC_PLLI2SM_DIV_2
ganlikun	0:13413ea9a877	5595	* @arg @ref LL_RCC_PLLI2SM_DIV_3
ganlikun	0:13413ea9a877	5596	* @arg @ref LL_RCC_PLLI2SM_DIV_4
ganlikun	0:13413ea9a877	5597	* @arg @ref LL_RCC_PLLI2SM_DIV_5
ganlikun	0:13413ea9a877	5598	* @arg @ref LL_RCC_PLLI2SM_DIV_6
ganlikun	0:13413ea9a877	5599	* @arg @ref LL_RCC_PLLI2SM_DIV_7
ganlikun	0:13413ea9a877	5600	* @arg @ref LL_RCC_PLLI2SM_DIV_8
ganlikun	0:13413ea9a877	5601	* @arg @ref LL_RCC_PLLI2SM_DIV_9
ganlikun	0:13413ea9a877	5602	* @arg @ref LL_RCC_PLLI2SM_DIV_10
ganlikun	0:13413ea9a877	5603	* @arg @ref LL_RCC_PLLI2SM_DIV_11
ganlikun	0:13413ea9a877	5604	* @arg @ref LL_RCC_PLLI2SM_DIV_12
ganlikun	0:13413ea9a877	5605	* @arg @ref LL_RCC_PLLI2SM_DIV_13
ganlikun	0:13413ea9a877	5606	* @arg @ref LL_RCC_PLLI2SM_DIV_14
ganlikun	0:13413ea9a877	5607	* @arg @ref LL_RCC_PLLI2SM_DIV_15
ganlikun	0:13413ea9a877	5608	* @arg @ref LL_RCC_PLLI2SM_DIV_16
ganlikun	0:13413ea9a877	5609	* @arg @ref LL_RCC_PLLI2SM_DIV_17
ganlikun	0:13413ea9a877	5610	* @arg @ref LL_RCC_PLLI2SM_DIV_18
ganlikun	0:13413ea9a877	5611	* @arg @ref LL_RCC_PLLI2SM_DIV_19
ganlikun	0:13413ea9a877	5612	* @arg @ref LL_RCC_PLLI2SM_DIV_20
ganlikun	0:13413ea9a877	5613	* @arg @ref LL_RCC_PLLI2SM_DIV_21
ganlikun	0:13413ea9a877	5614	* @arg @ref LL_RCC_PLLI2SM_DIV_22
ganlikun	0:13413ea9a877	5615	* @arg @ref LL_RCC_PLLI2SM_DIV_23
ganlikun	0:13413ea9a877	5616	* @arg @ref LL_RCC_PLLI2SM_DIV_24
ganlikun	0:13413ea9a877	5617	* @arg @ref LL_RCC_PLLI2SM_DIV_25
ganlikun	0:13413ea9a877	5618	* @arg @ref LL_RCC_PLLI2SM_DIV_26
ganlikun	0:13413ea9a877	5619	* @arg @ref LL_RCC_PLLI2SM_DIV_27
ganlikun	0:13413ea9a877	5620	* @arg @ref LL_RCC_PLLI2SM_DIV_28
ganlikun	0:13413ea9a877	5621	* @arg @ref LL_RCC_PLLI2SM_DIV_29
ganlikun	0:13413ea9a877	5622	* @arg @ref LL_RCC_PLLI2SM_DIV_30
ganlikun	0:13413ea9a877	5623	* @arg @ref LL_RCC_PLLI2SM_DIV_31
ganlikun	0:13413ea9a877	5624	* @arg @ref LL_RCC_PLLI2SM_DIV_32
ganlikun	0:13413ea9a877	5625	* @arg @ref LL_RCC_PLLI2SM_DIV_33
ganlikun	0:13413ea9a877	5626	* @arg @ref LL_RCC_PLLI2SM_DIV_34
ganlikun	0:13413ea9a877	5627	* @arg @ref LL_RCC_PLLI2SM_DIV_35
ganlikun	0:13413ea9a877	5628	* @arg @ref LL_RCC_PLLI2SM_DIV_36
ganlikun	0:13413ea9a877	5629	* @arg @ref LL_RCC_PLLI2SM_DIV_37
ganlikun	0:13413ea9a877	5630	* @arg @ref LL_RCC_PLLI2SM_DIV_38
ganlikun	0:13413ea9a877	5631	* @arg @ref LL_RCC_PLLI2SM_DIV_39
ganlikun	0:13413ea9a877	5632	* @arg @ref LL_RCC_PLLI2SM_DIV_40
ganlikun	0:13413ea9a877	5633	* @arg @ref LL_RCC_PLLI2SM_DIV_41
ganlikun	0:13413ea9a877	5634	* @arg @ref LL_RCC_PLLI2SM_DIV_42
ganlikun	0:13413ea9a877	5635	* @arg @ref LL_RCC_PLLI2SM_DIV_43
ganlikun	0:13413ea9a877	5636	* @arg @ref LL_RCC_PLLI2SM_DIV_44
ganlikun	0:13413ea9a877	5637	* @arg @ref LL_RCC_PLLI2SM_DIV_45
ganlikun	0:13413ea9a877	5638	* @arg @ref LL_RCC_PLLI2SM_DIV_46
ganlikun	0:13413ea9a877	5639	* @arg @ref LL_RCC_PLLI2SM_DIV_47
ganlikun	0:13413ea9a877	5640	* @arg @ref LL_RCC_PLLI2SM_DIV_48
ganlikun	0:13413ea9a877	5641	* @arg @ref LL_RCC_PLLI2SM_DIV_49
ganlikun	0:13413ea9a877	5642	* @arg @ref LL_RCC_PLLI2SM_DIV_50
ganlikun	0:13413ea9a877	5643	* @arg @ref LL_RCC_PLLI2SM_DIV_51
ganlikun	0:13413ea9a877	5644	* @arg @ref LL_RCC_PLLI2SM_DIV_52
ganlikun	0:13413ea9a877	5645	* @arg @ref LL_RCC_PLLI2SM_DIV_53
ganlikun	0:13413ea9a877	5646	* @arg @ref LL_RCC_PLLI2SM_DIV_54
ganlikun	0:13413ea9a877	5647	* @arg @ref LL_RCC_PLLI2SM_DIV_55
ganlikun	0:13413ea9a877	5648	* @arg @ref LL_RCC_PLLI2SM_DIV_56
ganlikun	0:13413ea9a877	5649	* @arg @ref LL_RCC_PLLI2SM_DIV_57
ganlikun	0:13413ea9a877	5650	* @arg @ref LL_RCC_PLLI2SM_DIV_58
ganlikun	0:13413ea9a877	5651	* @arg @ref LL_RCC_PLLI2SM_DIV_59
ganlikun	0:13413ea9a877	5652	* @arg @ref LL_RCC_PLLI2SM_DIV_60
ganlikun	0:13413ea9a877	5653	* @arg @ref LL_RCC_PLLI2SM_DIV_61
ganlikun	0:13413ea9a877	5654	* @arg @ref LL_RCC_PLLI2SM_DIV_62
ganlikun	0:13413ea9a877	5655	* @arg @ref LL_RCC_PLLI2SM_DIV_63
ganlikun	0:13413ea9a877	5656	* @param PLLN Between 50/192(*) and 432
ganlikun	0:13413ea9a877	5657	*
ganlikun	0:13413ea9a877	5658	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	5659	* @param PLLR This parameter can be one of the following values:
ganlikun	0:13413ea9a877	5660	* @arg @ref LL_RCC_PLLI2SR_DIV_2
ganlikun	0:13413ea9a877	5661	* @arg @ref LL_RCC_PLLI2SR_DIV_3
ganlikun	0:13413ea9a877	5662	* @arg @ref LL_RCC_PLLI2SR_DIV_4
ganlikun	0:13413ea9a877	5663	* @arg @ref LL_RCC_PLLI2SR_DIV_5
ganlikun	0:13413ea9a877	5664	* @arg @ref LL_RCC_PLLI2SR_DIV_6
ganlikun	0:13413ea9a877	5665	* @arg @ref LL_RCC_PLLI2SR_DIV_7
ganlikun	0:13413ea9a877	5666	* @retval None
ganlikun	0:13413ea9a877	5667	*/
ganlikun	0:13413ea9a877	5668	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
ganlikun	0:13413ea9a877	5669	{
ganlikun	0:13413ea9a877	5670	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
ganlikun	0:13413ea9a877	5671	MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
ganlikun	0:13413ea9a877	5672	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
ganlikun	0:13413ea9a877	5673	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
ganlikun	0:13413ea9a877	5674	#else
ganlikun	0:13413ea9a877	5675	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
ganlikun	0:13413ea9a877	5676	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
ganlikun	0:13413ea9a877	5677	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN \| RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos \| PLLR);
ganlikun	0:13413ea9a877	5678	}
ganlikun	0:13413ea9a877	5679
ganlikun	0:13413ea9a877	5680	/**
ganlikun	0:13413ea9a877	5681	* @brief Get I2SPLL multiplication factor for VCO
ganlikun	0:13413ea9a877	5682	* @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN
ganlikun	0:13413ea9a877	5683	* @retval Between 50/192(*) and 432
ganlikun	0:13413ea9a877	5684	*
ganlikun	0:13413ea9a877	5685	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	5686	*/
ganlikun	0:13413ea9a877	5687	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
ganlikun	0:13413ea9a877	5688	{
ganlikun	0:13413ea9a877	5689	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
ganlikun	0:13413ea9a877	5690	}
ganlikun	0:13413ea9a877	5691
ganlikun	0:13413ea9a877	5692	#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
ganlikun	0:13413ea9a877	5693	/**
ganlikun	0:13413ea9a877	5694	* @brief Get I2SPLL division factor for PLLI2SQ
ganlikun	0:13413ea9a877	5695	* @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ
ganlikun	0:13413ea9a877	5696	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	5697	* @arg @ref LL_RCC_PLLI2SQ_DIV_2
ganlikun	0:13413ea9a877	5698	* @arg @ref LL_RCC_PLLI2SQ_DIV_3
ganlikun	0:13413ea9a877	5699	* @arg @ref LL_RCC_PLLI2SQ_DIV_4
ganlikun	0:13413ea9a877	5700	* @arg @ref LL_RCC_PLLI2SQ_DIV_5
ganlikun	0:13413ea9a877	5701	* @arg @ref LL_RCC_PLLI2SQ_DIV_6
ganlikun	0:13413ea9a877	5702	* @arg @ref LL_RCC_PLLI2SQ_DIV_7
ganlikun	0:13413ea9a877	5703	* @arg @ref LL_RCC_PLLI2SQ_DIV_8
ganlikun	0:13413ea9a877	5704	* @arg @ref LL_RCC_PLLI2SQ_DIV_9
ganlikun	0:13413ea9a877	5705	* @arg @ref LL_RCC_PLLI2SQ_DIV_10
ganlikun	0:13413ea9a877	5706	* @arg @ref LL_RCC_PLLI2SQ_DIV_11
ganlikun	0:13413ea9a877	5707	* @arg @ref LL_RCC_PLLI2SQ_DIV_12
ganlikun	0:13413ea9a877	5708	* @arg @ref LL_RCC_PLLI2SQ_DIV_13
ganlikun	0:13413ea9a877	5709	* @arg @ref LL_RCC_PLLI2SQ_DIV_14
ganlikun	0:13413ea9a877	5710	* @arg @ref LL_RCC_PLLI2SQ_DIV_15
ganlikun	0:13413ea9a877	5711	*/
ganlikun	0:13413ea9a877	5712	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
ganlikun	0:13413ea9a877	5713	{
ganlikun	0:13413ea9a877	5714	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
ganlikun	0:13413ea9a877	5715	}
ganlikun	0:13413ea9a877	5716	#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
ganlikun	0:13413ea9a877	5717
ganlikun	0:13413ea9a877	5718	/**
ganlikun	0:13413ea9a877	5719	* @brief Get I2SPLL division factor for PLLI2SR
ganlikun	0:13413ea9a877	5720	* @note used for PLLI2SCLK (I2S clock)
ganlikun	0:13413ea9a877	5721	* @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR
ganlikun	0:13413ea9a877	5722	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	5723	* @arg @ref LL_RCC_PLLI2SR_DIV_2
ganlikun	0:13413ea9a877	5724	* @arg @ref LL_RCC_PLLI2SR_DIV_3
ganlikun	0:13413ea9a877	5725	* @arg @ref LL_RCC_PLLI2SR_DIV_4
ganlikun	0:13413ea9a877	5726	* @arg @ref LL_RCC_PLLI2SR_DIV_5
ganlikun	0:13413ea9a877	5727	* @arg @ref LL_RCC_PLLI2SR_DIV_6
ganlikun	0:13413ea9a877	5728	* @arg @ref LL_RCC_PLLI2SR_DIV_7
ganlikun	0:13413ea9a877	5729	*/
ganlikun	0:13413ea9a877	5730	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
ganlikun	0:13413ea9a877	5731	{
ganlikun	0:13413ea9a877	5732	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
ganlikun	0:13413ea9a877	5733	}
ganlikun	0:13413ea9a877	5734
ganlikun	0:13413ea9a877	5735	#if defined(RCC_PLLI2SCFGR_PLLI2SP)
ganlikun	0:13413ea9a877	5736	/**
ganlikun	0:13413ea9a877	5737	* @brief Get I2SPLL division factor for PLLI2SP
ganlikun	0:13413ea9a877	5738	* @note used for PLLSPDIFRXCLK (SPDIFRX clock)
ganlikun	0:13413ea9a877	5739	* @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP
ganlikun	0:13413ea9a877	5740	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	5741	* @arg @ref LL_RCC_PLLI2SP_DIV_2
ganlikun	0:13413ea9a877	5742	* @arg @ref LL_RCC_PLLI2SP_DIV_4
ganlikun	0:13413ea9a877	5743	* @arg @ref LL_RCC_PLLI2SP_DIV_6
ganlikun	0:13413ea9a877	5744	* @arg @ref LL_RCC_PLLI2SP_DIV_8
ganlikun	0:13413ea9a877	5745	*/
ganlikun	0:13413ea9a877	5746	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
ganlikun	0:13413ea9a877	5747	{
ganlikun	0:13413ea9a877	5748	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
ganlikun	0:13413ea9a877	5749	}
ganlikun	0:13413ea9a877	5750	#endif /* RCC_PLLI2SCFGR_PLLI2SP */
ganlikun	0:13413ea9a877	5751
ganlikun	0:13413ea9a877	5752	#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
ganlikun	0:13413ea9a877	5753	/**
ganlikun	0:13413ea9a877	5754	* @brief Get I2SPLL division factor for PLLI2SDIVQ
ganlikun	0:13413ea9a877	5755	* @note used PLLSAICLK selected (SAI clock)
ganlikun	0:13413ea9a877	5756	* @rmtoll DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ
ganlikun	0:13413ea9a877	5757	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	5758	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
ganlikun	0:13413ea9a877	5759	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
ganlikun	0:13413ea9a877	5760	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
ganlikun	0:13413ea9a877	5761	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
ganlikun	0:13413ea9a877	5762	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
ganlikun	0:13413ea9a877	5763	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
ganlikun	0:13413ea9a877	5764	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
ganlikun	0:13413ea9a877	5765	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
ganlikun	0:13413ea9a877	5766	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
ganlikun	0:13413ea9a877	5767	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
ganlikun	0:13413ea9a877	5768	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
ganlikun	0:13413ea9a877	5769	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
ganlikun	0:13413ea9a877	5770	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
ganlikun	0:13413ea9a877	5771	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
ganlikun	0:13413ea9a877	5772	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
ganlikun	0:13413ea9a877	5773	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
ganlikun	0:13413ea9a877	5774	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
ganlikun	0:13413ea9a877	5775	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
ganlikun	0:13413ea9a877	5776	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
ganlikun	0:13413ea9a877	5777	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
ganlikun	0:13413ea9a877	5778	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
ganlikun	0:13413ea9a877	5779	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
ganlikun	0:13413ea9a877	5780	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
ganlikun	0:13413ea9a877	5781	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
ganlikun	0:13413ea9a877	5782	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
ganlikun	0:13413ea9a877	5783	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
ganlikun	0:13413ea9a877	5784	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
ganlikun	0:13413ea9a877	5785	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
ganlikun	0:13413ea9a877	5786	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
ganlikun	0:13413ea9a877	5787	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
ganlikun	0:13413ea9a877	5788	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
ganlikun	0:13413ea9a877	5789	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
ganlikun	0:13413ea9a877	5790	*/
ganlikun	0:13413ea9a877	5791	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
ganlikun	0:13413ea9a877	5792	{
ganlikun	0:13413ea9a877	5793	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ));
ganlikun	0:13413ea9a877	5794	}
ganlikun	0:13413ea9a877	5795	#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
ganlikun	0:13413ea9a877	5796
ganlikun	0:13413ea9a877	5797	#if defined(RCC_DCKCFGR_PLLI2SDIVR)
ganlikun	0:13413ea9a877	5798	/**
ganlikun	0:13413ea9a877	5799	* @brief Get I2SPLL division factor for PLLI2SDIVR
ganlikun	0:13413ea9a877	5800	* @note used PLLSAICLK selected (SAI clock)
ganlikun	0:13413ea9a877	5801	* @rmtoll DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_GetDIVR
ganlikun	0:13413ea9a877	5802	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	5803	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_1
ganlikun	0:13413ea9a877	5804	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_2
ganlikun	0:13413ea9a877	5805	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_3
ganlikun	0:13413ea9a877	5806	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_4
ganlikun	0:13413ea9a877	5807	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_5
ganlikun	0:13413ea9a877	5808	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_6
ganlikun	0:13413ea9a877	5809	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_7
ganlikun	0:13413ea9a877	5810	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_8
ganlikun	0:13413ea9a877	5811	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_9
ganlikun	0:13413ea9a877	5812	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_10
ganlikun	0:13413ea9a877	5813	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_11
ganlikun	0:13413ea9a877	5814	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_12
ganlikun	0:13413ea9a877	5815	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_13
ganlikun	0:13413ea9a877	5816	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_14
ganlikun	0:13413ea9a877	5817	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_15
ganlikun	0:13413ea9a877	5818	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_16
ganlikun	0:13413ea9a877	5819	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_17
ganlikun	0:13413ea9a877	5820	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_18
ganlikun	0:13413ea9a877	5821	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_19
ganlikun	0:13413ea9a877	5822	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_20
ganlikun	0:13413ea9a877	5823	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_21
ganlikun	0:13413ea9a877	5824	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_22
ganlikun	0:13413ea9a877	5825	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_23
ganlikun	0:13413ea9a877	5826	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_24
ganlikun	0:13413ea9a877	5827	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_25
ganlikun	0:13413ea9a877	5828	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_26
ganlikun	0:13413ea9a877	5829	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_27
ganlikun	0:13413ea9a877	5830	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_28
ganlikun	0:13413ea9a877	5831	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_29
ganlikun	0:13413ea9a877	5832	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_30
ganlikun	0:13413ea9a877	5833	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_31
ganlikun	0:13413ea9a877	5834	*/
ganlikun	0:13413ea9a877	5835	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void)
ganlikun	0:13413ea9a877	5836	{
ganlikun	0:13413ea9a877	5837	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR));
ganlikun	0:13413ea9a877	5838	}
ganlikun	0:13413ea9a877	5839	#endif /* RCC_DCKCFGR_PLLI2SDIVR */
ganlikun	0:13413ea9a877	5840
ganlikun	0:13413ea9a877	5841	/**
ganlikun	0:13413ea9a877	5842	* @brief Get division factor for PLLI2S input clock
ganlikun	0:13413ea9a877	5843	* @rmtoll PLLCFGR PLLM LL_RCC_PLLI2S_GetDivider\n
ganlikun	0:13413ea9a877	5844	* PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_GetDivider
ganlikun	0:13413ea9a877	5845	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	5846	* @arg @ref LL_RCC_PLLI2SM_DIV_2
ganlikun	0:13413ea9a877	5847	* @arg @ref LL_RCC_PLLI2SM_DIV_3
ganlikun	0:13413ea9a877	5848	* @arg @ref LL_RCC_PLLI2SM_DIV_4
ganlikun	0:13413ea9a877	5849	* @arg @ref LL_RCC_PLLI2SM_DIV_5
ganlikun	0:13413ea9a877	5850	* @arg @ref LL_RCC_PLLI2SM_DIV_6
ganlikun	0:13413ea9a877	5851	* @arg @ref LL_RCC_PLLI2SM_DIV_7
ganlikun	0:13413ea9a877	5852	* @arg @ref LL_RCC_PLLI2SM_DIV_8
ganlikun	0:13413ea9a877	5853	* @arg @ref LL_RCC_PLLI2SM_DIV_9
ganlikun	0:13413ea9a877	5854	* @arg @ref LL_RCC_PLLI2SM_DIV_10
ganlikun	0:13413ea9a877	5855	* @arg @ref LL_RCC_PLLI2SM_DIV_11
ganlikun	0:13413ea9a877	5856	* @arg @ref LL_RCC_PLLI2SM_DIV_12
ganlikun	0:13413ea9a877	5857	* @arg @ref LL_RCC_PLLI2SM_DIV_13
ganlikun	0:13413ea9a877	5858	* @arg @ref LL_RCC_PLLI2SM_DIV_14
ganlikun	0:13413ea9a877	5859	* @arg @ref LL_RCC_PLLI2SM_DIV_15
ganlikun	0:13413ea9a877	5860	* @arg @ref LL_RCC_PLLI2SM_DIV_16
ganlikun	0:13413ea9a877	5861	* @arg @ref LL_RCC_PLLI2SM_DIV_17
ganlikun	0:13413ea9a877	5862	* @arg @ref LL_RCC_PLLI2SM_DIV_18
ganlikun	0:13413ea9a877	5863	* @arg @ref LL_RCC_PLLI2SM_DIV_19
ganlikun	0:13413ea9a877	5864	* @arg @ref LL_RCC_PLLI2SM_DIV_20
ganlikun	0:13413ea9a877	5865	* @arg @ref LL_RCC_PLLI2SM_DIV_21
ganlikun	0:13413ea9a877	5866	* @arg @ref LL_RCC_PLLI2SM_DIV_22
ganlikun	0:13413ea9a877	5867	* @arg @ref LL_RCC_PLLI2SM_DIV_23
ganlikun	0:13413ea9a877	5868	* @arg @ref LL_RCC_PLLI2SM_DIV_24
ganlikun	0:13413ea9a877	5869	* @arg @ref LL_RCC_PLLI2SM_DIV_25
ganlikun	0:13413ea9a877	5870	* @arg @ref LL_RCC_PLLI2SM_DIV_26
ganlikun	0:13413ea9a877	5871	* @arg @ref LL_RCC_PLLI2SM_DIV_27
ganlikun	0:13413ea9a877	5872	* @arg @ref LL_RCC_PLLI2SM_DIV_28
ganlikun	0:13413ea9a877	5873	* @arg @ref LL_RCC_PLLI2SM_DIV_29
ganlikun	0:13413ea9a877	5874	* @arg @ref LL_RCC_PLLI2SM_DIV_30
ganlikun	0:13413ea9a877	5875	* @arg @ref LL_RCC_PLLI2SM_DIV_31
ganlikun	0:13413ea9a877	5876	* @arg @ref LL_RCC_PLLI2SM_DIV_32
ganlikun	0:13413ea9a877	5877	* @arg @ref LL_RCC_PLLI2SM_DIV_33
ganlikun	0:13413ea9a877	5878	* @arg @ref LL_RCC_PLLI2SM_DIV_34
ganlikun	0:13413ea9a877	5879	* @arg @ref LL_RCC_PLLI2SM_DIV_35
ganlikun	0:13413ea9a877	5880	* @arg @ref LL_RCC_PLLI2SM_DIV_36
ganlikun	0:13413ea9a877	5881	* @arg @ref LL_RCC_PLLI2SM_DIV_37
ganlikun	0:13413ea9a877	5882	* @arg @ref LL_RCC_PLLI2SM_DIV_38
ganlikun	0:13413ea9a877	5883	* @arg @ref LL_RCC_PLLI2SM_DIV_39
ganlikun	0:13413ea9a877	5884	* @arg @ref LL_RCC_PLLI2SM_DIV_40
ganlikun	0:13413ea9a877	5885	* @arg @ref LL_RCC_PLLI2SM_DIV_41
ganlikun	0:13413ea9a877	5886	* @arg @ref LL_RCC_PLLI2SM_DIV_42
ganlikun	0:13413ea9a877	5887	* @arg @ref LL_RCC_PLLI2SM_DIV_43
ganlikun	0:13413ea9a877	5888	* @arg @ref LL_RCC_PLLI2SM_DIV_44
ganlikun	0:13413ea9a877	5889	* @arg @ref LL_RCC_PLLI2SM_DIV_45
ganlikun	0:13413ea9a877	5890	* @arg @ref LL_RCC_PLLI2SM_DIV_46
ganlikun	0:13413ea9a877	5891	* @arg @ref LL_RCC_PLLI2SM_DIV_47
ganlikun	0:13413ea9a877	5892	* @arg @ref LL_RCC_PLLI2SM_DIV_48
ganlikun	0:13413ea9a877	5893	* @arg @ref LL_RCC_PLLI2SM_DIV_49
ganlikun	0:13413ea9a877	5894	* @arg @ref LL_RCC_PLLI2SM_DIV_50
ganlikun	0:13413ea9a877	5895	* @arg @ref LL_RCC_PLLI2SM_DIV_51
ganlikun	0:13413ea9a877	5896	* @arg @ref LL_RCC_PLLI2SM_DIV_52
ganlikun	0:13413ea9a877	5897	* @arg @ref LL_RCC_PLLI2SM_DIV_53
ganlikun	0:13413ea9a877	5898	* @arg @ref LL_RCC_PLLI2SM_DIV_54
ganlikun	0:13413ea9a877	5899	* @arg @ref LL_RCC_PLLI2SM_DIV_55
ganlikun	0:13413ea9a877	5900	* @arg @ref LL_RCC_PLLI2SM_DIV_56
ganlikun	0:13413ea9a877	5901	* @arg @ref LL_RCC_PLLI2SM_DIV_57
ganlikun	0:13413ea9a877	5902	* @arg @ref LL_RCC_PLLI2SM_DIV_58
ganlikun	0:13413ea9a877	5903	* @arg @ref LL_RCC_PLLI2SM_DIV_59
ganlikun	0:13413ea9a877	5904	* @arg @ref LL_RCC_PLLI2SM_DIV_60
ganlikun	0:13413ea9a877	5905	* @arg @ref LL_RCC_PLLI2SM_DIV_61
ganlikun	0:13413ea9a877	5906	* @arg @ref LL_RCC_PLLI2SM_DIV_62
ganlikun	0:13413ea9a877	5907	* @arg @ref LL_RCC_PLLI2SM_DIV_63
ganlikun	0:13413ea9a877	5908	*/
ganlikun	0:13413ea9a877	5909	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void)
ganlikun	0:13413ea9a877	5910	{
ganlikun	0:13413ea9a877	5911	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
ganlikun	0:13413ea9a877	5912	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM));
ganlikun	0:13413ea9a877	5913	#else
ganlikun	0:13413ea9a877	5914	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
ganlikun	0:13413ea9a877	5915	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
ganlikun	0:13413ea9a877	5916	}
ganlikun	0:13413ea9a877	5917
ganlikun	0:13413ea9a877	5918	/**
ganlikun	0:13413ea9a877	5919	* @brief Get the oscillator used as PLL clock source.
ganlikun	0:13413ea9a877	5920	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_GetMainSource\n
ganlikun	0:13413ea9a877	5921	* PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_GetMainSource
ganlikun	0:13413ea9a877	5922	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	5923	* @arg @ref LL_RCC_PLLSOURCE_HSI
ganlikun	0:13413ea9a877	5924	* @arg @ref LL_RCC_PLLSOURCE_HSE
ganlikun	0:13413ea9a877	5925	* @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
ganlikun	0:13413ea9a877	5926	*
ganlikun	0:13413ea9a877	5927	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	5928	*/
ganlikun	0:13413ea9a877	5929	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void)
ganlikun	0:13413ea9a877	5930	{
ganlikun	0:13413ea9a877	5931	#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
ganlikun	0:13413ea9a877	5932	register uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
ganlikun	0:13413ea9a877	5933	register uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC);
ganlikun	0:13413ea9a877	5934	register uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U;
ganlikun	0:13413ea9a877	5935	return (uint32_t)(pllsrc \| plli2sssrc0 \| plli2sssrc1);
ganlikun	0:13413ea9a877	5936	#else
ganlikun	0:13413ea9a877	5937	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
ganlikun	0:13413ea9a877	5938	#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
ganlikun	0:13413ea9a877	5939	}
ganlikun	0:13413ea9a877	5940
ganlikun	0:13413ea9a877	5941	/**
ganlikun	0:13413ea9a877	5942	* @}
ganlikun	0:13413ea9a877	5943	*/
ganlikun	0:13413ea9a877	5944	#endif /* RCC_PLLI2S_SUPPORT */
ganlikun	0:13413ea9a877	5945
ganlikun	0:13413ea9a877	5946	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	5947	/** @defgroup RCC_LL_EF_PLLSAI PLLSAI
ganlikun	0:13413ea9a877	5948	* @{
ganlikun	0:13413ea9a877	5949	*/
ganlikun	0:13413ea9a877	5950
ganlikun	0:13413ea9a877	5951	/**
ganlikun	0:13413ea9a877	5952	* @brief Enable PLLSAI
ganlikun	0:13413ea9a877	5953	* @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable
ganlikun	0:13413ea9a877	5954	* @retval None
ganlikun	0:13413ea9a877	5955	*/
ganlikun	0:13413ea9a877	5956	__STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
ganlikun	0:13413ea9a877	5957	{
ganlikun	0:13413ea9a877	5958	SET_BIT(RCC->CR, RCC_CR_PLLSAION);
ganlikun	0:13413ea9a877	5959	}
ganlikun	0:13413ea9a877	5960
ganlikun	0:13413ea9a877	5961	/**
ganlikun	0:13413ea9a877	5962	* @brief Disable PLLSAI
ganlikun	0:13413ea9a877	5963	* @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable
ganlikun	0:13413ea9a877	5964	* @retval None
ganlikun	0:13413ea9a877	5965	*/
ganlikun	0:13413ea9a877	5966	__STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
ganlikun	0:13413ea9a877	5967	{
ganlikun	0:13413ea9a877	5968	CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
ganlikun	0:13413ea9a877	5969	}
ganlikun	0:13413ea9a877	5970
ganlikun	0:13413ea9a877	5971	/**
ganlikun	0:13413ea9a877	5972	* @brief Check if PLLSAI Ready
ganlikun	0:13413ea9a877	5973	* @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady
ganlikun	0:13413ea9a877	5974	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	5975	*/
ganlikun	0:13413ea9a877	5976	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
ganlikun	0:13413ea9a877	5977	{
ganlikun	0:13413ea9a877	5978	return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
ganlikun	0:13413ea9a877	5979	}
ganlikun	0:13413ea9a877	5980
ganlikun	0:13413ea9a877	5981	/**
ganlikun	0:13413ea9a877	5982	* @brief Configure PLLSAI used for SAI domain clock
ganlikun	0:13413ea9a877	5983	* @note PLL Source and PLLM Divider can be written only when PLL,
ganlikun	0:13413ea9a877	5984	* PLLI2S and PLLSAI(*) are disabled
ganlikun	0:13413ea9a877	5985	* @note PLLN/PLLQ can be written only when PLLSAI is disabled
ganlikun	0:13413ea9a877	5986	* @note This can be selected for SAI
ganlikun	0:13413ea9a877	5987	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n
ganlikun	0:13413ea9a877	5988	* PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n
ganlikun	0:13413ea9a877	5989	* PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_SAI\n
ganlikun	0:13413ea9a877	5990	* PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n
ganlikun	0:13413ea9a877	5991	* PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n
ganlikun	0:13413ea9a877	5992	* DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI
ganlikun	0:13413ea9a877	5993	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	5994	* @arg @ref LL_RCC_PLLSOURCE_HSI
ganlikun	0:13413ea9a877	5995	* @arg @ref LL_RCC_PLLSOURCE_HSE
ganlikun	0:13413ea9a877	5996	* @param PLLM This parameter can be one of the following values:
ganlikun	0:13413ea9a877	5997	* @arg @ref LL_RCC_PLLSAIM_DIV_2
ganlikun	0:13413ea9a877	5998	* @arg @ref LL_RCC_PLLSAIM_DIV_3
ganlikun	0:13413ea9a877	5999	* @arg @ref LL_RCC_PLLSAIM_DIV_4
ganlikun	0:13413ea9a877	6000	* @arg @ref LL_RCC_PLLSAIM_DIV_5
ganlikun	0:13413ea9a877	6001	* @arg @ref LL_RCC_PLLSAIM_DIV_6
ganlikun	0:13413ea9a877	6002	* @arg @ref LL_RCC_PLLSAIM_DIV_7
ganlikun	0:13413ea9a877	6003	* @arg @ref LL_RCC_PLLSAIM_DIV_8
ganlikun	0:13413ea9a877	6004	* @arg @ref LL_RCC_PLLSAIM_DIV_9
ganlikun	0:13413ea9a877	6005	* @arg @ref LL_RCC_PLLSAIM_DIV_10
ganlikun	0:13413ea9a877	6006	* @arg @ref LL_RCC_PLLSAIM_DIV_11
ganlikun	0:13413ea9a877	6007	* @arg @ref LL_RCC_PLLSAIM_DIV_12
ganlikun	0:13413ea9a877	6008	* @arg @ref LL_RCC_PLLSAIM_DIV_13
ganlikun	0:13413ea9a877	6009	* @arg @ref LL_RCC_PLLSAIM_DIV_14
ganlikun	0:13413ea9a877	6010	* @arg @ref LL_RCC_PLLSAIM_DIV_15
ganlikun	0:13413ea9a877	6011	* @arg @ref LL_RCC_PLLSAIM_DIV_16
ganlikun	0:13413ea9a877	6012	* @arg @ref LL_RCC_PLLSAIM_DIV_17
ganlikun	0:13413ea9a877	6013	* @arg @ref LL_RCC_PLLSAIM_DIV_18
ganlikun	0:13413ea9a877	6014	* @arg @ref LL_RCC_PLLSAIM_DIV_19
ganlikun	0:13413ea9a877	6015	* @arg @ref LL_RCC_PLLSAIM_DIV_20
ganlikun	0:13413ea9a877	6016	* @arg @ref LL_RCC_PLLSAIM_DIV_21
ganlikun	0:13413ea9a877	6017	* @arg @ref LL_RCC_PLLSAIM_DIV_22
ganlikun	0:13413ea9a877	6018	* @arg @ref LL_RCC_PLLSAIM_DIV_23
ganlikun	0:13413ea9a877	6019	* @arg @ref LL_RCC_PLLSAIM_DIV_24
ganlikun	0:13413ea9a877	6020	* @arg @ref LL_RCC_PLLSAIM_DIV_25
ganlikun	0:13413ea9a877	6021	* @arg @ref LL_RCC_PLLSAIM_DIV_26
ganlikun	0:13413ea9a877	6022	* @arg @ref LL_RCC_PLLSAIM_DIV_27
ganlikun	0:13413ea9a877	6023	* @arg @ref LL_RCC_PLLSAIM_DIV_28
ganlikun	0:13413ea9a877	6024	* @arg @ref LL_RCC_PLLSAIM_DIV_29
ganlikun	0:13413ea9a877	6025	* @arg @ref LL_RCC_PLLSAIM_DIV_30
ganlikun	0:13413ea9a877	6026	* @arg @ref LL_RCC_PLLSAIM_DIV_31
ganlikun	0:13413ea9a877	6027	* @arg @ref LL_RCC_PLLSAIM_DIV_32
ganlikun	0:13413ea9a877	6028	* @arg @ref LL_RCC_PLLSAIM_DIV_33
ganlikun	0:13413ea9a877	6029	* @arg @ref LL_RCC_PLLSAIM_DIV_34
ganlikun	0:13413ea9a877	6030	* @arg @ref LL_RCC_PLLSAIM_DIV_35
ganlikun	0:13413ea9a877	6031	* @arg @ref LL_RCC_PLLSAIM_DIV_36
ganlikun	0:13413ea9a877	6032	* @arg @ref LL_RCC_PLLSAIM_DIV_37
ganlikun	0:13413ea9a877	6033	* @arg @ref LL_RCC_PLLSAIM_DIV_38
ganlikun	0:13413ea9a877	6034	* @arg @ref LL_RCC_PLLSAIM_DIV_39
ganlikun	0:13413ea9a877	6035	* @arg @ref LL_RCC_PLLSAIM_DIV_40
ganlikun	0:13413ea9a877	6036	* @arg @ref LL_RCC_PLLSAIM_DIV_41
ganlikun	0:13413ea9a877	6037	* @arg @ref LL_RCC_PLLSAIM_DIV_42
ganlikun	0:13413ea9a877	6038	* @arg @ref LL_RCC_PLLSAIM_DIV_43
ganlikun	0:13413ea9a877	6039	* @arg @ref LL_RCC_PLLSAIM_DIV_44
ganlikun	0:13413ea9a877	6040	* @arg @ref LL_RCC_PLLSAIM_DIV_45
ganlikun	0:13413ea9a877	6041	* @arg @ref LL_RCC_PLLSAIM_DIV_46
ganlikun	0:13413ea9a877	6042	* @arg @ref LL_RCC_PLLSAIM_DIV_47
ganlikun	0:13413ea9a877	6043	* @arg @ref LL_RCC_PLLSAIM_DIV_48
ganlikun	0:13413ea9a877	6044	* @arg @ref LL_RCC_PLLSAIM_DIV_49
ganlikun	0:13413ea9a877	6045	* @arg @ref LL_RCC_PLLSAIM_DIV_50
ganlikun	0:13413ea9a877	6046	* @arg @ref LL_RCC_PLLSAIM_DIV_51
ganlikun	0:13413ea9a877	6047	* @arg @ref LL_RCC_PLLSAIM_DIV_52
ganlikun	0:13413ea9a877	6048	* @arg @ref LL_RCC_PLLSAIM_DIV_53
ganlikun	0:13413ea9a877	6049	* @arg @ref LL_RCC_PLLSAIM_DIV_54
ganlikun	0:13413ea9a877	6050	* @arg @ref LL_RCC_PLLSAIM_DIV_55
ganlikun	0:13413ea9a877	6051	* @arg @ref LL_RCC_PLLSAIM_DIV_56
ganlikun	0:13413ea9a877	6052	* @arg @ref LL_RCC_PLLSAIM_DIV_57
ganlikun	0:13413ea9a877	6053	* @arg @ref LL_RCC_PLLSAIM_DIV_58
ganlikun	0:13413ea9a877	6054	* @arg @ref LL_RCC_PLLSAIM_DIV_59
ganlikun	0:13413ea9a877	6055	* @arg @ref LL_RCC_PLLSAIM_DIV_60
ganlikun	0:13413ea9a877	6056	* @arg @ref LL_RCC_PLLSAIM_DIV_61
ganlikun	0:13413ea9a877	6057	* @arg @ref LL_RCC_PLLSAIM_DIV_62
ganlikun	0:13413ea9a877	6058	* @arg @ref LL_RCC_PLLSAIM_DIV_63
ganlikun	0:13413ea9a877	6059	* @param PLLN Between 49/50(*) and 432
ganlikun	0:13413ea9a877	6060	*
ganlikun	0:13413ea9a877	6061	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	6062	* @param PLLQ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6063	* @arg @ref LL_RCC_PLLSAIQ_DIV_2
ganlikun	0:13413ea9a877	6064	* @arg @ref LL_RCC_PLLSAIQ_DIV_3
ganlikun	0:13413ea9a877	6065	* @arg @ref LL_RCC_PLLSAIQ_DIV_4
ganlikun	0:13413ea9a877	6066	* @arg @ref LL_RCC_PLLSAIQ_DIV_5
ganlikun	0:13413ea9a877	6067	* @arg @ref LL_RCC_PLLSAIQ_DIV_6
ganlikun	0:13413ea9a877	6068	* @arg @ref LL_RCC_PLLSAIQ_DIV_7
ganlikun	0:13413ea9a877	6069	* @arg @ref LL_RCC_PLLSAIQ_DIV_8
ganlikun	0:13413ea9a877	6070	* @arg @ref LL_RCC_PLLSAIQ_DIV_9
ganlikun	0:13413ea9a877	6071	* @arg @ref LL_RCC_PLLSAIQ_DIV_10
ganlikun	0:13413ea9a877	6072	* @arg @ref LL_RCC_PLLSAIQ_DIV_11
ganlikun	0:13413ea9a877	6073	* @arg @ref LL_RCC_PLLSAIQ_DIV_12
ganlikun	0:13413ea9a877	6074	* @arg @ref LL_RCC_PLLSAIQ_DIV_13
ganlikun	0:13413ea9a877	6075	* @arg @ref LL_RCC_PLLSAIQ_DIV_14
ganlikun	0:13413ea9a877	6076	* @arg @ref LL_RCC_PLLSAIQ_DIV_15
ganlikun	0:13413ea9a877	6077	* @param PLLDIVQ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6078	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
ganlikun	0:13413ea9a877	6079	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
ganlikun	0:13413ea9a877	6080	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
ganlikun	0:13413ea9a877	6081	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
ganlikun	0:13413ea9a877	6082	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
ganlikun	0:13413ea9a877	6083	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
ganlikun	0:13413ea9a877	6084	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
ganlikun	0:13413ea9a877	6085	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
ganlikun	0:13413ea9a877	6086	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
ganlikun	0:13413ea9a877	6087	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
ganlikun	0:13413ea9a877	6088	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
ganlikun	0:13413ea9a877	6089	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
ganlikun	0:13413ea9a877	6090	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
ganlikun	0:13413ea9a877	6091	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
ganlikun	0:13413ea9a877	6092	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
ganlikun	0:13413ea9a877	6093	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
ganlikun	0:13413ea9a877	6094	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
ganlikun	0:13413ea9a877	6095	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
ganlikun	0:13413ea9a877	6096	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
ganlikun	0:13413ea9a877	6097	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
ganlikun	0:13413ea9a877	6098	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
ganlikun	0:13413ea9a877	6099	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
ganlikun	0:13413ea9a877	6100	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
ganlikun	0:13413ea9a877	6101	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
ganlikun	0:13413ea9a877	6102	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
ganlikun	0:13413ea9a877	6103	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
ganlikun	0:13413ea9a877	6104	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
ganlikun	0:13413ea9a877	6105	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
ganlikun	0:13413ea9a877	6106	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
ganlikun	0:13413ea9a877	6107	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
ganlikun	0:13413ea9a877	6108	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
ganlikun	0:13413ea9a877	6109	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
ganlikun	0:13413ea9a877	6110	* @retval None
ganlikun	0:13413ea9a877	6111	*/
ganlikun	0:13413ea9a877	6112	__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
ganlikun	0:13413ea9a877	6113	{
ganlikun	0:13413ea9a877	6114	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
ganlikun	0:13413ea9a877	6115	#if defined(RCC_PLLSAICFGR_PLLSAIM)
ganlikun	0:13413ea9a877	6116	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
ganlikun	0:13413ea9a877	6117	#else
ganlikun	0:13413ea9a877	6118	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
ganlikun	0:13413ea9a877	6119	#endif /* RCC_PLLSAICFGR_PLLSAIM */
ganlikun	0:13413ea9a877	6120	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN \| RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos \| PLLQ);
ganlikun	0:13413ea9a877	6121	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ);
ganlikun	0:13413ea9a877	6122	}
ganlikun	0:13413ea9a877	6123
ganlikun	0:13413ea9a877	6124	#if defined(RCC_PLLSAICFGR_PLLSAIP)
ganlikun	0:13413ea9a877	6125	/**
ganlikun	0:13413ea9a877	6126	* @brief Configure PLLSAI used for 48Mhz domain clock
ganlikun	0:13413ea9a877	6127	* @note PLL Source and PLLM Divider can be written only when PLL,
ganlikun	0:13413ea9a877	6128	* PLLI2S and PLLSAI(*) are disabled
ganlikun	0:13413ea9a877	6129	* @note PLLN/PLLP can be written only when PLLSAI is disabled
ganlikun	0:13413ea9a877	6130	* @note This can be selected for USB, RNG, SDIO
ganlikun	0:13413ea9a877	6131	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n
ganlikun	0:13413ea9a877	6132	* PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n
ganlikun	0:13413ea9a877	6133	* PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_48M\n
ganlikun	0:13413ea9a877	6134	* PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n
ganlikun	0:13413ea9a877	6135	* PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M
ganlikun	0:13413ea9a877	6136	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6137	* @arg @ref LL_RCC_PLLSOURCE_HSI
ganlikun	0:13413ea9a877	6138	* @arg @ref LL_RCC_PLLSOURCE_HSE
ganlikun	0:13413ea9a877	6139	* @param PLLM This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6140	* @arg @ref LL_RCC_PLLSAIM_DIV_2
ganlikun	0:13413ea9a877	6141	* @arg @ref LL_RCC_PLLSAIM_DIV_3
ganlikun	0:13413ea9a877	6142	* @arg @ref LL_RCC_PLLSAIM_DIV_4
ganlikun	0:13413ea9a877	6143	* @arg @ref LL_RCC_PLLSAIM_DIV_5
ganlikun	0:13413ea9a877	6144	* @arg @ref LL_RCC_PLLSAIM_DIV_6
ganlikun	0:13413ea9a877	6145	* @arg @ref LL_RCC_PLLSAIM_DIV_7
ganlikun	0:13413ea9a877	6146	* @arg @ref LL_RCC_PLLSAIM_DIV_8
ganlikun	0:13413ea9a877	6147	* @arg @ref LL_RCC_PLLSAIM_DIV_9
ganlikun	0:13413ea9a877	6148	* @arg @ref LL_RCC_PLLSAIM_DIV_10
ganlikun	0:13413ea9a877	6149	* @arg @ref LL_RCC_PLLSAIM_DIV_11
ganlikun	0:13413ea9a877	6150	* @arg @ref LL_RCC_PLLSAIM_DIV_12
ganlikun	0:13413ea9a877	6151	* @arg @ref LL_RCC_PLLSAIM_DIV_13
ganlikun	0:13413ea9a877	6152	* @arg @ref LL_RCC_PLLSAIM_DIV_14
ganlikun	0:13413ea9a877	6153	* @arg @ref LL_RCC_PLLSAIM_DIV_15
ganlikun	0:13413ea9a877	6154	* @arg @ref LL_RCC_PLLSAIM_DIV_16
ganlikun	0:13413ea9a877	6155	* @arg @ref LL_RCC_PLLSAIM_DIV_17
ganlikun	0:13413ea9a877	6156	* @arg @ref LL_RCC_PLLSAIM_DIV_18
ganlikun	0:13413ea9a877	6157	* @arg @ref LL_RCC_PLLSAIM_DIV_19
ganlikun	0:13413ea9a877	6158	* @arg @ref LL_RCC_PLLSAIM_DIV_20
ganlikun	0:13413ea9a877	6159	* @arg @ref LL_RCC_PLLSAIM_DIV_21
ganlikun	0:13413ea9a877	6160	* @arg @ref LL_RCC_PLLSAIM_DIV_22
ganlikun	0:13413ea9a877	6161	* @arg @ref LL_RCC_PLLSAIM_DIV_23
ganlikun	0:13413ea9a877	6162	* @arg @ref LL_RCC_PLLSAIM_DIV_24
ganlikun	0:13413ea9a877	6163	* @arg @ref LL_RCC_PLLSAIM_DIV_25
ganlikun	0:13413ea9a877	6164	* @arg @ref LL_RCC_PLLSAIM_DIV_26
ganlikun	0:13413ea9a877	6165	* @arg @ref LL_RCC_PLLSAIM_DIV_27
ganlikun	0:13413ea9a877	6166	* @arg @ref LL_RCC_PLLSAIM_DIV_28
ganlikun	0:13413ea9a877	6167	* @arg @ref LL_RCC_PLLSAIM_DIV_29
ganlikun	0:13413ea9a877	6168	* @arg @ref LL_RCC_PLLSAIM_DIV_30
ganlikun	0:13413ea9a877	6169	* @arg @ref LL_RCC_PLLSAIM_DIV_31
ganlikun	0:13413ea9a877	6170	* @arg @ref LL_RCC_PLLSAIM_DIV_32
ganlikun	0:13413ea9a877	6171	* @arg @ref LL_RCC_PLLSAIM_DIV_33
ganlikun	0:13413ea9a877	6172	* @arg @ref LL_RCC_PLLSAIM_DIV_34
ganlikun	0:13413ea9a877	6173	* @arg @ref LL_RCC_PLLSAIM_DIV_35
ganlikun	0:13413ea9a877	6174	* @arg @ref LL_RCC_PLLSAIM_DIV_36
ganlikun	0:13413ea9a877	6175	* @arg @ref LL_RCC_PLLSAIM_DIV_37
ganlikun	0:13413ea9a877	6176	* @arg @ref LL_RCC_PLLSAIM_DIV_38
ganlikun	0:13413ea9a877	6177	* @arg @ref LL_RCC_PLLSAIM_DIV_39
ganlikun	0:13413ea9a877	6178	* @arg @ref LL_RCC_PLLSAIM_DIV_40
ganlikun	0:13413ea9a877	6179	* @arg @ref LL_RCC_PLLSAIM_DIV_41
ganlikun	0:13413ea9a877	6180	* @arg @ref LL_RCC_PLLSAIM_DIV_42
ganlikun	0:13413ea9a877	6181	* @arg @ref LL_RCC_PLLSAIM_DIV_43
ganlikun	0:13413ea9a877	6182	* @arg @ref LL_RCC_PLLSAIM_DIV_44
ganlikun	0:13413ea9a877	6183	* @arg @ref LL_RCC_PLLSAIM_DIV_45
ganlikun	0:13413ea9a877	6184	* @arg @ref LL_RCC_PLLSAIM_DIV_46
ganlikun	0:13413ea9a877	6185	* @arg @ref LL_RCC_PLLSAIM_DIV_47
ganlikun	0:13413ea9a877	6186	* @arg @ref LL_RCC_PLLSAIM_DIV_48
ganlikun	0:13413ea9a877	6187	* @arg @ref LL_RCC_PLLSAIM_DIV_49
ganlikun	0:13413ea9a877	6188	* @arg @ref LL_RCC_PLLSAIM_DIV_50
ganlikun	0:13413ea9a877	6189	* @arg @ref LL_RCC_PLLSAIM_DIV_51
ganlikun	0:13413ea9a877	6190	* @arg @ref LL_RCC_PLLSAIM_DIV_52
ganlikun	0:13413ea9a877	6191	* @arg @ref LL_RCC_PLLSAIM_DIV_53
ganlikun	0:13413ea9a877	6192	* @arg @ref LL_RCC_PLLSAIM_DIV_54
ganlikun	0:13413ea9a877	6193	* @arg @ref LL_RCC_PLLSAIM_DIV_55
ganlikun	0:13413ea9a877	6194	* @arg @ref LL_RCC_PLLSAIM_DIV_56
ganlikun	0:13413ea9a877	6195	* @arg @ref LL_RCC_PLLSAIM_DIV_57
ganlikun	0:13413ea9a877	6196	* @arg @ref LL_RCC_PLLSAIM_DIV_58
ganlikun	0:13413ea9a877	6197	* @arg @ref LL_RCC_PLLSAIM_DIV_59
ganlikun	0:13413ea9a877	6198	* @arg @ref LL_RCC_PLLSAIM_DIV_60
ganlikun	0:13413ea9a877	6199	* @arg @ref LL_RCC_PLLSAIM_DIV_61
ganlikun	0:13413ea9a877	6200	* @arg @ref LL_RCC_PLLSAIM_DIV_62
ganlikun	0:13413ea9a877	6201	* @arg @ref LL_RCC_PLLSAIM_DIV_63
ganlikun	0:13413ea9a877	6202	* @param PLLN Between 50 and 432
ganlikun	0:13413ea9a877	6203	* @param PLLP This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6204	* @arg @ref LL_RCC_PLLSAIP_DIV_2
ganlikun	0:13413ea9a877	6205	* @arg @ref LL_RCC_PLLSAIP_DIV_4
ganlikun	0:13413ea9a877	6206	* @arg @ref LL_RCC_PLLSAIP_DIV_6
ganlikun	0:13413ea9a877	6207	* @arg @ref LL_RCC_PLLSAIP_DIV_8
ganlikun	0:13413ea9a877	6208	* @retval None
ganlikun	0:13413ea9a877	6209	*/
ganlikun	0:13413ea9a877	6210	__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
ganlikun	0:13413ea9a877	6211	{
ganlikun	0:13413ea9a877	6212	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
ganlikun	0:13413ea9a877	6213	#if defined(RCC_PLLSAICFGR_PLLSAIM)
ganlikun	0:13413ea9a877	6214	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
ganlikun	0:13413ea9a877	6215	#else
ganlikun	0:13413ea9a877	6216	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
ganlikun	0:13413ea9a877	6217	#endif /* RCC_PLLSAICFGR_PLLSAIM */
ganlikun	0:13413ea9a877	6218	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN \| RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos \| PLLP);
ganlikun	0:13413ea9a877	6219	}
ganlikun	0:13413ea9a877	6220	#endif /* RCC_PLLSAICFGR_PLLSAIP */
ganlikun	0:13413ea9a877	6221
ganlikun	0:13413ea9a877	6222	#if defined(LTDC)
ganlikun	0:13413ea9a877	6223	/**
ganlikun	0:13413ea9a877	6224	* @brief Configure PLLSAI used for LTDC domain clock
ganlikun	0:13413ea9a877	6225	* @note PLL Source and PLLM Divider can be written only when PLL,
ganlikun	0:13413ea9a877	6226	* PLLI2S and PLLSAI(*) are disabled
ganlikun	0:13413ea9a877	6227	* @note PLLN/PLLR can be written only when PLLSAI is disabled
ganlikun	0:13413ea9a877	6228	* @note This can be selected for LTDC
ganlikun	0:13413ea9a877	6229	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n
ganlikun	0:13413ea9a877	6230	* PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n
ganlikun	0:13413ea9a877	6231	* PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n
ganlikun	0:13413ea9a877	6232	* PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n
ganlikun	0:13413ea9a877	6233	* DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC
ganlikun	0:13413ea9a877	6234	* @param Source This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6235	* @arg @ref LL_RCC_PLLSOURCE_HSI
ganlikun	0:13413ea9a877	6236	* @arg @ref LL_RCC_PLLSOURCE_HSE
ganlikun	0:13413ea9a877	6237	* @param PLLM This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6238	* @arg @ref LL_RCC_PLLSAIM_DIV_2
ganlikun	0:13413ea9a877	6239	* @arg @ref LL_RCC_PLLSAIM_DIV_3
ganlikun	0:13413ea9a877	6240	* @arg @ref LL_RCC_PLLSAIM_DIV_4
ganlikun	0:13413ea9a877	6241	* @arg @ref LL_RCC_PLLSAIM_DIV_5
ganlikun	0:13413ea9a877	6242	* @arg @ref LL_RCC_PLLSAIM_DIV_6
ganlikun	0:13413ea9a877	6243	* @arg @ref LL_RCC_PLLSAIM_DIV_7
ganlikun	0:13413ea9a877	6244	* @arg @ref LL_RCC_PLLSAIM_DIV_8
ganlikun	0:13413ea9a877	6245	* @arg @ref LL_RCC_PLLSAIM_DIV_9
ganlikun	0:13413ea9a877	6246	* @arg @ref LL_RCC_PLLSAIM_DIV_10
ganlikun	0:13413ea9a877	6247	* @arg @ref LL_RCC_PLLSAIM_DIV_11
ganlikun	0:13413ea9a877	6248	* @arg @ref LL_RCC_PLLSAIM_DIV_12
ganlikun	0:13413ea9a877	6249	* @arg @ref LL_RCC_PLLSAIM_DIV_13
ganlikun	0:13413ea9a877	6250	* @arg @ref LL_RCC_PLLSAIM_DIV_14
ganlikun	0:13413ea9a877	6251	* @arg @ref LL_RCC_PLLSAIM_DIV_15
ganlikun	0:13413ea9a877	6252	* @arg @ref LL_RCC_PLLSAIM_DIV_16
ganlikun	0:13413ea9a877	6253	* @arg @ref LL_RCC_PLLSAIM_DIV_17
ganlikun	0:13413ea9a877	6254	* @arg @ref LL_RCC_PLLSAIM_DIV_18
ganlikun	0:13413ea9a877	6255	* @arg @ref LL_RCC_PLLSAIM_DIV_19
ganlikun	0:13413ea9a877	6256	* @arg @ref LL_RCC_PLLSAIM_DIV_20
ganlikun	0:13413ea9a877	6257	* @arg @ref LL_RCC_PLLSAIM_DIV_21
ganlikun	0:13413ea9a877	6258	* @arg @ref LL_RCC_PLLSAIM_DIV_22
ganlikun	0:13413ea9a877	6259	* @arg @ref LL_RCC_PLLSAIM_DIV_23
ganlikun	0:13413ea9a877	6260	* @arg @ref LL_RCC_PLLSAIM_DIV_24
ganlikun	0:13413ea9a877	6261	* @arg @ref LL_RCC_PLLSAIM_DIV_25
ganlikun	0:13413ea9a877	6262	* @arg @ref LL_RCC_PLLSAIM_DIV_26
ganlikun	0:13413ea9a877	6263	* @arg @ref LL_RCC_PLLSAIM_DIV_27
ganlikun	0:13413ea9a877	6264	* @arg @ref LL_RCC_PLLSAIM_DIV_28
ganlikun	0:13413ea9a877	6265	* @arg @ref LL_RCC_PLLSAIM_DIV_29
ganlikun	0:13413ea9a877	6266	* @arg @ref LL_RCC_PLLSAIM_DIV_30
ganlikun	0:13413ea9a877	6267	* @arg @ref LL_RCC_PLLSAIM_DIV_31
ganlikun	0:13413ea9a877	6268	* @arg @ref LL_RCC_PLLSAIM_DIV_32
ganlikun	0:13413ea9a877	6269	* @arg @ref LL_RCC_PLLSAIM_DIV_33
ganlikun	0:13413ea9a877	6270	* @arg @ref LL_RCC_PLLSAIM_DIV_34
ganlikun	0:13413ea9a877	6271	* @arg @ref LL_RCC_PLLSAIM_DIV_35
ganlikun	0:13413ea9a877	6272	* @arg @ref LL_RCC_PLLSAIM_DIV_36
ganlikun	0:13413ea9a877	6273	* @arg @ref LL_RCC_PLLSAIM_DIV_37
ganlikun	0:13413ea9a877	6274	* @arg @ref LL_RCC_PLLSAIM_DIV_38
ganlikun	0:13413ea9a877	6275	* @arg @ref LL_RCC_PLLSAIM_DIV_39
ganlikun	0:13413ea9a877	6276	* @arg @ref LL_RCC_PLLSAIM_DIV_40
ganlikun	0:13413ea9a877	6277	* @arg @ref LL_RCC_PLLSAIM_DIV_41
ganlikun	0:13413ea9a877	6278	* @arg @ref LL_RCC_PLLSAIM_DIV_42
ganlikun	0:13413ea9a877	6279	* @arg @ref LL_RCC_PLLSAIM_DIV_43
ganlikun	0:13413ea9a877	6280	* @arg @ref LL_RCC_PLLSAIM_DIV_44
ganlikun	0:13413ea9a877	6281	* @arg @ref LL_RCC_PLLSAIM_DIV_45
ganlikun	0:13413ea9a877	6282	* @arg @ref LL_RCC_PLLSAIM_DIV_46
ganlikun	0:13413ea9a877	6283	* @arg @ref LL_RCC_PLLSAIM_DIV_47
ganlikun	0:13413ea9a877	6284	* @arg @ref LL_RCC_PLLSAIM_DIV_48
ganlikun	0:13413ea9a877	6285	* @arg @ref LL_RCC_PLLSAIM_DIV_49
ganlikun	0:13413ea9a877	6286	* @arg @ref LL_RCC_PLLSAIM_DIV_50
ganlikun	0:13413ea9a877	6287	* @arg @ref LL_RCC_PLLSAIM_DIV_51
ganlikun	0:13413ea9a877	6288	* @arg @ref LL_RCC_PLLSAIM_DIV_52
ganlikun	0:13413ea9a877	6289	* @arg @ref LL_RCC_PLLSAIM_DIV_53
ganlikun	0:13413ea9a877	6290	* @arg @ref LL_RCC_PLLSAIM_DIV_54
ganlikun	0:13413ea9a877	6291	* @arg @ref LL_RCC_PLLSAIM_DIV_55
ganlikun	0:13413ea9a877	6292	* @arg @ref LL_RCC_PLLSAIM_DIV_56
ganlikun	0:13413ea9a877	6293	* @arg @ref LL_RCC_PLLSAIM_DIV_57
ganlikun	0:13413ea9a877	6294	* @arg @ref LL_RCC_PLLSAIM_DIV_58
ganlikun	0:13413ea9a877	6295	* @arg @ref LL_RCC_PLLSAIM_DIV_59
ganlikun	0:13413ea9a877	6296	* @arg @ref LL_RCC_PLLSAIM_DIV_60
ganlikun	0:13413ea9a877	6297	* @arg @ref LL_RCC_PLLSAIM_DIV_61
ganlikun	0:13413ea9a877	6298	* @arg @ref LL_RCC_PLLSAIM_DIV_62
ganlikun	0:13413ea9a877	6299	* @arg @ref LL_RCC_PLLSAIM_DIV_63
ganlikun	0:13413ea9a877	6300	* @param PLLN Between 49/50(*) and 432
ganlikun	0:13413ea9a877	6301	*
ganlikun	0:13413ea9a877	6302	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	6303	* @param PLLR This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6304	* @arg @ref LL_RCC_PLLSAIR_DIV_2
ganlikun	0:13413ea9a877	6305	* @arg @ref LL_RCC_PLLSAIR_DIV_3
ganlikun	0:13413ea9a877	6306	* @arg @ref LL_RCC_PLLSAIR_DIV_4
ganlikun	0:13413ea9a877	6307	* @arg @ref LL_RCC_PLLSAIR_DIV_5
ganlikun	0:13413ea9a877	6308	* @arg @ref LL_RCC_PLLSAIR_DIV_6
ganlikun	0:13413ea9a877	6309	* @arg @ref LL_RCC_PLLSAIR_DIV_7
ganlikun	0:13413ea9a877	6310	* @param PLLDIVR This parameter can be one of the following values:
ganlikun	0:13413ea9a877	6311	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
ganlikun	0:13413ea9a877	6312	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
ganlikun	0:13413ea9a877	6313	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
ganlikun	0:13413ea9a877	6314	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
ganlikun	0:13413ea9a877	6315	* @retval None
ganlikun	0:13413ea9a877	6316	*/
ganlikun	0:13413ea9a877	6317	__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
ganlikun	0:13413ea9a877	6318	{
ganlikun	0:13413ea9a877	6319	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
ganlikun	0:13413ea9a877	6320	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN \| RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos \| PLLR);
ganlikun	0:13413ea9a877	6321	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR);
ganlikun	0:13413ea9a877	6322	}
ganlikun	0:13413ea9a877	6323	#endif /* LTDC */
ganlikun	0:13413ea9a877	6324
ganlikun	0:13413ea9a877	6325	/**
ganlikun	0:13413ea9a877	6326	* @brief Get division factor for PLLSAI input clock
ganlikun	0:13413ea9a877	6327	* @rmtoll PLLCFGR PLLM LL_RCC_PLLSAI_GetDivider\n
ganlikun	0:13413ea9a877	6328	* PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_GetDivider
ganlikun	0:13413ea9a877	6329	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	6330	* @arg @ref LL_RCC_PLLSAIM_DIV_2
ganlikun	0:13413ea9a877	6331	* @arg @ref LL_RCC_PLLSAIM_DIV_3
ganlikun	0:13413ea9a877	6332	* @arg @ref LL_RCC_PLLSAIM_DIV_4
ganlikun	0:13413ea9a877	6333	* @arg @ref LL_RCC_PLLSAIM_DIV_5
ganlikun	0:13413ea9a877	6334	* @arg @ref LL_RCC_PLLSAIM_DIV_6
ganlikun	0:13413ea9a877	6335	* @arg @ref LL_RCC_PLLSAIM_DIV_7
ganlikun	0:13413ea9a877	6336	* @arg @ref LL_RCC_PLLSAIM_DIV_8
ganlikun	0:13413ea9a877	6337	* @arg @ref LL_RCC_PLLSAIM_DIV_9
ganlikun	0:13413ea9a877	6338	* @arg @ref LL_RCC_PLLSAIM_DIV_10
ganlikun	0:13413ea9a877	6339	* @arg @ref LL_RCC_PLLSAIM_DIV_11
ganlikun	0:13413ea9a877	6340	* @arg @ref LL_RCC_PLLSAIM_DIV_12
ganlikun	0:13413ea9a877	6341	* @arg @ref LL_RCC_PLLSAIM_DIV_13
ganlikun	0:13413ea9a877	6342	* @arg @ref LL_RCC_PLLSAIM_DIV_14
ganlikun	0:13413ea9a877	6343	* @arg @ref LL_RCC_PLLSAIM_DIV_15
ganlikun	0:13413ea9a877	6344	* @arg @ref LL_RCC_PLLSAIM_DIV_16
ganlikun	0:13413ea9a877	6345	* @arg @ref LL_RCC_PLLSAIM_DIV_17
ganlikun	0:13413ea9a877	6346	* @arg @ref LL_RCC_PLLSAIM_DIV_18
ganlikun	0:13413ea9a877	6347	* @arg @ref LL_RCC_PLLSAIM_DIV_19
ganlikun	0:13413ea9a877	6348	* @arg @ref LL_RCC_PLLSAIM_DIV_20
ganlikun	0:13413ea9a877	6349	* @arg @ref LL_RCC_PLLSAIM_DIV_21
ganlikun	0:13413ea9a877	6350	* @arg @ref LL_RCC_PLLSAIM_DIV_22
ganlikun	0:13413ea9a877	6351	* @arg @ref LL_RCC_PLLSAIM_DIV_23
ganlikun	0:13413ea9a877	6352	* @arg @ref LL_RCC_PLLSAIM_DIV_24
ganlikun	0:13413ea9a877	6353	* @arg @ref LL_RCC_PLLSAIM_DIV_25
ganlikun	0:13413ea9a877	6354	* @arg @ref LL_RCC_PLLSAIM_DIV_26
ganlikun	0:13413ea9a877	6355	* @arg @ref LL_RCC_PLLSAIM_DIV_27
ganlikun	0:13413ea9a877	6356	* @arg @ref LL_RCC_PLLSAIM_DIV_28
ganlikun	0:13413ea9a877	6357	* @arg @ref LL_RCC_PLLSAIM_DIV_29
ganlikun	0:13413ea9a877	6358	* @arg @ref LL_RCC_PLLSAIM_DIV_30
ganlikun	0:13413ea9a877	6359	* @arg @ref LL_RCC_PLLSAIM_DIV_31
ganlikun	0:13413ea9a877	6360	* @arg @ref LL_RCC_PLLSAIM_DIV_32
ganlikun	0:13413ea9a877	6361	* @arg @ref LL_RCC_PLLSAIM_DIV_33
ganlikun	0:13413ea9a877	6362	* @arg @ref LL_RCC_PLLSAIM_DIV_34
ganlikun	0:13413ea9a877	6363	* @arg @ref LL_RCC_PLLSAIM_DIV_35
ganlikun	0:13413ea9a877	6364	* @arg @ref LL_RCC_PLLSAIM_DIV_36
ganlikun	0:13413ea9a877	6365	* @arg @ref LL_RCC_PLLSAIM_DIV_37
ganlikun	0:13413ea9a877	6366	* @arg @ref LL_RCC_PLLSAIM_DIV_38
ganlikun	0:13413ea9a877	6367	* @arg @ref LL_RCC_PLLSAIM_DIV_39
ganlikun	0:13413ea9a877	6368	* @arg @ref LL_RCC_PLLSAIM_DIV_40
ganlikun	0:13413ea9a877	6369	* @arg @ref LL_RCC_PLLSAIM_DIV_41
ganlikun	0:13413ea9a877	6370	* @arg @ref LL_RCC_PLLSAIM_DIV_42
ganlikun	0:13413ea9a877	6371	* @arg @ref LL_RCC_PLLSAIM_DIV_43
ganlikun	0:13413ea9a877	6372	* @arg @ref LL_RCC_PLLSAIM_DIV_44
ganlikun	0:13413ea9a877	6373	* @arg @ref LL_RCC_PLLSAIM_DIV_45
ganlikun	0:13413ea9a877	6374	* @arg @ref LL_RCC_PLLSAIM_DIV_46
ganlikun	0:13413ea9a877	6375	* @arg @ref LL_RCC_PLLSAIM_DIV_47
ganlikun	0:13413ea9a877	6376	* @arg @ref LL_RCC_PLLSAIM_DIV_48
ganlikun	0:13413ea9a877	6377	* @arg @ref LL_RCC_PLLSAIM_DIV_49
ganlikun	0:13413ea9a877	6378	* @arg @ref LL_RCC_PLLSAIM_DIV_50
ganlikun	0:13413ea9a877	6379	* @arg @ref LL_RCC_PLLSAIM_DIV_51
ganlikun	0:13413ea9a877	6380	* @arg @ref LL_RCC_PLLSAIM_DIV_52
ganlikun	0:13413ea9a877	6381	* @arg @ref LL_RCC_PLLSAIM_DIV_53
ganlikun	0:13413ea9a877	6382	* @arg @ref LL_RCC_PLLSAIM_DIV_54
ganlikun	0:13413ea9a877	6383	* @arg @ref LL_RCC_PLLSAIM_DIV_55
ganlikun	0:13413ea9a877	6384	* @arg @ref LL_RCC_PLLSAIM_DIV_56
ganlikun	0:13413ea9a877	6385	* @arg @ref LL_RCC_PLLSAIM_DIV_57
ganlikun	0:13413ea9a877	6386	* @arg @ref LL_RCC_PLLSAIM_DIV_58
ganlikun	0:13413ea9a877	6387	* @arg @ref LL_RCC_PLLSAIM_DIV_59
ganlikun	0:13413ea9a877	6388	* @arg @ref LL_RCC_PLLSAIM_DIV_60
ganlikun	0:13413ea9a877	6389	* @arg @ref LL_RCC_PLLSAIM_DIV_61
ganlikun	0:13413ea9a877	6390	* @arg @ref LL_RCC_PLLSAIM_DIV_62
ganlikun	0:13413ea9a877	6391	* @arg @ref LL_RCC_PLLSAIM_DIV_63
ganlikun	0:13413ea9a877	6392	*/
ganlikun	0:13413ea9a877	6393	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void)
ganlikun	0:13413ea9a877	6394	{
ganlikun	0:13413ea9a877	6395	#if defined(RCC_PLLSAICFGR_PLLSAIM)
ganlikun	0:13413ea9a877	6396	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM));
ganlikun	0:13413ea9a877	6397	#else
ganlikun	0:13413ea9a877	6398	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
ganlikun	0:13413ea9a877	6399	#endif /* RCC_PLLSAICFGR_PLLSAIM */
ganlikun	0:13413ea9a877	6400	}
ganlikun	0:13413ea9a877	6401
ganlikun	0:13413ea9a877	6402	/**
ganlikun	0:13413ea9a877	6403	* @brief Get SAIPLL multiplication factor for VCO
ganlikun	0:13413ea9a877	6404	* @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN
ganlikun	0:13413ea9a877	6405	* @retval Between 49/50(*) and 432
ganlikun	0:13413ea9a877	6406	*
ganlikun	0:13413ea9a877	6407	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	6408	*/
ganlikun	0:13413ea9a877	6409	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)
ganlikun	0:13413ea9a877	6410	{
ganlikun	0:13413ea9a877	6411	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
ganlikun	0:13413ea9a877	6412	}
ganlikun	0:13413ea9a877	6413
ganlikun	0:13413ea9a877	6414	/**
ganlikun	0:13413ea9a877	6415	* @brief Get SAIPLL division factor for PLLSAIQ
ganlikun	0:13413ea9a877	6416	* @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ
ganlikun	0:13413ea9a877	6417	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	6418	* @arg @ref LL_RCC_PLLSAIQ_DIV_2
ganlikun	0:13413ea9a877	6419	* @arg @ref LL_RCC_PLLSAIQ_DIV_3
ganlikun	0:13413ea9a877	6420	* @arg @ref LL_RCC_PLLSAIQ_DIV_4
ganlikun	0:13413ea9a877	6421	* @arg @ref LL_RCC_PLLSAIQ_DIV_5
ganlikun	0:13413ea9a877	6422	* @arg @ref LL_RCC_PLLSAIQ_DIV_6
ganlikun	0:13413ea9a877	6423	* @arg @ref LL_RCC_PLLSAIQ_DIV_7
ganlikun	0:13413ea9a877	6424	* @arg @ref LL_RCC_PLLSAIQ_DIV_8
ganlikun	0:13413ea9a877	6425	* @arg @ref LL_RCC_PLLSAIQ_DIV_9
ganlikun	0:13413ea9a877	6426	* @arg @ref LL_RCC_PLLSAIQ_DIV_10
ganlikun	0:13413ea9a877	6427	* @arg @ref LL_RCC_PLLSAIQ_DIV_11
ganlikun	0:13413ea9a877	6428	* @arg @ref LL_RCC_PLLSAIQ_DIV_12
ganlikun	0:13413ea9a877	6429	* @arg @ref LL_RCC_PLLSAIQ_DIV_13
ganlikun	0:13413ea9a877	6430	* @arg @ref LL_RCC_PLLSAIQ_DIV_14
ganlikun	0:13413ea9a877	6431	* @arg @ref LL_RCC_PLLSAIQ_DIV_15
ganlikun	0:13413ea9a877	6432	*/
ganlikun	0:13413ea9a877	6433	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)
ganlikun	0:13413ea9a877	6434	{
ganlikun	0:13413ea9a877	6435	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));
ganlikun	0:13413ea9a877	6436	}
ganlikun	0:13413ea9a877	6437
ganlikun	0:13413ea9a877	6438	#if defined(RCC_PLLSAICFGR_PLLSAIR)
ganlikun	0:13413ea9a877	6439	/**
ganlikun	0:13413ea9a877	6440	* @brief Get SAIPLL division factor for PLLSAIR
ganlikun	0:13413ea9a877	6441	* @note used for PLLSAICLK (SAI clock)
ganlikun	0:13413ea9a877	6442	* @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR
ganlikun	0:13413ea9a877	6443	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	6444	* @arg @ref LL_RCC_PLLSAIR_DIV_2
ganlikun	0:13413ea9a877	6445	* @arg @ref LL_RCC_PLLSAIR_DIV_3
ganlikun	0:13413ea9a877	6446	* @arg @ref LL_RCC_PLLSAIR_DIV_4
ganlikun	0:13413ea9a877	6447	* @arg @ref LL_RCC_PLLSAIR_DIV_5
ganlikun	0:13413ea9a877	6448	* @arg @ref LL_RCC_PLLSAIR_DIV_6
ganlikun	0:13413ea9a877	6449	* @arg @ref LL_RCC_PLLSAIR_DIV_7
ganlikun	0:13413ea9a877	6450	*/
ganlikun	0:13413ea9a877	6451	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)
ganlikun	0:13413ea9a877	6452	{
ganlikun	0:13413ea9a877	6453	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));
ganlikun	0:13413ea9a877	6454	}
ganlikun	0:13413ea9a877	6455	#endif /* RCC_PLLSAICFGR_PLLSAIR */
ganlikun	0:13413ea9a877	6456
ganlikun	0:13413ea9a877	6457	#if defined(RCC_PLLSAICFGR_PLLSAIP)
ganlikun	0:13413ea9a877	6458	/**
ganlikun	0:13413ea9a877	6459	* @brief Get SAIPLL division factor for PLLSAIP
ganlikun	0:13413ea9a877	6460	* @note used for PLL48MCLK (48M domain clock)
ganlikun	0:13413ea9a877	6461	* @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP
ganlikun	0:13413ea9a877	6462	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	6463	* @arg @ref LL_RCC_PLLSAIP_DIV_2
ganlikun	0:13413ea9a877	6464	* @arg @ref LL_RCC_PLLSAIP_DIV_4
ganlikun	0:13413ea9a877	6465	* @arg @ref LL_RCC_PLLSAIP_DIV_6
ganlikun	0:13413ea9a877	6466	* @arg @ref LL_RCC_PLLSAIP_DIV_8
ganlikun	0:13413ea9a877	6467	*/
ganlikun	0:13413ea9a877	6468	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)
ganlikun	0:13413ea9a877	6469	{
ganlikun	0:13413ea9a877	6470	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));
ganlikun	0:13413ea9a877	6471	}
ganlikun	0:13413ea9a877	6472	#endif /* RCC_PLLSAICFGR_PLLSAIP */
ganlikun	0:13413ea9a877	6473
ganlikun	0:13413ea9a877	6474	/**
ganlikun	0:13413ea9a877	6475	* @brief Get SAIPLL division factor for PLLSAIDIVQ
ganlikun	0:13413ea9a877	6476	* @note used PLLSAICLK selected (SAI clock)
ganlikun	0:13413ea9a877	6477	* @rmtoll DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ
ganlikun	0:13413ea9a877	6478	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	6479	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
ganlikun	0:13413ea9a877	6480	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
ganlikun	0:13413ea9a877	6481	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
ganlikun	0:13413ea9a877	6482	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
ganlikun	0:13413ea9a877	6483	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
ganlikun	0:13413ea9a877	6484	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
ganlikun	0:13413ea9a877	6485	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
ganlikun	0:13413ea9a877	6486	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
ganlikun	0:13413ea9a877	6487	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
ganlikun	0:13413ea9a877	6488	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
ganlikun	0:13413ea9a877	6489	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
ganlikun	0:13413ea9a877	6490	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
ganlikun	0:13413ea9a877	6491	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
ganlikun	0:13413ea9a877	6492	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
ganlikun	0:13413ea9a877	6493	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
ganlikun	0:13413ea9a877	6494	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
ganlikun	0:13413ea9a877	6495	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
ganlikun	0:13413ea9a877	6496	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
ganlikun	0:13413ea9a877	6497	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
ganlikun	0:13413ea9a877	6498	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
ganlikun	0:13413ea9a877	6499	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
ganlikun	0:13413ea9a877	6500	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
ganlikun	0:13413ea9a877	6501	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
ganlikun	0:13413ea9a877	6502	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
ganlikun	0:13413ea9a877	6503	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
ganlikun	0:13413ea9a877	6504	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
ganlikun	0:13413ea9a877	6505	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
ganlikun	0:13413ea9a877	6506	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
ganlikun	0:13413ea9a877	6507	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
ganlikun	0:13413ea9a877	6508	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
ganlikun	0:13413ea9a877	6509	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
ganlikun	0:13413ea9a877	6510	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
ganlikun	0:13413ea9a877	6511	*/
ganlikun	0:13413ea9a877	6512	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)
ganlikun	0:13413ea9a877	6513	{
ganlikun	0:13413ea9a877	6514	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ));
ganlikun	0:13413ea9a877	6515	}
ganlikun	0:13413ea9a877	6516
ganlikun	0:13413ea9a877	6517	#if defined(RCC_DCKCFGR_PLLSAIDIVR)
ganlikun	0:13413ea9a877	6518	/**
ganlikun	0:13413ea9a877	6519	* @brief Get SAIPLL division factor for PLLSAIDIVR
ganlikun	0:13413ea9a877	6520	* @note used for LTDC domain clock
ganlikun	0:13413ea9a877	6521	* @rmtoll DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR
ganlikun	0:13413ea9a877	6522	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	6523	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
ganlikun	0:13413ea9a877	6524	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
ganlikun	0:13413ea9a877	6525	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
ganlikun	0:13413ea9a877	6526	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
ganlikun	0:13413ea9a877	6527	*/
ganlikun	0:13413ea9a877	6528	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)
ganlikun	0:13413ea9a877	6529	{
ganlikun	0:13413ea9a877	6530	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR));
ganlikun	0:13413ea9a877	6531	}
ganlikun	0:13413ea9a877	6532	#endif /* RCC_DCKCFGR_PLLSAIDIVR */
ganlikun	0:13413ea9a877	6533
ganlikun	0:13413ea9a877	6534	/**
ganlikun	0:13413ea9a877	6535	* @}
ganlikun	0:13413ea9a877	6536	*/
ganlikun	0:13413ea9a877	6537	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	6538
ganlikun	0:13413ea9a877	6539	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
ganlikun	0:13413ea9a877	6540	* @{
ganlikun	0:13413ea9a877	6541	*/
ganlikun	0:13413ea9a877	6542
ganlikun	0:13413ea9a877	6543	/**
ganlikun	0:13413ea9a877	6544	* @brief Clear LSI ready interrupt flag
ganlikun	0:13413ea9a877	6545	* @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
ganlikun	0:13413ea9a877	6546	* @retval None
ganlikun	0:13413ea9a877	6547	*/
ganlikun	0:13413ea9a877	6548	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
ganlikun	0:13413ea9a877	6549	{
ganlikun	0:13413ea9a877	6550	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
ganlikun	0:13413ea9a877	6551	}
ganlikun	0:13413ea9a877	6552
ganlikun	0:13413ea9a877	6553	/**
ganlikun	0:13413ea9a877	6554	* @brief Clear LSE ready interrupt flag
ganlikun	0:13413ea9a877	6555	* @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
ganlikun	0:13413ea9a877	6556	* @retval None
ganlikun	0:13413ea9a877	6557	*/
ganlikun	0:13413ea9a877	6558	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
ganlikun	0:13413ea9a877	6559	{
ganlikun	0:13413ea9a877	6560	SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
ganlikun	0:13413ea9a877	6561	}
ganlikun	0:13413ea9a877	6562
ganlikun	0:13413ea9a877	6563	/**
ganlikun	0:13413ea9a877	6564	* @brief Clear HSI ready interrupt flag
ganlikun	0:13413ea9a877	6565	* @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
ganlikun	0:13413ea9a877	6566	* @retval None
ganlikun	0:13413ea9a877	6567	*/
ganlikun	0:13413ea9a877	6568	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
ganlikun	0:13413ea9a877	6569	{
ganlikun	0:13413ea9a877	6570	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
ganlikun	0:13413ea9a877	6571	}
ganlikun	0:13413ea9a877	6572
ganlikun	0:13413ea9a877	6573	/**
ganlikun	0:13413ea9a877	6574	* @brief Clear HSE ready interrupt flag
ganlikun	0:13413ea9a877	6575	* @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
ganlikun	0:13413ea9a877	6576	* @retval None
ganlikun	0:13413ea9a877	6577	*/
ganlikun	0:13413ea9a877	6578	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
ganlikun	0:13413ea9a877	6579	{
ganlikun	0:13413ea9a877	6580	SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
ganlikun	0:13413ea9a877	6581	}
ganlikun	0:13413ea9a877	6582
ganlikun	0:13413ea9a877	6583	/**
ganlikun	0:13413ea9a877	6584	* @brief Clear PLL ready interrupt flag
ganlikun	0:13413ea9a877	6585	* @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
ganlikun	0:13413ea9a877	6586	* @retval None
ganlikun	0:13413ea9a877	6587	*/
ganlikun	0:13413ea9a877	6588	__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
ganlikun	0:13413ea9a877	6589	{
ganlikun	0:13413ea9a877	6590	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
ganlikun	0:13413ea9a877	6591	}
ganlikun	0:13413ea9a877	6592
ganlikun	0:13413ea9a877	6593	#if defined(RCC_PLLI2S_SUPPORT)
ganlikun	0:13413ea9a877	6594	/**
ganlikun	0:13413ea9a877	6595	* @brief Clear PLLI2S ready interrupt flag
ganlikun	0:13413ea9a877	6596	* @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY
ganlikun	0:13413ea9a877	6597	* @retval None
ganlikun	0:13413ea9a877	6598	*/
ganlikun	0:13413ea9a877	6599	__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
ganlikun	0:13413ea9a877	6600	{
ganlikun	0:13413ea9a877	6601	SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
ganlikun	0:13413ea9a877	6602	}
ganlikun	0:13413ea9a877	6603
ganlikun	0:13413ea9a877	6604	#endif /* RCC_PLLI2S_SUPPORT */
ganlikun	0:13413ea9a877	6605
ganlikun	0:13413ea9a877	6606	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	6607	/**
ganlikun	0:13413ea9a877	6608	* @brief Clear PLLSAI ready interrupt flag
ganlikun	0:13413ea9a877	6609	* @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY
ganlikun	0:13413ea9a877	6610	* @retval None
ganlikun	0:13413ea9a877	6611	*/
ganlikun	0:13413ea9a877	6612	__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)
ganlikun	0:13413ea9a877	6613	{
ganlikun	0:13413ea9a877	6614	SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
ganlikun	0:13413ea9a877	6615	}
ganlikun	0:13413ea9a877	6616
ganlikun	0:13413ea9a877	6617	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	6618
ganlikun	0:13413ea9a877	6619	/**
ganlikun	0:13413ea9a877	6620	* @brief Clear Clock security system interrupt flag
ganlikun	0:13413ea9a877	6621	* @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
ganlikun	0:13413ea9a877	6622	* @retval None
ganlikun	0:13413ea9a877	6623	*/
ganlikun	0:13413ea9a877	6624	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
ganlikun	0:13413ea9a877	6625	{
ganlikun	0:13413ea9a877	6626	SET_BIT(RCC->CIR, RCC_CIR_CSSC);
ganlikun	0:13413ea9a877	6627	}
ganlikun	0:13413ea9a877	6628
ganlikun	0:13413ea9a877	6629	/**
ganlikun	0:13413ea9a877	6630	* @brief Check if LSI ready interrupt occurred or not
ganlikun	0:13413ea9a877	6631	* @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
ganlikun	0:13413ea9a877	6632	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	6633	*/
ganlikun	0:13413ea9a877	6634	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
ganlikun	0:13413ea9a877	6635	{
ganlikun	0:13413ea9a877	6636	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
ganlikun	0:13413ea9a877	6637	}
ganlikun	0:13413ea9a877	6638
ganlikun	0:13413ea9a877	6639	/**
ganlikun	0:13413ea9a877	6640	* @brief Check if LSE ready interrupt occurred or not
ganlikun	0:13413ea9a877	6641	* @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
ganlikun	0:13413ea9a877	6642	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	6643	*/
ganlikun	0:13413ea9a877	6644	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
ganlikun	0:13413ea9a877	6645	{
ganlikun	0:13413ea9a877	6646	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
ganlikun	0:13413ea9a877	6647	}
ganlikun	0:13413ea9a877	6648
ganlikun	0:13413ea9a877	6649	/**
ganlikun	0:13413ea9a877	6650	* @brief Check if HSI ready interrupt occurred or not
ganlikun	0:13413ea9a877	6651	* @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
ganlikun	0:13413ea9a877	6652	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	6653	*/
ganlikun	0:13413ea9a877	6654	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
ganlikun	0:13413ea9a877	6655	{
ganlikun	0:13413ea9a877	6656	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
ganlikun	0:13413ea9a877	6657	}
ganlikun	0:13413ea9a877	6658
ganlikun	0:13413ea9a877	6659	/**
ganlikun	0:13413ea9a877	6660	* @brief Check if HSE ready interrupt occurred or not
ganlikun	0:13413ea9a877	6661	* @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
ganlikun	0:13413ea9a877	6662	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	6663	*/
ganlikun	0:13413ea9a877	6664	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
ganlikun	0:13413ea9a877	6665	{
ganlikun	0:13413ea9a877	6666	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
ganlikun	0:13413ea9a877	6667	}
ganlikun	0:13413ea9a877	6668
ganlikun	0:13413ea9a877	6669	/**
ganlikun	0:13413ea9a877	6670	* @brief Check if PLL ready interrupt occurred or not
ganlikun	0:13413ea9a877	6671	* @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
ganlikun	0:13413ea9a877	6672	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	6673	*/
ganlikun	0:13413ea9a877	6674	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
ganlikun	0:13413ea9a877	6675	{
ganlikun	0:13413ea9a877	6676	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
ganlikun	0:13413ea9a877	6677	}
ganlikun	0:13413ea9a877	6678
ganlikun	0:13413ea9a877	6679	#if defined(RCC_PLLI2S_SUPPORT)
ganlikun	0:13413ea9a877	6680	/**
ganlikun	0:13413ea9a877	6681	* @brief Check if PLLI2S ready interrupt occurred or not
ganlikun	0:13413ea9a877	6682	* @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY
ganlikun	0:13413ea9a877	6683	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	6684	*/
ganlikun	0:13413ea9a877	6685	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
ganlikun	0:13413ea9a877	6686	{
ganlikun	0:13413ea9a877	6687	return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
ganlikun	0:13413ea9a877	6688	}
ganlikun	0:13413ea9a877	6689	#endif /* RCC_PLLI2S_SUPPORT */
ganlikun	0:13413ea9a877	6690
ganlikun	0:13413ea9a877	6691	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	6692	/**
ganlikun	0:13413ea9a877	6693	* @brief Check if PLLSAI ready interrupt occurred or not
ganlikun	0:13413ea9a877	6694	* @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY
ganlikun	0:13413ea9a877	6695	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	6696	*/
ganlikun	0:13413ea9a877	6697	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)
ganlikun	0:13413ea9a877	6698	{
ganlikun	0:13413ea9a877	6699	return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));
ganlikun	0:13413ea9a877	6700	}
ganlikun	0:13413ea9a877	6701	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	6702
ganlikun	0:13413ea9a877	6703	/**
ganlikun	0:13413ea9a877	6704	* @brief Check if Clock security system interrupt occurred or not
ganlikun	0:13413ea9a877	6705	* @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
ganlikun	0:13413ea9a877	6706	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	6707	*/
ganlikun	0:13413ea9a877	6708	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
ganlikun	0:13413ea9a877	6709	{
ganlikun	0:13413ea9a877	6710	return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
ganlikun	0:13413ea9a877	6711	}
ganlikun	0:13413ea9a877	6712
ganlikun	0:13413ea9a877	6713	/**
ganlikun	0:13413ea9a877	6714	* @brief Check if RCC flag Independent Watchdog reset is set or not.
ganlikun	0:13413ea9a877	6715	* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
ganlikun	0:13413ea9a877	6716	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	6717	*/
ganlikun	0:13413ea9a877	6718	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
ganlikun	0:13413ea9a877	6719	{
ganlikun	0:13413ea9a877	6720	return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
ganlikun	0:13413ea9a877	6721	}
ganlikun	0:13413ea9a877	6722
ganlikun	0:13413ea9a877	6723	/**
ganlikun	0:13413ea9a877	6724	* @brief Check if RCC flag Low Power reset is set or not.
ganlikun	0:13413ea9a877	6725	* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
ganlikun	0:13413ea9a877	6726	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	6727	*/
ganlikun	0:13413ea9a877	6728	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
ganlikun	0:13413ea9a877	6729	{
ganlikun	0:13413ea9a877	6730	return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
ganlikun	0:13413ea9a877	6731	}
ganlikun	0:13413ea9a877	6732
ganlikun	0:13413ea9a877	6733	/**
ganlikun	0:13413ea9a877	6734	* @brief Check if RCC flag Pin reset is set or not.
ganlikun	0:13413ea9a877	6735	* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
ganlikun	0:13413ea9a877	6736	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	6737	*/
ganlikun	0:13413ea9a877	6738	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
ganlikun	0:13413ea9a877	6739	{
ganlikun	0:13413ea9a877	6740	return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
ganlikun	0:13413ea9a877	6741	}
ganlikun	0:13413ea9a877	6742
ganlikun	0:13413ea9a877	6743	/**
ganlikun	0:13413ea9a877	6744	* @brief Check if RCC flag POR/PDR reset is set or not.
ganlikun	0:13413ea9a877	6745	* @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
ganlikun	0:13413ea9a877	6746	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	6747	*/
ganlikun	0:13413ea9a877	6748	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
ganlikun	0:13413ea9a877	6749	{
ganlikun	0:13413ea9a877	6750	return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
ganlikun	0:13413ea9a877	6751	}
ganlikun	0:13413ea9a877	6752
ganlikun	0:13413ea9a877	6753	/**
ganlikun	0:13413ea9a877	6754	* @brief Check if RCC flag Software reset is set or not.
ganlikun	0:13413ea9a877	6755	* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
ganlikun	0:13413ea9a877	6756	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	6757	*/
ganlikun	0:13413ea9a877	6758	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
ganlikun	0:13413ea9a877	6759	{
ganlikun	0:13413ea9a877	6760	return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
ganlikun	0:13413ea9a877	6761	}
ganlikun	0:13413ea9a877	6762
ganlikun	0:13413ea9a877	6763	/**
ganlikun	0:13413ea9a877	6764	* @brief Check if RCC flag Window Watchdog reset is set or not.
ganlikun	0:13413ea9a877	6765	* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
ganlikun	0:13413ea9a877	6766	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	6767	*/
ganlikun	0:13413ea9a877	6768	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
ganlikun	0:13413ea9a877	6769	{
ganlikun	0:13413ea9a877	6770	return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
ganlikun	0:13413ea9a877	6771	}
ganlikun	0:13413ea9a877	6772
ganlikun	0:13413ea9a877	6773	#if defined(RCC_CSR_BORRSTF)
ganlikun	0:13413ea9a877	6774	/**
ganlikun	0:13413ea9a877	6775	* @brief Check if RCC flag BOR reset is set or not.
ganlikun	0:13413ea9a877	6776	* @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
ganlikun	0:13413ea9a877	6777	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	6778	*/
ganlikun	0:13413ea9a877	6779	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
ganlikun	0:13413ea9a877	6780	{
ganlikun	0:13413ea9a877	6781	return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
ganlikun	0:13413ea9a877	6782	}
ganlikun	0:13413ea9a877	6783	#endif /* RCC_CSR_BORRSTF */
ganlikun	0:13413ea9a877	6784
ganlikun	0:13413ea9a877	6785	/**
ganlikun	0:13413ea9a877	6786	* @brief Set RMVF bit to clear the reset flags.
ganlikun	0:13413ea9a877	6787	* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
ganlikun	0:13413ea9a877	6788	* @retval None
ganlikun	0:13413ea9a877	6789	*/
ganlikun	0:13413ea9a877	6790	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
ganlikun	0:13413ea9a877	6791	{
ganlikun	0:13413ea9a877	6792	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
ganlikun	0:13413ea9a877	6793	}
ganlikun	0:13413ea9a877	6794
ganlikun	0:13413ea9a877	6795	/**
ganlikun	0:13413ea9a877	6796	* @}
ganlikun	0:13413ea9a877	6797	*/
ganlikun	0:13413ea9a877	6798
ganlikun	0:13413ea9a877	6799	/** @defgroup RCC_LL_EF_IT_Management IT Management
ganlikun	0:13413ea9a877	6800	* @{
ganlikun	0:13413ea9a877	6801	*/
ganlikun	0:13413ea9a877	6802
ganlikun	0:13413ea9a877	6803	/**
ganlikun	0:13413ea9a877	6804	* @brief Enable LSI ready interrupt
ganlikun	0:13413ea9a877	6805	* @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
ganlikun	0:13413ea9a877	6806	* @retval None
ganlikun	0:13413ea9a877	6807	*/
ganlikun	0:13413ea9a877	6808	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
ganlikun	0:13413ea9a877	6809	{
ganlikun	0:13413ea9a877	6810	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
ganlikun	0:13413ea9a877	6811	}
ganlikun	0:13413ea9a877	6812
ganlikun	0:13413ea9a877	6813	/**
ganlikun	0:13413ea9a877	6814	* @brief Enable LSE ready interrupt
ganlikun	0:13413ea9a877	6815	* @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
ganlikun	0:13413ea9a877	6816	* @retval None
ganlikun	0:13413ea9a877	6817	*/
ganlikun	0:13413ea9a877	6818	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
ganlikun	0:13413ea9a877	6819	{
ganlikun	0:13413ea9a877	6820	SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
ganlikun	0:13413ea9a877	6821	}
ganlikun	0:13413ea9a877	6822
ganlikun	0:13413ea9a877	6823	/**
ganlikun	0:13413ea9a877	6824	* @brief Enable HSI ready interrupt
ganlikun	0:13413ea9a877	6825	* @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
ganlikun	0:13413ea9a877	6826	* @retval None
ganlikun	0:13413ea9a877	6827	*/
ganlikun	0:13413ea9a877	6828	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
ganlikun	0:13413ea9a877	6829	{
ganlikun	0:13413ea9a877	6830	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
ganlikun	0:13413ea9a877	6831	}
ganlikun	0:13413ea9a877	6832
ganlikun	0:13413ea9a877	6833	/**
ganlikun	0:13413ea9a877	6834	* @brief Enable HSE ready interrupt
ganlikun	0:13413ea9a877	6835	* @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
ganlikun	0:13413ea9a877	6836	* @retval None
ganlikun	0:13413ea9a877	6837	*/
ganlikun	0:13413ea9a877	6838	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
ganlikun	0:13413ea9a877	6839	{
ganlikun	0:13413ea9a877	6840	SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
ganlikun	0:13413ea9a877	6841	}
ganlikun	0:13413ea9a877	6842
ganlikun	0:13413ea9a877	6843	/**
ganlikun	0:13413ea9a877	6844	* @brief Enable PLL ready interrupt
ganlikun	0:13413ea9a877	6845	* @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
ganlikun	0:13413ea9a877	6846	* @retval None
ganlikun	0:13413ea9a877	6847	*/
ganlikun	0:13413ea9a877	6848	__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
ganlikun	0:13413ea9a877	6849	{
ganlikun	0:13413ea9a877	6850	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
ganlikun	0:13413ea9a877	6851	}
ganlikun	0:13413ea9a877	6852
ganlikun	0:13413ea9a877	6853	#if defined(RCC_PLLI2S_SUPPORT)
ganlikun	0:13413ea9a877	6854	/**
ganlikun	0:13413ea9a877	6855	* @brief Enable PLLI2S ready interrupt
ganlikun	0:13413ea9a877	6856	* @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY
ganlikun	0:13413ea9a877	6857	* @retval None
ganlikun	0:13413ea9a877	6858	*/
ganlikun	0:13413ea9a877	6859	__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
ganlikun	0:13413ea9a877	6860	{
ganlikun	0:13413ea9a877	6861	SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
ganlikun	0:13413ea9a877	6862	}
ganlikun	0:13413ea9a877	6863	#endif /* RCC_PLLI2S_SUPPORT */
ganlikun	0:13413ea9a877	6864
ganlikun	0:13413ea9a877	6865	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	6866	/**
ganlikun	0:13413ea9a877	6867	* @brief Enable PLLSAI ready interrupt
ganlikun	0:13413ea9a877	6868	* @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY
ganlikun	0:13413ea9a877	6869	* @retval None
ganlikun	0:13413ea9a877	6870	*/
ganlikun	0:13413ea9a877	6871	__STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)
ganlikun	0:13413ea9a877	6872	{
ganlikun	0:13413ea9a877	6873	SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
ganlikun	0:13413ea9a877	6874	}
ganlikun	0:13413ea9a877	6875	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	6876
ganlikun	0:13413ea9a877	6877	/**
ganlikun	0:13413ea9a877	6878	* @brief Disable LSI ready interrupt
ganlikun	0:13413ea9a877	6879	* @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
ganlikun	0:13413ea9a877	6880	* @retval None
ganlikun	0:13413ea9a877	6881	*/
ganlikun	0:13413ea9a877	6882	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
ganlikun	0:13413ea9a877	6883	{
ganlikun	0:13413ea9a877	6884	CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
ganlikun	0:13413ea9a877	6885	}
ganlikun	0:13413ea9a877	6886
ganlikun	0:13413ea9a877	6887	/**
ganlikun	0:13413ea9a877	6888	* @brief Disable LSE ready interrupt
ganlikun	0:13413ea9a877	6889	* @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
ganlikun	0:13413ea9a877	6890	* @retval None
ganlikun	0:13413ea9a877	6891	*/
ganlikun	0:13413ea9a877	6892	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
ganlikun	0:13413ea9a877	6893	{
ganlikun	0:13413ea9a877	6894	CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
ganlikun	0:13413ea9a877	6895	}
ganlikun	0:13413ea9a877	6896
ganlikun	0:13413ea9a877	6897	/**
ganlikun	0:13413ea9a877	6898	* @brief Disable HSI ready interrupt
ganlikun	0:13413ea9a877	6899	* @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
ganlikun	0:13413ea9a877	6900	* @retval None
ganlikun	0:13413ea9a877	6901	*/
ganlikun	0:13413ea9a877	6902	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
ganlikun	0:13413ea9a877	6903	{
ganlikun	0:13413ea9a877	6904	CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
ganlikun	0:13413ea9a877	6905	}
ganlikun	0:13413ea9a877	6906
ganlikun	0:13413ea9a877	6907	/**
ganlikun	0:13413ea9a877	6908	* @brief Disable HSE ready interrupt
ganlikun	0:13413ea9a877	6909	* @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
ganlikun	0:13413ea9a877	6910	* @retval None
ganlikun	0:13413ea9a877	6911	*/
ganlikun	0:13413ea9a877	6912	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
ganlikun	0:13413ea9a877	6913	{
ganlikun	0:13413ea9a877	6914	CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
ganlikun	0:13413ea9a877	6915	}
ganlikun	0:13413ea9a877	6916
ganlikun	0:13413ea9a877	6917	/**
ganlikun	0:13413ea9a877	6918	* @brief Disable PLL ready interrupt
ganlikun	0:13413ea9a877	6919	* @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
ganlikun	0:13413ea9a877	6920	* @retval None
ganlikun	0:13413ea9a877	6921	*/
ganlikun	0:13413ea9a877	6922	__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
ganlikun	0:13413ea9a877	6923	{
ganlikun	0:13413ea9a877	6924	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
ganlikun	0:13413ea9a877	6925	}
ganlikun	0:13413ea9a877	6926
ganlikun	0:13413ea9a877	6927	#if defined(RCC_PLLI2S_SUPPORT)
ganlikun	0:13413ea9a877	6928	/**
ganlikun	0:13413ea9a877	6929	* @brief Disable PLLI2S ready interrupt
ganlikun	0:13413ea9a877	6930	* @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY
ganlikun	0:13413ea9a877	6931	* @retval None
ganlikun	0:13413ea9a877	6932	*/
ganlikun	0:13413ea9a877	6933	__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
ganlikun	0:13413ea9a877	6934	{
ganlikun	0:13413ea9a877	6935	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
ganlikun	0:13413ea9a877	6936	}
ganlikun	0:13413ea9a877	6937
ganlikun	0:13413ea9a877	6938	#endif /* RCC_PLLI2S_SUPPORT */
ganlikun	0:13413ea9a877	6939
ganlikun	0:13413ea9a877	6940	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	6941	/**
ganlikun	0:13413ea9a877	6942	* @brief Disable PLLSAI ready interrupt
ganlikun	0:13413ea9a877	6943	* @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY
ganlikun	0:13413ea9a877	6944	* @retval None
ganlikun	0:13413ea9a877	6945	*/
ganlikun	0:13413ea9a877	6946	__STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)
ganlikun	0:13413ea9a877	6947	{
ganlikun	0:13413ea9a877	6948	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
ganlikun	0:13413ea9a877	6949	}
ganlikun	0:13413ea9a877	6950	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	6951
ganlikun	0:13413ea9a877	6952	/**
ganlikun	0:13413ea9a877	6953	* @brief Checks if LSI ready interrupt source is enabled or disabled.
ganlikun	0:13413ea9a877	6954	* @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
ganlikun	0:13413ea9a877	6955	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	6956	*/
ganlikun	0:13413ea9a877	6957	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
ganlikun	0:13413ea9a877	6958	{
ganlikun	0:13413ea9a877	6959	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
ganlikun	0:13413ea9a877	6960	}
ganlikun	0:13413ea9a877	6961
ganlikun	0:13413ea9a877	6962	/**
ganlikun	0:13413ea9a877	6963	* @brief Checks if LSE ready interrupt source is enabled or disabled.
ganlikun	0:13413ea9a877	6964	* @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
ganlikun	0:13413ea9a877	6965	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	6966	*/
ganlikun	0:13413ea9a877	6967	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
ganlikun	0:13413ea9a877	6968	{
ganlikun	0:13413ea9a877	6969	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
ganlikun	0:13413ea9a877	6970	}
ganlikun	0:13413ea9a877	6971
ganlikun	0:13413ea9a877	6972	/**
ganlikun	0:13413ea9a877	6973	* @brief Checks if HSI ready interrupt source is enabled or disabled.
ganlikun	0:13413ea9a877	6974	* @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
ganlikun	0:13413ea9a877	6975	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	6976	*/
ganlikun	0:13413ea9a877	6977	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
ganlikun	0:13413ea9a877	6978	{
ganlikun	0:13413ea9a877	6979	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
ganlikun	0:13413ea9a877	6980	}
ganlikun	0:13413ea9a877	6981
ganlikun	0:13413ea9a877	6982	/**
ganlikun	0:13413ea9a877	6983	* @brief Checks if HSE ready interrupt source is enabled or disabled.
ganlikun	0:13413ea9a877	6984	* @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
ganlikun	0:13413ea9a877	6985	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	6986	*/
ganlikun	0:13413ea9a877	6987	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
ganlikun	0:13413ea9a877	6988	{
ganlikun	0:13413ea9a877	6989	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
ganlikun	0:13413ea9a877	6990	}
ganlikun	0:13413ea9a877	6991
ganlikun	0:13413ea9a877	6992	/**
ganlikun	0:13413ea9a877	6993	* @brief Checks if PLL ready interrupt source is enabled or disabled.
ganlikun	0:13413ea9a877	6994	* @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
ganlikun	0:13413ea9a877	6995	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	6996	*/
ganlikun	0:13413ea9a877	6997	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
ganlikun	0:13413ea9a877	6998	{
ganlikun	0:13413ea9a877	6999	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
ganlikun	0:13413ea9a877	7000	}
ganlikun	0:13413ea9a877	7001
ganlikun	0:13413ea9a877	7002	#if defined(RCC_PLLI2S_SUPPORT)
ganlikun	0:13413ea9a877	7003	/**
ganlikun	0:13413ea9a877	7004	* @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
ganlikun	0:13413ea9a877	7005	* @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
ganlikun	0:13413ea9a877	7006	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	7007	*/
ganlikun	0:13413ea9a877	7008	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
ganlikun	0:13413ea9a877	7009	{
ganlikun	0:13413ea9a877	7010	return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
ganlikun	0:13413ea9a877	7011	}
ganlikun	0:13413ea9a877	7012
ganlikun	0:13413ea9a877	7013	#endif /* RCC_PLLI2S_SUPPORT */
ganlikun	0:13413ea9a877	7014
ganlikun	0:13413ea9a877	7015	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	7016	/**
ganlikun	0:13413ea9a877	7017	* @brief Checks if PLLSAI ready interrupt source is enabled or disabled.
ganlikun	0:13413ea9a877	7018	* @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY
ganlikun	0:13413ea9a877	7019	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	7020	*/
ganlikun	0:13413ea9a877	7021	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)
ganlikun	0:13413ea9a877	7022	{
ganlikun	0:13413ea9a877	7023	return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));
ganlikun	0:13413ea9a877	7024	}
ganlikun	0:13413ea9a877	7025	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	7026
ganlikun	0:13413ea9a877	7027	/**
ganlikun	0:13413ea9a877	7028	* @}
ganlikun	0:13413ea9a877	7029	*/
ganlikun	0:13413ea9a877	7030
ganlikun	0:13413ea9a877	7031	#if defined(USE_FULL_LL_DRIVER)
ganlikun	0:13413ea9a877	7032	/** @defgroup RCC_LL_EF_Init De-initialization function
ganlikun	0:13413ea9a877	7033	* @{
ganlikun	0:13413ea9a877	7034	*/
ganlikun	0:13413ea9a877	7035	ErrorStatus LL_RCC_DeInit(void);
ganlikun	0:13413ea9a877	7036	/**
ganlikun	0:13413ea9a877	7037	* @}
ganlikun	0:13413ea9a877	7038	*/
ganlikun	0:13413ea9a877	7039
ganlikun	0:13413ea9a877	7040	/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
ganlikun	0:13413ea9a877	7041	* @{
ganlikun	0:13413ea9a877	7042	*/
ganlikun	0:13413ea9a877	7043	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
ganlikun	0:13413ea9a877	7044	#if defined(FMPI2C1)
ganlikun	0:13413ea9a877	7045	uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource);
ganlikun	0:13413ea9a877	7046	#endif /* FMPI2C1 */
ganlikun	0:13413ea9a877	7047	#if defined(LPTIM1)
ganlikun	0:13413ea9a877	7048	uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
ganlikun	0:13413ea9a877	7049	#endif /* LPTIM1 */
ganlikun	0:13413ea9a877	7050	#if defined(SAI1)
ganlikun	0:13413ea9a877	7051	uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
ganlikun	0:13413ea9a877	7052	#endif /* SAI1 */
ganlikun	0:13413ea9a877	7053	#if defined(SDIO)
ganlikun	0:13413ea9a877	7054	uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource);
ganlikun	0:13413ea9a877	7055	#endif /* SDIO */
ganlikun	0:13413ea9a877	7056	#if defined(RNG)
ganlikun	0:13413ea9a877	7057	uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
ganlikun	0:13413ea9a877	7058	#endif /* RNG */
ganlikun	0:13413ea9a877	7059	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
ganlikun	0:13413ea9a877	7060	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
ganlikun	0:13413ea9a877	7061	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
ganlikun	0:13413ea9a877	7062	#if defined(DFSDM1_Channel0)
ganlikun	0:13413ea9a877	7063	uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
ganlikun	0:13413ea9a877	7064	uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
ganlikun	0:13413ea9a877	7065	#endif /* DFSDM1_Channel0 */
ganlikun	0:13413ea9a877	7066	uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
ganlikun	0:13413ea9a877	7067	#if defined(CEC)
ganlikun	0:13413ea9a877	7068	uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
ganlikun	0:13413ea9a877	7069	#endif /* CEC */
ganlikun	0:13413ea9a877	7070	#if defined(LTDC)
ganlikun	0:13413ea9a877	7071	uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
ganlikun	0:13413ea9a877	7072	#endif /* LTDC */
ganlikun	0:13413ea9a877	7073	#if defined(SPDIFRX)
ganlikun	0:13413ea9a877	7074	uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
ganlikun	0:13413ea9a877	7075	#endif /* SPDIFRX */
ganlikun	0:13413ea9a877	7076	#if defined(DSI)
ganlikun	0:13413ea9a877	7077	uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
ganlikun	0:13413ea9a877	7078	#endif /* DSI */
ganlikun	0:13413ea9a877	7079	/**
ganlikun	0:13413ea9a877	7080	* @}
ganlikun	0:13413ea9a877	7081	*/
ganlikun	0:13413ea9a877	7082	#endif /* USE_FULL_LL_DRIVER */
ganlikun	0:13413ea9a877	7083
ganlikun	0:13413ea9a877	7084	/**
ganlikun	0:13413ea9a877	7085	* @}
ganlikun	0:13413ea9a877	7086	*/
ganlikun	0:13413ea9a877	7087
ganlikun	0:13413ea9a877	7088	/**
ganlikun	0:13413ea9a877	7089	* @}
ganlikun	0:13413ea9a877	7090	*/
ganlikun	0:13413ea9a877	7091
ganlikun	0:13413ea9a877	7092	#endif /* defined(RCC) */
ganlikun	0:13413ea9a877	7093
ganlikun	0:13413ea9a877	7094	/**
ganlikun	0:13413ea9a877	7095	* @}
ganlikun	0:13413ea9a877	7096	*/
ganlikun	0:13413ea9a877	7097
ganlikun	0:13413ea9a877	7098	#ifdef __cplusplus
ganlikun	0:13413ea9a877	7099	}
ganlikun	0:13413ea9a877	7100	#endif
ganlikun	0:13413ea9a877	7101
ganlikun	0:13413ea9a877	7102	#endif /* __STM32F4xx_LL_RCC_H */
ganlikun	0:13413ea9a877	7103
ganlikun	0:13413ea9a877	7104	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
ganlikun	0:13413ea9a877	7105

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Type:	Library
Created:	05 Jul 2022
Imports:	1
Forks:	0
Commits:	1
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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.h@0:13413ea9a877, 2022-06-12 (annotated)

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