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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.c@0:13413ea9a877, 2022-06-12 (annotated)

Committer:: ganlikun
Date:: Sun Jun 12 14:02:44 2022 +0000
Revision:: 0:13413ea9a877

Who changed what in which revision?

User	Revision	Line number	New contents of line
ganlikun	0:13413ea9a877	1	/**
ganlikun	0:13413ea9a877	2	******************************************************************************
ganlikun	0:13413ea9a877	3	* @file stm32f4xx_ll_rcc.c
ganlikun	0:13413ea9a877	4	* @author MCD Application Team
ganlikun	0:13413ea9a877	5	* @version V1.7.1
ganlikun	0:13413ea9a877	6	* @date 14-April-2017
ganlikun	0:13413ea9a877	7	* @brief RCC LL module driver.
ganlikun	0:13413ea9a877	8	******************************************************************************
ganlikun	0:13413ea9a877	9	* @attention
ganlikun	0:13413ea9a877	10	*
ganlikun	0:13413ea9a877	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun	0:13413ea9a877	12	*
ganlikun	0:13413ea9a877	13	* Redistribution and use in source and binary forms, with or without modification,
ganlikun	0:13413ea9a877	14	* are permitted provided that the following conditions are met:
ganlikun	0:13413ea9a877	15	* 1. Redistributions of source code must retain the above copyright notice,
ganlikun	0:13413ea9a877	16	* this list of conditions and the following disclaimer.
ganlikun	0:13413ea9a877	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun	0:13413ea9a877	18	* this list of conditions and the following disclaimer in the documentation
ganlikun	0:13413ea9a877	19	* and/or other materials provided with the distribution.
ganlikun	0:13413ea9a877	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun	0:13413ea9a877	21	* may be used to endorse or promote products derived from this software
ganlikun	0:13413ea9a877	22	* without specific prior written permission.
ganlikun	0:13413ea9a877	23	*
ganlikun	0:13413ea9a877	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun	0:13413ea9a877	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun	0:13413ea9a877	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun	0:13413ea9a877	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun	0:13413ea9a877	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun	0:13413ea9a877	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun	0:13413ea9a877	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun	0:13413ea9a877	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun	0:13413ea9a877	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun	0:13413ea9a877	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun	0:13413ea9a877	34	*
ganlikun	0:13413ea9a877	35	******************************************************************************
ganlikun	0:13413ea9a877	36	*/
ganlikun	0:13413ea9a877	37	#if defined(USE_FULL_LL_DRIVER)
ganlikun	0:13413ea9a877	38
ganlikun	0:13413ea9a877	39	/* Includes ------------------------------------------------------------------*/
ganlikun	0:13413ea9a877	40	#include "stm32f4xx_ll_rcc.h"
ganlikun	0:13413ea9a877	41	#ifdef USE_FULL_ASSERT
ganlikun	0:13413ea9a877	42	#include "stm32_assert.h"
ganlikun	0:13413ea9a877	43	#else
ganlikun	0:13413ea9a877	44	#define assert_param(expr) ((void)0U)
ganlikun	0:13413ea9a877	45	#endif
ganlikun	0:13413ea9a877	46	/** @addtogroup STM32F4xx_LL_Driver
ganlikun	0:13413ea9a877	47	* @{
ganlikun	0:13413ea9a877	48	*/
ganlikun	0:13413ea9a877	49
ganlikun	0:13413ea9a877	50	#if defined(RCC)
ganlikun	0:13413ea9a877	51
ganlikun	0:13413ea9a877	52	/** @addtogroup RCC_LL
ganlikun	0:13413ea9a877	53	* @{
ganlikun	0:13413ea9a877	54	*/
ganlikun	0:13413ea9a877	55
ganlikun	0:13413ea9a877	56	/* Private types -------------------------------------------------------------*/
ganlikun	0:13413ea9a877	57	/* Private variables ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	58	/* Private constants ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	59	/* Private macros ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	60	/** @addtogroup RCC_LL_Private_Macros
ganlikun	0:13413ea9a877	61	* @{
ganlikun	0:13413ea9a877	62	*/
ganlikun	0:13413ea9a877	63	#if defined(FMPI2C1)
ganlikun	0:13413ea9a877	64	#define IS_LL_RCC_FMPI2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_FMPI2C1_CLKSOURCE)
ganlikun	0:13413ea9a877	65	#endif /* FMPI2C1 */
ganlikun	0:13413ea9a877	66
ganlikun	0:13413ea9a877	67	#if defined(LPTIM1)
ganlikun	0:13413ea9a877	68	#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
ganlikun	0:13413ea9a877	69	#endif /* LPTIM1 */
ganlikun	0:13413ea9a877	70
ganlikun	0:13413ea9a877	71	#if defined(SAI1)
ganlikun	0:13413ea9a877	72	#if defined(RCC_DCKCFGR_SAI1SRC)
ganlikun	0:13413ea9a877	73	#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
ganlikun	0:13413ea9a877	74	\|\| ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
ganlikun	0:13413ea9a877	75	#elif defined(RCC_DCKCFGR_SAI1ASRC)
ganlikun	0:13413ea9a877	76	#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_A_CLKSOURCE) \
ganlikun	0:13413ea9a877	77	\|\| ((__VALUE__) == LL_RCC_SAI1_B_CLKSOURCE))
ganlikun	0:13413ea9a877	78	#endif /* RCC_DCKCFGR_SAI1SRC */
ganlikun	0:13413ea9a877	79	#endif /* SAI1 */
ganlikun	0:13413ea9a877	80
ganlikun	0:13413ea9a877	81	#if defined(SDIO)
ganlikun	0:13413ea9a877	82	#define IS_LL_RCC_SDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDIO_CLKSOURCE))
ganlikun	0:13413ea9a877	83	#endif /* SDIO */
ganlikun	0:13413ea9a877	84
ganlikun	0:13413ea9a877	85	#if defined(RNG)
ganlikun	0:13413ea9a877	86	#define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
ganlikun	0:13413ea9a877	87	#endif /* RNG */
ganlikun	0:13413ea9a877	88
ganlikun	0:13413ea9a877	89	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
ganlikun	0:13413ea9a877	90	#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
ganlikun	0:13413ea9a877	91	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
ganlikun	0:13413ea9a877	92
ganlikun	0:13413ea9a877	93	#if defined(DFSDM2_Channel0)
ganlikun	0:13413ea9a877	94	#define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
ganlikun	0:13413ea9a877	95
ganlikun	0:13413ea9a877	96	#define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE) \
ganlikun	0:13413ea9a877	97	\|\| ((__VALUE__) == LL_RCC_DFSDM2_AUDIO_CLKSOURCE))
ganlikun	0:13413ea9a877	98	#elif defined(DFSDM1_Channel0)
ganlikun	0:13413ea9a877	99	#define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
ganlikun	0:13413ea9a877	100
ganlikun	0:13413ea9a877	101	#define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))
ganlikun	0:13413ea9a877	102	#endif /* DFSDM2_Channel0 */
ganlikun	0:13413ea9a877	103
ganlikun	0:13413ea9a877	104	#if defined(RCC_DCKCFGR_I2S2SRC)
ganlikun	0:13413ea9a877	105	#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE) \
ganlikun	0:13413ea9a877	106	\|\| ((__VALUE__) == LL_RCC_I2S2_CLKSOURCE))
ganlikun	0:13413ea9a877	107	#else
ganlikun	0:13413ea9a877	108	#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))
ganlikun	0:13413ea9a877	109	#endif /* RCC_DCKCFGR_I2S2SRC */
ganlikun	0:13413ea9a877	110
ganlikun	0:13413ea9a877	111	#if defined(CEC)
ganlikun	0:13413ea9a877	112	#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
ganlikun	0:13413ea9a877	113	#endif /* CEC */
ganlikun	0:13413ea9a877	114
ganlikun	0:13413ea9a877	115	#if defined(DSI)
ganlikun	0:13413ea9a877	116	#define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
ganlikun	0:13413ea9a877	117	#endif /* DSI */
ganlikun	0:13413ea9a877	118
ganlikun	0:13413ea9a877	119	#if defined(LTDC)
ganlikun	0:13413ea9a877	120	#define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))
ganlikun	0:13413ea9a877	121	#endif /* LTDC */
ganlikun	0:13413ea9a877	122
ganlikun	0:13413ea9a877	123	#if defined(SPDIFRX)
ganlikun	0:13413ea9a877	124	#define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE))
ganlikun	0:13413ea9a877	125	#endif /* SPDIFRX */
ganlikun	0:13413ea9a877	126	/**
ganlikun	0:13413ea9a877	127	* @}
ganlikun	0:13413ea9a877	128	*/
ganlikun	0:13413ea9a877	129
ganlikun	0:13413ea9a877	130	/* Private function prototypes -----------------------------------------------*/
ganlikun	0:13413ea9a877	131	/** @defgroup RCC_LL_Private_Functions RCC Private functions
ganlikun	0:13413ea9a877	132	* @{
ganlikun	0:13413ea9a877	133	*/
ganlikun	0:13413ea9a877	134	uint32_t RCC_GetSystemClockFreq(void);
ganlikun	0:13413ea9a877	135	uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
ganlikun	0:13413ea9a877	136	uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
ganlikun	0:13413ea9a877	137	uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
ganlikun	0:13413ea9a877	138	uint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source);
ganlikun	0:13413ea9a877	139	uint32_t RCC_PLL_GetFreqDomain_48M(void);
ganlikun	0:13413ea9a877	140	#if defined(RCC_DCKCFGR_I2SSRC) \|\| defined(RCC_DCKCFGR_I2S1SRC)
ganlikun	0:13413ea9a877	141	uint32_t RCC_PLL_GetFreqDomain_I2S(void);
ganlikun	0:13413ea9a877	142	#endif /* RCC_DCKCFGR_I2SSRC \|\| RCC_DCKCFGR_I2S1SRC */
ganlikun	0:13413ea9a877	143	#if defined(SPDIFRX)
ganlikun	0:13413ea9a877	144	uint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void);
ganlikun	0:13413ea9a877	145	#endif /* SPDIFRX */
ganlikun	0:13413ea9a877	146	#if defined(RCC_PLLCFGR_PLLR)
ganlikun	0:13413ea9a877	147	#if defined(SAI1)
ganlikun	0:13413ea9a877	148	uint32_t RCC_PLL_GetFreqDomain_SAI(void);
ganlikun	0:13413ea9a877	149	#endif /* SAI1 */
ganlikun	0:13413ea9a877	150	#endif /* RCC_PLLCFGR_PLLR */
ganlikun	0:13413ea9a877	151	#if defined(DSI)
ganlikun	0:13413ea9a877	152	uint32_t RCC_PLL_GetFreqDomain_DSI(void);
ganlikun	0:13413ea9a877	153	#endif /* DSI */
ganlikun	0:13413ea9a877	154	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	155	uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void);
ganlikun	0:13413ea9a877	156	#if defined(RCC_PLLSAICFGR_PLLSAIP)
ganlikun	0:13413ea9a877	157	uint32_t RCC_PLLSAI_GetFreqDomain_48M(void);
ganlikun	0:13413ea9a877	158	#endif /* RCC_PLLSAICFGR_PLLSAIP */
ganlikun	0:13413ea9a877	159	#if defined(LTDC)
ganlikun	0:13413ea9a877	160	uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void);
ganlikun	0:13413ea9a877	161	#endif /* LTDC */
ganlikun	0:13413ea9a877	162	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	163	#if defined(RCC_PLLI2S_SUPPORT)
ganlikun	0:13413ea9a877	164	uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
ganlikun	0:13413ea9a877	165	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
ganlikun	0:13413ea9a877	166	uint32_t RCC_PLLI2S_GetFreqDomain_48M(void);
ganlikun	0:13413ea9a877	167	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
ganlikun	0:13413ea9a877	168	#if defined(SAI1)
ganlikun	0:13413ea9a877	169	uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void);
ganlikun	0:13413ea9a877	170	#endif /* SAI1 */
ganlikun	0:13413ea9a877	171	#if defined(SPDIFRX)
ganlikun	0:13413ea9a877	172	uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void);
ganlikun	0:13413ea9a877	173	#endif /* SPDIFRX */
ganlikun	0:13413ea9a877	174	#endif /* RCC_PLLI2S_SUPPORT */
ganlikun	0:13413ea9a877	175	/**
ganlikun	0:13413ea9a877	176	* @}
ganlikun	0:13413ea9a877	177	*/
ganlikun	0:13413ea9a877	178
ganlikun	0:13413ea9a877	179
ganlikun	0:13413ea9a877	180	/* Exported functions --------------------------------------------------------*/
ganlikun	0:13413ea9a877	181	/** @addtogroup RCC_LL_Exported_Functions
ganlikun	0:13413ea9a877	182	* @{
ganlikun	0:13413ea9a877	183	*/
ganlikun	0:13413ea9a877	184
ganlikun	0:13413ea9a877	185	/** @addtogroup RCC_LL_EF_Init
ganlikun	0:13413ea9a877	186	* @{
ganlikun	0:13413ea9a877	187	*/
ganlikun	0:13413ea9a877	188
ganlikun	0:13413ea9a877	189	/**
ganlikun	0:13413ea9a877	190	* @brief Reset the RCC clock configuration to the default reset state.
ganlikun	0:13413ea9a877	191	* @note The default reset state of the clock configuration is given below:
ganlikun	0:13413ea9a877	192	* - HSI ON and used as system clock source
ganlikun	0:13413ea9a877	193	* - HSE and PLL OFF
ganlikun	0:13413ea9a877	194	* - AHB, APB1 and APB2 prescaler set to 1.
ganlikun	0:13413ea9a877	195	* - CSS, MCO OFF
ganlikun	0:13413ea9a877	196	* - All interrupts disabled
ganlikun	0:13413ea9a877	197	* @note This function doesn't modify the configuration of the
ganlikun	0:13413ea9a877	198	* - Peripheral clocks
ganlikun	0:13413ea9a877	199	* - LSI, LSE and RTC clocks
ganlikun	0:13413ea9a877	200	* @retval An ErrorStatus enumeration value:
ganlikun	0:13413ea9a877	201	* - SUCCESS: RCC registers are de-initialized
ganlikun	0:13413ea9a877	202	* - ERROR: not applicable
ganlikun	0:13413ea9a877	203	*/
ganlikun	0:13413ea9a877	204	ErrorStatus LL_RCC_DeInit(void)
ganlikun	0:13413ea9a877	205	{
ganlikun	0:13413ea9a877	206	uint32_t vl_mask = 0U;
ganlikun	0:13413ea9a877	207
ganlikun	0:13413ea9a877	208	/* Set HSION bit */
ganlikun	0:13413ea9a877	209	LL_RCC_HSI_Enable();
ganlikun	0:13413ea9a877	210
ganlikun	0:13413ea9a877	211	/* Reset CFGR register */
ganlikun	0:13413ea9a877	212	LL_RCC_WriteReg(CFGR, 0x00000000U);
ganlikun	0:13413ea9a877	213
ganlikun	0:13413ea9a877	214	vl_mask = 0xFFFFFFFFU;
ganlikun	0:13413ea9a877	215
ganlikun	0:13413ea9a877	216	/* Reset HSEON, PLLSYSON bits */
ganlikun	0:13413ea9a877	217	CLEAR_BIT(vl_mask, (RCC_CR_HSEON \| RCC_CR_HSEBYP \| RCC_CR_PLLON \| RCC_CR_CSSON));
ganlikun	0:13413ea9a877	218
ganlikun	0:13413ea9a877	219	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	220	/* Reset PLLSAION bit */
ganlikun	0:13413ea9a877	221	CLEAR_BIT(vl_mask, RCC_CR_PLLSAION);
ganlikun	0:13413ea9a877	222	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	223
ganlikun	0:13413ea9a877	224	#if defined(RCC_PLLI2S_SUPPORT)
ganlikun	0:13413ea9a877	225	/* Reset PLLI2SON bit */
ganlikun	0:13413ea9a877	226	CLEAR_BIT(vl_mask, RCC_CR_PLLI2SON);
ganlikun	0:13413ea9a877	227	#endif /* RCC_PLLI2S_SUPPORT */
ganlikun	0:13413ea9a877	228
ganlikun	0:13413ea9a877	229	/* Write new mask in CR register */
ganlikun	0:13413ea9a877	230	LL_RCC_WriteReg(CR, vl_mask);
ganlikun	0:13413ea9a877	231
ganlikun	0:13413ea9a877	232	/* Set HSITRIM bits to the reset value*/
ganlikun	0:13413ea9a877	233	LL_RCC_HSI_SetCalibTrimming(0x10U);
ganlikun	0:13413ea9a877	234
ganlikun	0:13413ea9a877	235	/* Reset PLLCFGR register */
ganlikun	0:13413ea9a877	236	LL_RCC_WriteReg(PLLCFGR, RCC_PLLCFGR_RST_VALUE);
ganlikun	0:13413ea9a877	237
ganlikun	0:13413ea9a877	238	#if defined(RCC_PLLI2S_SUPPORT)
ganlikun	0:13413ea9a877	239	/* Reset PLLI2SCFGR register */
ganlikun	0:13413ea9a877	240	LL_RCC_WriteReg(PLLI2SCFGR, RCC_PLLI2SCFGR_RST_VALUE);
ganlikun	0:13413ea9a877	241	#endif /* RCC_PLLI2S_SUPPORT */
ganlikun	0:13413ea9a877	242
ganlikun	0:13413ea9a877	243	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	244	/* Reset PLLSAICFGR register */
ganlikun	0:13413ea9a877	245	LL_RCC_WriteReg(PLLSAICFGR, RCC_PLLSAICFGR_RST_VALUE);
ganlikun	0:13413ea9a877	246	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	247
ganlikun	0:13413ea9a877	248	/* Reset HSEBYP bit */
ganlikun	0:13413ea9a877	249	LL_RCC_HSE_DisableBypass();
ganlikun	0:13413ea9a877	250
ganlikun	0:13413ea9a877	251	/* Disable all interrupts */
ganlikun	0:13413ea9a877	252	LL_RCC_WriteReg(CIR, 0x00000000U);
ganlikun	0:13413ea9a877	253
ganlikun	0:13413ea9a877	254	return SUCCESS;
ganlikun	0:13413ea9a877	255	}
ganlikun	0:13413ea9a877	256
ganlikun	0:13413ea9a877	257	/**
ganlikun	0:13413ea9a877	258	* @}
ganlikun	0:13413ea9a877	259	*/
ganlikun	0:13413ea9a877	260
ganlikun	0:13413ea9a877	261	/** @addtogroup RCC_LL_EF_Get_Freq
ganlikun	0:13413ea9a877	262	* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
ganlikun	0:13413ea9a877	263	* and different peripheral clocks available on the device.
ganlikun	0:13413ea9a877	264	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
ganlikun	0:13413ea9a877	265	* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
ganlikun	0:13413ea9a877	266	* @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
ganlikun	0:13413ea9a877	267	* or HSI_VALUE(**) multiplied/divided by the PLL factors.
ganlikun	0:13413ea9a877	268	* @note (**) HSI_VALUE is a constant defined in this file (default value
ganlikun	0:13413ea9a877	269	* 16 MHz) but the real value may vary depending on the variations
ganlikun	0:13413ea9a877	270	* in voltage and temperature.
ganlikun	0:13413ea9a877	271	* @note (***) HSE_VALUE is a constant defined in this file (default value
ganlikun	0:13413ea9a877	272	* 25 MHz), user has to ensure that HSE_VALUE is same as the real
ganlikun	0:13413ea9a877	273	* frequency of the crystal used. Otherwise, this function may
ganlikun	0:13413ea9a877	274	* have wrong result.
ganlikun	0:13413ea9a877	275	* @note The result of this function could be incorrect when using fractional
ganlikun	0:13413ea9a877	276	* value for HSE crystal.
ganlikun	0:13413ea9a877	277	* @note This function can be used by the user application to compute the
ganlikun	0:13413ea9a877	278	* baud-rate for the communication peripherals or configure other parameters.
ganlikun	0:13413ea9a877	279	* @{
ganlikun	0:13413ea9a877	280	*/
ganlikun	0:13413ea9a877	281
ganlikun	0:13413ea9a877	282	/**
ganlikun	0:13413ea9a877	283	* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
ganlikun	0:13413ea9a877	284	* @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
ganlikun	0:13413ea9a877	285	* must be called to update structure fields. Otherwise, any
ganlikun	0:13413ea9a877	286	* configuration based on this function will be incorrect.
ganlikun	0:13413ea9a877	287	* @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
ganlikun	0:13413ea9a877	288	* @retval None
ganlikun	0:13413ea9a877	289	*/
ganlikun	0:13413ea9a877	290	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
ganlikun	0:13413ea9a877	291	{
ganlikun	0:13413ea9a877	292	/* Get SYSCLK frequency */
ganlikun	0:13413ea9a877	293	RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
ganlikun	0:13413ea9a877	294
ganlikun	0:13413ea9a877	295	/* HCLK clock frequency */
ganlikun	0:13413ea9a877	296	RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
ganlikun	0:13413ea9a877	297
ganlikun	0:13413ea9a877	298	/* PCLK1 clock frequency */
ganlikun	0:13413ea9a877	299	RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
ganlikun	0:13413ea9a877	300
ganlikun	0:13413ea9a877	301	/* PCLK2 clock frequency */
ganlikun	0:13413ea9a877	302	RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
ganlikun	0:13413ea9a877	303	}
ganlikun	0:13413ea9a877	304
ganlikun	0:13413ea9a877	305	#if defined(FMPI2C1)
ganlikun	0:13413ea9a877	306	/**
ganlikun	0:13413ea9a877	307	* @brief Return FMPI2Cx clock frequency
ganlikun	0:13413ea9a877	308	* @param FMPI2CxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	309	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
ganlikun	0:13413ea9a877	310	* @retval FMPI2C clock frequency (in Hz)
ganlikun	0:13413ea9a877	311	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
ganlikun	0:13413ea9a877	312	*/
ganlikun	0:13413ea9a877	313	uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource)
ganlikun	0:13413ea9a877	314	{
ganlikun	0:13413ea9a877	315	uint32_t FMPI2C_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
ganlikun	0:13413ea9a877	316
ganlikun	0:13413ea9a877	317	/* Check parameter */
ganlikun	0:13413ea9a877	318	assert_param(IS_LL_RCC_FMPI2C_CLKSOURCE(FMPI2CxSource));
ganlikun	0:13413ea9a877	319
ganlikun	0:13413ea9a877	320	if (FMPI2CxSource == LL_RCC_FMPI2C1_CLKSOURCE)
ganlikun	0:13413ea9a877	321	{
ganlikun	0:13413ea9a877	322	/* FMPI2C1 CLK clock frequency */
ganlikun	0:13413ea9a877	323	switch (LL_RCC_GetFMPI2CClockSource(FMPI2CxSource))
ganlikun	0:13413ea9a877	324	{
ganlikun	0:13413ea9a877	325	case LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK: /* FMPI2C1 Clock is System Clock */
ganlikun	0:13413ea9a877	326	FMPI2C_frequency = RCC_GetSystemClockFreq();
ganlikun	0:13413ea9a877	327	break;
ganlikun	0:13413ea9a877	328
ganlikun	0:13413ea9a877	329	case LL_RCC_FMPI2C1_CLKSOURCE_HSI: /* FMPI2C1 Clock is HSI Osc. */
ganlikun	0:13413ea9a877	330	if (LL_RCC_HSI_IsReady())
ganlikun	0:13413ea9a877	331	{
ganlikun	0:13413ea9a877	332	FMPI2C_frequency = HSI_VALUE;
ganlikun	0:13413ea9a877	333	}
ganlikun	0:13413ea9a877	334	break;
ganlikun	0:13413ea9a877	335
ganlikun	0:13413ea9a877	336	case LL_RCC_FMPI2C1_CLKSOURCE_PCLK1: /* FMPI2C1 Clock is PCLK1 */
ganlikun	0:13413ea9a877	337	default:
ganlikun	0:13413ea9a877	338	FMPI2C_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
ganlikun	0:13413ea9a877	339	break;
ganlikun	0:13413ea9a877	340	}
ganlikun	0:13413ea9a877	341	}
ganlikun	0:13413ea9a877	342
ganlikun	0:13413ea9a877	343	return FMPI2C_frequency;
ganlikun	0:13413ea9a877	344	}
ganlikun	0:13413ea9a877	345	#endif /* FMPI2C1 */
ganlikun	0:13413ea9a877	346
ganlikun	0:13413ea9a877	347	/**
ganlikun	0:13413ea9a877	348	* @brief Return I2Sx clock frequency
ganlikun	0:13413ea9a877	349	* @param I2SxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	350	* @arg @ref LL_RCC_I2S1_CLKSOURCE
ganlikun	0:13413ea9a877	351	* @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
ganlikun	0:13413ea9a877	352	*
ganlikun	0:13413ea9a877	353	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	354	* @retval I2S clock frequency (in Hz)
ganlikun	0:13413ea9a877	355	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
ganlikun	0:13413ea9a877	356	*/
ganlikun	0:13413ea9a877	357	uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
ganlikun	0:13413ea9a877	358	{
ganlikun	0:13413ea9a877	359	uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
ganlikun	0:13413ea9a877	360
ganlikun	0:13413ea9a877	361	/* Check parameter */
ganlikun	0:13413ea9a877	362	assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
ganlikun	0:13413ea9a877	363
ganlikun	0:13413ea9a877	364	if (I2SxSource == LL_RCC_I2S1_CLKSOURCE)
ganlikun	0:13413ea9a877	365	{
ganlikun	0:13413ea9a877	366	/* I2S1 CLK clock frequency */
ganlikun	0:13413ea9a877	367	switch (LL_RCC_GetI2SClockSource(I2SxSource))
ganlikun	0:13413ea9a877	368	{
ganlikun	0:13413ea9a877	369	#if defined(RCC_PLLI2S_SUPPORT)
ganlikun	0:13413ea9a877	370	case LL_RCC_I2S1_CLKSOURCE_PLLI2S: /* I2S1 Clock is PLLI2S */
ganlikun	0:13413ea9a877	371	if (LL_RCC_PLLI2S_IsReady())
ganlikun	0:13413ea9a877	372	{
ganlikun	0:13413ea9a877	373	i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
ganlikun	0:13413ea9a877	374	}
ganlikun	0:13413ea9a877	375	break;
ganlikun	0:13413ea9a877	376	#endif /* RCC_PLLI2S_SUPPORT */
ganlikun	0:13413ea9a877	377
ganlikun	0:13413ea9a877	378	#if defined(RCC_DCKCFGR_I2SSRC) \|\| defined(RCC_DCKCFGR_I2S1SRC)
ganlikun	0:13413ea9a877	379	case LL_RCC_I2S1_CLKSOURCE_PLL: /* I2S1 Clock is PLL */
ganlikun	0:13413ea9a877	380	if (LL_RCC_PLL_IsReady())
ganlikun	0:13413ea9a877	381	{
ganlikun	0:13413ea9a877	382	i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
ganlikun	0:13413ea9a877	383	}
ganlikun	0:13413ea9a877	384	break;
ganlikun	0:13413ea9a877	385
ganlikun	0:13413ea9a877	386	case LL_RCC_I2S1_CLKSOURCE_PLLSRC: /* I2S1 Clock is PLL Main source */
ganlikun	0:13413ea9a877	387	switch (LL_RCC_PLL_GetMainSource())
ganlikun	0:13413ea9a877	388	{
ganlikun	0:13413ea9a877	389	case LL_RCC_PLLSOURCE_HSE: /* I2S1 Clock is HSE Osc. */
ganlikun	0:13413ea9a877	390	if (LL_RCC_HSE_IsReady())
ganlikun	0:13413ea9a877	391	{
ganlikun	0:13413ea9a877	392	i2s_frequency = HSE_VALUE;
ganlikun	0:13413ea9a877	393	}
ganlikun	0:13413ea9a877	394	break;
ganlikun	0:13413ea9a877	395
ganlikun	0:13413ea9a877	396	case LL_RCC_PLLSOURCE_HSI: /* I2S1 Clock is HSI Osc. */
ganlikun	0:13413ea9a877	397	default:
ganlikun	0:13413ea9a877	398	if (LL_RCC_HSI_IsReady())
ganlikun	0:13413ea9a877	399	{
ganlikun	0:13413ea9a877	400	i2s_frequency = HSI_VALUE;
ganlikun	0:13413ea9a877	401	}
ganlikun	0:13413ea9a877	402	break;
ganlikun	0:13413ea9a877	403	}
ganlikun	0:13413ea9a877	404	break;
ganlikun	0:13413ea9a877	405	#endif /* RCC_DCKCFGR_I2SSRC \|\| RCC_DCKCFGR_I2S1SRC */
ganlikun	0:13413ea9a877	406
ganlikun	0:13413ea9a877	407	case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */
ganlikun	0:13413ea9a877	408	default:
ganlikun	0:13413ea9a877	409	i2s_frequency = EXTERNAL_CLOCK_VALUE;
ganlikun	0:13413ea9a877	410	break;
ganlikun	0:13413ea9a877	411	}
ganlikun	0:13413ea9a877	412	}
ganlikun	0:13413ea9a877	413	#if defined(RCC_DCKCFGR_I2S2SRC)
ganlikun	0:13413ea9a877	414	else
ganlikun	0:13413ea9a877	415	{
ganlikun	0:13413ea9a877	416	/* I2S2 CLK clock frequency */
ganlikun	0:13413ea9a877	417	switch (LL_RCC_GetI2SClockSource(I2SxSource))
ganlikun	0:13413ea9a877	418	{
ganlikun	0:13413ea9a877	419	case LL_RCC_I2S2_CLKSOURCE_PLLI2S: /* I2S2 Clock is PLLI2S */
ganlikun	0:13413ea9a877	420	if (LL_RCC_PLLI2S_IsReady())
ganlikun	0:13413ea9a877	421	{
ganlikun	0:13413ea9a877	422	i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
ganlikun	0:13413ea9a877	423	}
ganlikun	0:13413ea9a877	424	break;
ganlikun	0:13413ea9a877	425
ganlikun	0:13413ea9a877	426	case LL_RCC_I2S2_CLKSOURCE_PLL: /* I2S2 Clock is PLL */
ganlikun	0:13413ea9a877	427	if (LL_RCC_PLL_IsReady())
ganlikun	0:13413ea9a877	428	{
ganlikun	0:13413ea9a877	429	i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
ganlikun	0:13413ea9a877	430	}
ganlikun	0:13413ea9a877	431	break;
ganlikun	0:13413ea9a877	432
ganlikun	0:13413ea9a877	433	case LL_RCC_I2S2_CLKSOURCE_PLLSRC: /* I2S2 Clock is PLL Main source */
ganlikun	0:13413ea9a877	434	switch (LL_RCC_PLL_GetMainSource())
ganlikun	0:13413ea9a877	435	{
ganlikun	0:13413ea9a877	436	case LL_RCC_PLLSOURCE_HSE: /* I2S2 Clock is HSE Osc. */
ganlikun	0:13413ea9a877	437	if (LL_RCC_HSE_IsReady())
ganlikun	0:13413ea9a877	438	{
ganlikun	0:13413ea9a877	439	i2s_frequency = HSE_VALUE;
ganlikun	0:13413ea9a877	440	}
ganlikun	0:13413ea9a877	441	break;
ganlikun	0:13413ea9a877	442
ganlikun	0:13413ea9a877	443	case LL_RCC_PLLSOURCE_HSI: /* I2S2 Clock is HSI Osc. */
ganlikun	0:13413ea9a877	444	default:
ganlikun	0:13413ea9a877	445	if (LL_RCC_HSI_IsReady())
ganlikun	0:13413ea9a877	446	{
ganlikun	0:13413ea9a877	447	i2s_frequency = HSI_VALUE;
ganlikun	0:13413ea9a877	448	}
ganlikun	0:13413ea9a877	449	break;
ganlikun	0:13413ea9a877	450	}
ganlikun	0:13413ea9a877	451	break;
ganlikun	0:13413ea9a877	452
ganlikun	0:13413ea9a877	453	case LL_RCC_I2S2_CLKSOURCE_PIN: /* I2S2 Clock is External clock */
ganlikun	0:13413ea9a877	454	default:
ganlikun	0:13413ea9a877	455	i2s_frequency = EXTERNAL_CLOCK_VALUE;
ganlikun	0:13413ea9a877	456	break;
ganlikun	0:13413ea9a877	457	}
ganlikun	0:13413ea9a877	458	}
ganlikun	0:13413ea9a877	459	#endif /* RCC_DCKCFGR_I2S2SRC */
ganlikun	0:13413ea9a877	460
ganlikun	0:13413ea9a877	461	return i2s_frequency;
ganlikun	0:13413ea9a877	462	}
ganlikun	0:13413ea9a877	463
ganlikun	0:13413ea9a877	464	#if defined(LPTIM1)
ganlikun	0:13413ea9a877	465	/**
ganlikun	0:13413ea9a877	466	* @brief Return LPTIMx clock frequency
ganlikun	0:13413ea9a877	467	* @param LPTIMxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	468	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
ganlikun	0:13413ea9a877	469	* @retval LPTIM clock frequency (in Hz)
ganlikun	0:13413ea9a877	470	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
ganlikun	0:13413ea9a877	471	*/
ganlikun	0:13413ea9a877	472	uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
ganlikun	0:13413ea9a877	473	{
ganlikun	0:13413ea9a877	474	uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
ganlikun	0:13413ea9a877	475
ganlikun	0:13413ea9a877	476	/* Check parameter */
ganlikun	0:13413ea9a877	477	assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
ganlikun	0:13413ea9a877	478
ganlikun	0:13413ea9a877	479	if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
ganlikun	0:13413ea9a877	480	{
ganlikun	0:13413ea9a877	481	/* LPTIM1CLK clock frequency */
ganlikun	0:13413ea9a877	482	switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
ganlikun	0:13413ea9a877	483	{
ganlikun	0:13413ea9a877	484	case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
ganlikun	0:13413ea9a877	485	if (LL_RCC_LSI_IsReady())
ganlikun	0:13413ea9a877	486	{
ganlikun	0:13413ea9a877	487	lptim_frequency = LSI_VALUE;
ganlikun	0:13413ea9a877	488	}
ganlikun	0:13413ea9a877	489	break;
ganlikun	0:13413ea9a877	490
ganlikun	0:13413ea9a877	491	case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
ganlikun	0:13413ea9a877	492	if (LL_RCC_HSI_IsReady())
ganlikun	0:13413ea9a877	493	{
ganlikun	0:13413ea9a877	494	lptim_frequency = HSI_VALUE;
ganlikun	0:13413ea9a877	495	}
ganlikun	0:13413ea9a877	496	break;
ganlikun	0:13413ea9a877	497
ganlikun	0:13413ea9a877	498	case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
ganlikun	0:13413ea9a877	499	if (LL_RCC_LSE_IsReady())
ganlikun	0:13413ea9a877	500	{
ganlikun	0:13413ea9a877	501	lptim_frequency = LSE_VALUE;
ganlikun	0:13413ea9a877	502	}
ganlikun	0:13413ea9a877	503	break;
ganlikun	0:13413ea9a877	504
ganlikun	0:13413ea9a877	505	case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
ganlikun	0:13413ea9a877	506	default:
ganlikun	0:13413ea9a877	507	lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
ganlikun	0:13413ea9a877	508	break;
ganlikun	0:13413ea9a877	509	}
ganlikun	0:13413ea9a877	510	}
ganlikun	0:13413ea9a877	511
ganlikun	0:13413ea9a877	512	return lptim_frequency;
ganlikun	0:13413ea9a877	513	}
ganlikun	0:13413ea9a877	514	#endif /* LPTIM1 */
ganlikun	0:13413ea9a877	515
ganlikun	0:13413ea9a877	516	#if defined(SAI1)
ganlikun	0:13413ea9a877	517	/**
ganlikun	0:13413ea9a877	518	* @brief Return SAIx clock frequency
ganlikun	0:13413ea9a877	519	* @param SAIxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	520	* @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
ganlikun	0:13413ea9a877	521	* @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
ganlikun	0:13413ea9a877	522	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
ganlikun	0:13413ea9a877	523	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
ganlikun	0:13413ea9a877	524	*
ganlikun	0:13413ea9a877	525	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	526	* @retval SAI clock frequency (in Hz)
ganlikun	0:13413ea9a877	527	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
ganlikun	0:13413ea9a877	528	*/
ganlikun	0:13413ea9a877	529	uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
ganlikun	0:13413ea9a877	530	{
ganlikun	0:13413ea9a877	531	uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
ganlikun	0:13413ea9a877	532
ganlikun	0:13413ea9a877	533	/* Check parameter */
ganlikun	0:13413ea9a877	534	assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
ganlikun	0:13413ea9a877	535
ganlikun	0:13413ea9a877	536	#if defined(RCC_DCKCFGR_SAI1SRC)
ganlikun	0:13413ea9a877	537	if ((SAIxSource == LL_RCC_SAI1_CLKSOURCE) \|\| (SAIxSource == LL_RCC_SAI2_CLKSOURCE))
ganlikun	0:13413ea9a877	538	{
ganlikun	0:13413ea9a877	539	/* SAI1CLK clock frequency */
ganlikun	0:13413ea9a877	540	switch (LL_RCC_GetSAIClockSource(SAIxSource))
ganlikun	0:13413ea9a877	541	{
ganlikun	0:13413ea9a877	542	case LL_RCC_SAI1_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 clock source */
ganlikun	0:13413ea9a877	543	case LL_RCC_SAI2_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI2 clock source */
ganlikun	0:13413ea9a877	544	if (LL_RCC_PLLSAI_IsReady())
ganlikun	0:13413ea9a877	545	{
ganlikun	0:13413ea9a877	546	sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
ganlikun	0:13413ea9a877	547	}
ganlikun	0:13413ea9a877	548	break;
ganlikun	0:13413ea9a877	549
ganlikun	0:13413ea9a877	550	case LL_RCC_SAI1_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 clock source */
ganlikun	0:13413ea9a877	551	case LL_RCC_SAI2_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI2 clock source */
ganlikun	0:13413ea9a877	552	if (LL_RCC_PLLI2S_IsReady())
ganlikun	0:13413ea9a877	553	{
ganlikun	0:13413ea9a877	554	sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
ganlikun	0:13413ea9a877	555	}
ganlikun	0:13413ea9a877	556	break;
ganlikun	0:13413ea9a877	557
ganlikun	0:13413ea9a877	558	case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
ganlikun	0:13413ea9a877	559	case LL_RCC_SAI2_CLKSOURCE_PLL: /* PLL clock used as SAI2 clock source */
ganlikun	0:13413ea9a877	560	if (LL_RCC_PLL_IsReady())
ganlikun	0:13413ea9a877	561	{
ganlikun	0:13413ea9a877	562	sai_frequency = RCC_PLL_GetFreqDomain_SAI();
ganlikun	0:13413ea9a877	563	}
ganlikun	0:13413ea9a877	564	break;
ganlikun	0:13413ea9a877	565
ganlikun	0:13413ea9a877	566	case LL_RCC_SAI2_CLKSOURCE_PLLSRC:
ganlikun	0:13413ea9a877	567	switch (LL_RCC_PLL_GetMainSource())
ganlikun	0:13413ea9a877	568	{
ganlikun	0:13413ea9a877	569	case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI2 clock source */
ganlikun	0:13413ea9a877	570	if (LL_RCC_HSE_IsReady())
ganlikun	0:13413ea9a877	571	{
ganlikun	0:13413ea9a877	572	sai_frequency = HSE_VALUE;
ganlikun	0:13413ea9a877	573	}
ganlikun	0:13413ea9a877	574	break;
ganlikun	0:13413ea9a877	575
ganlikun	0:13413ea9a877	576	case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI2 clock source */
ganlikun	0:13413ea9a877	577	default:
ganlikun	0:13413ea9a877	578	if (LL_RCC_HSI_IsReady())
ganlikun	0:13413ea9a877	579	{
ganlikun	0:13413ea9a877	580	sai_frequency = HSI_VALUE;
ganlikun	0:13413ea9a877	581	}
ganlikun	0:13413ea9a877	582	break;
ganlikun	0:13413ea9a877	583	}
ganlikun	0:13413ea9a877	584	break;
ganlikun	0:13413ea9a877	585
ganlikun	0:13413ea9a877	586	case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
ganlikun	0:13413ea9a877	587	default:
ganlikun	0:13413ea9a877	588	sai_frequency = EXTERNAL_CLOCK_VALUE;
ganlikun	0:13413ea9a877	589	break;
ganlikun	0:13413ea9a877	590	}
ganlikun	0:13413ea9a877	591	}
ganlikun	0:13413ea9a877	592	#endif /* RCC_DCKCFGR_SAI1SRC */
ganlikun	0:13413ea9a877	593	#if defined(RCC_DCKCFGR_SAI1ASRC)
ganlikun	0:13413ea9a877	594	if ((SAIxSource == LL_RCC_SAI1_A_CLKSOURCE) \|\| (SAIxSource == LL_RCC_SAI1_B_CLKSOURCE))
ganlikun	0:13413ea9a877	595	{
ganlikun	0:13413ea9a877	596	/* SAI1CLK clock frequency */
ganlikun	0:13413ea9a877	597	switch (LL_RCC_GetSAIClockSource(SAIxSource))
ganlikun	0:13413ea9a877	598	{
ganlikun	0:13413ea9a877	599	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	600	case LL_RCC_SAI1_A_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 Block A clock source */
ganlikun	0:13413ea9a877	601	case LL_RCC_SAI1_B_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 Block B clock source */
ganlikun	0:13413ea9a877	602	if (LL_RCC_PLLSAI_IsReady())
ganlikun	0:13413ea9a877	603	{
ganlikun	0:13413ea9a877	604	sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
ganlikun	0:13413ea9a877	605	}
ganlikun	0:13413ea9a877	606	break;
ganlikun	0:13413ea9a877	607	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	608
ganlikun	0:13413ea9a877	609	case LL_RCC_SAI1_A_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 Block A clock source */
ganlikun	0:13413ea9a877	610	case LL_RCC_SAI1_B_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 Block B clock source */
ganlikun	0:13413ea9a877	611	if (LL_RCC_PLLI2S_IsReady())
ganlikun	0:13413ea9a877	612	{
ganlikun	0:13413ea9a877	613	sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
ganlikun	0:13413ea9a877	614	}
ganlikun	0:13413ea9a877	615	break;
ganlikun	0:13413ea9a877	616
ganlikun	0:13413ea9a877	617	#if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
ganlikun	0:13413ea9a877	618	case LL_RCC_SAI1_A_CLKSOURCE_PLL: /* PLL clock used as SAI1 Block A clock source */
ganlikun	0:13413ea9a877	619	case LL_RCC_SAI1_B_CLKSOURCE_PLL: /* PLL clock used as SAI1 Block B clock source */
ganlikun	0:13413ea9a877	620	if (LL_RCC_PLL_IsReady())
ganlikun	0:13413ea9a877	621	{
ganlikun	0:13413ea9a877	622	sai_frequency = RCC_PLL_GetFreqDomain_SAI();
ganlikun	0:13413ea9a877	623	}
ganlikun	0:13413ea9a877	624	break;
ganlikun	0:13413ea9a877	625
ganlikun	0:13413ea9a877	626	case LL_RCC_SAI1_A_CLKSOURCE_PLLSRC:
ganlikun	0:13413ea9a877	627	case LL_RCC_SAI1_B_CLKSOURCE_PLLSRC:
ganlikun	0:13413ea9a877	628	switch (LL_RCC_PLL_GetMainSource())
ganlikun	0:13413ea9a877	629	{
ganlikun	0:13413ea9a877	630	case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI1 Block A or B clock source */
ganlikun	0:13413ea9a877	631	if (LL_RCC_HSE_IsReady())
ganlikun	0:13413ea9a877	632	{
ganlikun	0:13413ea9a877	633	sai_frequency = HSE_VALUE;
ganlikun	0:13413ea9a877	634	}
ganlikun	0:13413ea9a877	635	break;
ganlikun	0:13413ea9a877	636
ganlikun	0:13413ea9a877	637	case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI1 Block A or B clock source */
ganlikun	0:13413ea9a877	638	default:
ganlikun	0:13413ea9a877	639	if (LL_RCC_HSI_IsReady())
ganlikun	0:13413ea9a877	640	{
ganlikun	0:13413ea9a877	641	sai_frequency = HSI_VALUE;
ganlikun	0:13413ea9a877	642	}
ganlikun	0:13413ea9a877	643	break;
ganlikun	0:13413ea9a877	644	}
ganlikun	0:13413ea9a877	645	break;
ganlikun	0:13413ea9a877	646	#endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
ganlikun	0:13413ea9a877	647
ganlikun	0:13413ea9a877	648	case LL_RCC_SAI1_A_CLKSOURCE_PIN: /* External input clock used as SAI1 Block A clock source */
ganlikun	0:13413ea9a877	649	case LL_RCC_SAI1_B_CLKSOURCE_PIN: /* External input clock used as SAI1 Block B clock source */
ganlikun	0:13413ea9a877	650	default:
ganlikun	0:13413ea9a877	651	sai_frequency = EXTERNAL_CLOCK_VALUE;
ganlikun	0:13413ea9a877	652	break;
ganlikun	0:13413ea9a877	653	}
ganlikun	0:13413ea9a877	654	}
ganlikun	0:13413ea9a877	655	#endif /* RCC_DCKCFGR_SAI1ASRC */
ganlikun	0:13413ea9a877	656
ganlikun	0:13413ea9a877	657	return sai_frequency;
ganlikun	0:13413ea9a877	658	}
ganlikun	0:13413ea9a877	659	#endif /* SAI1 */
ganlikun	0:13413ea9a877	660
ganlikun	0:13413ea9a877	661	#if defined(SDIO)
ganlikun	0:13413ea9a877	662	/**
ganlikun	0:13413ea9a877	663	* @brief Return SDIOx clock frequency
ganlikun	0:13413ea9a877	664	* @param SDIOxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	665	* @arg @ref LL_RCC_SDIO_CLKSOURCE
ganlikun	0:13413ea9a877	666	* @retval SDIO clock frequency (in Hz)
ganlikun	0:13413ea9a877	667	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
ganlikun	0:13413ea9a877	668	*/
ganlikun	0:13413ea9a877	669	uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource)
ganlikun	0:13413ea9a877	670	{
ganlikun	0:13413ea9a877	671	uint32_t SDIO_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
ganlikun	0:13413ea9a877	672
ganlikun	0:13413ea9a877	673	/* Check parameter */
ganlikun	0:13413ea9a877	674	assert_param(IS_LL_RCC_SDIO_CLKSOURCE(SDIOxSource));
ganlikun	0:13413ea9a877	675
ganlikun	0:13413ea9a877	676	if (SDIOxSource == LL_RCC_SDIO_CLKSOURCE)
ganlikun	0:13413ea9a877	677	{
ganlikun	0:13413ea9a877	678	#if defined(RCC_DCKCFGR_SDIOSEL) \|\| defined(RCC_DCKCFGR2_SDIOSEL)
ganlikun	0:13413ea9a877	679	/* SDIOCLK clock frequency */
ganlikun	0:13413ea9a877	680	switch (LL_RCC_GetSDIOClockSource(SDIOxSource))
ganlikun	0:13413ea9a877	681	{
ganlikun	0:13413ea9a877	682	case LL_RCC_SDIO_CLKSOURCE_PLL48CLK: /* PLL48M clock used as SDIO clock source */
ganlikun	0:13413ea9a877	683	switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
ganlikun	0:13413ea9a877	684	{
ganlikun	0:13413ea9a877	685	case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */
ganlikun	0:13413ea9a877	686	if (LL_RCC_PLL_IsReady())
ganlikun	0:13413ea9a877	687	{
ganlikun	0:13413ea9a877	688	SDIO_frequency = RCC_PLL_GetFreqDomain_48M();
ganlikun	0:13413ea9a877	689	}
ganlikun	0:13413ea9a877	690	break;
ganlikun	0:13413ea9a877	691
ganlikun	0:13413ea9a877	692	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	693	case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */
ganlikun	0:13413ea9a877	694	default:
ganlikun	0:13413ea9a877	695	if (LL_RCC_PLLSAI_IsReady())
ganlikun	0:13413ea9a877	696	{
ganlikun	0:13413ea9a877	697	SDIO_frequency = RCC_PLLSAI_GetFreqDomain_48M();
ganlikun	0:13413ea9a877	698	}
ganlikun	0:13413ea9a877	699	break;
ganlikun	0:13413ea9a877	700	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	701
ganlikun	0:13413ea9a877	702	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
ganlikun	0:13413ea9a877	703	case LL_RCC_CK48M_CLKSOURCE_PLLI2S: /* PLLI2S clock used as 48Mhz domain clock */
ganlikun	0:13413ea9a877	704	default:
ganlikun	0:13413ea9a877	705	if (LL_RCC_PLLI2S_IsReady())
ganlikun	0:13413ea9a877	706	{
ganlikun	0:13413ea9a877	707	SDIO_frequency = RCC_PLLI2S_GetFreqDomain_48M();
ganlikun	0:13413ea9a877	708	}
ganlikun	0:13413ea9a877	709	break;
ganlikun	0:13413ea9a877	710	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
ganlikun	0:13413ea9a877	711	}
ganlikun	0:13413ea9a877	712	break;
ganlikun	0:13413ea9a877	713
ganlikun	0:13413ea9a877	714	case LL_RCC_SDIO_CLKSOURCE_SYSCLK: /* PLL clock used as SDIO clock source */
ganlikun	0:13413ea9a877	715	default:
ganlikun	0:13413ea9a877	716	SDIO_frequency = RCC_GetSystemClockFreq();
ganlikun	0:13413ea9a877	717	break;
ganlikun	0:13413ea9a877	718	}
ganlikun	0:13413ea9a877	719	#else
ganlikun	0:13413ea9a877	720	/* PLL clock used as 48Mhz domain clock */
ganlikun	0:13413ea9a877	721	if (LL_RCC_PLL_IsReady())
ganlikun	0:13413ea9a877	722	{
ganlikun	0:13413ea9a877	723	SDIO_frequency = RCC_PLL_GetFreqDomain_48M();
ganlikun	0:13413ea9a877	724	}
ganlikun	0:13413ea9a877	725	#endif /* RCC_DCKCFGR_SDIOSEL \|\| RCC_DCKCFGR2_SDIOSEL */
ganlikun	0:13413ea9a877	726	}
ganlikun	0:13413ea9a877	727
ganlikun	0:13413ea9a877	728	return SDIO_frequency;
ganlikun	0:13413ea9a877	729	}
ganlikun	0:13413ea9a877	730	#endif /* SDIO */
ganlikun	0:13413ea9a877	731
ganlikun	0:13413ea9a877	732	#if defined(RNG)
ganlikun	0:13413ea9a877	733	/**
ganlikun	0:13413ea9a877	734	* @brief Return RNGx clock frequency
ganlikun	0:13413ea9a877	735	* @param RNGxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	736	* @arg @ref LL_RCC_RNG_CLKSOURCE
ganlikun	0:13413ea9a877	737	* @retval RNG clock frequency (in Hz)
ganlikun	0:13413ea9a877	738	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
ganlikun	0:13413ea9a877	739	*/
ganlikun	0:13413ea9a877	740	uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
ganlikun	0:13413ea9a877	741	{
ganlikun	0:13413ea9a877	742	uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
ganlikun	0:13413ea9a877	743
ganlikun	0:13413ea9a877	744	/* Check parameter */
ganlikun	0:13413ea9a877	745	assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
ganlikun	0:13413ea9a877	746
ganlikun	0:13413ea9a877	747	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
ganlikun	0:13413ea9a877	748	/* RNGCLK clock frequency */
ganlikun	0:13413ea9a877	749	switch (LL_RCC_GetRNGClockSource(RNGxSource))
ganlikun	0:13413ea9a877	750	{
ganlikun	0:13413ea9a877	751	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
ganlikun	0:13413ea9a877	752	case LL_RCC_RNG_CLKSOURCE_PLLI2S: /* PLLI2S clock used as RNG clock source */
ganlikun	0:13413ea9a877	753	if (LL_RCC_PLLI2S_IsReady())
ganlikun	0:13413ea9a877	754	{
ganlikun	0:13413ea9a877	755	rng_frequency = RCC_PLLI2S_GetFreqDomain_48M();
ganlikun	0:13413ea9a877	756	}
ganlikun	0:13413ea9a877	757	break;
ganlikun	0:13413ea9a877	758	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
ganlikun	0:13413ea9a877	759
ganlikun	0:13413ea9a877	760	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	761	case LL_RCC_RNG_CLKSOURCE_PLLSAI: /* PLLSAI clock used as RNG clock source */
ganlikun	0:13413ea9a877	762	if (LL_RCC_PLLSAI_IsReady())
ganlikun	0:13413ea9a877	763	{
ganlikun	0:13413ea9a877	764	rng_frequency = RCC_PLLSAI_GetFreqDomain_48M();
ganlikun	0:13413ea9a877	765	}
ganlikun	0:13413ea9a877	766	break;
ganlikun	0:13413ea9a877	767	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	768
ganlikun	0:13413ea9a877	769	case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
ganlikun	0:13413ea9a877	770	default:
ganlikun	0:13413ea9a877	771	if (LL_RCC_PLL_IsReady())
ganlikun	0:13413ea9a877	772	{
ganlikun	0:13413ea9a877	773	rng_frequency = RCC_PLL_GetFreqDomain_48M();
ganlikun	0:13413ea9a877	774	}
ganlikun	0:13413ea9a877	775	break;
ganlikun	0:13413ea9a877	776	}
ganlikun	0:13413ea9a877	777	#else
ganlikun	0:13413ea9a877	778	/* PLL clock used as RNG clock source */
ganlikun	0:13413ea9a877	779	if (LL_RCC_PLL_IsReady())
ganlikun	0:13413ea9a877	780	{
ganlikun	0:13413ea9a877	781	rng_frequency = RCC_PLL_GetFreqDomain_48M();
ganlikun	0:13413ea9a877	782	}
ganlikun	0:13413ea9a877	783	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
ganlikun	0:13413ea9a877	784
ganlikun	0:13413ea9a877	785	return rng_frequency;
ganlikun	0:13413ea9a877	786	}
ganlikun	0:13413ea9a877	787	#endif /* RNG */
ganlikun	0:13413ea9a877	788
ganlikun	0:13413ea9a877	789	#if defined(CEC)
ganlikun	0:13413ea9a877	790	/**
ganlikun	0:13413ea9a877	791	* @brief Return CEC clock frequency
ganlikun	0:13413ea9a877	792	* @param CECxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	793	* @arg @ref LL_RCC_CEC_CLKSOURCE
ganlikun	0:13413ea9a877	794	* @retval CEC clock frequency (in Hz)
ganlikun	0:13413ea9a877	795	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
ganlikun	0:13413ea9a877	796	*/
ganlikun	0:13413ea9a877	797	uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
ganlikun	0:13413ea9a877	798	{
ganlikun	0:13413ea9a877	799	uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
ganlikun	0:13413ea9a877	800
ganlikun	0:13413ea9a877	801	/* Check parameter */
ganlikun	0:13413ea9a877	802	assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
ganlikun	0:13413ea9a877	803
ganlikun	0:13413ea9a877	804	/* CECCLK clock frequency */
ganlikun	0:13413ea9a877	805	switch (LL_RCC_GetCECClockSource(CECxSource))
ganlikun	0:13413ea9a877	806	{
ganlikun	0:13413ea9a877	807	case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE Osc. */
ganlikun	0:13413ea9a877	808	if (LL_RCC_LSE_IsReady())
ganlikun	0:13413ea9a877	809	{
ganlikun	0:13413ea9a877	810	cec_frequency = LSE_VALUE;
ganlikun	0:13413ea9a877	811	}
ganlikun	0:13413ea9a877	812	break;
ganlikun	0:13413ea9a877	813
ganlikun	0:13413ea9a877	814	case LL_RCC_CEC_CLKSOURCE_HSI_DIV488: /* CEC Clock is HSI Osc. */
ganlikun	0:13413ea9a877	815	default:
ganlikun	0:13413ea9a877	816	if (LL_RCC_HSI_IsReady())
ganlikun	0:13413ea9a877	817	{
ganlikun	0:13413ea9a877	818	cec_frequency = HSI_VALUE/488U;
ganlikun	0:13413ea9a877	819	}
ganlikun	0:13413ea9a877	820	break;
ganlikun	0:13413ea9a877	821	}
ganlikun	0:13413ea9a877	822
ganlikun	0:13413ea9a877	823	return cec_frequency;
ganlikun	0:13413ea9a877	824	}
ganlikun	0:13413ea9a877	825	#endif /* CEC */
ganlikun	0:13413ea9a877	826
ganlikun	0:13413ea9a877	827	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
ganlikun	0:13413ea9a877	828	/**
ganlikun	0:13413ea9a877	829	* @brief Return USBx clock frequency
ganlikun	0:13413ea9a877	830	* @param USBxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	831	* @arg @ref LL_RCC_USB_CLKSOURCE
ganlikun	0:13413ea9a877	832	* @retval USB clock frequency (in Hz)
ganlikun	0:13413ea9a877	833	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
ganlikun	0:13413ea9a877	834	*/
ganlikun	0:13413ea9a877	835	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
ganlikun	0:13413ea9a877	836	{
ganlikun	0:13413ea9a877	837	uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
ganlikun	0:13413ea9a877	838
ganlikun	0:13413ea9a877	839	/* Check parameter */
ganlikun	0:13413ea9a877	840	assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
ganlikun	0:13413ea9a877	841
ganlikun	0:13413ea9a877	842	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
ganlikun	0:13413ea9a877	843	/* USBCLK clock frequency */
ganlikun	0:13413ea9a877	844	switch (LL_RCC_GetUSBClockSource(USBxSource))
ganlikun	0:13413ea9a877	845	{
ganlikun	0:13413ea9a877	846	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
ganlikun	0:13413ea9a877	847	case LL_RCC_USB_CLKSOURCE_PLLI2S: /* PLLI2S clock used as USB clock source */
ganlikun	0:13413ea9a877	848	if (LL_RCC_PLLI2S_IsReady())
ganlikun	0:13413ea9a877	849	{
ganlikun	0:13413ea9a877	850	usb_frequency = RCC_PLLI2S_GetFreqDomain_48M();
ganlikun	0:13413ea9a877	851	}
ganlikun	0:13413ea9a877	852	break;
ganlikun	0:13413ea9a877	853
ganlikun	0:13413ea9a877	854	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
ganlikun	0:13413ea9a877	855
ganlikun	0:13413ea9a877	856	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	857	case LL_RCC_USB_CLKSOURCE_PLLSAI: /* PLLSAI clock used as USB clock source */
ganlikun	0:13413ea9a877	858	if (LL_RCC_PLLSAI_IsReady())
ganlikun	0:13413ea9a877	859	{
ganlikun	0:13413ea9a877	860	usb_frequency = RCC_PLLSAI_GetFreqDomain_48M();
ganlikun	0:13413ea9a877	861	}
ganlikun	0:13413ea9a877	862	break;
ganlikun	0:13413ea9a877	863	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	864
ganlikun	0:13413ea9a877	865	case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
ganlikun	0:13413ea9a877	866	default:
ganlikun	0:13413ea9a877	867	if (LL_RCC_PLL_IsReady())
ganlikun	0:13413ea9a877	868	{
ganlikun	0:13413ea9a877	869	usb_frequency = RCC_PLL_GetFreqDomain_48M();
ganlikun	0:13413ea9a877	870	}
ganlikun	0:13413ea9a877	871	break;
ganlikun	0:13413ea9a877	872	}
ganlikun	0:13413ea9a877	873	#else
ganlikun	0:13413ea9a877	874	/* PLL clock used as USB clock source */
ganlikun	0:13413ea9a877	875	if (LL_RCC_PLL_IsReady())
ganlikun	0:13413ea9a877	876	{
ganlikun	0:13413ea9a877	877	usb_frequency = RCC_PLL_GetFreqDomain_48M();
ganlikun	0:13413ea9a877	878	}
ganlikun	0:13413ea9a877	879	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
ganlikun	0:13413ea9a877	880
ganlikun	0:13413ea9a877	881	return usb_frequency;
ganlikun	0:13413ea9a877	882	}
ganlikun	0:13413ea9a877	883	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
ganlikun	0:13413ea9a877	884
ganlikun	0:13413ea9a877	885	#if defined(DFSDM1_Channel0)
ganlikun	0:13413ea9a877	886	/**
ganlikun	0:13413ea9a877	887	* @brief Return DFSDMx clock frequency
ganlikun	0:13413ea9a877	888	* @param DFSDMxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	889	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE
ganlikun	0:13413ea9a877	890	* @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
ganlikun	0:13413ea9a877	891	*
ganlikun	0:13413ea9a877	892	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	893	* @retval DFSDM clock frequency (in Hz)
ganlikun	0:13413ea9a877	894	*/
ganlikun	0:13413ea9a877	895	uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
ganlikun	0:13413ea9a877	896	{
ganlikun	0:13413ea9a877	897	uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
ganlikun	0:13413ea9a877	898
ganlikun	0:13413ea9a877	899	/* Check parameter */
ganlikun	0:13413ea9a877	900	assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
ganlikun	0:13413ea9a877	901
ganlikun	0:13413ea9a877	902	if (DFSDMxSource == LL_RCC_DFSDM1_CLKSOURCE)
ganlikun	0:13413ea9a877	903	{
ganlikun	0:13413ea9a877	904	/* DFSDM1CLK clock frequency */
ganlikun	0:13413ea9a877	905	switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
ganlikun	0:13413ea9a877	906	{
ganlikun	0:13413ea9a877	907	case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */
ganlikun	0:13413ea9a877	908	dfsdm_frequency = RCC_GetSystemClockFreq();
ganlikun	0:13413ea9a877	909	break;
ganlikun	0:13413ea9a877	910
ganlikun	0:13413ea9a877	911	case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */
ganlikun	0:13413ea9a877	912	default:
ganlikun	0:13413ea9a877	913	dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
ganlikun	0:13413ea9a877	914	break;
ganlikun	0:13413ea9a877	915	}
ganlikun	0:13413ea9a877	916	}
ganlikun	0:13413ea9a877	917	#if defined(DFSDM2_Channel0)
ganlikun	0:13413ea9a877	918	else
ganlikun	0:13413ea9a877	919	{
ganlikun	0:13413ea9a877	920	/* DFSDM2CLK clock frequency */
ganlikun	0:13413ea9a877	921	switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
ganlikun	0:13413ea9a877	922	{
ganlikun	0:13413ea9a877	923	case LL_RCC_DFSDM2_CLKSOURCE_SYSCLK: /* DFSDM2 Clock is SYSCLK */
ganlikun	0:13413ea9a877	924	dfsdm_frequency = RCC_GetSystemClockFreq();
ganlikun	0:13413ea9a877	925	break;
ganlikun	0:13413ea9a877	926
ganlikun	0:13413ea9a877	927	case LL_RCC_DFSDM2_CLKSOURCE_PCLK2: /* DFSDM2 Clock is PCLK2 */
ganlikun	0:13413ea9a877	928	default:
ganlikun	0:13413ea9a877	929	dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
ganlikun	0:13413ea9a877	930	break;
ganlikun	0:13413ea9a877	931	}
ganlikun	0:13413ea9a877	932	}
ganlikun	0:13413ea9a877	933	#endif /* DFSDM2_Channel0 */
ganlikun	0:13413ea9a877	934
ganlikun	0:13413ea9a877	935	return dfsdm_frequency;
ganlikun	0:13413ea9a877	936	}
ganlikun	0:13413ea9a877	937
ganlikun	0:13413ea9a877	938	/**
ganlikun	0:13413ea9a877	939	* @brief Return DFSDMx Audio clock frequency
ganlikun	0:13413ea9a877	940	* @param DFSDMxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	941	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
ganlikun	0:13413ea9a877	942	* @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
ganlikun	0:13413ea9a877	943	*
ganlikun	0:13413ea9a877	944	* (*) value not defined in all devices.
ganlikun	0:13413ea9a877	945	* @retval DFSDM clock frequency (in Hz)
ganlikun	0:13413ea9a877	946	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
ganlikun	0:13413ea9a877	947	*/
ganlikun	0:13413ea9a877	948	uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
ganlikun	0:13413ea9a877	949	{
ganlikun	0:13413ea9a877	950	uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
ganlikun	0:13413ea9a877	951
ganlikun	0:13413ea9a877	952	/* Check parameter */
ganlikun	0:13413ea9a877	953	assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));
ganlikun	0:13413ea9a877	954
ganlikun	0:13413ea9a877	955	if (DFSDMxSource == LL_RCC_DFSDM1_AUDIO_CLKSOURCE)
ganlikun	0:13413ea9a877	956	{
ganlikun	0:13413ea9a877	957	/* DFSDM1CLK clock frequency */
ganlikun	0:13413ea9a877	958	switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
ganlikun	0:13413ea9a877	959	{
ganlikun	0:13413ea9a877	960	case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1: /* I2S1 clock used as DFSDM1 clock */
ganlikun	0:13413ea9a877	961	dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
ganlikun	0:13413ea9a877	962	break;
ganlikun	0:13413ea9a877	963
ganlikun	0:13413ea9a877	964	case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2: /* I2S2 clock used as DFSDM1 clock */
ganlikun	0:13413ea9a877	965	default:
ganlikun	0:13413ea9a877	966	dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
ganlikun	0:13413ea9a877	967	break;
ganlikun	0:13413ea9a877	968	}
ganlikun	0:13413ea9a877	969	}
ganlikun	0:13413ea9a877	970	#if defined(DFSDM2_Channel0)
ganlikun	0:13413ea9a877	971	else
ganlikun	0:13413ea9a877	972	{
ganlikun	0:13413ea9a877	973	/* DFSDM2CLK clock frequency */
ganlikun	0:13413ea9a877	974	switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
ganlikun	0:13413ea9a877	975	{
ganlikun	0:13413ea9a877	976	case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1: /* I2S1 clock used as DFSDM2 clock */
ganlikun	0:13413ea9a877	977	dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
ganlikun	0:13413ea9a877	978	break;
ganlikun	0:13413ea9a877	979
ganlikun	0:13413ea9a877	980	case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2: /* I2S2 clock used as DFSDM2 clock */
ganlikun	0:13413ea9a877	981	default:
ganlikun	0:13413ea9a877	982	dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
ganlikun	0:13413ea9a877	983	break;
ganlikun	0:13413ea9a877	984	}
ganlikun	0:13413ea9a877	985	}
ganlikun	0:13413ea9a877	986	#endif /* DFSDM2_Channel0 */
ganlikun	0:13413ea9a877	987
ganlikun	0:13413ea9a877	988	return dfsdm_frequency;
ganlikun	0:13413ea9a877	989	}
ganlikun	0:13413ea9a877	990	#endif /* DFSDM1_Channel0 */
ganlikun	0:13413ea9a877	991
ganlikun	0:13413ea9a877	992	#if defined(DSI)
ganlikun	0:13413ea9a877	993	/**
ganlikun	0:13413ea9a877	994	* @brief Return DSI clock frequency
ganlikun	0:13413ea9a877	995	* @param DSIxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	996	* @arg @ref LL_RCC_DSI_CLKSOURCE
ganlikun	0:13413ea9a877	997	* @retval DSI clock frequency (in Hz)
ganlikun	0:13413ea9a877	998	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
ganlikun	0:13413ea9a877	999	* - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
ganlikun	0:13413ea9a877	1000	*/
ganlikun	0:13413ea9a877	1001	uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
ganlikun	0:13413ea9a877	1002	{
ganlikun	0:13413ea9a877	1003	uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
ganlikun	0:13413ea9a877	1004
ganlikun	0:13413ea9a877	1005	/* Check parameter */
ganlikun	0:13413ea9a877	1006	assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));
ganlikun	0:13413ea9a877	1007
ganlikun	0:13413ea9a877	1008	/* DSICLK clock frequency */
ganlikun	0:13413ea9a877	1009	switch (LL_RCC_GetDSIClockSource(DSIxSource))
ganlikun	0:13413ea9a877	1010	{
ganlikun	0:13413ea9a877	1011	case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLL Osc. */
ganlikun	0:13413ea9a877	1012	if (LL_RCC_PLL_IsReady())
ganlikun	0:13413ea9a877	1013	{
ganlikun	0:13413ea9a877	1014	dsi_frequency = RCC_PLL_GetFreqDomain_DSI();
ganlikun	0:13413ea9a877	1015	}
ganlikun	0:13413ea9a877	1016	break;
ganlikun	0:13413ea9a877	1017
ganlikun	0:13413ea9a877	1018	case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */
ganlikun	0:13413ea9a877	1019	default:
ganlikun	0:13413ea9a877	1020	dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
ganlikun	0:13413ea9a877	1021	break;
ganlikun	0:13413ea9a877	1022	}
ganlikun	0:13413ea9a877	1023
ganlikun	0:13413ea9a877	1024	return dsi_frequency;
ganlikun	0:13413ea9a877	1025	}
ganlikun	0:13413ea9a877	1026	#endif /* DSI */
ganlikun	0:13413ea9a877	1027
ganlikun	0:13413ea9a877	1028	#if defined(LTDC)
ganlikun	0:13413ea9a877	1029	/**
ganlikun	0:13413ea9a877	1030	* @brief Return LTDC clock frequency
ganlikun	0:13413ea9a877	1031	* @param LTDCxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1032	* @arg @ref LL_RCC_LTDC_CLKSOURCE
ganlikun	0:13413ea9a877	1033	* @retval LTDC clock frequency (in Hz)
ganlikun	0:13413ea9a877	1034	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
ganlikun	0:13413ea9a877	1035	*/
ganlikun	0:13413ea9a877	1036	uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
ganlikun	0:13413ea9a877	1037	{
ganlikun	0:13413ea9a877	1038	uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
ganlikun	0:13413ea9a877	1039
ganlikun	0:13413ea9a877	1040	/* Check parameter */
ganlikun	0:13413ea9a877	1041	assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
ganlikun	0:13413ea9a877	1042
ganlikun	0:13413ea9a877	1043	if (LL_RCC_PLLSAI_IsReady())
ganlikun	0:13413ea9a877	1044	{
ganlikun	0:13413ea9a877	1045	ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC();
ganlikun	0:13413ea9a877	1046	}
ganlikun	0:13413ea9a877	1047
ganlikun	0:13413ea9a877	1048	return ltdc_frequency;
ganlikun	0:13413ea9a877	1049	}
ganlikun	0:13413ea9a877	1050	#endif /* LTDC */
ganlikun	0:13413ea9a877	1051
ganlikun	0:13413ea9a877	1052	#if defined(SPDIFRX)
ganlikun	0:13413ea9a877	1053	/**
ganlikun	0:13413ea9a877	1054	* @brief Return SPDIFRX clock frequency
ganlikun	0:13413ea9a877	1055	* @param SPDIFRXxSource This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1056	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
ganlikun	0:13413ea9a877	1057	* @retval SPDIFRX clock frequency (in Hz)
ganlikun	0:13413ea9a877	1058	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
ganlikun	0:13413ea9a877	1059	*/
ganlikun	0:13413ea9a877	1060	uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)
ganlikun	0:13413ea9a877	1061	{
ganlikun	0:13413ea9a877	1062	uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
ganlikun	0:13413ea9a877	1063
ganlikun	0:13413ea9a877	1064	/* Check parameter */
ganlikun	0:13413ea9a877	1065	assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));
ganlikun	0:13413ea9a877	1066
ganlikun	0:13413ea9a877	1067	/* SPDIFRX1CLK clock frequency */
ganlikun	0:13413ea9a877	1068	switch (LL_RCC_GetSPDIFRXClockSource(SPDIFRXxSource))
ganlikun	0:13413ea9a877	1069	{
ganlikun	0:13413ea9a877	1070	case LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S: /* SPDIFRX Clock is PLLI2S Osc. */
ganlikun	0:13413ea9a877	1071	if (LL_RCC_PLLI2S_IsReady())
ganlikun	0:13413ea9a877	1072	{
ganlikun	0:13413ea9a877	1073	spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX();
ganlikun	0:13413ea9a877	1074	}
ganlikun	0:13413ea9a877	1075	break;
ganlikun	0:13413ea9a877	1076
ganlikun	0:13413ea9a877	1077	case LL_RCC_SPDIFRX1_CLKSOURCE_PLL: /* SPDIFRX Clock is PLL Osc. */
ganlikun	0:13413ea9a877	1078	default:
ganlikun	0:13413ea9a877	1079	if (LL_RCC_PLL_IsReady())
ganlikun	0:13413ea9a877	1080	{
ganlikun	0:13413ea9a877	1081	spdifrx_frequency = RCC_PLL_GetFreqDomain_SPDIFRX();
ganlikun	0:13413ea9a877	1082	}
ganlikun	0:13413ea9a877	1083	break;
ganlikun	0:13413ea9a877	1084	}
ganlikun	0:13413ea9a877	1085
ganlikun	0:13413ea9a877	1086	return spdifrx_frequency;
ganlikun	0:13413ea9a877	1087	}
ganlikun	0:13413ea9a877	1088	#endif /* SPDIFRX */
ganlikun	0:13413ea9a877	1089
ganlikun	0:13413ea9a877	1090	/**
ganlikun	0:13413ea9a877	1091	* @}
ganlikun	0:13413ea9a877	1092	*/
ganlikun	0:13413ea9a877	1093
ganlikun	0:13413ea9a877	1094	/**
ganlikun	0:13413ea9a877	1095	* @}
ganlikun	0:13413ea9a877	1096	*/
ganlikun	0:13413ea9a877	1097
ganlikun	0:13413ea9a877	1098	/** @addtogroup RCC_LL_Private_Functions
ganlikun	0:13413ea9a877	1099	* @{
ganlikun	0:13413ea9a877	1100	*/
ganlikun	0:13413ea9a877	1101
ganlikun	0:13413ea9a877	1102	/**
ganlikun	0:13413ea9a877	1103	* @brief Return SYSTEM clock frequency
ganlikun	0:13413ea9a877	1104	* @retval SYSTEM clock frequency (in Hz)
ganlikun	0:13413ea9a877	1105	*/
ganlikun	0:13413ea9a877	1106	uint32_t RCC_GetSystemClockFreq(void)
ganlikun	0:13413ea9a877	1107	{
ganlikun	0:13413ea9a877	1108	uint32_t frequency = 0U;
ganlikun	0:13413ea9a877	1109
ganlikun	0:13413ea9a877	1110	/* Get SYSCLK source -------------------------------------------------------*/
ganlikun	0:13413ea9a877	1111	switch (LL_RCC_GetSysClkSource())
ganlikun	0:13413ea9a877	1112	{
ganlikun	0:13413ea9a877	1113	case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
ganlikun	0:13413ea9a877	1114	frequency = HSI_VALUE;
ganlikun	0:13413ea9a877	1115	break;
ganlikun	0:13413ea9a877	1116
ganlikun	0:13413ea9a877	1117	case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
ganlikun	0:13413ea9a877	1118	frequency = HSE_VALUE;
ganlikun	0:13413ea9a877	1119	break;
ganlikun	0:13413ea9a877	1120
ganlikun	0:13413ea9a877	1121	case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
ganlikun	0:13413ea9a877	1122	frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLL);
ganlikun	0:13413ea9a877	1123	break;
ganlikun	0:13413ea9a877	1124
ganlikun	0:13413ea9a877	1125	#if defined(RCC_PLLR_SYSCLK_SUPPORT)
ganlikun	0:13413ea9a877	1126	case LL_RCC_SYS_CLKSOURCE_STATUS_PLLR: /* PLLR used as system clock source */
ganlikun	0:13413ea9a877	1127	frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLLR);
ganlikun	0:13413ea9a877	1128	break;
ganlikun	0:13413ea9a877	1129	#endif /* RCC_PLLR_SYSCLK_SUPPORT */
ganlikun	0:13413ea9a877	1130
ganlikun	0:13413ea9a877	1131	default:
ganlikun	0:13413ea9a877	1132	frequency = HSI_VALUE;
ganlikun	0:13413ea9a877	1133	break;
ganlikun	0:13413ea9a877	1134	}
ganlikun	0:13413ea9a877	1135
ganlikun	0:13413ea9a877	1136	return frequency;
ganlikun	0:13413ea9a877	1137	}
ganlikun	0:13413ea9a877	1138
ganlikun	0:13413ea9a877	1139	/**
ganlikun	0:13413ea9a877	1140	* @brief Return HCLK clock frequency
ganlikun	0:13413ea9a877	1141	* @param SYSCLK_Frequency SYSCLK clock frequency
ganlikun	0:13413ea9a877	1142	* @retval HCLK clock frequency (in Hz)
ganlikun	0:13413ea9a877	1143	*/
ganlikun	0:13413ea9a877	1144	uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
ganlikun	0:13413ea9a877	1145	{
ganlikun	0:13413ea9a877	1146	/* HCLK clock frequency */
ganlikun	0:13413ea9a877	1147	return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
ganlikun	0:13413ea9a877	1148	}
ganlikun	0:13413ea9a877	1149
ganlikun	0:13413ea9a877	1150	/**
ganlikun	0:13413ea9a877	1151	* @brief Return PCLK1 clock frequency
ganlikun	0:13413ea9a877	1152	* @param HCLK_Frequency HCLK clock frequency
ganlikun	0:13413ea9a877	1153	* @retval PCLK1 clock frequency (in Hz)
ganlikun	0:13413ea9a877	1154	*/
ganlikun	0:13413ea9a877	1155	uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
ganlikun	0:13413ea9a877	1156	{
ganlikun	0:13413ea9a877	1157	/* PCLK1 clock frequency */
ganlikun	0:13413ea9a877	1158	return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
ganlikun	0:13413ea9a877	1159	}
ganlikun	0:13413ea9a877	1160
ganlikun	0:13413ea9a877	1161	/**
ganlikun	0:13413ea9a877	1162	* @brief Return PCLK2 clock frequency
ganlikun	0:13413ea9a877	1163	* @param HCLK_Frequency HCLK clock frequency
ganlikun	0:13413ea9a877	1164	* @retval PCLK2 clock frequency (in Hz)
ganlikun	0:13413ea9a877	1165	*/
ganlikun	0:13413ea9a877	1166	uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
ganlikun	0:13413ea9a877	1167	{
ganlikun	0:13413ea9a877	1168	/* PCLK2 clock frequency */
ganlikun	0:13413ea9a877	1169	return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
ganlikun	0:13413ea9a877	1170	}
ganlikun	0:13413ea9a877	1171
ganlikun	0:13413ea9a877	1172	/**
ganlikun	0:13413ea9a877	1173	* @brief Return PLL clock frequency used for system domain
ganlikun	0:13413ea9a877	1174	* @param SYSCLK_Source System clock source
ganlikun	0:13413ea9a877	1175	* @retval PLL clock frequency (in Hz)
ganlikun	0:13413ea9a877	1176	*/
ganlikun	0:13413ea9a877	1177	uint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source)
ganlikun	0:13413ea9a877	1178	{
ganlikun	0:13413ea9a877	1179	uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U;
ganlikun	0:13413ea9a877	1180
ganlikun	0:13413ea9a877	1181	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
ganlikun	0:13413ea9a877	1182	SYSCLK = PLL_VCO / (PLLP or PLLR)
ganlikun	0:13413ea9a877	1183	*/
ganlikun	0:13413ea9a877	1184	pllsource = LL_RCC_PLL_GetMainSource();
ganlikun	0:13413ea9a877	1185
ganlikun	0:13413ea9a877	1186	switch (pllsource)
ganlikun	0:13413ea9a877	1187	{
ganlikun	0:13413ea9a877	1188	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
ganlikun	0:13413ea9a877	1189	pllinputfreq = HSI_VALUE;
ganlikun	0:13413ea9a877	1190	break;
ganlikun	0:13413ea9a877	1191
ganlikun	0:13413ea9a877	1192	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
ganlikun	0:13413ea9a877	1193	pllinputfreq = HSE_VALUE;
ganlikun	0:13413ea9a877	1194	break;
ganlikun	0:13413ea9a877	1195
ganlikun	0:13413ea9a877	1196	default:
ganlikun	0:13413ea9a877	1197	pllinputfreq = HSI_VALUE;
ganlikun	0:13413ea9a877	1198	break;
ganlikun	0:13413ea9a877	1199	}
ganlikun	0:13413ea9a877	1200
ganlikun	0:13413ea9a877	1201	if (SYSCLK_Source == LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
ganlikun	0:13413ea9a877	1202	{
ganlikun	0:13413ea9a877	1203	plloutputfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
ganlikun	0:13413ea9a877	1204	LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
ganlikun	0:13413ea9a877	1205	}
ganlikun	0:13413ea9a877	1206	#if defined(RCC_PLLR_SYSCLK_SUPPORT)
ganlikun	0:13413ea9a877	1207	else
ganlikun	0:13413ea9a877	1208	{
ganlikun	0:13413ea9a877	1209	plloutputfreq = __LL_RCC_CALC_PLLRCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
ganlikun	0:13413ea9a877	1210	LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
ganlikun	0:13413ea9a877	1211	}
ganlikun	0:13413ea9a877	1212	#endif /* RCC_PLLR_SYSCLK_SUPPORT */
ganlikun	0:13413ea9a877	1213
ganlikun	0:13413ea9a877	1214	return plloutputfreq;
ganlikun	0:13413ea9a877	1215	}
ganlikun	0:13413ea9a877	1216
ganlikun	0:13413ea9a877	1217	/**
ganlikun	0:13413ea9a877	1218	* @brief Return PLL clock frequency used for 48 MHz domain
ganlikun	0:13413ea9a877	1219	* @retval PLL clock frequency (in Hz)
ganlikun	0:13413ea9a877	1220	*/
ganlikun	0:13413ea9a877	1221	uint32_t RCC_PLL_GetFreqDomain_48M(void)
ganlikun	0:13413ea9a877	1222	{
ganlikun	0:13413ea9a877	1223	uint32_t pllinputfreq = 0U, pllsource = 0U;
ganlikun	0:13413ea9a877	1224
ganlikun	0:13413ea9a877	1225	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
ganlikun	0:13413ea9a877	1226	48M Domain clock = PLL_VCO / PLLQ
ganlikun	0:13413ea9a877	1227	*/
ganlikun	0:13413ea9a877	1228	pllsource = LL_RCC_PLL_GetMainSource();
ganlikun	0:13413ea9a877	1229
ganlikun	0:13413ea9a877	1230	switch (pllsource)
ganlikun	0:13413ea9a877	1231	{
ganlikun	0:13413ea9a877	1232	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
ganlikun	0:13413ea9a877	1233	pllinputfreq = HSI_VALUE;
ganlikun	0:13413ea9a877	1234	break;
ganlikun	0:13413ea9a877	1235
ganlikun	0:13413ea9a877	1236	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
ganlikun	0:13413ea9a877	1237	pllinputfreq = HSE_VALUE;
ganlikun	0:13413ea9a877	1238	break;
ganlikun	0:13413ea9a877	1239
ganlikun	0:13413ea9a877	1240	default:
ganlikun	0:13413ea9a877	1241	pllinputfreq = HSI_VALUE;
ganlikun	0:13413ea9a877	1242	break;
ganlikun	0:13413ea9a877	1243	}
ganlikun	0:13413ea9a877	1244	return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
ganlikun	0:13413ea9a877	1245	LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
ganlikun	0:13413ea9a877	1246	}
ganlikun	0:13413ea9a877	1247
ganlikun	0:13413ea9a877	1248	#if defined(DSI)
ganlikun	0:13413ea9a877	1249	/**
ganlikun	0:13413ea9a877	1250	* @brief Return PLL clock frequency used for DSI clock
ganlikun	0:13413ea9a877	1251	* @retval PLL clock frequency (in Hz)
ganlikun	0:13413ea9a877	1252	*/
ganlikun	0:13413ea9a877	1253	uint32_t RCC_PLL_GetFreqDomain_DSI(void)
ganlikun	0:13413ea9a877	1254	{
ganlikun	0:13413ea9a877	1255	uint32_t pllinputfreq = 0U, pllsource = 0U;
ganlikun	0:13413ea9a877	1256
ganlikun	0:13413ea9a877	1257	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
ganlikun	0:13413ea9a877	1258	DSICLK = PLL_VCO / PLLR
ganlikun	0:13413ea9a877	1259	*/
ganlikun	0:13413ea9a877	1260	pllsource = LL_RCC_PLL_GetMainSource();
ganlikun	0:13413ea9a877	1261
ganlikun	0:13413ea9a877	1262	switch (pllsource)
ganlikun	0:13413ea9a877	1263	{
ganlikun	0:13413ea9a877	1264	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
ganlikun	0:13413ea9a877	1265	pllinputfreq = HSE_VALUE;
ganlikun	0:13413ea9a877	1266	break;
ganlikun	0:13413ea9a877	1267
ganlikun	0:13413ea9a877	1268	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
ganlikun	0:13413ea9a877	1269	default:
ganlikun	0:13413ea9a877	1270	pllinputfreq = HSI_VALUE;
ganlikun	0:13413ea9a877	1271	break;
ganlikun	0:13413ea9a877	1272	}
ganlikun	0:13413ea9a877	1273	return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
ganlikun	0:13413ea9a877	1274	LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
ganlikun	0:13413ea9a877	1275	}
ganlikun	0:13413ea9a877	1276	#endif /* DSI */
ganlikun	0:13413ea9a877	1277
ganlikun	0:13413ea9a877	1278	#if defined(RCC_DCKCFGR_I2SSRC) \|\| defined(RCC_DCKCFGR_I2S1SRC)
ganlikun	0:13413ea9a877	1279	/**
ganlikun	0:13413ea9a877	1280	* @brief Return PLL clock frequency used for I2S clock
ganlikun	0:13413ea9a877	1281	* @retval PLL clock frequency (in Hz)
ganlikun	0:13413ea9a877	1282	*/
ganlikun	0:13413ea9a877	1283	uint32_t RCC_PLL_GetFreqDomain_I2S(void)
ganlikun	0:13413ea9a877	1284	{
ganlikun	0:13413ea9a877	1285	uint32_t pllinputfreq = 0U, pllsource = 0U;
ganlikun	0:13413ea9a877	1286
ganlikun	0:13413ea9a877	1287	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
ganlikun	0:13413ea9a877	1288	I2SCLK = PLL_VCO / PLLR
ganlikun	0:13413ea9a877	1289	*/
ganlikun	0:13413ea9a877	1290	pllsource = LL_RCC_PLL_GetMainSource();
ganlikun	0:13413ea9a877	1291
ganlikun	0:13413ea9a877	1292	switch (pllsource)
ganlikun	0:13413ea9a877	1293	{
ganlikun	0:13413ea9a877	1294	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
ganlikun	0:13413ea9a877	1295	pllinputfreq = HSE_VALUE;
ganlikun	0:13413ea9a877	1296	break;
ganlikun	0:13413ea9a877	1297
ganlikun	0:13413ea9a877	1298	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
ganlikun	0:13413ea9a877	1299	default:
ganlikun	0:13413ea9a877	1300	pllinputfreq = HSI_VALUE;
ganlikun	0:13413ea9a877	1301	break;
ganlikun	0:13413ea9a877	1302	}
ganlikun	0:13413ea9a877	1303	return __LL_RCC_CALC_PLLCLK_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
ganlikun	0:13413ea9a877	1304	LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
ganlikun	0:13413ea9a877	1305	}
ganlikun	0:13413ea9a877	1306	#endif /* RCC_DCKCFGR_I2SSRC \|\| RCC_DCKCFGR_I2S1SRC */
ganlikun	0:13413ea9a877	1307
ganlikun	0:13413ea9a877	1308	#if defined(SPDIFRX)
ganlikun	0:13413ea9a877	1309	/**
ganlikun	0:13413ea9a877	1310	* @brief Return PLL clock frequency used for SPDIFRX clock
ganlikun	0:13413ea9a877	1311	* @retval PLL clock frequency (in Hz)
ganlikun	0:13413ea9a877	1312	*/
ganlikun	0:13413ea9a877	1313	uint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void)
ganlikun	0:13413ea9a877	1314	{
ganlikun	0:13413ea9a877	1315	uint32_t pllinputfreq = 0U, pllsource = 0U;
ganlikun	0:13413ea9a877	1316
ganlikun	0:13413ea9a877	1317	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
ganlikun	0:13413ea9a877	1318	SPDIFRXCLK = PLL_VCO / PLLR
ganlikun	0:13413ea9a877	1319	*/
ganlikun	0:13413ea9a877	1320	pllsource = LL_RCC_PLL_GetMainSource();
ganlikun	0:13413ea9a877	1321
ganlikun	0:13413ea9a877	1322	switch (pllsource)
ganlikun	0:13413ea9a877	1323	{
ganlikun	0:13413ea9a877	1324	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
ganlikun	0:13413ea9a877	1325	pllinputfreq = HSE_VALUE;
ganlikun	0:13413ea9a877	1326	break;
ganlikun	0:13413ea9a877	1327
ganlikun	0:13413ea9a877	1328	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
ganlikun	0:13413ea9a877	1329	default:
ganlikun	0:13413ea9a877	1330	pllinputfreq = HSI_VALUE;
ganlikun	0:13413ea9a877	1331	break;
ganlikun	0:13413ea9a877	1332	}
ganlikun	0:13413ea9a877	1333	return __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
ganlikun	0:13413ea9a877	1334	LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
ganlikun	0:13413ea9a877	1335	}
ganlikun	0:13413ea9a877	1336	#endif /* SPDIFRX */
ganlikun	0:13413ea9a877	1337
ganlikun	0:13413ea9a877	1338	#if defined(RCC_PLLCFGR_PLLR)
ganlikun	0:13413ea9a877	1339	#if defined(SAI1)
ganlikun	0:13413ea9a877	1340	/**
ganlikun	0:13413ea9a877	1341	* @brief Return PLL clock frequency used for SAI clock
ganlikun	0:13413ea9a877	1342	* @retval PLL clock frequency (in Hz)
ganlikun	0:13413ea9a877	1343	*/
ganlikun	0:13413ea9a877	1344	uint32_t RCC_PLL_GetFreqDomain_SAI(void)
ganlikun	0:13413ea9a877	1345	{
ganlikun	0:13413ea9a877	1346	uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U;
ganlikun	0:13413ea9a877	1347
ganlikun	0:13413ea9a877	1348	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
ganlikun	0:13413ea9a877	1349	SAICLK = (PLL_VCO / PLLR) / PLLDIVR
ganlikun	0:13413ea9a877	1350	or
ganlikun	0:13413ea9a877	1351	SAICLK = PLL_VCO / PLLR
ganlikun	0:13413ea9a877	1352	*/
ganlikun	0:13413ea9a877	1353	pllsource = LL_RCC_PLL_GetMainSource();
ganlikun	0:13413ea9a877	1354
ganlikun	0:13413ea9a877	1355	switch (pllsource)
ganlikun	0:13413ea9a877	1356	{
ganlikun	0:13413ea9a877	1357	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
ganlikun	0:13413ea9a877	1358	pllinputfreq = HSE_VALUE;
ganlikun	0:13413ea9a877	1359	break;
ganlikun	0:13413ea9a877	1360
ganlikun	0:13413ea9a877	1361	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
ganlikun	0:13413ea9a877	1362	default:
ganlikun	0:13413ea9a877	1363	pllinputfreq = HSI_VALUE;
ganlikun	0:13413ea9a877	1364	break;
ganlikun	0:13413ea9a877	1365	}
ganlikun	0:13413ea9a877	1366
ganlikun	0:13413ea9a877	1367	#if defined(RCC_DCKCFGR_PLLDIVR)
ganlikun	0:13413ea9a877	1368	plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
ganlikun	0:13413ea9a877	1369	LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR(), LL_RCC_PLL_GetDIVR());
ganlikun	0:13413ea9a877	1370	#else
ganlikun	0:13413ea9a877	1371	plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
ganlikun	0:13413ea9a877	1372	LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
ganlikun	0:13413ea9a877	1373	#endif /* RCC_DCKCFGR_PLLDIVR */
ganlikun	0:13413ea9a877	1374
ganlikun	0:13413ea9a877	1375	return plloutputfreq;
ganlikun	0:13413ea9a877	1376	}
ganlikun	0:13413ea9a877	1377	#endif /* SAI1 */
ganlikun	0:13413ea9a877	1378	#endif /* RCC_PLLCFGR_PLLR */
ganlikun	0:13413ea9a877	1379
ganlikun	0:13413ea9a877	1380	#if defined(RCC_PLLSAI_SUPPORT)
ganlikun	0:13413ea9a877	1381	/**
ganlikun	0:13413ea9a877	1382	* @brief Return PLLSAI clock frequency used for SAI domain
ganlikun	0:13413ea9a877	1383	* @retval PLLSAI clock frequency (in Hz)
ganlikun	0:13413ea9a877	1384	*/
ganlikun	0:13413ea9a877	1385	uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void)
ganlikun	0:13413ea9a877	1386	{
ganlikun	0:13413ea9a877	1387	uint32_t pllinputfreq = 0U, pllsource = 0U;
ganlikun	0:13413ea9a877	1388
ganlikun	0:13413ea9a877	1389	/* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
ganlikun	0:13413ea9a877	1390	SAI domain clock = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ
ganlikun	0:13413ea9a877	1391	*/
ganlikun	0:13413ea9a877	1392	pllsource = LL_RCC_PLL_GetMainSource();
ganlikun	0:13413ea9a877	1393
ganlikun	0:13413ea9a877	1394	switch (pllsource)
ganlikun	0:13413ea9a877	1395	{
ganlikun	0:13413ea9a877	1396	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
ganlikun	0:13413ea9a877	1397	pllinputfreq = HSI_VALUE;
ganlikun	0:13413ea9a877	1398	break;
ganlikun	0:13413ea9a877	1399
ganlikun	0:13413ea9a877	1400	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
ganlikun	0:13413ea9a877	1401	pllinputfreq = HSE_VALUE;
ganlikun	0:13413ea9a877	1402	break;
ganlikun	0:13413ea9a877	1403
ganlikun	0:13413ea9a877	1404	default:
ganlikun	0:13413ea9a877	1405	pllinputfreq = HSI_VALUE;
ganlikun	0:13413ea9a877	1406	break;
ganlikun	0:13413ea9a877	1407	}
ganlikun	0:13413ea9a877	1408	return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
ganlikun	0:13413ea9a877	1409	LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_GetDIVQ());
ganlikun	0:13413ea9a877	1410	}
ganlikun	0:13413ea9a877	1411
ganlikun	0:13413ea9a877	1412	#if defined(RCC_PLLSAICFGR_PLLSAIP)
ganlikun	0:13413ea9a877	1413	/**
ganlikun	0:13413ea9a877	1414	* @brief Return PLLSAI clock frequency used for 48Mhz domain
ganlikun	0:13413ea9a877	1415	* @retval PLLSAI clock frequency (in Hz)
ganlikun	0:13413ea9a877	1416	*/
ganlikun	0:13413ea9a877	1417	uint32_t RCC_PLLSAI_GetFreqDomain_48M(void)
ganlikun	0:13413ea9a877	1418	{
ganlikun	0:13413ea9a877	1419	uint32_t pllinputfreq = 0U, pllsource = 0U;
ganlikun	0:13413ea9a877	1420
ganlikun	0:13413ea9a877	1421	/* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
ganlikun	0:13413ea9a877	1422	48M Domain clock = PLLSAI_VCO / PLLSAIP
ganlikun	0:13413ea9a877	1423	*/
ganlikun	0:13413ea9a877	1424	pllsource = LL_RCC_PLL_GetMainSource();
ganlikun	0:13413ea9a877	1425
ganlikun	0:13413ea9a877	1426	switch (pllsource)
ganlikun	0:13413ea9a877	1427	{
ganlikun	0:13413ea9a877	1428	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
ganlikun	0:13413ea9a877	1429	pllinputfreq = HSI_VALUE;
ganlikun	0:13413ea9a877	1430	break;
ganlikun	0:13413ea9a877	1431
ganlikun	0:13413ea9a877	1432	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
ganlikun	0:13413ea9a877	1433	pllinputfreq = HSE_VALUE;
ganlikun	0:13413ea9a877	1434	break;
ganlikun	0:13413ea9a877	1435
ganlikun	0:13413ea9a877	1436	default:
ganlikun	0:13413ea9a877	1437	pllinputfreq = HSI_VALUE;
ganlikun	0:13413ea9a877	1438	break;
ganlikun	0:13413ea9a877	1439	}
ganlikun	0:13413ea9a877	1440	return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
ganlikun	0:13413ea9a877	1441	LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP());
ganlikun	0:13413ea9a877	1442	}
ganlikun	0:13413ea9a877	1443	#endif /* RCC_PLLSAICFGR_PLLSAIP */
ganlikun	0:13413ea9a877	1444
ganlikun	0:13413ea9a877	1445	#if defined(LTDC)
ganlikun	0:13413ea9a877	1446	/**
ganlikun	0:13413ea9a877	1447	* @brief Return PLLSAI clock frequency used for LTDC domain
ganlikun	0:13413ea9a877	1448	* @retval PLLSAI clock frequency (in Hz)
ganlikun	0:13413ea9a877	1449	*/
ganlikun	0:13413ea9a877	1450	uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void)
ganlikun	0:13413ea9a877	1451	{
ganlikun	0:13413ea9a877	1452	uint32_t pllinputfreq = 0U, pllsource = 0U;
ganlikun	0:13413ea9a877	1453
ganlikun	0:13413ea9a877	1454	/* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
ganlikun	0:13413ea9a877	1455	LTDC Domain clock = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR
ganlikun	0:13413ea9a877	1456	*/
ganlikun	0:13413ea9a877	1457	pllsource = LL_RCC_PLL_GetMainSource();
ganlikun	0:13413ea9a877	1458
ganlikun	0:13413ea9a877	1459	switch (pllsource)
ganlikun	0:13413ea9a877	1460	{
ganlikun	0:13413ea9a877	1461	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
ganlikun	0:13413ea9a877	1462	pllinputfreq = HSI_VALUE;
ganlikun	0:13413ea9a877	1463	break;
ganlikun	0:13413ea9a877	1464
ganlikun	0:13413ea9a877	1465	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
ganlikun	0:13413ea9a877	1466	pllinputfreq = HSE_VALUE;
ganlikun	0:13413ea9a877	1467	break;
ganlikun	0:13413ea9a877	1468
ganlikun	0:13413ea9a877	1469	default:
ganlikun	0:13413ea9a877	1470	pllinputfreq = HSI_VALUE;
ganlikun	0:13413ea9a877	1471	break;
ganlikun	0:13413ea9a877	1472	}
ganlikun	0:13413ea9a877	1473	return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
ganlikun	0:13413ea9a877	1474	LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR());
ganlikun	0:13413ea9a877	1475	}
ganlikun	0:13413ea9a877	1476	#endif /* LTDC */
ganlikun	0:13413ea9a877	1477	#endif /* RCC_PLLSAI_SUPPORT */
ganlikun	0:13413ea9a877	1478
ganlikun	0:13413ea9a877	1479	#if defined(RCC_PLLI2S_SUPPORT)
ganlikun	0:13413ea9a877	1480	#if defined(SAI1)
ganlikun	0:13413ea9a877	1481	/**
ganlikun	0:13413ea9a877	1482	* @brief Return PLLI2S clock frequency used for SAI domains
ganlikun	0:13413ea9a877	1483	* @retval PLLI2S clock frequency (in Hz)
ganlikun	0:13413ea9a877	1484	*/
ganlikun	0:13413ea9a877	1485	uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void)
ganlikun	0:13413ea9a877	1486	{
ganlikun	0:13413ea9a877	1487	uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
ganlikun	0:13413ea9a877	1488
ganlikun	0:13413ea9a877	1489	/* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
ganlikun	0:13413ea9a877	1490	SAI domain clock = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ
ganlikun	0:13413ea9a877	1491	or
ganlikun	0:13413ea9a877	1492	SAI domain clock = (PLLI2S_VCO / PLLI2SR) / PLLI2SDIVR
ganlikun	0:13413ea9a877	1493	*/
ganlikun	0:13413ea9a877	1494	plli2ssource = LL_RCC_PLLI2S_GetMainSource();
ganlikun	0:13413ea9a877	1495
ganlikun	0:13413ea9a877	1496	switch (plli2ssource)
ganlikun	0:13413ea9a877	1497	{
ganlikun	0:13413ea9a877	1498	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
ganlikun	0:13413ea9a877	1499	plli2sinputfreq = HSE_VALUE;
ganlikun	0:13413ea9a877	1500	break;
ganlikun	0:13413ea9a877	1501
ganlikun	0:13413ea9a877	1502	#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
ganlikun	0:13413ea9a877	1503	case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
ganlikun	0:13413ea9a877	1504	plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
ganlikun	0:13413ea9a877	1505	break;
ganlikun	0:13413ea9a877	1506	#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
ganlikun	0:13413ea9a877	1507
ganlikun	0:13413ea9a877	1508	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
ganlikun	0:13413ea9a877	1509	default:
ganlikun	0:13413ea9a877	1510	plli2sinputfreq = HSI_VALUE;
ganlikun	0:13413ea9a877	1511	break;
ganlikun	0:13413ea9a877	1512	}
ganlikun	0:13413ea9a877	1513
ganlikun	0:13413ea9a877	1514	#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
ganlikun	0:13413ea9a877	1515	plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
ganlikun	0:13413ea9a877	1516	LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ());
ganlikun	0:13413ea9a877	1517	#else
ganlikun	0:13413ea9a877	1518	plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
ganlikun	0:13413ea9a877	1519	LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR(), LL_RCC_PLLI2S_GetDIVR());
ganlikun	0:13413ea9a877	1520	#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
ganlikun	0:13413ea9a877	1521
ganlikun	0:13413ea9a877	1522	return plli2soutputfreq;
ganlikun	0:13413ea9a877	1523	}
ganlikun	0:13413ea9a877	1524	#endif /* SAI1 */
ganlikun	0:13413ea9a877	1525
ganlikun	0:13413ea9a877	1526	#if defined(SPDIFRX)
ganlikun	0:13413ea9a877	1527	/**
ganlikun	0:13413ea9a877	1528	* @brief Return PLLI2S clock frequency used for SPDIFRX domain
ganlikun	0:13413ea9a877	1529	* @retval PLLI2S clock frequency (in Hz)
ganlikun	0:13413ea9a877	1530	*/
ganlikun	0:13413ea9a877	1531	uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)
ganlikun	0:13413ea9a877	1532	{
ganlikun	0:13413ea9a877	1533	uint32_t pllinputfreq = 0U, pllsource = 0U;
ganlikun	0:13413ea9a877	1534
ganlikun	0:13413ea9a877	1535	/* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
ganlikun	0:13413ea9a877	1536	SPDIFRX Domain clock = PLLI2S_VCO / PLLI2SP
ganlikun	0:13413ea9a877	1537	*/
ganlikun	0:13413ea9a877	1538	pllsource = LL_RCC_PLLI2S_GetMainSource();
ganlikun	0:13413ea9a877	1539
ganlikun	0:13413ea9a877	1540	switch (pllsource)
ganlikun	0:13413ea9a877	1541	{
ganlikun	0:13413ea9a877	1542	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
ganlikun	0:13413ea9a877	1543	pllinputfreq = HSE_VALUE;
ganlikun	0:13413ea9a877	1544	break;
ganlikun	0:13413ea9a877	1545
ganlikun	0:13413ea9a877	1546	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
ganlikun	0:13413ea9a877	1547	default:
ganlikun	0:13413ea9a877	1548	pllinputfreq = HSI_VALUE;
ganlikun	0:13413ea9a877	1549	break;
ganlikun	0:13413ea9a877	1550	}
ganlikun	0:13413ea9a877	1551
ganlikun	0:13413ea9a877	1552	return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLLI2S_GetDivider(),
ganlikun	0:13413ea9a877	1553	LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP());
ganlikun	0:13413ea9a877	1554	}
ganlikun	0:13413ea9a877	1555	#endif /* SPDIFRX */
ganlikun	0:13413ea9a877	1556
ganlikun	0:13413ea9a877	1557	/**
ganlikun	0:13413ea9a877	1558	* @brief Return PLLI2S clock frequency used for I2S domain
ganlikun	0:13413ea9a877	1559	* @retval PLLI2S clock frequency (in Hz)
ganlikun	0:13413ea9a877	1560	*/
ganlikun	0:13413ea9a877	1561	uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
ganlikun	0:13413ea9a877	1562	{
ganlikun	0:13413ea9a877	1563	uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
ganlikun	0:13413ea9a877	1564
ganlikun	0:13413ea9a877	1565	/* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
ganlikun	0:13413ea9a877	1566	I2S Domain clock = PLLI2S_VCO / PLLI2SR
ganlikun	0:13413ea9a877	1567	*/
ganlikun	0:13413ea9a877	1568	plli2ssource = LL_RCC_PLLI2S_GetMainSource();
ganlikun	0:13413ea9a877	1569
ganlikun	0:13413ea9a877	1570	switch (plli2ssource)
ganlikun	0:13413ea9a877	1571	{
ganlikun	0:13413ea9a877	1572	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
ganlikun	0:13413ea9a877	1573	plli2sinputfreq = HSE_VALUE;
ganlikun	0:13413ea9a877	1574	break;
ganlikun	0:13413ea9a877	1575
ganlikun	0:13413ea9a877	1576	#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
ganlikun	0:13413ea9a877	1577	case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
ganlikun	0:13413ea9a877	1578	plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
ganlikun	0:13413ea9a877	1579	break;
ganlikun	0:13413ea9a877	1580	#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
ganlikun	0:13413ea9a877	1581
ganlikun	0:13413ea9a877	1582	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
ganlikun	0:13413ea9a877	1583	default:
ganlikun	0:13413ea9a877	1584	plli2sinputfreq = HSI_VALUE;
ganlikun	0:13413ea9a877	1585	break;
ganlikun	0:13413ea9a877	1586	}
ganlikun	0:13413ea9a877	1587
ganlikun	0:13413ea9a877	1588	plli2soutputfreq = __LL_RCC_CALC_PLLI2S_I2S_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
ganlikun	0:13413ea9a877	1589	LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR());
ganlikun	0:13413ea9a877	1590
ganlikun	0:13413ea9a877	1591	return plli2soutputfreq;
ganlikun	0:13413ea9a877	1592	}
ganlikun	0:13413ea9a877	1593
ganlikun	0:13413ea9a877	1594	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
ganlikun	0:13413ea9a877	1595	/**
ganlikun	0:13413ea9a877	1596	* @brief Return PLLI2S clock frequency used for 48Mhz domain
ganlikun	0:13413ea9a877	1597	* @retval PLLI2S clock frequency (in Hz)
ganlikun	0:13413ea9a877	1598	*/
ganlikun	0:13413ea9a877	1599	uint32_t RCC_PLLI2S_GetFreqDomain_48M(void)
ganlikun	0:13413ea9a877	1600	{
ganlikun	0:13413ea9a877	1601	uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
ganlikun	0:13413ea9a877	1602
ganlikun	0:13413ea9a877	1603	/* PLL48M_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
ganlikun	0:13413ea9a877	1604	48M Domain clock = PLLI2S_VCO / PLLI2SQ
ganlikun	0:13413ea9a877	1605	*/
ganlikun	0:13413ea9a877	1606	plli2ssource = LL_RCC_PLLI2S_GetMainSource();
ganlikun	0:13413ea9a877	1607
ganlikun	0:13413ea9a877	1608	switch (plli2ssource)
ganlikun	0:13413ea9a877	1609	{
ganlikun	0:13413ea9a877	1610	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
ganlikun	0:13413ea9a877	1611	plli2sinputfreq = HSE_VALUE;
ganlikun	0:13413ea9a877	1612	break;
ganlikun	0:13413ea9a877	1613
ganlikun	0:13413ea9a877	1614	#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
ganlikun	0:13413ea9a877	1615	case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
ganlikun	0:13413ea9a877	1616	plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
ganlikun	0:13413ea9a877	1617	break;
ganlikun	0:13413ea9a877	1618	#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
ganlikun	0:13413ea9a877	1619
ganlikun	0:13413ea9a877	1620	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
ganlikun	0:13413ea9a877	1621	default:
ganlikun	0:13413ea9a877	1622	plli2sinputfreq = HSI_VALUE;
ganlikun	0:13413ea9a877	1623	break;
ganlikun	0:13413ea9a877	1624	}
ganlikun	0:13413ea9a877	1625
ganlikun	0:13413ea9a877	1626	plli2soutputfreq = __LL_RCC_CALC_PLLI2S_48M_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
ganlikun	0:13413ea9a877	1627	LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ());
ganlikun	0:13413ea9a877	1628
ganlikun	0:13413ea9a877	1629	return plli2soutputfreq;
ganlikun	0:13413ea9a877	1630	}
ganlikun	0:13413ea9a877	1631	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
ganlikun	0:13413ea9a877	1632	#endif /* RCC_PLLI2S_SUPPORT */
ganlikun	0:13413ea9a877	1633	/**
ganlikun	0:13413ea9a877	1634	* @}
ganlikun	0:13413ea9a877	1635	*/
ganlikun	0:13413ea9a877	1636
ganlikun	0:13413ea9a877	1637	/**
ganlikun	0:13413ea9a877	1638	* @}
ganlikun	0:13413ea9a877	1639	*/
ganlikun	0:13413ea9a877	1640
ganlikun	0:13413ea9a877	1641	#endif /* defined(RCC) */
ganlikun	0:13413ea9a877	1642
ganlikun	0:13413ea9a877	1643	/**
ganlikun	0:13413ea9a877	1644	* @}
ganlikun	0:13413ea9a877	1645	*/
ganlikun	0:13413ea9a877	1646
ganlikun	0:13413ea9a877	1647	#endif /* USE_FULL_LL_DRIVER */
ganlikun	0:13413ea9a877	1648
ganlikun	0:13413ea9a877	1649	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
ganlikun	0:13413ea9a877	1650

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Type:	Library
Created:	05 Jul 2022
Imports:	1
Forks:	0
Commits:	1
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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.c@0:13413ea9a877, 2022-06-12 (annotated)

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