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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.h@0:13413ea9a877, 2022-06-12 (annotated)

Committer:: ganlikun
Date:: Sun Jun 12 14:02:44 2022 +0000
Revision:: 0:13413ea9a877

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User	Revision	Line number	New contents of line
ganlikun	0:13413ea9a877	1	/**
ganlikun	0:13413ea9a877	2	******************************************************************************
ganlikun	0:13413ea9a877	3	* @file stm32f4xx_ll_i2c.h
ganlikun	0:13413ea9a877	4	* @author MCD Application Team
ganlikun	0:13413ea9a877	5	* @version V1.7.1
ganlikun	0:13413ea9a877	6	* @date 14-April-2017
ganlikun	0:13413ea9a877	7	* @brief Header file of I2C LL module.
ganlikun	0:13413ea9a877	8	******************************************************************************
ganlikun	0:13413ea9a877	9	* @attention
ganlikun	0:13413ea9a877	10	*
ganlikun	0:13413ea9a877	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun	0:13413ea9a877	12	*
ganlikun	0:13413ea9a877	13	* Redistribution and use in source and binary forms, with or without modification,
ganlikun	0:13413ea9a877	14	* are permitted provided that the following conditions are met:
ganlikun	0:13413ea9a877	15	* 1. Redistributions of source code must retain the above copyright notice,
ganlikun	0:13413ea9a877	16	* this list of conditions and the following disclaimer.
ganlikun	0:13413ea9a877	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun	0:13413ea9a877	18	* this list of conditions and the following disclaimer in the documentation
ganlikun	0:13413ea9a877	19	* and/or other materials provided with the distribution.
ganlikun	0:13413ea9a877	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun	0:13413ea9a877	21	* may be used to endorse or promote products derived from this software
ganlikun	0:13413ea9a877	22	* without specific prior written permission.
ganlikun	0:13413ea9a877	23	*
ganlikun	0:13413ea9a877	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun	0:13413ea9a877	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun	0:13413ea9a877	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun	0:13413ea9a877	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun	0:13413ea9a877	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun	0:13413ea9a877	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun	0:13413ea9a877	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun	0:13413ea9a877	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun	0:13413ea9a877	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun	0:13413ea9a877	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun	0:13413ea9a877	34	*
ganlikun	0:13413ea9a877	35	******************************************************************************
ganlikun	0:13413ea9a877	36	*/
ganlikun	0:13413ea9a877	37
ganlikun	0:13413ea9a877	38	/* Define to prevent recursive inclusion -------------------------------------*/
ganlikun	0:13413ea9a877	39	#ifndef __STM32F4xx_LL_I2C_H
ganlikun	0:13413ea9a877	40	#define __STM32F4xx_LL_I2C_H
ganlikun	0:13413ea9a877	41
ganlikun	0:13413ea9a877	42	#ifdef __cplusplus
ganlikun	0:13413ea9a877	43	extern "C" {
ganlikun	0:13413ea9a877	44	#endif
ganlikun	0:13413ea9a877	45
ganlikun	0:13413ea9a877	46	/* Includes ------------------------------------------------------------------*/
ganlikun	0:13413ea9a877	47	#include "stm32f4xx.h"
ganlikun	0:13413ea9a877	48
ganlikun	0:13413ea9a877	49	/** @addtogroup STM32F4xx_LL_Driver
ganlikun	0:13413ea9a877	50	* @{
ganlikun	0:13413ea9a877	51	*/
ganlikun	0:13413ea9a877	52
ganlikun	0:13413ea9a877	53	#if defined (I2C1) \|\| defined (I2C2) \|\| defined (I2C3)
ganlikun	0:13413ea9a877	54
ganlikun	0:13413ea9a877	55	/** @defgroup I2C_LL I2C
ganlikun	0:13413ea9a877	56	* @{
ganlikun	0:13413ea9a877	57	*/
ganlikun	0:13413ea9a877	58
ganlikun	0:13413ea9a877	59	/* Private types -------------------------------------------------------------*/
ganlikun	0:13413ea9a877	60	/* Private variables ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	61
ganlikun	0:13413ea9a877	62	/* Private constants ---------------------------------------------------------*/
ganlikun	0:13413ea9a877	63	/** @defgroup I2C_LL_Private_Constants I2C Private Constants
ganlikun	0:13413ea9a877	64	* @{
ganlikun	0:13413ea9a877	65	*/
ganlikun	0:13413ea9a877	66
ganlikun	0:13413ea9a877	67	/* Defines used to perform compute and check in the macros */
ganlikun	0:13413ea9a877	68	#define LL_I2C_MAX_SPEED_STANDARD 100000U
ganlikun	0:13413ea9a877	69	#define LL_I2C_MAX_SPEED_FAST 400000U
ganlikun	0:13413ea9a877	70	/**
ganlikun	0:13413ea9a877	71	* @}
ganlikun	0:13413ea9a877	72	*/
ganlikun	0:13413ea9a877	73
ganlikun	0:13413ea9a877	74	/* Private macros ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	75	#if defined(USE_FULL_LL_DRIVER)
ganlikun	0:13413ea9a877	76	/** @defgroup I2C_LL_Private_Macros I2C Private Macros
ganlikun	0:13413ea9a877	77	* @{
ganlikun	0:13413ea9a877	78	*/
ganlikun	0:13413ea9a877	79	/**
ganlikun	0:13413ea9a877	80	* @}
ganlikun	0:13413ea9a877	81	*/
ganlikun	0:13413ea9a877	82	#endif /USE_FULL_LL_DRIVER/
ganlikun	0:13413ea9a877	83
ganlikun	0:13413ea9a877	84	/* Exported types ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	85	#if defined(USE_FULL_LL_DRIVER)
ganlikun	0:13413ea9a877	86	/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
ganlikun	0:13413ea9a877	87	* @{
ganlikun	0:13413ea9a877	88	*/
ganlikun	0:13413ea9a877	89	typedef struct
ganlikun	0:13413ea9a877	90	{
ganlikun	0:13413ea9a877	91	uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
ganlikun	0:13413ea9a877	92	This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
ganlikun	0:13413ea9a877	93
ganlikun	0:13413ea9a877	94	This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
ganlikun	0:13413ea9a877	95
ganlikun	0:13413ea9a877	96	uint32_t ClockSpeed; /*!< Specifies the clock frequency.
ganlikun	0:13413ea9a877	97	This parameter must be set to a value lower than 400kHz (in Hz)
ganlikun	0:13413ea9a877	98
ganlikun	0:13413ea9a877	99	This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
ganlikun	0:13413ea9a877	100	or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
ganlikun	0:13413ea9a877	101
ganlikun	0:13413ea9a877	102	uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
ganlikun	0:13413ea9a877	103	This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
ganlikun	0:13413ea9a877	104
ganlikun	0:13413ea9a877	105	This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
ganlikun	0:13413ea9a877	106
ganlikun	0:13413ea9a877	107	#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
ganlikun	0:13413ea9a877	108	uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
ganlikun	0:13413ea9a877	109	This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
ganlikun	0:13413ea9a877	110
ganlikun	0:13413ea9a877	111	This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
ganlikun	0:13413ea9a877	112
ganlikun	0:13413ea9a877	113	uint32_t DigitalFilter; /*!< Configures the digital noise filter.
ganlikun	0:13413ea9a877	114	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
ganlikun	0:13413ea9a877	115
ganlikun	0:13413ea9a877	116	This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
ganlikun	0:13413ea9a877	117
ganlikun	0:13413ea9a877	118	#endif
ganlikun	0:13413ea9a877	119	uint32_t OwnAddress1; /*!< Specifies the device own address 1.
ganlikun	0:13413ea9a877	120	This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
ganlikun	0:13413ea9a877	121
ganlikun	0:13413ea9a877	122	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
ganlikun	0:13413ea9a877	123
ganlikun	0:13413ea9a877	124	uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
ganlikun	0:13413ea9a877	125	This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
ganlikun	0:13413ea9a877	126
ganlikun	0:13413ea9a877	127	This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
ganlikun	0:13413ea9a877	128
ganlikun	0:13413ea9a877	129	uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
ganlikun	0:13413ea9a877	130	This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
ganlikun	0:13413ea9a877	131
ganlikun	0:13413ea9a877	132	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
ganlikun	0:13413ea9a877	133	} LL_I2C_InitTypeDef;
ganlikun	0:13413ea9a877	134	/**
ganlikun	0:13413ea9a877	135	* @}
ganlikun	0:13413ea9a877	136	*/
ganlikun	0:13413ea9a877	137	#endif /USE_FULL_LL_DRIVER/
ganlikun	0:13413ea9a877	138
ganlikun	0:13413ea9a877	139	/* Exported constants --------------------------------------------------------*/
ganlikun	0:13413ea9a877	140	/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
ganlikun	0:13413ea9a877	141	* @{
ganlikun	0:13413ea9a877	142	*/
ganlikun	0:13413ea9a877	143
ganlikun	0:13413ea9a877	144	/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
ganlikun	0:13413ea9a877	145	* @brief Flags defines which can be used with LL_I2C_ReadReg function
ganlikun	0:13413ea9a877	146	* @{
ganlikun	0:13413ea9a877	147	*/
ganlikun	0:13413ea9a877	148	#define LL_I2C_SR1_SB I2C_SR1_SB /!< Start Bit (master mode) /
ganlikun	0:13413ea9a877	149	#define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or
ganlikun	0:13413ea9a877	150	Address matched flag (slave mode) */
ganlikun	0:13413ea9a877	151	#define LL_I2C_SR1_BTF I2C_SR1_BTF /!< Byte Transfer Finished flag /
ganlikun	0:13413ea9a877	152	#define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /!< 10-bit header sent (master mode) /
ganlikun	0:13413ea9a877	153	#define LL_I2C_SR1_STOPF I2C_SR1_STOPF /!< Stop detection flag (slave mode) /
ganlikun	0:13413ea9a877	154	#define LL_I2C_SR1_RXNE I2C_SR1_RXNE /!< Data register not empty (receivers) /
ganlikun	0:13413ea9a877	155	#define LL_I2C_SR1_TXE I2C_SR1_TXE /!< Data register empty (transmitters) /
ganlikun	0:13413ea9a877	156	#define LL_I2C_SR1_BERR I2C_SR1_BERR /!< Bus error /
ganlikun	0:13413ea9a877	157	#define LL_I2C_SR1_ARLO I2C_SR1_ARLO /!< Arbitration lost /
ganlikun	0:13413ea9a877	158	#define LL_I2C_SR1_AF I2C_SR1_AF /!< Acknowledge failure flag /
ganlikun	0:13413ea9a877	159	#define LL_I2C_SR1_OVR I2C_SR1_OVR /!< Overrun/Underrun /
ganlikun	0:13413ea9a877	160	#define LL_I2C_SR1_PECERR I2C_ISR_PECERR /!< PEC Error in reception (SMBus mode) /
ganlikun	0:13413ea9a877	161	#define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /!< Timeout detection flag (SMBus mode) /
ganlikun	0:13413ea9a877	162	#define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /!< SMBus alert (SMBus mode) /
ganlikun	0:13413ea9a877	163	#define LL_I2C_SR2_MSL I2C_SR2_MSL /!< Master/Slave flag /
ganlikun	0:13413ea9a877	164	#define LL_I2C_SR2_BUSY I2C_SR2_BUSY /!< Bus busy flag /
ganlikun	0:13413ea9a877	165	#define LL_I2C_SR2_TRA I2C_SR2_TRA /!< Transmitter/receiver direction /
ganlikun	0:13413ea9a877	166	#define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /!< General call address (Slave mode) /
ganlikun	0:13413ea9a877	167	#define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /!< SMBus Device default address (Slave mode) /
ganlikun	0:13413ea9a877	168	#define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /!< SMBus Host address (Slave mode) /
ganlikun	0:13413ea9a877	169	#define LL_I2C_SR2_DUALF I2C_SR2_DUALF /!< Dual flag (Slave mode) /
ganlikun	0:13413ea9a877	170	/**
ganlikun	0:13413ea9a877	171	* @}
ganlikun	0:13413ea9a877	172	*/
ganlikun	0:13413ea9a877	173
ganlikun	0:13413ea9a877	174	/** @defgroup I2C_LL_EC_IT IT Defines
ganlikun	0:13413ea9a877	175	* @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
ganlikun	0:13413ea9a877	176	* @{
ganlikun	0:13413ea9a877	177	*/
ganlikun	0:13413ea9a877	178	#define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /!< Events interrupts enable /
ganlikun	0:13413ea9a877	179	#define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /!< Buffer interrupts enable /
ganlikun	0:13413ea9a877	180	#define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /!< Error interrupts enable /
ganlikun	0:13413ea9a877	181	/**
ganlikun	0:13413ea9a877	182	* @}
ganlikun	0:13413ea9a877	183	*/
ganlikun	0:13413ea9a877	184
ganlikun	0:13413ea9a877	185	#if defined(I2C_FLTR_ANOFF)
ganlikun	0:13413ea9a877	186	/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
ganlikun	0:13413ea9a877	187	* @{
ganlikun	0:13413ea9a877	188	*/
ganlikun	0:13413ea9a877	189	#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /!< Analog filter is enabled. /
ganlikun	0:13413ea9a877	190	#define LL_I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF /!< Analog filter is disabled./
ganlikun	0:13413ea9a877	191	/**
ganlikun	0:13413ea9a877	192	* @}
ganlikun	0:13413ea9a877	193	*/
ganlikun	0:13413ea9a877	194
ganlikun	0:13413ea9a877	195	#endif
ganlikun	0:13413ea9a877	196	/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
ganlikun	0:13413ea9a877	197	* @{
ganlikun	0:13413ea9a877	198	*/
ganlikun	0:13413ea9a877	199	#define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /!< Own address 1 is a 7-bit address. /
ganlikun	0:13413ea9a877	200	#define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE \| 0x00004000U) /!< Own address 1 is a 10-bit address. /
ganlikun	0:13413ea9a877	201	/**
ganlikun	0:13413ea9a877	202	* @}
ganlikun	0:13413ea9a877	203	*/
ganlikun	0:13413ea9a877	204
ganlikun	0:13413ea9a877	205	/** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
ganlikun	0:13413ea9a877	206	* @{
ganlikun	0:13413ea9a877	207	*/
ganlikun	0:13413ea9a877	208	#define LL_I2C_DUTYCYCLE_2 0x00000000U /!< I2C fast mode Tlow/Thigh = 2 /
ganlikun	0:13413ea9a877	209	#define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /!< I2C fast mode Tlow/Thigh = 16/9 /
ganlikun	0:13413ea9a877	210	/**
ganlikun	0:13413ea9a877	211	* @}
ganlikun	0:13413ea9a877	212	*/
ganlikun	0:13413ea9a877	213
ganlikun	0:13413ea9a877	214	/** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
ganlikun	0:13413ea9a877	215	* @{
ganlikun	0:13413ea9a877	216	*/
ganlikun	0:13413ea9a877	217	#define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /!< Master clock speed range is standard mode /
ganlikun	0:13413ea9a877	218	#define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /!< Master clock speed range is fast mode /
ganlikun	0:13413ea9a877	219	/**
ganlikun	0:13413ea9a877	220	* @}
ganlikun	0:13413ea9a877	221	*/
ganlikun	0:13413ea9a877	222
ganlikun	0:13413ea9a877	223	/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
ganlikun	0:13413ea9a877	224	* @{
ganlikun	0:13413ea9a877	225	*/
ganlikun	0:13413ea9a877	226	#define LL_I2C_MODE_I2C 0x00000000U /!< I2C Master or Slave mode /
ganlikun	0:13413ea9a877	227	#define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS \| I2C_CR1_SMBTYPE \| I2C_CR1_ENARP) /!< SMBus Host address acknowledge /
ganlikun	0:13413ea9a877	228	#define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /!< SMBus Device default mode (Default address not acknowledge) /
ganlikun	0:13413ea9a877	229	#define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS \| I2C_CR1_ENARP) /!< SMBus Device Default address acknowledge /
ganlikun	0:13413ea9a877	230	/**
ganlikun	0:13413ea9a877	231	* @}
ganlikun	0:13413ea9a877	232	*/
ganlikun	0:13413ea9a877	233
ganlikun	0:13413ea9a877	234	/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
ganlikun	0:13413ea9a877	235	* @{
ganlikun	0:13413ea9a877	236	*/
ganlikun	0:13413ea9a877	237	#define LL_I2C_ACK I2C_CR1_ACK /!< ACK is sent after current received byte. /
ganlikun	0:13413ea9a877	238	#define LL_I2C_NACK 0x00000000U /!< NACK is sent after current received byte./
ganlikun	0:13413ea9a877	239	/**
ganlikun	0:13413ea9a877	240	* @}
ganlikun	0:13413ea9a877	241	*/
ganlikun	0:13413ea9a877	242
ganlikun	0:13413ea9a877	243	/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
ganlikun	0:13413ea9a877	244	* @{
ganlikun	0:13413ea9a877	245	*/
ganlikun	0:13413ea9a877	246	#define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /!< Bus is in write transfer /
ganlikun	0:13413ea9a877	247	#define LL_I2C_DIRECTION_READ 0x00000000U /!< Bus is in read transfer /
ganlikun	0:13413ea9a877	248	/**
ganlikun	0:13413ea9a877	249	* @}
ganlikun	0:13413ea9a877	250	*/
ganlikun	0:13413ea9a877	251
ganlikun	0:13413ea9a877	252	/**
ganlikun	0:13413ea9a877	253	* @}
ganlikun	0:13413ea9a877	254	*/
ganlikun	0:13413ea9a877	255
ganlikun	0:13413ea9a877	256	/* Exported macro ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	257	/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
ganlikun	0:13413ea9a877	258	* @{
ganlikun	0:13413ea9a877	259	*/
ganlikun	0:13413ea9a877	260
ganlikun	0:13413ea9a877	261	/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
ganlikun	0:13413ea9a877	262	* @{
ganlikun	0:13413ea9a877	263	*/
ganlikun	0:13413ea9a877	264
ganlikun	0:13413ea9a877	265	/**
ganlikun	0:13413ea9a877	266	* @brief Write a value in I2C register
ganlikun	0:13413ea9a877	267	* @param __INSTANCE__ I2C Instance
ganlikun	0:13413ea9a877	268	* @param __REG__ Register to be written
ganlikun	0:13413ea9a877	269	* @param __VALUE__ Value to be written in the register
ganlikun	0:13413ea9a877	270	* @retval None
ganlikun	0:13413ea9a877	271	*/
ganlikun	0:13413ea9a877	272	#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
ganlikun	0:13413ea9a877	273
ganlikun	0:13413ea9a877	274	/**
ganlikun	0:13413ea9a877	275	* @brief Read a value in I2C register
ganlikun	0:13413ea9a877	276	* @param __INSTANCE__ I2C Instance
ganlikun	0:13413ea9a877	277	* @param __REG__ Register to be read
ganlikun	0:13413ea9a877	278	* @retval Register value
ganlikun	0:13413ea9a877	279	*/
ganlikun	0:13413ea9a877	280	#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
ganlikun	0:13413ea9a877	281	/**
ganlikun	0:13413ea9a877	282	* @}
ganlikun	0:13413ea9a877	283	*/
ganlikun	0:13413ea9a877	284
ganlikun	0:13413ea9a877	285	/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
ganlikun	0:13413ea9a877	286	* @{
ganlikun	0:13413ea9a877	287	*/
ganlikun	0:13413ea9a877	288
ganlikun	0:13413ea9a877	289	/**
ganlikun	0:13413ea9a877	290	* @brief Convert Peripheral Clock Frequency in Mhz.
ganlikun	0:13413ea9a877	291	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
ganlikun	0:13413ea9a877	292	* @retval Value of peripheral clock (in Mhz)
ganlikun	0:13413ea9a877	293	*/
ganlikun	0:13413ea9a877	294	#define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
ganlikun	0:13413ea9a877	295
ganlikun	0:13413ea9a877	296	/**
ganlikun	0:13413ea9a877	297	* @brief Convert Peripheral Clock Frequency in Hz.
ganlikun	0:13413ea9a877	298	* @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
ganlikun	0:13413ea9a877	299	* @retval Value of peripheral clock (in Hz)
ganlikun	0:13413ea9a877	300	*/
ganlikun	0:13413ea9a877	301	#define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
ganlikun	0:13413ea9a877	302
ganlikun	0:13413ea9a877	303	/**
ganlikun	0:13413ea9a877	304	* @brief Compute I2C Clock rising time.
ganlikun	0:13413ea9a877	305	* @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
ganlikun	0:13413ea9a877	306	* @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
ganlikun	0:13413ea9a877	307	* @retval Value between Min_Data=0x02 and Max_Data=0x3F
ganlikun	0:13413ea9a877	308	*/
ganlikun	0:13413ea9a877	309	#define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
ganlikun	0:13413ea9a877	310
ganlikun	0:13413ea9a877	311	/**
ganlikun	0:13413ea9a877	312	* @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
ganlikun	0:13413ea9a877	313	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
ganlikun	0:13413ea9a877	314	* @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
ganlikun	0:13413ea9a877	315	* @param __DUTYCYCLE__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	316	* @arg @ref LL_I2C_DUTYCYCLE_2
ganlikun	0:13413ea9a877	317	* @arg @ref LL_I2C_DUTYCYCLE_16_9
ganlikun	0:13413ea9a877	318	* @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
ganlikun	0:13413ea9a877	319	*/
ganlikun	0:13413ea9a877	320	#define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
ganlikun	0:13413ea9a877	321	(__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
ganlikun	0:13413ea9a877	322	(__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
ganlikun	0:13413ea9a877	323
ganlikun	0:13413ea9a877	324	/**
ganlikun	0:13413ea9a877	325	* @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
ganlikun	0:13413ea9a877	326	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
ganlikun	0:13413ea9a877	327	* @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
ganlikun	0:13413ea9a877	328	* @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
ganlikun	0:13413ea9a877	329	*/
ganlikun	0:13413ea9a877	330	#define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
ganlikun	0:13413ea9a877	331
ganlikun	0:13413ea9a877	332	/**
ganlikun	0:13413ea9a877	333	* @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
ganlikun	0:13413ea9a877	334	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
ganlikun	0:13413ea9a877	335	* @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
ganlikun	0:13413ea9a877	336	* @param __DUTYCYCLE__ This parameter can be one of the following values:
ganlikun	0:13413ea9a877	337	* @arg @ref LL_I2C_DUTYCYCLE_2
ganlikun	0:13413ea9a877	338	* @arg @ref LL_I2C_DUTYCYCLE_16_9
ganlikun	0:13413ea9a877	339	* @retval Value between Min_Data=0x001 and Max_Data=0xFFF
ganlikun	0:13413ea9a877	340	*/
ganlikun	0:13413ea9a877	341	#define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
ganlikun	0:13413ea9a877	342	(((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
ganlikun	0:13413ea9a877	343	(((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
ganlikun	0:13413ea9a877	344
ganlikun	0:13413ea9a877	345	/**
ganlikun	0:13413ea9a877	346	* @brief Get the Least significant bits of a 10-Bits address.
ganlikun	0:13413ea9a877	347	* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
ganlikun	0:13413ea9a877	348	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
ganlikun	0:13413ea9a877	349	*/
ganlikun	0:13413ea9a877	350	#define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
ganlikun	0:13413ea9a877	351
ganlikun	0:13413ea9a877	352	/**
ganlikun	0:13413ea9a877	353	* @brief Convert a 10-Bits address to a 10-Bits header with Write direction.
ganlikun	0:13413ea9a877	354	* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
ganlikun	0:13413ea9a877	355	* @retval Value between Min_Data=0xF0 and Max_Data=0xF6
ganlikun	0:13413ea9a877	356	*/
ganlikun	0:13413ea9a877	357	#define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) \| (uint16_t)(0xF0))))
ganlikun	0:13413ea9a877	358
ganlikun	0:13413ea9a877	359	/**
ganlikun	0:13413ea9a877	360	* @brief Convert a 10-Bits address to a 10-Bits header with Read direction.
ganlikun	0:13413ea9a877	361	* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
ganlikun	0:13413ea9a877	362	* @retval Value between Min_Data=0xF1 and Max_Data=0xF7
ganlikun	0:13413ea9a877	363	*/
ganlikun	0:13413ea9a877	364	#define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) \| (uint16_t)(0xF1))))
ganlikun	0:13413ea9a877	365
ganlikun	0:13413ea9a877	366	/**
ganlikun	0:13413ea9a877	367	* @}
ganlikun	0:13413ea9a877	368	*/
ganlikun	0:13413ea9a877	369
ganlikun	0:13413ea9a877	370	/**
ganlikun	0:13413ea9a877	371	* @}
ganlikun	0:13413ea9a877	372	*/
ganlikun	0:13413ea9a877	373
ganlikun	0:13413ea9a877	374	/* Exported functions --------------------------------------------------------*/
ganlikun	0:13413ea9a877	375
ganlikun	0:13413ea9a877	376	/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
ganlikun	0:13413ea9a877	377	* @{
ganlikun	0:13413ea9a877	378	*/
ganlikun	0:13413ea9a877	379
ganlikun	0:13413ea9a877	380	/** @defgroup I2C_LL_EF_Configuration Configuration
ganlikun	0:13413ea9a877	381	* @{
ganlikun	0:13413ea9a877	382	*/
ganlikun	0:13413ea9a877	383
ganlikun	0:13413ea9a877	384	/**
ganlikun	0:13413ea9a877	385	* @brief Enable I2C peripheral (PE = 1).
ganlikun	0:13413ea9a877	386	* @rmtoll CR1 PE LL_I2C_Enable
ganlikun	0:13413ea9a877	387	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	388	* @retval None
ganlikun	0:13413ea9a877	389	*/
ganlikun	0:13413ea9a877	390	__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	391	{
ganlikun	0:13413ea9a877	392	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
ganlikun	0:13413ea9a877	393	}
ganlikun	0:13413ea9a877	394
ganlikun	0:13413ea9a877	395	/**
ganlikun	0:13413ea9a877	396	* @brief Disable I2C peripheral (PE = 0).
ganlikun	0:13413ea9a877	397	* @rmtoll CR1 PE LL_I2C_Disable
ganlikun	0:13413ea9a877	398	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	399	* @retval None
ganlikun	0:13413ea9a877	400	*/
ganlikun	0:13413ea9a877	401	__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	402	{
ganlikun	0:13413ea9a877	403	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
ganlikun	0:13413ea9a877	404	}
ganlikun	0:13413ea9a877	405
ganlikun	0:13413ea9a877	406	/**
ganlikun	0:13413ea9a877	407	* @brief Check if the I2C peripheral is enabled or disabled.
ganlikun	0:13413ea9a877	408	* @rmtoll CR1 PE LL_I2C_IsEnabled
ganlikun	0:13413ea9a877	409	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	410	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	411	*/
ganlikun	0:13413ea9a877	412	__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	413	{
ganlikun	0:13413ea9a877	414	return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
ganlikun	0:13413ea9a877	415	}
ganlikun	0:13413ea9a877	416
ganlikun	0:13413ea9a877	417	#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
ganlikun	0:13413ea9a877	418	/**
ganlikun	0:13413ea9a877	419	* @brief Configure Noise Filters (Analog and Digital).
ganlikun	0:13413ea9a877	420	* @note If the analog filter is also enabled, the digital filter is added to analog filter.
ganlikun	0:13413ea9a877	421	* The filters can only be programmed when the I2C is disabled (PE = 0).
ganlikun	0:13413ea9a877	422	* @rmtoll FLTR ANOFF LL_I2C_ConfigFilters\n
ganlikun	0:13413ea9a877	423	* FLTR DNF LL_I2C_ConfigFilters
ganlikun	0:13413ea9a877	424	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	425	* @param AnalogFilter This parameter can be one of the following values:
ganlikun	0:13413ea9a877	426	* @arg @ref LL_I2C_ANALOGFILTER_ENABLE
ganlikun	0:13413ea9a877	427	* @arg @ref LL_I2C_ANALOGFILTER_DISABLE
ganlikun	0:13413ea9a877	428	* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1)
ganlikun	0:13413ea9a877	429	* This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1.
ganlikun	0:13413ea9a877	430	* @retval None
ganlikun	0:13413ea9a877	431	*/
ganlikun	0:13413ea9a877	432	__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
ganlikun	0:13413ea9a877	433	{
ganlikun	0:13413ea9a877	434	MODIFY_REG(I2Cx->FLTR, I2C_FLTR_ANOFF \| I2C_FLTR_DNF, AnalogFilter \| DigitalFilter);
ganlikun	0:13413ea9a877	435	}
ganlikun	0:13413ea9a877	436	#endif
ganlikun	0:13413ea9a877	437	#if defined(I2C_FLTR_DNF)
ganlikun	0:13413ea9a877	438
ganlikun	0:13413ea9a877	439	/**
ganlikun	0:13413ea9a877	440	* @brief Configure Digital Noise Filter.
ganlikun	0:13413ea9a877	441	* @note If the analog filter is also enabled, the digital filter is added to analog filter.
ganlikun	0:13413ea9a877	442	* This filter can only be programmed when the I2C is disabled (PE = 0).
ganlikun	0:13413ea9a877	443	* @rmtoll FLTR DNF LL_I2C_SetDigitalFilter
ganlikun	0:13413ea9a877	444	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	445	* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1)
ganlikun	0:13413ea9a877	446	* This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1.
ganlikun	0:13413ea9a877	447	* @retval None
ganlikun	0:13413ea9a877	448	*/
ganlikun	0:13413ea9a877	449	__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
ganlikun	0:13413ea9a877	450	{
ganlikun	0:13413ea9a877	451	MODIFY_REG(I2Cx->FLTR, I2C_FLTR_DNF, DigitalFilter);
ganlikun	0:13413ea9a877	452	}
ganlikun	0:13413ea9a877	453
ganlikun	0:13413ea9a877	454	/**
ganlikun	0:13413ea9a877	455	* @brief Get the current Digital Noise Filter configuration.
ganlikun	0:13413ea9a877	456	* @rmtoll FLTR DNF LL_I2C_GetDigitalFilter
ganlikun	0:13413ea9a877	457	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	458	* @retval Value between Min_Data=0x0 and Max_Data=0xF
ganlikun	0:13413ea9a877	459	*/
ganlikun	0:13413ea9a877	460	__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	461	{
ganlikun	0:13413ea9a877	462	return (uint32_t)(READ_BIT(I2Cx->FLTR, I2C_FLTR_DNF));
ganlikun	0:13413ea9a877	463	}
ganlikun	0:13413ea9a877	464	#endif
ganlikun	0:13413ea9a877	465	#if defined(I2C_FLTR_ANOFF)
ganlikun	0:13413ea9a877	466
ganlikun	0:13413ea9a877	467	/**
ganlikun	0:13413ea9a877	468	* @brief Enable Analog Noise Filter.
ganlikun	0:13413ea9a877	469	* @note This filter can only be programmed when the I2C is disabled (PE = 0).
ganlikun	0:13413ea9a877	470	* @rmtoll FLTR ANOFF LL_I2C_EnableAnalogFilter
ganlikun	0:13413ea9a877	471	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	472	* @retval None
ganlikun	0:13413ea9a877	473	*/
ganlikun	0:13413ea9a877	474	__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	475	{
ganlikun	0:13413ea9a877	476	CLEAR_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF);
ganlikun	0:13413ea9a877	477	}
ganlikun	0:13413ea9a877	478
ganlikun	0:13413ea9a877	479	/**
ganlikun	0:13413ea9a877	480	* @brief Disable Analog Noise Filter.
ganlikun	0:13413ea9a877	481	* @note This filter can only be programmed when the I2C is disabled (PE = 0).
ganlikun	0:13413ea9a877	482	* @rmtoll FLTR ANOFF LL_I2C_DisableAnalogFilter
ganlikun	0:13413ea9a877	483	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	484	* @retval None
ganlikun	0:13413ea9a877	485	*/
ganlikun	0:13413ea9a877	486	__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	487	{
ganlikun	0:13413ea9a877	488	SET_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF);
ganlikun	0:13413ea9a877	489	}
ganlikun	0:13413ea9a877	490
ganlikun	0:13413ea9a877	491	/**
ganlikun	0:13413ea9a877	492	* @brief Check if Analog Noise Filter is enabled or disabled.
ganlikun	0:13413ea9a877	493	* @rmtoll FLTR ANOFF LL_I2C_IsEnabledAnalogFilter
ganlikun	0:13413ea9a877	494	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	495	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	496	*/
ganlikun	0:13413ea9a877	497	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	498	{
ganlikun	0:13413ea9a877	499	return (READ_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF) == (I2C_FLTR_ANOFF));
ganlikun	0:13413ea9a877	500	}
ganlikun	0:13413ea9a877	501	#endif
ganlikun	0:13413ea9a877	502
ganlikun	0:13413ea9a877	503	/**
ganlikun	0:13413ea9a877	504	* @brief Enable DMA transmission requests.
ganlikun	0:13413ea9a877	505	* @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX
ganlikun	0:13413ea9a877	506	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	507	* @retval None
ganlikun	0:13413ea9a877	508	*/
ganlikun	0:13413ea9a877	509	__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	510	{
ganlikun	0:13413ea9a877	511	SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
ganlikun	0:13413ea9a877	512	}
ganlikun	0:13413ea9a877	513
ganlikun	0:13413ea9a877	514	/**
ganlikun	0:13413ea9a877	515	* @brief Disable DMA transmission requests.
ganlikun	0:13413ea9a877	516	* @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX
ganlikun	0:13413ea9a877	517	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	518	* @retval None
ganlikun	0:13413ea9a877	519	*/
ganlikun	0:13413ea9a877	520	__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	521	{
ganlikun	0:13413ea9a877	522	CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
ganlikun	0:13413ea9a877	523	}
ganlikun	0:13413ea9a877	524
ganlikun	0:13413ea9a877	525	/**
ganlikun	0:13413ea9a877	526	* @brief Check if DMA transmission requests are enabled or disabled.
ganlikun	0:13413ea9a877	527	* @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
ganlikun	0:13413ea9a877	528	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	529	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	530	*/
ganlikun	0:13413ea9a877	531	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	532	{
ganlikun	0:13413ea9a877	533	return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
ganlikun	0:13413ea9a877	534	}
ganlikun	0:13413ea9a877	535
ganlikun	0:13413ea9a877	536	/**
ganlikun	0:13413ea9a877	537	* @brief Enable DMA reception requests.
ganlikun	0:13413ea9a877	538	* @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX
ganlikun	0:13413ea9a877	539	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	540	* @retval None
ganlikun	0:13413ea9a877	541	*/
ganlikun	0:13413ea9a877	542	__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	543	{
ganlikun	0:13413ea9a877	544	SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
ganlikun	0:13413ea9a877	545	}
ganlikun	0:13413ea9a877	546
ganlikun	0:13413ea9a877	547	/**
ganlikun	0:13413ea9a877	548	* @brief Disable DMA reception requests.
ganlikun	0:13413ea9a877	549	* @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX
ganlikun	0:13413ea9a877	550	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	551	* @retval None
ganlikun	0:13413ea9a877	552	*/
ganlikun	0:13413ea9a877	553	__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	554	{
ganlikun	0:13413ea9a877	555	CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
ganlikun	0:13413ea9a877	556	}
ganlikun	0:13413ea9a877	557
ganlikun	0:13413ea9a877	558	/**
ganlikun	0:13413ea9a877	559	* @brief Check if DMA reception requests are enabled or disabled.
ganlikun	0:13413ea9a877	560	* @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
ganlikun	0:13413ea9a877	561	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	562	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	563	*/
ganlikun	0:13413ea9a877	564	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	565	{
ganlikun	0:13413ea9a877	566	return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
ganlikun	0:13413ea9a877	567	}
ganlikun	0:13413ea9a877	568
ganlikun	0:13413ea9a877	569	/**
ganlikun	0:13413ea9a877	570	* @brief Get the data register address used for DMA transfer.
ganlikun	0:13413ea9a877	571	* @rmtoll DR DR LL_I2C_DMA_GetRegAddr
ganlikun	0:13413ea9a877	572	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	573	* @retval Address of data register
ganlikun	0:13413ea9a877	574	*/
ganlikun	0:13413ea9a877	575	__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	576	{
ganlikun	0:13413ea9a877	577	return (uint32_t) & (I2Cx->DR);
ganlikun	0:13413ea9a877	578	}
ganlikun	0:13413ea9a877	579
ganlikun	0:13413ea9a877	580	/**
ganlikun	0:13413ea9a877	581	* @brief Enable Clock stretching.
ganlikun	0:13413ea9a877	582	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
ganlikun	0:13413ea9a877	583	* @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
ganlikun	0:13413ea9a877	584	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	585	* @retval None
ganlikun	0:13413ea9a877	586	*/
ganlikun	0:13413ea9a877	587	__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	588	{
ganlikun	0:13413ea9a877	589	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
ganlikun	0:13413ea9a877	590	}
ganlikun	0:13413ea9a877	591
ganlikun	0:13413ea9a877	592	/**
ganlikun	0:13413ea9a877	593	* @brief Disable Clock stretching.
ganlikun	0:13413ea9a877	594	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
ganlikun	0:13413ea9a877	595	* @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
ganlikun	0:13413ea9a877	596	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	597	* @retval None
ganlikun	0:13413ea9a877	598	*/
ganlikun	0:13413ea9a877	599	__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	600	{
ganlikun	0:13413ea9a877	601	SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
ganlikun	0:13413ea9a877	602	}
ganlikun	0:13413ea9a877	603
ganlikun	0:13413ea9a877	604	/**
ganlikun	0:13413ea9a877	605	* @brief Check if Clock stretching is enabled or disabled.
ganlikun	0:13413ea9a877	606	* @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
ganlikun	0:13413ea9a877	607	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	608	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	609	*/
ganlikun	0:13413ea9a877	610	__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	611	{
ganlikun	0:13413ea9a877	612	return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
ganlikun	0:13413ea9a877	613	}
ganlikun	0:13413ea9a877	614
ganlikun	0:13413ea9a877	615	/**
ganlikun	0:13413ea9a877	616	* @brief Enable General Call.
ganlikun	0:13413ea9a877	617	* @note When enabled the Address 0x00 is ACKed.
ganlikun	0:13413ea9a877	618	* @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall
ganlikun	0:13413ea9a877	619	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	620	* @retval None
ganlikun	0:13413ea9a877	621	*/
ganlikun	0:13413ea9a877	622	__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	623	{
ganlikun	0:13413ea9a877	624	SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
ganlikun	0:13413ea9a877	625	}
ganlikun	0:13413ea9a877	626
ganlikun	0:13413ea9a877	627	/**
ganlikun	0:13413ea9a877	628	* @brief Disable General Call.
ganlikun	0:13413ea9a877	629	* @note When disabled the Address 0x00 is NACKed.
ganlikun	0:13413ea9a877	630	* @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall
ganlikun	0:13413ea9a877	631	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	632	* @retval None
ganlikun	0:13413ea9a877	633	*/
ganlikun	0:13413ea9a877	634	__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	635	{
ganlikun	0:13413ea9a877	636	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
ganlikun	0:13413ea9a877	637	}
ganlikun	0:13413ea9a877	638
ganlikun	0:13413ea9a877	639	/**
ganlikun	0:13413ea9a877	640	* @brief Check if General Call is enabled or disabled.
ganlikun	0:13413ea9a877	641	* @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall
ganlikun	0:13413ea9a877	642	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	643	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	644	*/
ganlikun	0:13413ea9a877	645	__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	646	{
ganlikun	0:13413ea9a877	647	return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
ganlikun	0:13413ea9a877	648	}
ganlikun	0:13413ea9a877	649
ganlikun	0:13413ea9a877	650	/**
ganlikun	0:13413ea9a877	651	* @brief Set the Own Address1.
ganlikun	0:13413ea9a877	652	* @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n
ganlikun	0:13413ea9a877	653	* OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n
ganlikun	0:13413ea9a877	654	* OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n
ganlikun	0:13413ea9a877	655	* OAR1 ADDMODE LL_I2C_SetOwnAddress1
ganlikun	0:13413ea9a877	656	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	657	* @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
ganlikun	0:13413ea9a877	658	* @param OwnAddrSize This parameter can be one of the following values:
ganlikun	0:13413ea9a877	659	* @arg @ref LL_I2C_OWNADDRESS1_7BIT
ganlikun	0:13413ea9a877	660	* @arg @ref LL_I2C_OWNADDRESS1_10BIT
ganlikun	0:13413ea9a877	661	* @retval None
ganlikun	0:13413ea9a877	662	*/
ganlikun	0:13413ea9a877	663	__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
ganlikun	0:13413ea9a877	664	{
ganlikun	0:13413ea9a877	665	MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 \| I2C_OAR1_ADD1_7 \| I2C_OAR1_ADD8_9 \| I2C_OAR1_ADDMODE, OwnAddress1 \| OwnAddrSize);
ganlikun	0:13413ea9a877	666	}
ganlikun	0:13413ea9a877	667
ganlikun	0:13413ea9a877	668	/**
ganlikun	0:13413ea9a877	669	* @brief Set the 7bits Own Address2.
ganlikun	0:13413ea9a877	670	* @note This action has no effect if own address2 is enabled.
ganlikun	0:13413ea9a877	671	* @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2
ganlikun	0:13413ea9a877	672	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	673	* @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
ganlikun	0:13413ea9a877	674	* @retval None
ganlikun	0:13413ea9a877	675	*/
ganlikun	0:13413ea9a877	676	__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
ganlikun	0:13413ea9a877	677	{
ganlikun	0:13413ea9a877	678	MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
ganlikun	0:13413ea9a877	679	}
ganlikun	0:13413ea9a877	680
ganlikun	0:13413ea9a877	681	/**
ganlikun	0:13413ea9a877	682	* @brief Enable acknowledge on Own Address2 match address.
ganlikun	0:13413ea9a877	683	* @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2
ganlikun	0:13413ea9a877	684	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	685	* @retval None
ganlikun	0:13413ea9a877	686	*/
ganlikun	0:13413ea9a877	687	__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	688	{
ganlikun	0:13413ea9a877	689	SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
ganlikun	0:13413ea9a877	690	}
ganlikun	0:13413ea9a877	691
ganlikun	0:13413ea9a877	692	/**
ganlikun	0:13413ea9a877	693	* @brief Disable acknowledge on Own Address2 match address.
ganlikun	0:13413ea9a877	694	* @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2
ganlikun	0:13413ea9a877	695	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	696	* @retval None
ganlikun	0:13413ea9a877	697	*/
ganlikun	0:13413ea9a877	698	__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	699	{
ganlikun	0:13413ea9a877	700	CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
ganlikun	0:13413ea9a877	701	}
ganlikun	0:13413ea9a877	702
ganlikun	0:13413ea9a877	703	/**
ganlikun	0:13413ea9a877	704	* @brief Check if Own Address1 acknowledge is enabled or disabled.
ganlikun	0:13413ea9a877	705	* @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
ganlikun	0:13413ea9a877	706	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	707	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	708	*/
ganlikun	0:13413ea9a877	709	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	710	{
ganlikun	0:13413ea9a877	711	return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
ganlikun	0:13413ea9a877	712	}
ganlikun	0:13413ea9a877	713
ganlikun	0:13413ea9a877	714	/**
ganlikun	0:13413ea9a877	715	* @brief Configure the Peripheral clock frequency.
ganlikun	0:13413ea9a877	716	* @rmtoll CR2 FREQ LL_I2C_SetPeriphClock
ganlikun	0:13413ea9a877	717	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	718	* @param PeriphClock Peripheral Clock (in Hz)
ganlikun	0:13413ea9a877	719	* @retval None
ganlikun	0:13413ea9a877	720	*/
ganlikun	0:13413ea9a877	721	__STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
ganlikun	0:13413ea9a877	722	{
ganlikun	0:13413ea9a877	723	MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
ganlikun	0:13413ea9a877	724	}
ganlikun	0:13413ea9a877	725
ganlikun	0:13413ea9a877	726	/**
ganlikun	0:13413ea9a877	727	* @brief Get the Peripheral clock frequency.
ganlikun	0:13413ea9a877	728	* @rmtoll CR2 FREQ LL_I2C_GetPeriphClock
ganlikun	0:13413ea9a877	729	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	730	* @retval Value of Peripheral Clock (in Hz)
ganlikun	0:13413ea9a877	731	*/
ganlikun	0:13413ea9a877	732	__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	733	{
ganlikun	0:13413ea9a877	734	return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
ganlikun	0:13413ea9a877	735	}
ganlikun	0:13413ea9a877	736
ganlikun	0:13413ea9a877	737	/**
ganlikun	0:13413ea9a877	738	* @brief Configure the Duty cycle (Fast mode only).
ganlikun	0:13413ea9a877	739	* @rmtoll CCR DUTY LL_I2C_SetDutyCycle
ganlikun	0:13413ea9a877	740	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	741	* @param DutyCycle This parameter can be one of the following values:
ganlikun	0:13413ea9a877	742	* @arg @ref LL_I2C_DUTYCYCLE_2
ganlikun	0:13413ea9a877	743	* @arg @ref LL_I2C_DUTYCYCLE_16_9
ganlikun	0:13413ea9a877	744	* @retval None
ganlikun	0:13413ea9a877	745	*/
ganlikun	0:13413ea9a877	746	__STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
ganlikun	0:13413ea9a877	747	{
ganlikun	0:13413ea9a877	748	MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
ganlikun	0:13413ea9a877	749	}
ganlikun	0:13413ea9a877	750
ganlikun	0:13413ea9a877	751	/**
ganlikun	0:13413ea9a877	752	* @brief Get the Duty cycle (Fast mode only).
ganlikun	0:13413ea9a877	753	* @rmtoll CCR DUTY LL_I2C_GetDutyCycle
ganlikun	0:13413ea9a877	754	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	755	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	756	* @arg @ref LL_I2C_DUTYCYCLE_2
ganlikun	0:13413ea9a877	757	* @arg @ref LL_I2C_DUTYCYCLE_16_9
ganlikun	0:13413ea9a877	758	*/
ganlikun	0:13413ea9a877	759	__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	760	{
ganlikun	0:13413ea9a877	761	return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
ganlikun	0:13413ea9a877	762	}
ganlikun	0:13413ea9a877	763
ganlikun	0:13413ea9a877	764	/**
ganlikun	0:13413ea9a877	765	* @brief Configure the I2C master clock speed mode.
ganlikun	0:13413ea9a877	766	* @rmtoll CCR FS LL_I2C_SetClockSpeedMode
ganlikun	0:13413ea9a877	767	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	768	* @param ClockSpeedMode This parameter can be one of the following values:
ganlikun	0:13413ea9a877	769	* @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
ganlikun	0:13413ea9a877	770	* @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
ganlikun	0:13413ea9a877	771	* @retval None
ganlikun	0:13413ea9a877	772	*/
ganlikun	0:13413ea9a877	773	__STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
ganlikun	0:13413ea9a877	774	{
ganlikun	0:13413ea9a877	775	MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
ganlikun	0:13413ea9a877	776	}
ganlikun	0:13413ea9a877	777
ganlikun	0:13413ea9a877	778	/**
ganlikun	0:13413ea9a877	779	* @brief Get the the I2C master speed mode.
ganlikun	0:13413ea9a877	780	* @rmtoll CCR FS LL_I2C_GetClockSpeedMode
ganlikun	0:13413ea9a877	781	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	782	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	783	* @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
ganlikun	0:13413ea9a877	784	* @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
ganlikun	0:13413ea9a877	785	*/
ganlikun	0:13413ea9a877	786	__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	787	{
ganlikun	0:13413ea9a877	788	return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
ganlikun	0:13413ea9a877	789	}
ganlikun	0:13413ea9a877	790
ganlikun	0:13413ea9a877	791	/**
ganlikun	0:13413ea9a877	792	* @brief Configure the SCL, SDA rising time.
ganlikun	0:13413ea9a877	793	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
ganlikun	0:13413ea9a877	794	* @rmtoll TRISE TRISE LL_I2C_SetRiseTime
ganlikun	0:13413ea9a877	795	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	796	* @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
ganlikun	0:13413ea9a877	797	* @retval None
ganlikun	0:13413ea9a877	798	*/
ganlikun	0:13413ea9a877	799	__STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
ganlikun	0:13413ea9a877	800	{
ganlikun	0:13413ea9a877	801	MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
ganlikun	0:13413ea9a877	802	}
ganlikun	0:13413ea9a877	803
ganlikun	0:13413ea9a877	804	/**
ganlikun	0:13413ea9a877	805	* @brief Get the SCL, SDA rising time.
ganlikun	0:13413ea9a877	806	* @rmtoll TRISE TRISE LL_I2C_GetRiseTime
ganlikun	0:13413ea9a877	807	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	808	* @retval Value between Min_Data=0x02 and Max_Data=0x3F
ganlikun	0:13413ea9a877	809	*/
ganlikun	0:13413ea9a877	810	__STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	811	{
ganlikun	0:13413ea9a877	812	return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
ganlikun	0:13413ea9a877	813	}
ganlikun	0:13413ea9a877	814
ganlikun	0:13413ea9a877	815	/**
ganlikun	0:13413ea9a877	816	* @brief Configure the SCL high and low period.
ganlikun	0:13413ea9a877	817	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
ganlikun	0:13413ea9a877	818	* @rmtoll CCR CCR LL_I2C_SetClockPeriod
ganlikun	0:13413ea9a877	819	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	820	* @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
ganlikun	0:13413ea9a877	821	* @retval None
ganlikun	0:13413ea9a877	822	*/
ganlikun	0:13413ea9a877	823	__STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
ganlikun	0:13413ea9a877	824	{
ganlikun	0:13413ea9a877	825	MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
ganlikun	0:13413ea9a877	826	}
ganlikun	0:13413ea9a877	827
ganlikun	0:13413ea9a877	828	/**
ganlikun	0:13413ea9a877	829	* @brief Get the SCL high and low period.
ganlikun	0:13413ea9a877	830	* @rmtoll CCR CCR LL_I2C_GetClockPeriod
ganlikun	0:13413ea9a877	831	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	832	* @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
ganlikun	0:13413ea9a877	833	*/
ganlikun	0:13413ea9a877	834	__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	835	{
ganlikun	0:13413ea9a877	836	return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
ganlikun	0:13413ea9a877	837	}
ganlikun	0:13413ea9a877	838
ganlikun	0:13413ea9a877	839	/**
ganlikun	0:13413ea9a877	840	* @brief Configure the SCL speed.
ganlikun	0:13413ea9a877	841	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
ganlikun	0:13413ea9a877	842	* @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n
ganlikun	0:13413ea9a877	843	* TRISE TRISE LL_I2C_ConfigSpeed\n
ganlikun	0:13413ea9a877	844	* CCR FS LL_I2C_ConfigSpeed\n
ganlikun	0:13413ea9a877	845	* CCR DUTY LL_I2C_ConfigSpeed\n
ganlikun	0:13413ea9a877	846	* CCR CCR LL_I2C_ConfigSpeed
ganlikun	0:13413ea9a877	847	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	848	* @param PeriphClock Peripheral Clock (in Hz)
ganlikun	0:13413ea9a877	849	* @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
ganlikun	0:13413ea9a877	850	* @param DutyCycle This parameter can be one of the following values:
ganlikun	0:13413ea9a877	851	* @arg @ref LL_I2C_DUTYCYCLE_2
ganlikun	0:13413ea9a877	852	* @arg @ref LL_I2C_DUTYCYCLE_16_9
ganlikun	0:13413ea9a877	853	* @retval None
ganlikun	0:13413ea9a877	854	*/
ganlikun	0:13413ea9a877	855	__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
ganlikun	0:13413ea9a877	856	uint32_t DutyCycle)
ganlikun	0:13413ea9a877	857	{
ganlikun	0:13413ea9a877	858	register uint32_t freqrange = 0x0U;
ganlikun	0:13413ea9a877	859	register uint32_t clockconfig = 0x0U;
ganlikun	0:13413ea9a877	860
ganlikun	0:13413ea9a877	861	/* Compute frequency range */
ganlikun	0:13413ea9a877	862	freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
ganlikun	0:13413ea9a877	863
ganlikun	0:13413ea9a877	864	/* Configure I2Cx: Frequency range register */
ganlikun	0:13413ea9a877	865	MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
ganlikun	0:13413ea9a877	866
ganlikun	0:13413ea9a877	867	/* Configure I2Cx: Rise Time register */
ganlikun	0:13413ea9a877	868	MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
ganlikun	0:13413ea9a877	869
ganlikun	0:13413ea9a877	870	/* Configure Speed mode, Duty Cycle and Clock control register value */
ganlikun	0:13413ea9a877	871	if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
ganlikun	0:13413ea9a877	872	{
ganlikun	0:13413ea9a877	873	/* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
ganlikun	0:13413ea9a877	874	clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE \| \
ganlikun	0:13413ea9a877	875	__LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) \| \
ganlikun	0:13413ea9a877	876	DutyCycle;
ganlikun	0:13413ea9a877	877	}
ganlikun	0:13413ea9a877	878	else
ganlikun	0:13413ea9a877	879	{
ganlikun	0:13413ea9a877	880	/* Set Speed mode at standard for Clock Speed request in standard clock range */
ganlikun	0:13413ea9a877	881	clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE \| \
ganlikun	0:13413ea9a877	882	__LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
ganlikun	0:13413ea9a877	883	}
ganlikun	0:13413ea9a877	884
ganlikun	0:13413ea9a877	885	/* Configure I2Cx: Clock control register */
ganlikun	0:13413ea9a877	886	MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS \| I2C_CCR_DUTY \| I2C_CCR_CCR), clockconfig);
ganlikun	0:13413ea9a877	887	}
ganlikun	0:13413ea9a877	888
ganlikun	0:13413ea9a877	889	/**
ganlikun	0:13413ea9a877	890	* @brief Configure peripheral mode.
ganlikun	0:13413ea9a877	891	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
ganlikun	0:13413ea9a877	892	* SMBus feature is supported by the I2Cx Instance.
ganlikun	0:13413ea9a877	893	* @rmtoll CR1 SMBUS LL_I2C_SetMode\n
ganlikun	0:13413ea9a877	894	* CR1 SMBTYPE LL_I2C_SetMode\n
ganlikun	0:13413ea9a877	895	* CR1 ENARP LL_I2C_SetMode
ganlikun	0:13413ea9a877	896	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	897	* @param PeripheralMode This parameter can be one of the following values:
ganlikun	0:13413ea9a877	898	* @arg @ref LL_I2C_MODE_I2C
ganlikun	0:13413ea9a877	899	* @arg @ref LL_I2C_MODE_SMBUS_HOST
ganlikun	0:13413ea9a877	900	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
ganlikun	0:13413ea9a877	901	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
ganlikun	0:13413ea9a877	902	* @retval None
ganlikun	0:13413ea9a877	903	*/
ganlikun	0:13413ea9a877	904	__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
ganlikun	0:13413ea9a877	905	{
ganlikun	0:13413ea9a877	906	MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS \| I2C_CR1_SMBTYPE \| I2C_CR1_ENARP, PeripheralMode);
ganlikun	0:13413ea9a877	907	}
ganlikun	0:13413ea9a877	908
ganlikun	0:13413ea9a877	909	/**
ganlikun	0:13413ea9a877	910	* @brief Get peripheral mode.
ganlikun	0:13413ea9a877	911	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
ganlikun	0:13413ea9a877	912	* SMBus feature is supported by the I2Cx Instance.
ganlikun	0:13413ea9a877	913	* @rmtoll CR1 SMBUS LL_I2C_GetMode\n
ganlikun	0:13413ea9a877	914	* CR1 SMBTYPE LL_I2C_GetMode\n
ganlikun	0:13413ea9a877	915	* CR1 ENARP LL_I2C_GetMode
ganlikun	0:13413ea9a877	916	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	917	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	918	* @arg @ref LL_I2C_MODE_I2C
ganlikun	0:13413ea9a877	919	* @arg @ref LL_I2C_MODE_SMBUS_HOST
ganlikun	0:13413ea9a877	920	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
ganlikun	0:13413ea9a877	921	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
ganlikun	0:13413ea9a877	922	*/
ganlikun	0:13413ea9a877	923	__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	924	{
ganlikun	0:13413ea9a877	925	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS \| I2C_CR1_SMBTYPE \| I2C_CR1_ENARP));
ganlikun	0:13413ea9a877	926	}
ganlikun	0:13413ea9a877	927
ganlikun	0:13413ea9a877	928	/**
ganlikun	0:13413ea9a877	929	* @brief Enable SMBus alert (Host or Device mode)
ganlikun	0:13413ea9a877	930	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
ganlikun	0:13413ea9a877	931	* SMBus feature is supported by the I2Cx Instance.
ganlikun	0:13413ea9a877	932	* @note SMBus Device mode:
ganlikun	0:13413ea9a877	933	* - SMBus Alert pin is drived low and
ganlikun	0:13413ea9a877	934	* Alert Response Address Header acknowledge is enabled.
ganlikun	0:13413ea9a877	935	* SMBus Host mode:
ganlikun	0:13413ea9a877	936	* - SMBus Alert pin management is supported.
ganlikun	0:13413ea9a877	937	* @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert
ganlikun	0:13413ea9a877	938	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	939	* @retval None
ganlikun	0:13413ea9a877	940	*/
ganlikun	0:13413ea9a877	941	__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	942	{
ganlikun	0:13413ea9a877	943	SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
ganlikun	0:13413ea9a877	944	}
ganlikun	0:13413ea9a877	945
ganlikun	0:13413ea9a877	946	/**
ganlikun	0:13413ea9a877	947	* @brief Disable SMBus alert (Host or Device mode)
ganlikun	0:13413ea9a877	948	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
ganlikun	0:13413ea9a877	949	* SMBus feature is supported by the I2Cx Instance.
ganlikun	0:13413ea9a877	950	* @note SMBus Device mode:
ganlikun	0:13413ea9a877	951	* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
ganlikun	0:13413ea9a877	952	* Alert Response Address Header acknowledge is disabled.
ganlikun	0:13413ea9a877	953	* SMBus Host mode:
ganlikun	0:13413ea9a877	954	* - SMBus Alert pin management is not supported.
ganlikun	0:13413ea9a877	955	* @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert
ganlikun	0:13413ea9a877	956	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	957	* @retval None
ganlikun	0:13413ea9a877	958	*/
ganlikun	0:13413ea9a877	959	__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	960	{
ganlikun	0:13413ea9a877	961	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
ganlikun	0:13413ea9a877	962	}
ganlikun	0:13413ea9a877	963
ganlikun	0:13413ea9a877	964	/**
ganlikun	0:13413ea9a877	965	* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
ganlikun	0:13413ea9a877	966	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
ganlikun	0:13413ea9a877	967	* SMBus feature is supported by the I2Cx Instance.
ganlikun	0:13413ea9a877	968	* @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert
ganlikun	0:13413ea9a877	969	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	970	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	971	*/
ganlikun	0:13413ea9a877	972	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	973	{
ganlikun	0:13413ea9a877	974	return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
ganlikun	0:13413ea9a877	975	}
ganlikun	0:13413ea9a877	976
ganlikun	0:13413ea9a877	977	/**
ganlikun	0:13413ea9a877	978	* @brief Enable SMBus Packet Error Calculation (PEC).
ganlikun	0:13413ea9a877	979	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
ganlikun	0:13413ea9a877	980	* SMBus feature is supported by the I2Cx Instance.
ganlikun	0:13413ea9a877	981	* @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC
ganlikun	0:13413ea9a877	982	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	983	* @retval None
ganlikun	0:13413ea9a877	984	*/
ganlikun	0:13413ea9a877	985	__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	986	{
ganlikun	0:13413ea9a877	987	SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
ganlikun	0:13413ea9a877	988	}
ganlikun	0:13413ea9a877	989
ganlikun	0:13413ea9a877	990	/**
ganlikun	0:13413ea9a877	991	* @brief Disable SMBus Packet Error Calculation (PEC).
ganlikun	0:13413ea9a877	992	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
ganlikun	0:13413ea9a877	993	* SMBus feature is supported by the I2Cx Instance.
ganlikun	0:13413ea9a877	994	* @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC
ganlikun	0:13413ea9a877	995	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	996	* @retval None
ganlikun	0:13413ea9a877	997	*/
ganlikun	0:13413ea9a877	998	__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	999	{
ganlikun	0:13413ea9a877	1000	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
ganlikun	0:13413ea9a877	1001	}
ganlikun	0:13413ea9a877	1002
ganlikun	0:13413ea9a877	1003	/**
ganlikun	0:13413ea9a877	1004	* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
ganlikun	0:13413ea9a877	1005	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
ganlikun	0:13413ea9a877	1006	* SMBus feature is supported by the I2Cx Instance.
ganlikun	0:13413ea9a877	1007	* @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
ganlikun	0:13413ea9a877	1008	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1009	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1010	*/
ganlikun	0:13413ea9a877	1011	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1012	{
ganlikun	0:13413ea9a877	1013	return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
ganlikun	0:13413ea9a877	1014	}
ganlikun	0:13413ea9a877	1015
ganlikun	0:13413ea9a877	1016	/**
ganlikun	0:13413ea9a877	1017	* @}
ganlikun	0:13413ea9a877	1018	*/
ganlikun	0:13413ea9a877	1019
ganlikun	0:13413ea9a877	1020	/** @defgroup I2C_LL_EF_IT_Management IT_Management
ganlikun	0:13413ea9a877	1021	* @{
ganlikun	0:13413ea9a877	1022	*/
ganlikun	0:13413ea9a877	1023
ganlikun	0:13413ea9a877	1024	/**
ganlikun	0:13413ea9a877	1025	* @brief Enable TXE interrupt.
ganlikun	0:13413ea9a877	1026	* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n
ganlikun	0:13413ea9a877	1027	* CR2 ITBUFEN LL_I2C_EnableIT_TX
ganlikun	0:13413ea9a877	1028	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1029	* @retval None
ganlikun	0:13413ea9a877	1030	*/
ganlikun	0:13413ea9a877	1031	__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1032	{
ganlikun	0:13413ea9a877	1033	SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
ganlikun	0:13413ea9a877	1034	}
ganlikun	0:13413ea9a877	1035
ganlikun	0:13413ea9a877	1036	/**
ganlikun	0:13413ea9a877	1037	* @brief Disable TXE interrupt.
ganlikun	0:13413ea9a877	1038	* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n
ganlikun	0:13413ea9a877	1039	* CR2 ITBUFEN LL_I2C_DisableIT_TX
ganlikun	0:13413ea9a877	1040	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1041	* @retval None
ganlikun	0:13413ea9a877	1042	*/
ganlikun	0:13413ea9a877	1043	__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1044	{
ganlikun	0:13413ea9a877	1045	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
ganlikun	0:13413ea9a877	1046	}
ganlikun	0:13413ea9a877	1047
ganlikun	0:13413ea9a877	1048	/**
ganlikun	0:13413ea9a877	1049	* @brief Check if the TXE Interrupt is enabled or disabled.
ganlikun	0:13413ea9a877	1050	* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n
ganlikun	0:13413ea9a877	1051	* CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
ganlikun	0:13413ea9a877	1052	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1053	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1054	*/
ganlikun	0:13413ea9a877	1055	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1056	{
ganlikun	0:13413ea9a877	1057	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN));
ganlikun	0:13413ea9a877	1058	}
ganlikun	0:13413ea9a877	1059
ganlikun	0:13413ea9a877	1060	/**
ganlikun	0:13413ea9a877	1061	* @brief Enable RXNE interrupt.
ganlikun	0:13413ea9a877	1062	* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n
ganlikun	0:13413ea9a877	1063	* CR2 ITBUFEN LL_I2C_EnableIT_RX
ganlikun	0:13413ea9a877	1064	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1065	* @retval None
ganlikun	0:13413ea9a877	1066	*/
ganlikun	0:13413ea9a877	1067	__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1068	{
ganlikun	0:13413ea9a877	1069	SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
ganlikun	0:13413ea9a877	1070	}
ganlikun	0:13413ea9a877	1071
ganlikun	0:13413ea9a877	1072	/**
ganlikun	0:13413ea9a877	1073	* @brief Disable RXNE interrupt.
ganlikun	0:13413ea9a877	1074	* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n
ganlikun	0:13413ea9a877	1075	* CR2 ITBUFEN LL_I2C_DisableIT_RX
ganlikun	0:13413ea9a877	1076	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1077	* @retval None
ganlikun	0:13413ea9a877	1078	*/
ganlikun	0:13413ea9a877	1079	__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1080	{
ganlikun	0:13413ea9a877	1081	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
ganlikun	0:13413ea9a877	1082	}
ganlikun	0:13413ea9a877	1083
ganlikun	0:13413ea9a877	1084	/**
ganlikun	0:13413ea9a877	1085	* @brief Check if the RXNE Interrupt is enabled or disabled.
ganlikun	0:13413ea9a877	1086	* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n
ganlikun	0:13413ea9a877	1087	* CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
ganlikun	0:13413ea9a877	1088	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1089	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1090	*/
ganlikun	0:13413ea9a877	1091	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1092	{
ganlikun	0:13413ea9a877	1093	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN));
ganlikun	0:13413ea9a877	1094	}
ganlikun	0:13413ea9a877	1095
ganlikun	0:13413ea9a877	1096	/**
ganlikun	0:13413ea9a877	1097	* @brief Enable Events interrupts.
ganlikun	0:13413ea9a877	1098	* @note Any of these events will generate interrupt :
ganlikun	0:13413ea9a877	1099	* Start Bit (SB)
ganlikun	0:13413ea9a877	1100	* Address sent, Address matched (ADDR)
ganlikun	0:13413ea9a877	1101	* 10-bit header sent (ADD10)
ganlikun	0:13413ea9a877	1102	* Stop detection (STOPF)
ganlikun	0:13413ea9a877	1103	* Byte transfer finished (BTF)
ganlikun	0:13413ea9a877	1104	*
ganlikun	0:13413ea9a877	1105	* @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
ganlikun	0:13413ea9a877	1106	* Receive buffer not empty (RXNE)
ganlikun	0:13413ea9a877	1107	* Transmit buffer empty (TXE)
ganlikun	0:13413ea9a877	1108	* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT
ganlikun	0:13413ea9a877	1109	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1110	* @retval None
ganlikun	0:13413ea9a877	1111	*/
ganlikun	0:13413ea9a877	1112	__STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1113	{
ganlikun	0:13413ea9a877	1114	SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
ganlikun	0:13413ea9a877	1115	}
ganlikun	0:13413ea9a877	1116
ganlikun	0:13413ea9a877	1117	/**
ganlikun	0:13413ea9a877	1118	* @brief Disable Events interrupts.
ganlikun	0:13413ea9a877	1119	* @note Any of these events will generate interrupt :
ganlikun	0:13413ea9a877	1120	* Start Bit (SB)
ganlikun	0:13413ea9a877	1121	* Address sent, Address matched (ADDR)
ganlikun	0:13413ea9a877	1122	* 10-bit header sent (ADD10)
ganlikun	0:13413ea9a877	1123	* Stop detection (STOPF)
ganlikun	0:13413ea9a877	1124	* Byte transfer finished (BTF)
ganlikun	0:13413ea9a877	1125	* Receive buffer not empty (RXNE)
ganlikun	0:13413ea9a877	1126	* Transmit buffer empty (TXE)
ganlikun	0:13413ea9a877	1127	* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT
ganlikun	0:13413ea9a877	1128	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1129	* @retval None
ganlikun	0:13413ea9a877	1130	*/
ganlikun	0:13413ea9a877	1131	__STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1132	{
ganlikun	0:13413ea9a877	1133	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
ganlikun	0:13413ea9a877	1134	}
ganlikun	0:13413ea9a877	1135
ganlikun	0:13413ea9a877	1136	/**
ganlikun	0:13413ea9a877	1137	* @brief Check if Events interrupts are enabled or disabled.
ganlikun	0:13413ea9a877	1138	* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
ganlikun	0:13413ea9a877	1139	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1140	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1141	*/
ganlikun	0:13413ea9a877	1142	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1143	{
ganlikun	0:13413ea9a877	1144	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
ganlikun	0:13413ea9a877	1145	}
ganlikun	0:13413ea9a877	1146
ganlikun	0:13413ea9a877	1147	/**
ganlikun	0:13413ea9a877	1148	* @brief Enable Buffer interrupts.
ganlikun	0:13413ea9a877	1149	* @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
ganlikun	0:13413ea9a877	1150	* Receive buffer not empty (RXNE)
ganlikun	0:13413ea9a877	1151	* Transmit buffer empty (TXE)
ganlikun	0:13413ea9a877	1152	* @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF
ganlikun	0:13413ea9a877	1153	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1154	* @retval None
ganlikun	0:13413ea9a877	1155	*/
ganlikun	0:13413ea9a877	1156	__STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1157	{
ganlikun	0:13413ea9a877	1158	SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
ganlikun	0:13413ea9a877	1159	}
ganlikun	0:13413ea9a877	1160
ganlikun	0:13413ea9a877	1161	/**
ganlikun	0:13413ea9a877	1162	* @brief Disable Buffer interrupts.
ganlikun	0:13413ea9a877	1163	* @note Any of these Buffer events will generate interrupt :
ganlikun	0:13413ea9a877	1164	* Receive buffer not empty (RXNE)
ganlikun	0:13413ea9a877	1165	* Transmit buffer empty (TXE)
ganlikun	0:13413ea9a877	1166	* @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF
ganlikun	0:13413ea9a877	1167	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1168	* @retval None
ganlikun	0:13413ea9a877	1169	*/
ganlikun	0:13413ea9a877	1170	__STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1171	{
ganlikun	0:13413ea9a877	1172	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
ganlikun	0:13413ea9a877	1173	}
ganlikun	0:13413ea9a877	1174
ganlikun	0:13413ea9a877	1175	/**
ganlikun	0:13413ea9a877	1176	* @brief Check if Buffer interrupts are enabled or disabled.
ganlikun	0:13413ea9a877	1177	* @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
ganlikun	0:13413ea9a877	1178	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1179	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1180	*/
ganlikun	0:13413ea9a877	1181	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1182	{
ganlikun	0:13413ea9a877	1183	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
ganlikun	0:13413ea9a877	1184	}
ganlikun	0:13413ea9a877	1185
ganlikun	0:13413ea9a877	1186	/**
ganlikun	0:13413ea9a877	1187	* @brief Enable Error interrupts.
ganlikun	0:13413ea9a877	1188	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
ganlikun	0:13413ea9a877	1189	* SMBus feature is supported by the I2Cx Instance.
ganlikun	0:13413ea9a877	1190	* @note Any of these errors will generate interrupt :
ganlikun	0:13413ea9a877	1191	* Bus Error detection (BERR)
ganlikun	0:13413ea9a877	1192	* Arbitration Loss (ARLO)
ganlikun	0:13413ea9a877	1193	* Acknowledge Failure(AF)
ganlikun	0:13413ea9a877	1194	* Overrun/Underrun (OVR)
ganlikun	0:13413ea9a877	1195	* SMBus Timeout detection (TIMEOUT)
ganlikun	0:13413ea9a877	1196	* SMBus PEC error detection (PECERR)
ganlikun	0:13413ea9a877	1197	* SMBus Alert pin event detection (SMBALERT)
ganlikun	0:13413ea9a877	1198	* @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR
ganlikun	0:13413ea9a877	1199	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1200	* @retval None
ganlikun	0:13413ea9a877	1201	*/
ganlikun	0:13413ea9a877	1202	__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1203	{
ganlikun	0:13413ea9a877	1204	SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
ganlikun	0:13413ea9a877	1205	}
ganlikun	0:13413ea9a877	1206
ganlikun	0:13413ea9a877	1207	/**
ganlikun	0:13413ea9a877	1208	* @brief Disable Error interrupts.
ganlikun	0:13413ea9a877	1209	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
ganlikun	0:13413ea9a877	1210	* SMBus feature is supported by the I2Cx Instance.
ganlikun	0:13413ea9a877	1211	* @note Any of these errors will generate interrupt :
ganlikun	0:13413ea9a877	1212	* Bus Error detection (BERR)
ganlikun	0:13413ea9a877	1213	* Arbitration Loss (ARLO)
ganlikun	0:13413ea9a877	1214	* Acknowledge Failure(AF)
ganlikun	0:13413ea9a877	1215	* Overrun/Underrun (OVR)
ganlikun	0:13413ea9a877	1216	* SMBus Timeout detection (TIMEOUT)
ganlikun	0:13413ea9a877	1217	* SMBus PEC error detection (PECERR)
ganlikun	0:13413ea9a877	1218	* SMBus Alert pin event detection (SMBALERT)
ganlikun	0:13413ea9a877	1219	* @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR
ganlikun	0:13413ea9a877	1220	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1221	* @retval None
ganlikun	0:13413ea9a877	1222	*/
ganlikun	0:13413ea9a877	1223	__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1224	{
ganlikun	0:13413ea9a877	1225	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
ganlikun	0:13413ea9a877	1226	}
ganlikun	0:13413ea9a877	1227
ganlikun	0:13413ea9a877	1228	/**
ganlikun	0:13413ea9a877	1229	* @brief Check if Error interrupts are enabled or disabled.
ganlikun	0:13413ea9a877	1230	* @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR
ganlikun	0:13413ea9a877	1231	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1232	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1233	*/
ganlikun	0:13413ea9a877	1234	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1235	{
ganlikun	0:13413ea9a877	1236	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
ganlikun	0:13413ea9a877	1237	}
ganlikun	0:13413ea9a877	1238
ganlikun	0:13413ea9a877	1239	/**
ganlikun	0:13413ea9a877	1240	* @}
ganlikun	0:13413ea9a877	1241	*/
ganlikun	0:13413ea9a877	1242
ganlikun	0:13413ea9a877	1243	/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
ganlikun	0:13413ea9a877	1244	* @{
ganlikun	0:13413ea9a877	1245	*/
ganlikun	0:13413ea9a877	1246
ganlikun	0:13413ea9a877	1247	/**
ganlikun	0:13413ea9a877	1248	* @brief Indicate the status of Transmit data register empty flag.
ganlikun	0:13413ea9a877	1249	* @note RESET: When next data is written in Transmit data register.
ganlikun	0:13413ea9a877	1250	* SET: When Transmit data register is empty.
ganlikun	0:13413ea9a877	1251	* @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE
ganlikun	0:13413ea9a877	1252	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1253	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1254	*/
ganlikun	0:13413ea9a877	1255	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1256	{
ganlikun	0:13413ea9a877	1257	return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
ganlikun	0:13413ea9a877	1258	}
ganlikun	0:13413ea9a877	1259
ganlikun	0:13413ea9a877	1260	/**
ganlikun	0:13413ea9a877	1261	* @brief Indicate the status of Byte Transfer Finished flag.
ganlikun	0:13413ea9a877	1262	* RESET: When Data byte transfer not done.
ganlikun	0:13413ea9a877	1263	* SET: When Data byte transfer succeeded.
ganlikun	0:13413ea9a877	1264	* @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF
ganlikun	0:13413ea9a877	1265	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1266	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1267	*/
ganlikun	0:13413ea9a877	1268	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1269	{
ganlikun	0:13413ea9a877	1270	return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
ganlikun	0:13413ea9a877	1271	}
ganlikun	0:13413ea9a877	1272
ganlikun	0:13413ea9a877	1273	/**
ganlikun	0:13413ea9a877	1274	* @brief Indicate the status of Receive data register not empty flag.
ganlikun	0:13413ea9a877	1275	* @note RESET: When Receive data register is read.
ganlikun	0:13413ea9a877	1276	* SET: When the received data is copied in Receive data register.
ganlikun	0:13413ea9a877	1277	* @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE
ganlikun	0:13413ea9a877	1278	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1279	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1280	*/
ganlikun	0:13413ea9a877	1281	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1282	{
ganlikun	0:13413ea9a877	1283	return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
ganlikun	0:13413ea9a877	1284	}
ganlikun	0:13413ea9a877	1285
ganlikun	0:13413ea9a877	1286	/**
ganlikun	0:13413ea9a877	1287	* @brief Indicate the status of Start Bit (master mode).
ganlikun	0:13413ea9a877	1288	* @note RESET: When No Start condition.
ganlikun	0:13413ea9a877	1289	* SET: When Start condition is generated.
ganlikun	0:13413ea9a877	1290	* @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB
ganlikun	0:13413ea9a877	1291	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1292	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1293	*/
ganlikun	0:13413ea9a877	1294	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1295	{
ganlikun	0:13413ea9a877	1296	return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
ganlikun	0:13413ea9a877	1297	}
ganlikun	0:13413ea9a877	1298
ganlikun	0:13413ea9a877	1299	/**
ganlikun	0:13413ea9a877	1300	* @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
ganlikun	0:13413ea9a877	1301	* @note RESET: Clear default value.
ganlikun	0:13413ea9a877	1302	* SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
ganlikun	0:13413ea9a877	1303	* @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR
ganlikun	0:13413ea9a877	1304	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1305	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1306	*/
ganlikun	0:13413ea9a877	1307	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1308	{
ganlikun	0:13413ea9a877	1309	return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
ganlikun	0:13413ea9a877	1310	}
ganlikun	0:13413ea9a877	1311
ganlikun	0:13413ea9a877	1312	/**
ganlikun	0:13413ea9a877	1313	* @brief Indicate the status of 10-bit header sent (master mode).
ganlikun	0:13413ea9a877	1314	* @note RESET: When no ADD10 event occured.
ganlikun	0:13413ea9a877	1315	* SET: When the master has sent the first address byte (header).
ganlikun	0:13413ea9a877	1316	* @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
ganlikun	0:13413ea9a877	1317	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1318	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1319	*/
ganlikun	0:13413ea9a877	1320	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1321	{
ganlikun	0:13413ea9a877	1322	return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
ganlikun	0:13413ea9a877	1323	}
ganlikun	0:13413ea9a877	1324
ganlikun	0:13413ea9a877	1325	/**
ganlikun	0:13413ea9a877	1326	* @brief Indicate the status of Acknowledge failure flag.
ganlikun	0:13413ea9a877	1327	* @note RESET: No acknowledge failure.
ganlikun	0:13413ea9a877	1328	* SET: When an acknowledge failure is received after a byte transmission.
ganlikun	0:13413ea9a877	1329	* @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF
ganlikun	0:13413ea9a877	1330	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1331	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1332	*/
ganlikun	0:13413ea9a877	1333	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1334	{
ganlikun	0:13413ea9a877	1335	return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
ganlikun	0:13413ea9a877	1336	}
ganlikun	0:13413ea9a877	1337
ganlikun	0:13413ea9a877	1338	/**
ganlikun	0:13413ea9a877	1339	* @brief Indicate the status of Stop detection flag (slave mode).
ganlikun	0:13413ea9a877	1340	* @note RESET: Clear default value.
ganlikun	0:13413ea9a877	1341	* SET: When a Stop condition is detected.
ganlikun	0:13413ea9a877	1342	* @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP
ganlikun	0:13413ea9a877	1343	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1344	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1345	*/
ganlikun	0:13413ea9a877	1346	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1347	{
ganlikun	0:13413ea9a877	1348	return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
ganlikun	0:13413ea9a877	1349	}
ganlikun	0:13413ea9a877	1350
ganlikun	0:13413ea9a877	1351	/**
ganlikun	0:13413ea9a877	1352	* @brief Indicate the status of Bus error flag.
ganlikun	0:13413ea9a877	1353	* @note RESET: Clear default value.
ganlikun	0:13413ea9a877	1354	* SET: When a misplaced Start or Stop condition is detected.
ganlikun	0:13413ea9a877	1355	* @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR
ganlikun	0:13413ea9a877	1356	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1357	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1358	*/
ganlikun	0:13413ea9a877	1359	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1360	{
ganlikun	0:13413ea9a877	1361	return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
ganlikun	0:13413ea9a877	1362	}
ganlikun	0:13413ea9a877	1363
ganlikun	0:13413ea9a877	1364	/**
ganlikun	0:13413ea9a877	1365	* @brief Indicate the status of Arbitration lost flag.
ganlikun	0:13413ea9a877	1366	* @note RESET: Clear default value.
ganlikun	0:13413ea9a877	1367	* SET: When arbitration lost.
ganlikun	0:13413ea9a877	1368	* @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO
ganlikun	0:13413ea9a877	1369	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1370	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1371	*/
ganlikun	0:13413ea9a877	1372	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1373	{
ganlikun	0:13413ea9a877	1374	return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
ganlikun	0:13413ea9a877	1375	}
ganlikun	0:13413ea9a877	1376
ganlikun	0:13413ea9a877	1377	/**
ganlikun	0:13413ea9a877	1378	* @brief Indicate the status of Overrun/Underrun flag.
ganlikun	0:13413ea9a877	1379	* @note RESET: Clear default value.
ganlikun	0:13413ea9a877	1380	* SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
ganlikun	0:13413ea9a877	1381	* @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR
ganlikun	0:13413ea9a877	1382	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1383	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1384	*/
ganlikun	0:13413ea9a877	1385	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1386	{
ganlikun	0:13413ea9a877	1387	return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
ganlikun	0:13413ea9a877	1388	}
ganlikun	0:13413ea9a877	1389
ganlikun	0:13413ea9a877	1390	/**
ganlikun	0:13413ea9a877	1391	* @brief Indicate the status of SMBus PEC error flag in reception.
ganlikun	0:13413ea9a877	1392	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
ganlikun	0:13413ea9a877	1393	* SMBus feature is supported by the I2Cx Instance.
ganlikun	0:13413ea9a877	1394	* @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
ganlikun	0:13413ea9a877	1395	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1396	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1397	*/
ganlikun	0:13413ea9a877	1398	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1399	{
ganlikun	0:13413ea9a877	1400	return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
ganlikun	0:13413ea9a877	1401	}
ganlikun	0:13413ea9a877	1402
ganlikun	0:13413ea9a877	1403	/**
ganlikun	0:13413ea9a877	1404	* @brief Indicate the status of SMBus Timeout detection flag.
ganlikun	0:13413ea9a877	1405	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
ganlikun	0:13413ea9a877	1406	* SMBus feature is supported by the I2Cx Instance.
ganlikun	0:13413ea9a877	1407	* @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
ganlikun	0:13413ea9a877	1408	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1409	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1410	*/
ganlikun	0:13413ea9a877	1411	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1412	{
ganlikun	0:13413ea9a877	1413	return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
ganlikun	0:13413ea9a877	1414	}
ganlikun	0:13413ea9a877	1415
ganlikun	0:13413ea9a877	1416	/**
ganlikun	0:13413ea9a877	1417	* @brief Indicate the status of SMBus alert flag.
ganlikun	0:13413ea9a877	1418	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
ganlikun	0:13413ea9a877	1419	* SMBus feature is supported by the I2Cx Instance.
ganlikun	0:13413ea9a877	1420	* @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
ganlikun	0:13413ea9a877	1421	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1422	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1423	*/
ganlikun	0:13413ea9a877	1424	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1425	{
ganlikun	0:13413ea9a877	1426	return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
ganlikun	0:13413ea9a877	1427	}
ganlikun	0:13413ea9a877	1428
ganlikun	0:13413ea9a877	1429	/**
ganlikun	0:13413ea9a877	1430	* @brief Indicate the status of Bus Busy flag.
ganlikun	0:13413ea9a877	1431	* @note RESET: Clear default value.
ganlikun	0:13413ea9a877	1432	* SET: When a Start condition is detected.
ganlikun	0:13413ea9a877	1433	* @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY
ganlikun	0:13413ea9a877	1434	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1435	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1436	*/
ganlikun	0:13413ea9a877	1437	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1438	{
ganlikun	0:13413ea9a877	1439	return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
ganlikun	0:13413ea9a877	1440	}
ganlikun	0:13413ea9a877	1441
ganlikun	0:13413ea9a877	1442	/**
ganlikun	0:13413ea9a877	1443	* @brief Indicate the status of Dual flag.
ganlikun	0:13413ea9a877	1444	* @note RESET: Received address matched with OAR1.
ganlikun	0:13413ea9a877	1445	* SET: Received address matched with OAR2.
ganlikun	0:13413ea9a877	1446	* @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL
ganlikun	0:13413ea9a877	1447	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1448	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1449	*/
ganlikun	0:13413ea9a877	1450	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1451	{
ganlikun	0:13413ea9a877	1452	return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
ganlikun	0:13413ea9a877	1453	}
ganlikun	0:13413ea9a877	1454
ganlikun	0:13413ea9a877	1455	/**
ganlikun	0:13413ea9a877	1456	* @brief Indicate the status of SMBus Host address reception (Slave mode).
ganlikun	0:13413ea9a877	1457	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
ganlikun	0:13413ea9a877	1458	* SMBus feature is supported by the I2Cx Instance.
ganlikun	0:13413ea9a877	1459	* @note RESET: No SMBus Host address
ganlikun	0:13413ea9a877	1460	* SET: SMBus Host address received.
ganlikun	0:13413ea9a877	1461	* @note This status is cleared by hardware after a STOP condition or repeated START condition.
ganlikun	0:13413ea9a877	1462	* @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
ganlikun	0:13413ea9a877	1463	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1464	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1465	*/
ganlikun	0:13413ea9a877	1466	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1467	{
ganlikun	0:13413ea9a877	1468	return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
ganlikun	0:13413ea9a877	1469	}
ganlikun	0:13413ea9a877	1470
ganlikun	0:13413ea9a877	1471	/**
ganlikun	0:13413ea9a877	1472	* @brief Indicate the status of SMBus Device default address reception (Slave mode).
ganlikun	0:13413ea9a877	1473	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
ganlikun	0:13413ea9a877	1474	* SMBus feature is supported by the I2Cx Instance.
ganlikun	0:13413ea9a877	1475	* @note RESET: No SMBus Device default address
ganlikun	0:13413ea9a877	1476	* SET: SMBus Device default address received.
ganlikun	0:13413ea9a877	1477	* @note This status is cleared by hardware after a STOP condition or repeated START condition.
ganlikun	0:13413ea9a877	1478	* @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
ganlikun	0:13413ea9a877	1479	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1480	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1481	*/
ganlikun	0:13413ea9a877	1482	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1483	{
ganlikun	0:13413ea9a877	1484	return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
ganlikun	0:13413ea9a877	1485	}
ganlikun	0:13413ea9a877	1486
ganlikun	0:13413ea9a877	1487	/**
ganlikun	0:13413ea9a877	1488	* @brief Indicate the status of General call address reception (Slave mode).
ganlikun	0:13413ea9a877	1489	* @note RESET: No Generall call address
ganlikun	0:13413ea9a877	1490	* SET: General call address received.
ganlikun	0:13413ea9a877	1491	* @note This status is cleared by hardware after a STOP condition or repeated START condition.
ganlikun	0:13413ea9a877	1492	* @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
ganlikun	0:13413ea9a877	1493	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1494	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1495	*/
ganlikun	0:13413ea9a877	1496	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1497	{
ganlikun	0:13413ea9a877	1498	return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
ganlikun	0:13413ea9a877	1499	}
ganlikun	0:13413ea9a877	1500
ganlikun	0:13413ea9a877	1501	/**
ganlikun	0:13413ea9a877	1502	* @brief Indicate the status of Master/Slave flag.
ganlikun	0:13413ea9a877	1503	* @note RESET: Slave Mode.
ganlikun	0:13413ea9a877	1504	* SET: Master Mode.
ganlikun	0:13413ea9a877	1505	* @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL
ganlikun	0:13413ea9a877	1506	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1507	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1508	*/
ganlikun	0:13413ea9a877	1509	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1510	{
ganlikun	0:13413ea9a877	1511	return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
ganlikun	0:13413ea9a877	1512	}
ganlikun	0:13413ea9a877	1513
ganlikun	0:13413ea9a877	1514	/**
ganlikun	0:13413ea9a877	1515	* @brief Clear Address Matched flag.
ganlikun	0:13413ea9a877	1516	* @note Clearing this flag is done by a read access to the I2Cx_SR1
ganlikun	0:13413ea9a877	1517	* register followed by a read access to the I2Cx_SR2 register.
ganlikun	0:13413ea9a877	1518	* @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR
ganlikun	0:13413ea9a877	1519	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1520	* @retval None
ganlikun	0:13413ea9a877	1521	*/
ganlikun	0:13413ea9a877	1522	__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1523	{
ganlikun	0:13413ea9a877	1524	__IO uint32_t tmpreg;
ganlikun	0:13413ea9a877	1525	tmpreg = I2Cx->SR1;
ganlikun	0:13413ea9a877	1526	(void) tmpreg;
ganlikun	0:13413ea9a877	1527	tmpreg = I2Cx->SR2;
ganlikun	0:13413ea9a877	1528	(void) tmpreg;
ganlikun	0:13413ea9a877	1529	}
ganlikun	0:13413ea9a877	1530
ganlikun	0:13413ea9a877	1531	/**
ganlikun	0:13413ea9a877	1532	* @brief Clear Acknowledge failure flag.
ganlikun	0:13413ea9a877	1533	* @rmtoll SR1 AF LL_I2C_ClearFlag_AF
ganlikun	0:13413ea9a877	1534	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1535	* @retval None
ganlikun	0:13413ea9a877	1536	*/
ganlikun	0:13413ea9a877	1537	__STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1538	{
ganlikun	0:13413ea9a877	1539	CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
ganlikun	0:13413ea9a877	1540	}
ganlikun	0:13413ea9a877	1541
ganlikun	0:13413ea9a877	1542	/**
ganlikun	0:13413ea9a877	1543	* @brief Clear Stop detection flag.
ganlikun	0:13413ea9a877	1544	* @note Clearing this flag is done by a read access to the I2Cx_SR1
ganlikun	0:13413ea9a877	1545	* register followed by a write access to I2Cx_CR1 register.
ganlikun	0:13413ea9a877	1546	* @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n
ganlikun	0:13413ea9a877	1547	* CR1 PE LL_I2C_ClearFlag_STOP
ganlikun	0:13413ea9a877	1548	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1549	* @retval None
ganlikun	0:13413ea9a877	1550	*/
ganlikun	0:13413ea9a877	1551	__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1552	{
ganlikun	0:13413ea9a877	1553	__IO uint32_t tmpreg;
ganlikun	0:13413ea9a877	1554	tmpreg = I2Cx->SR1;
ganlikun	0:13413ea9a877	1555	(void) tmpreg;
ganlikun	0:13413ea9a877	1556	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
ganlikun	0:13413ea9a877	1557	}
ganlikun	0:13413ea9a877	1558
ganlikun	0:13413ea9a877	1559	/**
ganlikun	0:13413ea9a877	1560	* @brief Clear Bus error flag.
ganlikun	0:13413ea9a877	1561	* @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR
ganlikun	0:13413ea9a877	1562	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1563	* @retval None
ganlikun	0:13413ea9a877	1564	*/
ganlikun	0:13413ea9a877	1565	__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1566	{
ganlikun	0:13413ea9a877	1567	CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
ganlikun	0:13413ea9a877	1568	}
ganlikun	0:13413ea9a877	1569
ganlikun	0:13413ea9a877	1570	/**
ganlikun	0:13413ea9a877	1571	* @brief Clear Arbitration lost flag.
ganlikun	0:13413ea9a877	1572	* @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO
ganlikun	0:13413ea9a877	1573	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1574	* @retval None
ganlikun	0:13413ea9a877	1575	*/
ganlikun	0:13413ea9a877	1576	__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1577	{
ganlikun	0:13413ea9a877	1578	CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
ganlikun	0:13413ea9a877	1579	}
ganlikun	0:13413ea9a877	1580
ganlikun	0:13413ea9a877	1581	/**
ganlikun	0:13413ea9a877	1582	* @brief Clear Overrun/Underrun flag.
ganlikun	0:13413ea9a877	1583	* @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR
ganlikun	0:13413ea9a877	1584	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1585	* @retval None
ganlikun	0:13413ea9a877	1586	*/
ganlikun	0:13413ea9a877	1587	__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1588	{
ganlikun	0:13413ea9a877	1589	CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
ganlikun	0:13413ea9a877	1590	}
ganlikun	0:13413ea9a877	1591
ganlikun	0:13413ea9a877	1592	/**
ganlikun	0:13413ea9a877	1593	* @brief Clear SMBus PEC error flag.
ganlikun	0:13413ea9a877	1594	* @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
ganlikun	0:13413ea9a877	1595	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1596	* @retval None
ganlikun	0:13413ea9a877	1597	*/
ganlikun	0:13413ea9a877	1598	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1599	{
ganlikun	0:13413ea9a877	1600	CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
ganlikun	0:13413ea9a877	1601	}
ganlikun	0:13413ea9a877	1602
ganlikun	0:13413ea9a877	1603	/**
ganlikun	0:13413ea9a877	1604	* @brief Clear SMBus Timeout detection flag.
ganlikun	0:13413ea9a877	1605	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
ganlikun	0:13413ea9a877	1606	* SMBus feature is supported by the I2Cx Instance.
ganlikun	0:13413ea9a877	1607	* @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
ganlikun	0:13413ea9a877	1608	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1609	* @retval None
ganlikun	0:13413ea9a877	1610	*/
ganlikun	0:13413ea9a877	1611	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1612	{
ganlikun	0:13413ea9a877	1613	CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
ganlikun	0:13413ea9a877	1614	}
ganlikun	0:13413ea9a877	1615
ganlikun	0:13413ea9a877	1616	/**
ganlikun	0:13413ea9a877	1617	* @brief Clear SMBus Alert flag.
ganlikun	0:13413ea9a877	1618	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
ganlikun	0:13413ea9a877	1619	* SMBus feature is supported by the I2Cx Instance.
ganlikun	0:13413ea9a877	1620	* @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
ganlikun	0:13413ea9a877	1621	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1622	* @retval None
ganlikun	0:13413ea9a877	1623	*/
ganlikun	0:13413ea9a877	1624	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1625	{
ganlikun	0:13413ea9a877	1626	CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
ganlikun	0:13413ea9a877	1627	}
ganlikun	0:13413ea9a877	1628
ganlikun	0:13413ea9a877	1629	/**
ganlikun	0:13413ea9a877	1630	* @}
ganlikun	0:13413ea9a877	1631	*/
ganlikun	0:13413ea9a877	1632
ganlikun	0:13413ea9a877	1633	/** @defgroup I2C_LL_EF_Data_Management Data_Management
ganlikun	0:13413ea9a877	1634	* @{
ganlikun	0:13413ea9a877	1635	*/
ganlikun	0:13413ea9a877	1636
ganlikun	0:13413ea9a877	1637	/**
ganlikun	0:13413ea9a877	1638	* @brief Enable Reset of I2C peripheral.
ganlikun	0:13413ea9a877	1639	* @rmtoll CR1 SWRST LL_I2C_EnableReset
ganlikun	0:13413ea9a877	1640	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1641	* @retval None
ganlikun	0:13413ea9a877	1642	*/
ganlikun	0:13413ea9a877	1643	__STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1644	{
ganlikun	0:13413ea9a877	1645	SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
ganlikun	0:13413ea9a877	1646	}
ganlikun	0:13413ea9a877	1647
ganlikun	0:13413ea9a877	1648	/**
ganlikun	0:13413ea9a877	1649	* @brief Disable Reset of I2C peripheral.
ganlikun	0:13413ea9a877	1650	* @rmtoll CR1 SWRST LL_I2C_DisableReset
ganlikun	0:13413ea9a877	1651	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1652	* @retval None
ganlikun	0:13413ea9a877	1653	*/
ganlikun	0:13413ea9a877	1654	__STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1655	{
ganlikun	0:13413ea9a877	1656	CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
ganlikun	0:13413ea9a877	1657	}
ganlikun	0:13413ea9a877	1658
ganlikun	0:13413ea9a877	1659	/**
ganlikun	0:13413ea9a877	1660	* @brief Check if the I2C peripheral is under reset state or not.
ganlikun	0:13413ea9a877	1661	* @rmtoll CR1 SWRST LL_I2C_IsResetEnabled
ganlikun	0:13413ea9a877	1662	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1663	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1664	*/
ganlikun	0:13413ea9a877	1665	__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1666	{
ganlikun	0:13413ea9a877	1667	return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
ganlikun	0:13413ea9a877	1668	}
ganlikun	0:13413ea9a877	1669
ganlikun	0:13413ea9a877	1670	/**
ganlikun	0:13413ea9a877	1671	* @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
ganlikun	0:13413ea9a877	1672	* @note Usage in Slave or Master mode.
ganlikun	0:13413ea9a877	1673	* @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData
ganlikun	0:13413ea9a877	1674	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1675	* @param TypeAcknowledge This parameter can be one of the following values:
ganlikun	0:13413ea9a877	1676	* @arg @ref LL_I2C_ACK
ganlikun	0:13413ea9a877	1677	* @arg @ref LL_I2C_NACK
ganlikun	0:13413ea9a877	1678	* @retval None
ganlikun	0:13413ea9a877	1679	*/
ganlikun	0:13413ea9a877	1680	__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
ganlikun	0:13413ea9a877	1681	{
ganlikun	0:13413ea9a877	1682	MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
ganlikun	0:13413ea9a877	1683	}
ganlikun	0:13413ea9a877	1684
ganlikun	0:13413ea9a877	1685	/**
ganlikun	0:13413ea9a877	1686	* @brief Generate a START or RESTART condition
ganlikun	0:13413ea9a877	1687	* @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
ganlikun	0:13413ea9a877	1688	* This action has no effect when RELOAD is set.
ganlikun	0:13413ea9a877	1689	* @rmtoll CR1 START LL_I2C_GenerateStartCondition
ganlikun	0:13413ea9a877	1690	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1691	* @retval None
ganlikun	0:13413ea9a877	1692	*/
ganlikun	0:13413ea9a877	1693	__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1694	{
ganlikun	0:13413ea9a877	1695	SET_BIT(I2Cx->CR1, I2C_CR1_START);
ganlikun	0:13413ea9a877	1696	}
ganlikun	0:13413ea9a877	1697
ganlikun	0:13413ea9a877	1698	/**
ganlikun	0:13413ea9a877	1699	* @brief Generate a STOP condition after the current byte transfer (master mode).
ganlikun	0:13413ea9a877	1700	* @rmtoll CR1 STOP LL_I2C_GenerateStopCondition
ganlikun	0:13413ea9a877	1701	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1702	* @retval None
ganlikun	0:13413ea9a877	1703	*/
ganlikun	0:13413ea9a877	1704	__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1705	{
ganlikun	0:13413ea9a877	1706	SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
ganlikun	0:13413ea9a877	1707	}
ganlikun	0:13413ea9a877	1708
ganlikun	0:13413ea9a877	1709	/**
ganlikun	0:13413ea9a877	1710	* @brief Enable bit POS (master/host mode).
ganlikun	0:13413ea9a877	1711	* @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
ganlikun	0:13413ea9a877	1712	* @rmtoll CR1 POS LL_I2C_EnableBitPOS
ganlikun	0:13413ea9a877	1713	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1714	* @retval None
ganlikun	0:13413ea9a877	1715	*/
ganlikun	0:13413ea9a877	1716	__STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1717	{
ganlikun	0:13413ea9a877	1718	SET_BIT(I2Cx->CR1, I2C_CR1_POS);
ganlikun	0:13413ea9a877	1719	}
ganlikun	0:13413ea9a877	1720
ganlikun	0:13413ea9a877	1721	/**
ganlikun	0:13413ea9a877	1722	* @brief Disable bit POS (master/host mode).
ganlikun	0:13413ea9a877	1723	* @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
ganlikun	0:13413ea9a877	1724	* @rmtoll CR1 POS LL_I2C_DisableBitPOS
ganlikun	0:13413ea9a877	1725	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1726	* @retval None
ganlikun	0:13413ea9a877	1727	*/
ganlikun	0:13413ea9a877	1728	__STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1729	{
ganlikun	0:13413ea9a877	1730	CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
ganlikun	0:13413ea9a877	1731	}
ganlikun	0:13413ea9a877	1732
ganlikun	0:13413ea9a877	1733	/**
ganlikun	0:13413ea9a877	1734	* @brief Check if bit POS is enabled or disabled.
ganlikun	0:13413ea9a877	1735	* @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS
ganlikun	0:13413ea9a877	1736	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1737	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1738	*/
ganlikun	0:13413ea9a877	1739	__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1740	{
ganlikun	0:13413ea9a877	1741	return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
ganlikun	0:13413ea9a877	1742	}
ganlikun	0:13413ea9a877	1743
ganlikun	0:13413ea9a877	1744	/**
ganlikun	0:13413ea9a877	1745	* @brief Indicate the value of transfer direction.
ganlikun	0:13413ea9a877	1746	* @note RESET: Bus is in read transfer (peripheral point of view).
ganlikun	0:13413ea9a877	1747	* SET: Bus is in write transfer (peripheral point of view).
ganlikun	0:13413ea9a877	1748	* @rmtoll SR2 TRA LL_I2C_GetTransferDirection
ganlikun	0:13413ea9a877	1749	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1750	* @retval Returned value can be one of the following values:
ganlikun	0:13413ea9a877	1751	* @arg @ref LL_I2C_DIRECTION_WRITE
ganlikun	0:13413ea9a877	1752	* @arg @ref LL_I2C_DIRECTION_READ
ganlikun	0:13413ea9a877	1753	*/
ganlikun	0:13413ea9a877	1754	__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1755	{
ganlikun	0:13413ea9a877	1756	return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
ganlikun	0:13413ea9a877	1757	}
ganlikun	0:13413ea9a877	1758
ganlikun	0:13413ea9a877	1759	/**
ganlikun	0:13413ea9a877	1760	* @brief Enable DMA last transfer.
ganlikun	0:13413ea9a877	1761	* @note This action mean that next DMA EOT is the last transfer.
ganlikun	0:13413ea9a877	1762	* @rmtoll CR2 LAST LL_I2C_EnableLastDMA
ganlikun	0:13413ea9a877	1763	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1764	* @retval None
ganlikun	0:13413ea9a877	1765	*/
ganlikun	0:13413ea9a877	1766	__STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1767	{
ganlikun	0:13413ea9a877	1768	SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
ganlikun	0:13413ea9a877	1769	}
ganlikun	0:13413ea9a877	1770
ganlikun	0:13413ea9a877	1771	/**
ganlikun	0:13413ea9a877	1772	* @brief Disable DMA last transfer.
ganlikun	0:13413ea9a877	1773	* @note This action mean that next DMA EOT is not the last transfer.
ganlikun	0:13413ea9a877	1774	* @rmtoll CR2 LAST LL_I2C_DisableLastDMA
ganlikun	0:13413ea9a877	1775	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1776	* @retval None
ganlikun	0:13413ea9a877	1777	*/
ganlikun	0:13413ea9a877	1778	__STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1779	{
ganlikun	0:13413ea9a877	1780	CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
ganlikun	0:13413ea9a877	1781	}
ganlikun	0:13413ea9a877	1782
ganlikun	0:13413ea9a877	1783	/**
ganlikun	0:13413ea9a877	1784	* @brief Check if DMA last transfer is enabled or disabled.
ganlikun	0:13413ea9a877	1785	* @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA
ganlikun	0:13413ea9a877	1786	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1787	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1788	*/
ganlikun	0:13413ea9a877	1789	__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1790	{
ganlikun	0:13413ea9a877	1791	return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
ganlikun	0:13413ea9a877	1792	}
ganlikun	0:13413ea9a877	1793
ganlikun	0:13413ea9a877	1794	/**
ganlikun	0:13413ea9a877	1795	* @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
ganlikun	0:13413ea9a877	1796	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
ganlikun	0:13413ea9a877	1797	* SMBus feature is supported by the I2Cx Instance.
ganlikun	0:13413ea9a877	1798	* @note This feature is cleared by hardware when the PEC byte is transferred or compared,
ganlikun	0:13413ea9a877	1799	* or by a START or STOP condition, it is also cleared by software.
ganlikun	0:13413ea9a877	1800	* @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare
ganlikun	0:13413ea9a877	1801	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1802	* @retval None
ganlikun	0:13413ea9a877	1803	*/
ganlikun	0:13413ea9a877	1804	__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1805	{
ganlikun	0:13413ea9a877	1806	SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
ganlikun	0:13413ea9a877	1807	}
ganlikun	0:13413ea9a877	1808
ganlikun	0:13413ea9a877	1809	/**
ganlikun	0:13413ea9a877	1810	* @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
ganlikun	0:13413ea9a877	1811	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
ganlikun	0:13413ea9a877	1812	* SMBus feature is supported by the I2Cx Instance.
ganlikun	0:13413ea9a877	1813	* @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare
ganlikun	0:13413ea9a877	1814	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1815	* @retval None
ganlikun	0:13413ea9a877	1816	*/
ganlikun	0:13413ea9a877	1817	__STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1818	{
ganlikun	0:13413ea9a877	1819	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
ganlikun	0:13413ea9a877	1820	}
ganlikun	0:13413ea9a877	1821
ganlikun	0:13413ea9a877	1822	/**
ganlikun	0:13413ea9a877	1823	* @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
ganlikun	0:13413ea9a877	1824	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
ganlikun	0:13413ea9a877	1825	* SMBus feature is supported by the I2Cx Instance.
ganlikun	0:13413ea9a877	1826	* @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
ganlikun	0:13413ea9a877	1827	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1828	* @retval State of bit (1 or 0).
ganlikun	0:13413ea9a877	1829	*/
ganlikun	0:13413ea9a877	1830	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1831	{
ganlikun	0:13413ea9a877	1832	return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
ganlikun	0:13413ea9a877	1833	}
ganlikun	0:13413ea9a877	1834
ganlikun	0:13413ea9a877	1835	/**
ganlikun	0:13413ea9a877	1836	* @brief Get the SMBus Packet Error byte calculated.
ganlikun	0:13413ea9a877	1837	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
ganlikun	0:13413ea9a877	1838	* SMBus feature is supported by the I2Cx Instance.
ganlikun	0:13413ea9a877	1839	* @rmtoll SR2 PEC LL_I2C_GetSMBusPEC
ganlikun	0:13413ea9a877	1840	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1841	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
ganlikun	0:13413ea9a877	1842	*/
ganlikun	0:13413ea9a877	1843	__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1844	{
ganlikun	0:13413ea9a877	1845	return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
ganlikun	0:13413ea9a877	1846	}
ganlikun	0:13413ea9a877	1847
ganlikun	0:13413ea9a877	1848	/**
ganlikun	0:13413ea9a877	1849	* @brief Read Receive Data register.
ganlikun	0:13413ea9a877	1850	* @rmtoll DR DR LL_I2C_ReceiveData8
ganlikun	0:13413ea9a877	1851	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1852	* @retval Value between Min_Data=0x0 and Max_Data=0xFF
ganlikun	0:13413ea9a877	1853	*/
ganlikun	0:13413ea9a877	1854	__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
ganlikun	0:13413ea9a877	1855	{
ganlikun	0:13413ea9a877	1856	return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
ganlikun	0:13413ea9a877	1857	}
ganlikun	0:13413ea9a877	1858
ganlikun	0:13413ea9a877	1859	/**
ganlikun	0:13413ea9a877	1860	* @brief Write in Transmit Data Register .
ganlikun	0:13413ea9a877	1861	* @rmtoll DR DR LL_I2C_TransmitData8
ganlikun	0:13413ea9a877	1862	* @param I2Cx I2C Instance.
ganlikun	0:13413ea9a877	1863	* @param Data Value between Min_Data=0x0 and Max_Data=0xFF
ganlikun	0:13413ea9a877	1864	* @retval None
ganlikun	0:13413ea9a877	1865	*/
ganlikun	0:13413ea9a877	1866	__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
ganlikun	0:13413ea9a877	1867	{
ganlikun	0:13413ea9a877	1868	MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
ganlikun	0:13413ea9a877	1869	}
ganlikun	0:13413ea9a877	1870
ganlikun	0:13413ea9a877	1871	/**
ganlikun	0:13413ea9a877	1872	* @}
ganlikun	0:13413ea9a877	1873	*/
ganlikun	0:13413ea9a877	1874
ganlikun	0:13413ea9a877	1875	#if defined(USE_FULL_LL_DRIVER)
ganlikun	0:13413ea9a877	1876	/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
ganlikun	0:13413ea9a877	1877	* @{
ganlikun	0:13413ea9a877	1878	*/
ganlikun	0:13413ea9a877	1879
ganlikun	0:13413ea9a877	1880	uint32_t LL_I2C_Init(I2C_TypeDef I2Cx, LL_I2C_InitTypeDef I2C_InitStruct);
ganlikun	0:13413ea9a877	1881	uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
ganlikun	0:13413ea9a877	1882	void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
ganlikun	0:13413ea9a877	1883
ganlikun	0:13413ea9a877	1884
ganlikun	0:13413ea9a877	1885	/**
ganlikun	0:13413ea9a877	1886	* @}
ganlikun	0:13413ea9a877	1887	*/
ganlikun	0:13413ea9a877	1888	#endif /* USE_FULL_LL_DRIVER */
ganlikun	0:13413ea9a877	1889
ganlikun	0:13413ea9a877	1890	/**
ganlikun	0:13413ea9a877	1891	* @}
ganlikun	0:13413ea9a877	1892	*/
ganlikun	0:13413ea9a877	1893
ganlikun	0:13413ea9a877	1894	/**
ganlikun	0:13413ea9a877	1895	* @}
ganlikun	0:13413ea9a877	1896	*/
ganlikun	0:13413ea9a877	1897
ganlikun	0:13413ea9a877	1898	#endif /* I2C1 \|\| I2C2 \|\| I2C3 */
ganlikun	0:13413ea9a877	1899
ganlikun	0:13413ea9a877	1900	/**
ganlikun	0:13413ea9a877	1901	* @}
ganlikun	0:13413ea9a877	1902	*/
ganlikun	0:13413ea9a877	1903
ganlikun	0:13413ea9a877	1904	#ifdef __cplusplus
ganlikun	0:13413ea9a877	1905	}
ganlikun	0:13413ea9a877	1906	#endif
ganlikun	0:13413ea9a877	1907
ganlikun	0:13413ea9a877	1908	#endif /* __STM32F4xx_LL_I2C_H */
ganlikun	0:13413ea9a877	1909
ganlikun	0:13413ea9a877	1910	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
ganlikun	0:13413ea9a877	1911

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Type:	Library
Created:	05 Jul 2022
Imports:	1
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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.h@0:13413ea9a877, 2022-06-12 (annotated)

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